JP4784253B2 - Wafer inspection method and apparatus - Google Patents

Description

  The present invention relates to a wafer inspection method and a wafer inspection apparatus for inspecting a semiconductor wafer such as silicon manufactured by a Czochralski method (CZ method) or the like by a copper deposition method (Cu decoration method).

  As a method of detecting a crystal defect in a single crystal wafer such as silicon and inspecting its quality, there is a copper deposition method (Cu decoration method) (for example, see Patent Document 1). The copper deposition method uses the fact that an oxide film (insulating film) is formed on the surface of a wafer, and the oxide film becomes non-uniform at the defect site. By applying an electric field to the wafer, the non-uniform portion becomes an oxide film. In this method, dielectric breakdown is caused to deposit copper in the electrolyte solution. By observing the deposited copper, the defect site can be easily detected.

  However, in the copper detection method, when the electric field applied to the oxide film (effective electric field (voltage applied to the oxide film / oxide thickness)) increases, dielectric breakdown (abnormal dielectric breakdown) occurs in the oxide film even in the absence of defects. May occur, and copper may be deposited on that portion. It is difficult to distinguish the copper deposited on the wafer surface from the observation of the fracture traces, whether the copper deposition is defective or due to abnormal dielectric breakdown. I can not do it.

Therefore, a method has been proposed in which the electric field applied to the oxide film is controlled within a desired range so that an abnormal effective electric field is not applied to the oxide film (see, for example, Patent Document 2). The voltage applied to the oxide film is the voltage drop due to the resistance of the electrolyte solution (eg, methanol solution) and the resistance of the depletion layer (p-type) formed in the wafer from the voltage applied between the upper and lower electrodes. It can be thought of as the subtracted voltage. Therefore, in Patent Document 2, by applying a voltage between the electrodes in consideration of the resistance value of the electrolyte solution (methanol solution) and the resistance value of the depletion layer formed in the wafer, A voltage having a desired strength that causes dielectric breakdown only at an existing location, that is, an effective electric field having a desired strength is applied to the oxide film. At that time, the resistance value of the depletion layer formed on the wafer is controlled by controlling the illuminance (light quantity) of the light applied to the wafer.
Japanese Patent No. 3241296 JP 2003-044496 A

  By the way, in the copper deposition method, when a complete crystal wafer such as COP (Crystal Originated Particle) and a wafer such as hydrogen anneal, argon anneal or epitaxial having a complete region on the surface layer are to be inspected. It is necessary to manage and control the inspection conditions such as the resistance value of the methanol solution and the resistance value of the depletion layer with higher accuracy as described above. For example, a wafer made from a crystal grown under the complete crystal growth conditions without the presence of vacancy-type point defect aggregates has a low density of vacancy-type point defect aggregates and a complete crystal region where no aggregates exist. The boundary is less clear than the conventional crystal. Therefore, if the copper detection method is used for such wafer inspection, that is, the presence / absence of the presence of agglomerates of minute void type defects that are not detected by LSPC, dielectric breakdown (abnormal dielectric breakdown) that does not depend on crystal defects is caused. This is because the possibility of occurrence is extremely high.

  However, it is difficult to control the effective electric field applied to the oxide film with high accuracy by the conventional copper detection method. In particular, the characteristics of the depletion layer formed on the wafer change sensitively depending on the illuminance of light applied to the wafer, and it is not easy to strictly control this characteristic, that is, the resistance value. Therefore, in the inspection of a high-quality wafer such as the perfect crystal wafer described above, there is a problem that it is difficult to inspect it with high reliability by the copper detection method.

  The present invention has been made in view of such problems, and its purpose is to enable high-quality wafers such as perfect crystal wafers to be inspected with high reliability by the copper detection method. To provide an inspection method and a wafer inspection apparatus.

  In order to solve the above problems, the present inventor has found that it is effective to separate the step of causing dielectric breakdown of the oxide film and the step of reducing copper ions to deposit on the wafer surface. . That is, conventionally, in order to cause copper deposition, a positive voltage is applied to the oxide film side, and copper is deposited at a site where dielectric breakdown occurs at that voltage. In the present invention, as a first stage, a negative voltage is applied to the oxide film side to cause a dielectric breakdown at the defect position, and as a second stage, a positive low voltage is applied to the oxide film side and insulation is performed at the first stage. Copper was deposited at the defect position where the resistance was lowered due to the breakdown.

  Therefore, in the silicon wafer inspection method according to the present invention, a wafer to be inspected having an insulating film formed on the surface is disposed between two electrodes with an electrolyte solution containing copper ions interposed on the surface side, A wafer inspection method for depositing copper on a defect portion of the surface of the wafer by applying a voltage between the electrodes, wherein an electrode disposed on the surface side of the wafer is interposed between the two electrodes. A negative voltage applying step of applying a first voltage having a negative potential to an electrode disposed on the back surface side of the wafer, and after applying the first voltage, between the two electrodes, the surface side of the wafer A positive voltage applying step of applying a second voltage that is a positive potential with respect to the electrode arranged on the back side of the wafer, and depositing copper on the defective portion of the surface of the wafer; Yes That.

Preferably, the first voltage is a voltage with such a magnitude that dielectric breakdown occurs in the insulating film at the defective portion of the surface of the wafer.
Preferably, the second voltage is a voltage having a magnitude that does not cause a dielectric breakdown other than a defect in the insulating film on the surface of the wafer.

  In the silicon wafer inspection apparatus according to the present invention, a wafer to be inspected having an insulating film formed on the surface is disposed between two electrodes with an electrolyte solution containing copper ions interposed on the surface side. A wafer inspection apparatus for depositing copper on a defective portion of the surface of the wafer by applying a voltage between the electrodes, wherein an electrode disposed on the surface side of the wafer is between the two electrodes. A first voltage having a negative potential is applied to the electrode disposed on the back surface side of the wafer, and the electrode disposed on the front surface side of the wafer between the two electrodes after the application of the first voltage. Has an applied voltage control means for applying a second voltage having a positive potential to the electrode disposed on the back surface side of the wafer and precipitating copper on a defective portion of the surface of the wafer.

  According to the present invention, it is possible to provide a wafer inspection method and a wafer inspection apparatus capable of inspecting a high-quality wafer such as a complete crystal wafer with high reliability by a copper detection method.

An embodiment of a wafer inspection method and a wafer inspection apparatus according to the present invention will be described with reference to FIGS.
In the present embodiment, a method and apparatus for inspecting defects of a silicon bare wafer produced by crystal growth by the Czochralski method (CZ method) will be described.
FIG. 1 is a diagram showing a flow of processing of the defect inspection method for the silicon wafer, and FIG. 2 is a Cu deposition apparatus used in the copper (Cu) deposition treatment (step S16) of the inspection method shown in FIG. FIG. 3 is a diagram showing the flow of the Cu deposition process. FIG. 4 is a sectional view of the wafer for explaining the silicon wafer defect inspection method of the present embodiment.

  In the wafer inspection method of this embodiment, as shown in FIG. 1, first, as a pretreatment, wafer cleaning for removing external contamination sources such as particles attached to the wafer is performed on the bare wafer to be inspected. (Step S12).

  Next, the wafer is put into a diffusion device such as an electric furnace, thermal oxidation is performed, and an oxide film (insulating film) is formed on the wafer (step S13). During this thermal oxidation, if there are crystal defects such as pits on the surface of the wafer, a local oxide film seaning phenomenon that causes copper to be deposited later occurs along the periphery. The thermal oxide film is formed to a thickness of 25 to 150 nm, for example. By forming an oxide film with such a thickness, it is possible to favorably deposit copper at a later stage regardless of the history of the wafer.

  Next, in order to secure an electrical conduction path between the lower part of the wafer and the lower electrode plate of the Cu deposition apparatus during the subsequent Cu deposition process, the insulation on the back surface of the wafer on which the insulating film (thermal oxide film) is formed is provided. A part of the film is removed by etching (step S14). Etching is performed using hydrogen fluoride (HF) vapor. The insulating film on the entire back surface of the wafer may be peeled off, but it is sufficient if a minimum electrical path can be secured.

  When etching is completed, the wafer is washed with pure water to remove residues such as etching gas (step S15).

  And Cu precipitation process is performed (process S16).

Here, a Cu deposition apparatus used for the Cu deposition process will be described with reference to FIG.
A Cu deposition apparatus 1 shown in FIG. 2 includes a lower electrode (lower plate) 10 made of gold-plated copper, and an upper electrode made of pure copper having many small holes formed at equal intervals so that light can be irradiated onto the wafer surface. A plate (upper plate) 12, a side wall portion 14, a spacer 16, and a power source 18 are included.
The lower plate 10 and the upper plate 12 are arranged at a predetermined interval by a spacer 16, and are surrounded by a side wall portion 14. A space surrounded by the lower plate 10, the spacer 16, and the side wall portion 14 becomes a wafer seating portion 20. The side wall portion 14 and the spacer 16 are formed of an insulating material such as Teflon (“Teflon” is a registered trademark of DuPont, USA).

A connection terminal is connected to each of the lower plate 10 and the upper plate 12 and is connected to a power source 18.
The power source 18 is a voltage source that applies an arbitrary voltage to the lower plate 10 and the upper plate 12. In the Cu deposition method of this embodiment, the power source 18 is controlled, and a voltage is first applied so that the lower plate 10 is positive and the upper plate 12 is negative, and then the lower plate 10 is negative and the upper plate 12 is negative. A voltage is applied so that the plate 12 is positive.

Hereinafter, the flow of the Cu deposition process using the Cu deposition apparatus 1 will be described with reference to the flowchart of FIG. 3 and the wafer cross-sectional view of FIG.
In the Cu deposition process, first, the resistance value of the electrolyte solution using a dummy wafer is adjusted (step S20).
First, the upper plate 12 of the Cu deposition apparatus 1 is lifted and a dummy wafer is mounted on the lower plate 10 (step S21). As the dummy wafer, a wafer on which an oxide film having a thickness of 50 nm is formed is used.
Next, the upper plate 10 is installed, and methanol as a solvent for the electrolyte solution is poured into the wafer attachment part 20 in the Cu deposition apparatus 1 to such an extent that the upper plate 10 is submerged (step S22).

Next, a positive voltage is applied to the upper plate 10 made of pure copper soaked in methanol with respect to the lower plate 12 by the power source 18 to elute the copper ions (Cu ²⁺ ) into the methanol, thereby producing copper (Cu). Is oxidized (step S23). In this embodiment, a voltage of 50 V is applied between the lower plate 10 and the upper plate 12 for 30 minutes to oxidize copper.

  Next, the dummy wafer is taken out from the Cu deposition apparatus 1 (step S24), the test whether or not the resistance value of the methanol accommodated in the wafer attachment portion 20 is a desired value, and the desired value is obtained. If not, the adjustment is performed (step 25). The adjustment of the methanol resistance value is performed, for example, by adding new methanol when the methanol resistance value is too low, or by adding the copper ion elution process of steps S21 to S24 when the methanol resistance value is too high.

After the adjustment of the resistance value of the electrolyte solution (methanol solution) accommodated in the Cu deposition apparatus 1 is completed, a copper deposition process is performed on the wafer to be inspected (step S26).
First, a wafer to be inspected is mounted in the wafer seating portion 20 of the Cu deposition apparatus 1 (step S27). As shown in FIG. 4, the wafer to be inspected is a wafer 30 having a thermal oxide layer 34 that is an insulating film on a base material 31. At this time, the wafer 30 is a wafer seating portion of the Cu deposition apparatus 1. 20 is immersed in methanol.

Next, a voltage is applied between the lower plate 10 and the upper plate 12 by the power source 18 so that the upper plate 12 becomes a negative voltage with respect to the lower plate 10 (step S28). As a result, dielectric breakdown of the oxide film occurs at the site where the seaning phenomenon occurs in the thermal oxidation process of the wafer 30. Although a leakage current flows to the position due to dielectric breakdown, a positive voltage acts on the upper plate 12 from the lower plate 10 side in this step, so that copper ions Cu are formed on the surface of the insulating film 34. ²⁺ is not reduced, and no copper is deposited on the surface of the insulating film 34.

When a negative voltage is applied to the upper plate 12 at a predetermined voltage for a predetermined time, the lower plate 10 and the upper plate are then applied by the power source 18 so that the upper plate 12 becomes a positive voltage with respect to the lower plate 10. A voltage is applied between the two (step S29). As a result, a leakage current in the direction opposite to the state in step S28 flows at a location where dielectric breakdown has occurred first. That is, a positive voltage acts on the lower plate 10 from the upper plate 12 side, and an electron current flows from the lower plate 10 side toward the insulating film 34 of the wafer 30. As a result, the copper ion Cu ²⁺ in the electrolyte solution is reduced at the location where the leakage current on the surface of the insulating film 34 flows, and copper is deposited at that location (step S30).
Note that the voltage applied between the lower plate 10 and the upper plate 12 in step S29 is set so that the effective electric field applied to the insulating film is 6 MV / cm or less, more preferably in the range of 3 to 6 MV / cm. To do.

  When the copper deposition process is performed on the silicon wafer to be inspected in this way, the wafer is taken out from the Cu deposition apparatus 1 and the copper deposition state on the wafer surface is analyzed (step S17 (FIG. 1)). Thereby, the presence / absence, state, etc. of the crystal defect of the wafer can be inspected. This analysis is performed, for example, by observing the wafer with the naked eye or a scanning electron microscope (SEM).

  An inspection result when such a silicon wafer inspection method of this embodiment is applied to an actual wafer will be exemplified as an example. Here, for comparison, an inspection result obtained when an inspection is performed by a conventional method is also shown as a comparative example.

Example 1 and Comparative Example 1
First, a hydrogen annealed wafer, that is, a wafer manufactured by performing a heat treatment of holding a silicon wafer at a high temperature in a hydrogen gas atmosphere for several hours, and a defect (crystal defect) is detected by GOI evaluation using a polysilicon electrode. A wafer manufactured with such a high quality as to be impossible was inspected by the method of the present embodiment and the conventional method under a high electric field condition.
In the thermal oxidation process, an oxide film having a thickness of 50 nm was formed at a dry 02 temperature of 950 ° C.
In the dielectric breakdown process, an electric field of 10 MV / cm (voltage of 50 V with respect to an insulating film of 50 nm) in which abnormal copper deposition occurs by a conventional method was applied. Moreover, the copper deposition process was performed by applying an electric field of 5 MV / cm (voltage difference of 25 V with respect to an insulating film of 50 nm) without causing abnormal copper deposition.
That is, as a method according to the present invention (method as Example 1), a negative voltage of 50 V (10 MV / cm) is applied to the electrode on the oxide film side and held for 2 minutes, and then copper deposition is performed at a positive voltage of 25 V for 10 minutes. Carried out. In the conventional method (method as Comparative Example 1), a positive voltage of 50 V (10 MV / cm) was applied to the electrode on the oxide film side and held for 2 minutes, and then copper deposition was performed at a positive voltage of 25 V for 10 minutes.

The surface observation result of the wafer which performed copper deposition is shown in FIG.
5A is a view showing the surface of a wafer processed by the wafer inspection method according to the present embodiment, and FIG. 5B is a view showing the surface of the wafer processed by a conventional inspection method. is there.
As shown in FIG. 5A, in the inspection result by the wafer inspection method according to this embodiment, copper is hardly deposited on the wafer surface. On the other hand, in the inspection result by the conventional inspection method, as shown in FIG. 5B, copper is deposited on almost the entire surface of the wafer.
As described above, the wafer to be inspected is a wafer that has obtained a GOI evaluation indicating that there are almost no crystal defects. Therefore, in the wafer inspection method of this embodiment, the wafer can be properly evaluated. I understand that. On the other hand, in the conventional wafer inspection method, it can be considered that dielectric breakdown due to factors other than crystal defects and accompanying copper deposition occur on the entire surface of the wafer, and appropriate inspection of crystal defects on the wafer is possible. You can see that it was not done.

Example 2 and Comparative Example 2
Next, a polishing sample wafer having a crystal defect at the center was inspected, and inspection was performed by the method of this embodiment and the conventional method under normal electric field conditions.
In the thermal oxidation step, as in Example 1 and Comparative Example 1, an oxide film having a thickness of 50 nm was formed at a dry 02 temperature of 950 ° C.
In the dielectric breakdown process, an electric field of 7 MV / cm (voltage difference of 35 V with respect to a 50 nm insulating film) was applied. Moreover, the copper deposition process was performed by applying an electric field of 5 MV / cm (voltage difference of 25 V with respect to an insulating film of 50 nm) without causing abnormal copper deposition.
That is, in the method according to the present invention (method as Example 2), a negative voltage of 35 V (7 MV / cm) is applied to the electrode on the oxide film side, and after holding for 2 minutes, copper is deposited for 10 minutes at a positive voltage of 25 V. Carried out. Further, in the conventional inspection method (method as Comparative Example 2), a positive voltage of 35 V (7 MV / cm) is applied to the electrode on the oxide film side and held for 2 minutes, and then copper deposition is performed for 10 minutes at a positive voltage of 25 V. Carried out.

The surface observation result of the wafer which performed copper deposition is shown in FIG.
6A is a view showing the surface of a wafer processed by the wafer inspection method according to the present embodiment, and FIG. 6B is a view showing the surface of the wafer processed by a conventional inspection method. is there.
In both FIG. 6A and FIG. 6B, copper is similarly deposited at the center of the wafer where the crystal defects are considered to exist, and it is considered that both methods detect the crystal defects appropriately. . That is, the defect can be appropriately detected even in the conventional method under the normal electric field condition, and the defect can be similarly detected appropriately in the method according to the present embodiment.

  As described above, according to the silicon wafer inspection method of the present embodiment, under the conditions (normal electric field conditions) that can be properly inspected in the past, it can be inspected appropriately as in the prior art. Even under conditions that could not be properly inspected due to abnormal dielectric breakdown, that is, when a high electric field was applied to a complete crystal wafer, defects could be inspected appropriately. That is, a high quality wafer such as a complete crystal wafer can be inspected with high reliability by the copper detection method.

As described above, in the copper deposition method of this embodiment, after applying a positive voltage from the lower plate 10 to the upper plate 12 in step S28 (FIG. 3) to cause dielectric breakdown, the direction of the voltage is changed. Inverted, a positive voltage is applied from the upper plate 12 toward the lower plate 10 to supply electrons (leakage current) for depositing copper on the surface of the insulating layer 34.
Therefore, since the voltage at the dielectric breakdown stage is applied in a direction not causing the depletion layer, the voltage restriction is relaxed, and the illuminance management width can be set wider than the conventional method.

In order to control the effective electric field acting on the oxide film 34, as described above, the voltage applied between the upper plate 12 and the lower plate 10 and the upper portion of the electrolyte solution (methanol solution containing copper ions Cu ²⁺ ). The resistance value between the plate 12 and the lower plate 10 and, when a high resistance depletion layer is formed on the wafer 30, must be taken into account. However, since the depletion layer is not formed in the inspection method of this embodiment, it is not necessary to consider this, and it is only necessary to control only the resistance value of the electrolyte solution. Therefore, the effective electric field applied to the oxide film 34 can be easily and accurately controlled, and a high-quality wafer such as a complete crystal wafer can be inspected with high reliability.

  In addition, this embodiment is described in order to make an understanding of this invention easy, and does not limit this invention at all. Each element disclosed in the present embodiment includes all design changes and equivalents belonging to the technical scope of the present invention, and various suitable modifications can be made.

FIG. 1 is a diagram showing a flow of processing of a silicon wafer inspection method according to an embodiment of the present invention. FIG. 2 is a diagram showing a configuration of a copper deposition apparatus used in the copper deposition process of the inspection method shown in FIG. FIG. 3 is a diagram showing a flow of copper deposition treatment of the inspection method shown in FIG. FIG. 4 is a cross-sectional view of a wafer for explaining the inspection method shown in FIG. FIG. 5 is a first diagram for explaining a wafer inspection result by the inspection method of the present embodiment, and FIG. 5A is a view showing the surface of the wafer processed by the wafer inspection method according to the present embodiment. FIG. 5B is a view showing the surface of the wafer processed by the conventional inspection method. FIG. 6 is a second view for explaining the wafer inspection result by the inspection method of the present embodiment, and FIG. 6A is a view showing the surface of the wafer processed by the wafer inspection method according to the present embodiment. FIG. 6B is a view showing the surface of the wafer processed by the conventional inspection method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Copper (Cu) deposition apparatus 10 ... Lower plate 12 ... Upper plate 14 ... Side wall part 16 ... Spacer 18 ... Power supply 20 ... Wafer seating part 30 ... Wafer 31 ... Base material 33 ... Inversion layer 34 ... Oxide film (insulating film) )

Claims (6)

A wafer to be inspected having an insulating film formed on the surface is disposed between two electrodes with an electrolyte solution containing copper ions interposed on the surface side, and a voltage is applied between the electrodes to apply the surface of the wafer. A wafer inspection method for depositing copper on a defective part of
A negative voltage application step of applying a first voltage, which is a negative potential with respect to the electrode disposed on the back surface side of the wafer, between the electrodes, the electrode disposed on the front surface side of the wafer;
After the application of the first voltage, a second voltage is applied between the electrodes so that the electrode disposed on the front surface side of the wafer has a positive potential with respect to the electrode disposed on the back surface side of the wafer. And a positive voltage application step of depositing copper on a defect portion on the surface of the wafer.   2. The wafer inspection method according to claim 1, wherein the first voltage is a voltage having a magnitude that causes dielectric breakdown in the insulating film at a defect portion on the surface of the wafer.   3. The wafer inspection method according to claim 1, wherein the second voltage is a voltage that does not cause a dielectric breakdown other than a defect in the insulating film on the surface of the wafer. A wafer to be inspected having an insulating film formed on the surface is disposed between two electrodes with an electrolyte solution containing copper ions interposed on the surface side, and a voltage is applied between the electrodes to apply the surface of the wafer. A wafer inspection apparatus for depositing copper on the defective part of
A first voltage having a negative potential is applied between the electrodes, the electrode disposed on the front surface side of the wafer being negative with respect to the electrode disposed on the back surface side of the wafer, After the application, a second voltage is applied between the electrodes so that the electrode disposed on the front surface side of the wafer has a positive potential with respect to the electrode disposed on the back surface side of the wafer, A wafer inspection apparatus, comprising: an applied voltage control means for depositing copper on a defective portion of the surface.   5. The wafer inspection method according to claim 4, wherein the first voltage is a voltage having a magnitude that causes dielectric breakdown in the insulating film at the defective portion of the surface of the wafer. 6. The wafer inspection method according to claim 4, wherein the second voltage is a voltage that does not cause a dielectric breakdown other than a defect in the insulating film on the surface of the wafer.

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