JP4790334B2 - Nonvolatile memory device - Google Patents

Description

  The present invention relates to a non-volatile storage device incorporating a non-volatile memory such as a flash memory, and more particularly to prevention of a timeout that tends to occur with an increase in storage capacity.

  Nonvolatile storage devices such as memory cards, which have the advantage of being small and light, have come to be widely used in various technical fields, particularly consumer AV equipment and communication equipment. Many of these nonvolatile storage devices incorporate a nonvolatile memory such as a NAND flash memory.

  On the other hand, in such a flash memory, data can be directly written to an area that has not been written yet, like a magnetic disk, but on the other hand, data has already been written. The area has the property that data is first erased in units of blocks and data can be written only to the actual writing area after erasure.

  FIG. 8A shows a block configuration of a flash memory that is generally used at present. The flash memory is composed of a plurality of physical blocks 801 which are minimum erase units, and one physical block 801 is composed of a plurality of pages 802 which are data write units. In the example shown in the figure, one page is 512 B, and the capacity of one block is 512 KB × 32 pages and 16 KB.

  Next, processing when data is written in a nonvolatile storage device using such a flash memory as a storage medium using an information processing device (hereinafter referred to as a host) will be specifically described with reference to the drawings.

  FIG. 9 shows a state in which a memory card 110 which is a kind of nonvolatile storage device is mounted on the host 100. The memory card 110 basically writes data to the flash memory 111 or reads data from the flash memory 111 via a flash memory 11 1, which is a recording medium, and a flash interface (hereinafter abbreviated as a flash I / F) 112. A card controller 113 that performs data transfer, a buffer memory 114 that temporarily stores data transferred from the host 100, and a host I / F 115 that transfers data and control signals to and from the host 110.

FIG. 10 is a time chart showing a data flow between the host 100 and the memory card 110 when writing data to the memory card 110.
When writing data from the host 100 to the memory card 110, first, the write command 1001 shown in FIG. 10a is issued from the host 100 and transferred to the memory card 110 via the external bus 117, and subsequently, FIG. As shown in FIG. 5, data 1002 is transferred for each sector (512B) which is a unit of data transfer, and temporarily stored in the buffer memory 114 via the host I / F 115.

  At this time, as shown in FIG. 10C, every time data transfer of one sector is performed, the busy transmission circuit 118 in the host I / F 115 outputs a busy signal 1003 and transmits it to the host 100, and the buffer memory When it becomes possible to receive the next sector data within 114, the busy signal 1003 is canceled to make it ready.

  If the memory card 110 is ready, the host 100 performs data transfer of the next sector at any time, and the memory card 110 repeatedly outputs a busy signal. When there is no data to be transferred, the host 100 issues a stop command 1004 regardless of whether the memory card 110 is ready or busy. In response to this, the memory card 110 outputs a busy signal 1003 (the busy signal may already be output).

  The 512B data transferred from the host 100 is temporarily stored alternately in the buffers A119 and B120 in the buffer memory 114, and then written to the flash memory 111 according to the flow shown in FIG. After all the transferred data has been written, the memory card 110 releases the busy signal, returns to the ready state, and finishes the writing.

Next, with reference to the flowchart of FIG. 11, processing inside the card when writing data to the flash memory 111 will be described.
As described above, since data can be written to the memory card 110 only in an unwritten area, it is necessary to first set a physical block having an unwritten area as a write destination (step S1101). If it is necessary to secure a completed block (YES in S1102), the data is erased from the physical block in which unnecessary data is recorded to secure an empty block (S1103). On the other hand, if a write destination block having an unwritten area can be set and it is not necessary to secure a new erased block (NO in S1102), data is written to the block (S1104). ).

Writing is performed in units of pages. If there is data to be written, the writing is continued (YES in S1105), and until the writing of data for one block in logical address units is completed (NO in S1106), the same physical block The data writing process is repeated for S1104 (S1104). When data writing for one block is completed in logical address units (YES in S1106), a new physical block to be written is set, and the processing from S1101 to S1104 is repeated.
On the other hand, if there is no unwritten data on the way, the writing is terminated (NO in S1105).
JP-A-11-212862

In recent years, the capacity of one block constituting a memory card tends to increase in accordance with a request for an increase in storage capacity. 8 (B) and 8 (C) show the configuration of the blocks adopted with the increase in storage capacity. In FIG. 8 (B), 1 page is composed of 2 KB, 1 physical block is composed of 64 pages, The capacity of one physical block is 128 KB. FIG. 8C shows a block configuration adopted for a multi-valued type (four values in the figure) memory card. One page consists of 2 KB, one physical block consists of 128 pages, and the capacity of one physical block is 256 KB. Compared with the conventional block shown in FIG. 8A, the capacity is 16 times.
In the multi-value type, the memory capacity can be increased because 2-bit information can be held by taking four states in one memory cell. However, the write per page is larger than the conventional binary type. There is a demerit that time is long.

  FIG. 12 is a time chart (partially omitted) showing the flow of data in each part in the memory card 110 when writing to the memory card employing the multi-value type large block shown in FIG. FIG. 13 is obtained by adding a busy signal to the time chart at the top of FIG. The numbers in the time chart frame represent the number of pages.

The data flow of each part of the memory card at the time of data writing will be described below with reference to FIGS.
After the write command is issued from the host 100, data is sent from the host 100 to the host I / F 115 as a group of pages (2KB) which are write units of the flash memory 111 (a in FIG. 12), and the first 0 The page data is temporarily stored in the buffer A119 in the buffer memory 114 (same as b). Next, the data of the first page is sent from the host 100 and temporarily stored in the buffer B 120 in the buffer memory 114 (d).

  Subsequently, after the data of the 0th page is sent from the buffer A119 to the flash memory 111, writing is performed (same as c · f), and the data of the second page is temporarily stored in the vacant buffer A119. This process is repeated, and the writing of data for one block and 128 pages is completed (b, c, d, e, and f).

  By the way, in the example shown in the figure, copy processing is performed prior to data writing to the flash memory 111 (same as f). The copy process is a process for securing a data-erased empty block described with reference to the flowchart of FIG. 11, and specifically, all or a part of data recorded in a distributed manner in several blocks. Are collected in a block in which no data has been written, and then copied, and then the data of each block in which data distributed as a copy source is recorded is erased to secure an empty block. The memory card 110 alternatively performs such a copy process and a block-unit data write process in a time-sharing manner.

  When performing the copy process described above, in the case of a block with a relatively small capacity of 16 KB as shown in FIG. 8A, the processing time of one block is less than 10 ms including the data transfer and the writing time for each page. However, in the case of the block shown in FIG. 8B, the capacity per page and the number of pages increase, so that the time is about 25 ms. In the case of the block shown in FIG. Is about 125 ms.

  As described with reference to FIG. 10, every time data is transferred from the host 100 to the memory card 110 in units of sectors, a relatively short busy signal 1301 is returned to the host 100, but is stored in the buffer memory 114 during the copy process. Since the transferred data cannot be transferred to the flash memory 111, the copy process is completed as shown in FIG. 13g, and the busy signal 1302 is continuously output until the data in the buffer A is transferred to the flash memory 111. Is done.

  As the capacity of one block increases, the width of the busy signal 1302 that is output during the copy process becomes extremely longer than the busy signal 1301 in the normal state, so the host 100 determines that some abnormality has occurred in the memory card 110. There was a problem that timed out.

  In Patent Document 1, in order to solve such a problem, when there is a possibility that a busy signal having a long width is generated with the erasure of the flash memory, the busy signal is delayed by a certain period to delay the busy signal. By extending the signal width, the time for sending data from the host to the card is delayed to prevent the occurrence of timeout.

  However, in the case of Patent Document 1, since the normal writing process is resumed after the erasure of the flash memory is completed, the width of the busy signal may be extended only when there is an instruction from the host. There is a problem that the memory card itself cannot cope with the processing timing.

  The present invention solves such a conventional problem, and by providing means for setting the timing for starting the extension of the width of a busy signal, write processing and copy processing can be selected based on own judgment. Even in a memory card that is time-shared, the busy signal width can be extended to prevent the occurrence of a timeout.

In order to achieve the above object, the nonvolatile memory device of the present invention has been sent from an information processing device and a nonvolatile memory including a plurality of blocks which are erasure units and in which data is written in units of the blocks. A buffer memory for temporarily storing data, and a busy signal is transmitted to the information processing apparatus according to the data storage status in the buffer memory, and the timing for releasing the busy signal is delayed to extend the width of the busy signal An interface capable of writing, a write process for writing data sent from the information processing apparatus to the block of the nonvolatile memory, and a block in which data of all or a part of the area of the nonvolatile memory is not written. After copying the data of another block and filling all the blocks with data, the other block And a selectively perform controller and copy processing for allocating a free block to erase click data, the controller, when performing the copy processing, starts the width extension of the busy signal at said interface In addition, the width extension is controlled to be temporarily interrupted in accordance with the progress of the copy process .

In the nonvolatile memory device of the present invention, the controller may be configured to start reception of data to be written to the nonvolatile memory after the end of the copy process and release of the width extension after the buffer memory ends. Immediately before that, it is preferable that a signal for starting the width extension of the busy signal is transmitted to the interface.

In or non-volatile storage, wherein the interface is a busy transmitting circuit for transmitting the busy signal, and busy extension circuit for extending the width of delaying the timing of releasing the busy signal busy signal, said busy signal And a signal width setting circuit for setting the width of the signal.

  Similarly, the interface includes a busy transmission circuit that transmits the busy signal, and a busy extension circuit that receives a busy cancellation signal output from the controller in accordance with the progress of the copy process and sets a timing for canceling the busy signal. And may be provided.

  In the nonvolatile memory device of the present invention, it is preferable that the controller outputs a signal for canceling the busy signal width extension to the interface when the copy process is completed.

  According to the present invention, it is possible to provide a non-volatile storage device that does not cause a timeout even when the copy process takes a long time as the block capacity increases.

The best mode for carrying out the present invention will be described below with reference to the drawings.
( Reference form 1)
Figure 1 is a block diagram of a memory card in the reference embodiment 1 of the present invention, showing a state of being attached to the host. In the figure, parts having the same functions as those in FIG.

  In FIG. 1, reference numeral 100 denotes a host which is an information processing apparatus, and 110 denotes a memory card which is a kind of nonvolatile storage device. The memory card 110 is detachable from a slot (not shown) provided in the main body of the host 110. It is installed with.

  The memory card 110 includes a flash memory 111, a flash I / F 112, a card controller 113, a buffer memory 114, a host IF 115, and an internal bus 116.

  The card controller 113 controls the writing of data to the flash memory 111 and the reading of data from the flash memory 111 via the flash I / F 112 in accordance with instructions from the host 100. The buffer memory 114 temporarily stores data transferred from the host 100. In this embodiment, since the multi-value type large block shown in FIG. 8C is adopted as the flash memory 111, the capacity of each of the buffers A119 and B120 is 2 KB.

  The host I / F 115 transfers data to and from the host 100 via the external bus 117. The host I / F 115 includes a busy transmission circuit 118, a busy extension circuit 121, and a signal width setting circuit 122. The busy transmission circuit 118 checks whether or not the buffer memory 114 is free, and transmits a busy signal to the host 100 when data is already stored in the buffer memory 114 and no new data is accepted. The busy extension circuit 121 delays the timing for releasing the busy signal to give the busy signal a width, and the signal width setting circuit 122 sets the width of the busy signal.

2 and 3 is a time chart showing the flow of data in the memory card 110 in each section for writing data to the flash memory 111 in the present first reference, Figure 2 prior to writing data to the block copy FIG. 3 shows a case where a copy process is performed during data writing to a block.

  Hereinafter, the processing at the time of data writing will be described with reference to FIG. Based on the control of the card controller 113, as shown in FIG. 2f, when the copy process starts and the transfer of the 0th page data from the host 100 to the buffer A119 is started, the card controller 113 sends the busy extension circuit 121. A busy extension setting signal 201 is sent, and thereafter, the busy signal release timing is delayed as shown in FIG. 2g, and the width of the busy signal is extended.

  Specifically, the 0th page data (2 KB) is sent from the host 100 to the buffer A119 in units of sectors (512B) as indicated by numerical values 0 to 3 in the upper part of FIG. A busy signal is transmitted from the busy transmission circuit 118 each time (same g), but after the busy signal width is extended for a predetermined period determined by the signal width setting circuit 122, a ready state is entered (same a, b, g). . Similarly, the data of the first page is sent from the host 100 to the buffer B 120 in units of sectors (same as a and d). Note that the width of the busy signal set by the signal width setting circuit 122 is determined in consideration of the time required for the copy process and the time within a range where no timeout occurs in the host 100.

  Next, when the copy process in the flash memory 111 is completed, a busy extension cancellation signal 202 is sent from the card controller 113 to the busy extension circuit 121, and then a busy signal having a normal signal width is sent from the busy transmission circuit 118, and the flash Data is written to the memory 111 in units of pages.

  As is clear from FIG. 2, by extending the width of the busy signal, a busy signal having an extremely wide width is not sent during the copy process, so that a timeout in the host 100 can be prevented.

  FIG. 3 shows the case where the copy process is performed during the writing of data to two blocks, but when the 126th page data is transferred from the buffer A 119 to the flash memory 111 as shown in FIG. In other words, when the host 100 starts to transfer data of the 128th page, which is the first page of the block to be written next, to the buffer memory 114, the card controller 113 sends a busy extension setting signal 201 to the busy extension circuit 121. Then, the timing of sending data from the host 100 to the buffer memory 114 is delayed by extending the width of the busy signal in the same manner as in FIG. 2, and during the copy process, as in FIG. Timeout on host 100 because no busy signal with an extremely long width is sent. Produce the can be prevented.

  Next, with reference to the flowchart of FIG. 4, processing inside the card when data is written to the memory card 110 will be described. When writing is started, the card controller 113 sets a physical block as a writing destination (S401). If it is not necessary to secure an erased block (NO in S402), the data to the flash memory 111 is processed in the steps after S406. Write. At this time, the busy extension cancellation signal 202 is sent from the card controller 113 to the busy extension circuit 121 to release the busy signal width extension (S405), but at this time, the busy signal width extension has not been set yet. The operation is not affected.

  On the other hand, if it is necessary to secure an erased block (YES in S402), an empty block that has been erased is secured by copy processing (S404). Unlike the conventional example shown in FIG. Before, the busy extension setting signal 201 is output to the busy extension circuit 121 so as to extend the width of the busy signal (S403). Thereafter, an erased empty block is secured by performing copy processing (S404).

  After the copy process is completed and an empty block is secured, the card controller 113 outputs a busy extension release signal 202 to release the busy signal width extension (S405), and subsequently writes data to the secured empty block. Execute (S406).

  As described with reference to FIG. 3, since the copy process is also performed during the data write process in units of blocks, the card controller 113 determines that the data transferred from the buffer memory 114 to the flash memory 111 is the 126th page, that is, the logical address. In step S407, the busy extension setting signal 201 is transmitted to the busy extension circuit 121 to determine the width of the busy signal. The extension is set (S408).

  This is a process for a case where it is necessary to secure an erased block before writing the next block of data. Since it takes time to secure the erase block, a setting is made to extend the width of the busy signal before the head data of the next block is transferred from the host 100 to the memory card 110. On the other hand, if the data transferred from the buffer memory 114 to the flash memory 111 is not a predetermined size before the block boundary, no particular processing is performed (NO in S407).

Thereafter, when there is unwritten data and the logical block is filled with data (YES in S409 and S410), the process returns to S401, and whether or not it is necessary to set a new physical block and secure an erased block Judgment is made (S402). If it is not necessary to secure the erased block (NO in S402), the busy signal width extension is canceled (S405). As a result, the busy signal width extension (S408) set before the predetermined size of the logical block boundary is canceled.
On the other hand, when it is necessary to secure an erased block, the width extension of the busy signal is canceled after performing the copy process (S404) (S405).

  As shown in FIG. 3, the busy extension setting signal 201 is output when starting the copy process (S403), but the data before the predetermined size of the logical block boundary (the data on the 126th page in the figure) is already present. Since the busy extension setting signal 201 is output at the time of transfer from the buffer memory 114 to the flash memory 111 (S408), the operation is not affected.

  On the other hand, if there is still room in the block (NO in S410), data writing is continued in page units (S406), and if there is no unwritten data, the writing is terminated (NO in S409).

In FIG. 3, the busy extension setting signal 201 is output when the data of the 126th page is transferred from the buffer memory 114 to the flash memory 111. However, the busy extension setting signal 201 is written to the next block after the copy process. When the buffer data 114 is received at the time when the buffer memory 114 receives the data from the host 100, the data may be output at the same time as or just before the data is received.
(Embodiment 1 )

FIG. 5 is a block diagram of the memory card 110 according to the first embodiment of the present invention. 6 and 7 are time charts showing the flow of data when data is written to the flash memory 111 in the memory card of FIG. 5, and FIG. 6 shows a case where copy processing is performed prior to writing data to the block. FIG. 7 shows a case where copy processing is performed during data writing to the block.

Configuration of this embodiment 1 shown in FIG. 5, except functions slightly different from the signal width setting circuit point 122 is no, and busy extension circuit 501 is the same as that of the reference embodiment 1 shown in FIG. In the reference mode 1, the width of the extended busy signal is determined by the signal width setting circuit 122. However, in the present embodiment, as shown in FIGS. A release signal 601 is output to the busy extension circuit 501, and the busy extension circuit 501 releases the busy signal when receiving the busy release signal 601. For example, out of the copy process of 128 pages in one block, the busy release signal 601 is displayed every time the process for 32 pages is completed in FIG. 6 and every time the copy process is started and the process for 42 pages is completed in FIG. Is output to cancel the busy signal. Since the other processes are the same as in the first reference, the description thereof is omitted.

When the width of the busy signal is only extended for a predetermined time as in Reference Mode 1, when a copy process is performed on a block in which a part of the area is filled with data, the entire area in the block is copied. Compared with the case where processing is performed, the copy processing time is shortened, and the width of the busy signal is unnecessarily extended even though the buffer memory is free, and as a result, data transfer is delayed. If the busy release signal is output in accordance with the progress of the copy process as in the first embodiment, it is possible to appropriately control the free space in the buffer memory, and as a result, it is possible to avoid the risk of unnecessarily delaying data transfer.

Incidentally, Oite the form status of the embodiments has described the case of using a memory card using a flash memory as the storage medium as a non-volatile memory device, the present invention is not limited thereto, and erasing the block Needless to say, the present invention can be applied to many nonvolatile memory devices as a unit of writing.

  According to the nonvolatile memory device of the present invention, it is possible to achieve both the prevention of timeout in the host and the efficient writing to the nonvolatile memory, so that the nonvolatile memory device expected to become mainstream in the future is used. Useful to apply.

The block diagram which shows the structure of the memory card in the reference form 1 of this invention 4 is a time chart showing the flow of data in each unit when data is written in Reference Embodiment 1 of the present invention. 4 is a time chart showing the flow of data in each unit when data is written in Reference Embodiment 1 of the present invention. The flowchart which shows the data write-in process in the reference form 1 of this invention The block diagram which shows the structure of the memory card in Embodiment 1 of this invention. FIG. 3 is a time chart showing the data flow of each unit at the time of data writing according to the first embodiment of the present invention. FIG. 3 is a time chart showing the data flow of each unit at the time of data writing according to the first embodiment of the present invention. Diagram explaining the block configuration of the flash memory Block diagram of a conventional memory card Time chart of each part when writing data in a conventional memory card Flowchart showing data write processing in a conventional memory card Time chart showing the data flow of each part when writing data in a conventional memory card Time chart at the top of FIG.

Explanation of symbols

100 Host 110 Memory card 111 Flash memory 112 Flash I / F
113 Card controller 114 Buffer memory 115 Host I / F
116 Internal bus 117 External bus 118 Busy transmission circuit 121 Busy extension circuit 122 Signal width setting circuit 501 Busy extension circuit

Claims (4)

A non-volatile memory that includes a plurality of blocks that are erasure units and in which data is written in units of the blocks;
A buffer memory for temporarily storing data sent from the information processing device;
An interface capable of transmitting a busy signal to the information processing device in accordance with the storage state of data in the buffer memory and extending the width of the busy signal by delaying the timing of releasing the busy signal;
Write processing for writing data sent from the information processing device to the block of the non-volatile memory, and copying data of another block to a block in which data of all or part of the non-volatile memory is not written Then, after all the blocks are filled with data, a controller that selectively performs a copy process for erasing the data of the other blocks and securing a free block,
The controller starts to extend the width of the busy signal in the interface when performing the copy process, and controls to temporarily interrupt the width extension in accordance with the progress of the copy process. A non-volatile memory device. The non-volatile memory device according to claim 1, wherein the controller outputs a signal for canceling the extension of the width of the busy signal to the interface when the copy process is completed. The controller sends the busy signal to the interface at or immediately before the buffer memory starts receiving data to be written to the nonvolatile memory after the copy process is completed and the width extension is released . The nonvolatile memory device according to claim 2 , wherein a signal for starting width extension is transmitted. The interface includes a busy transmission circuit that transmits the busy signal, and a busy extension circuit that receives a busy cancellation signal output from the controller in accordance with the progress of the copy processing and sets a timing for canceling the busy signal. The non-volatile memory device according to claim 1, further comprising: a non-volatile memory device according to claim 1;

Images