JP4796372B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effective when applied to the manufacture of a semiconductor device using a plasma manufacturing apparatus.

  In Japanese Patent Laid-Open No. 2003-282545 (Patent Document 1), the plasma production apparatus (plasma apparatus) detects the impedance in the stable period of plasma discharge, and stops the power supply when it is determined as abnormal discharge by the arithmetic control process. Technology is disclosed.

  Japanese Patent Laid-Open No. 2002-305182 (Patent Document 2) discloses a technique for monitoring an abnormality by comparing a peak voltage of plasma discharge with a preset value.

  In Japanese Patent Application Laid-Open No. 2003-173974 (Patent Document 3), after the plasma reaches a stable period, the traveling wave power signal is monitored and the waveform is filtered and differentiated to compare the maximum and minimum values of the reflected wave. A technique for monitoring abnormal discharge is disclosed.

  Japanese Patent Application Laid-Open No. 2004-220923 (Patent Document 4) discloses a technique for detecting abnormal discharge by smoothing a traveling wave and a reflected wave of plasma and calculating a ratio of the reflected wave to the traveling wave.

  Japanese Patent Application Laid-Open No. 2002-324783 (Patent Document 5) discloses a technique for monitoring whether voltage or current is monitored and digitizing it at the time of stable discharge of plasma, and determining whether or not it is abnormal from the captured amplitude.

  Japanese Patent Application Laid-Open No. 10-74734 (Patent Document 6) discloses a technique for monitoring a change in plasma impedance and detecting abnormal discharge with a detector.

  Japanese Patent Laid-Open No. 9-199430 (Patent Document 7) discloses a technique in which a sequencer receives plasma discharge detection and moves a magnet controller from the sequencer to adjust the clearance of the plasma production apparatus.

In Japanese Patent Application Laid-Open No. 2004-288849 (Patent Document 8), an abnormal discharge of plasma is acquired by monitoring electromagnetic waves to acquire data into a data logger, and is determined to be abnormal discharge according to a predetermined determination criterion of a table. Is disclosed.
JP 2003-282545 A ([0022] to [0030], FIGS. 1 to 3) Japanese Patent Laid-Open No. 2002-305182 ([0012] to [0015], FIGS. 1 and 2) Japanese Unexamined Patent Publication No. 2003-17397 ([0013] to [0022], FIGS. 4 to 8) Japanese Unexamined Patent Publication No. 2004-220923 ([0019] to [0022], FIG. 1) JP 2002-324783 A ([0027] to [0031], FIGS. 2 and 3) Japanese Patent Laid-Open No. 10-74734 ([0018], [0019], [0028] to [0030], FIGS. 1 and 2) JP-A-9-199430 ([0008] to [0014], FIG. 1) JP 2004-288849 A ([0024] to [0028], FIGS. 7 to 9)

  With the miniaturization of semiconductor integrated circuits, semiconductor devices equipped with semiconductor integrated circuits have, for example, processing defects that occur during etching such as wiring processing and via hole processing, and deposition that occurs when depositing and embedding interlayer insulation films, etc. Defects are likely to occur. When these processing defects and deposition defects occur, various problems occur in the semiconductor device, and the manufacturing yield of the semiconductor device decreases.

  By the way, wiring processing, via hole processing, and the like are performed by using, for example, a plasma etching apparatus, and deposition of an interlayer insulating film or the like is performed by, for example, using a plasma CVD (Chemical Vapor Deposition) apparatus. In plasma processing using a plasma manufacturing apparatus such as a plasma etching apparatus or a plasma CVD apparatus, abnormal plasma discharge may occur. For this reason, for example, as described in Japanese Patent Application Laid-Open No. 2003-282545 (Patent Document 1, etc.), measures are taken to stop the power supply when it is determined that the plasma is abnormally discharged.

  Below, an example of the defect which generate | occur | produces in a semiconductor device is demonstrated with reference to FIG. FIG. 10 is an explanatory diagram showing an example of a defect that occurs in a semiconductor device. In the figure, reference numeral 1 is a semiconductor substrate, reference numeral 2 is a wiring, reference numeral 3 is a source / drain, reference numerals 4a and 4b are contacts, and reference numeral 5 is The gate electrode, reference numeral 6 denotes element isolation, reference numeral 7 denotes a gate insulating film, reference numeral 8 denotes an opening for a via hole, and reference numeral 9 denotes an interlayer insulating film.

  As shown in FIG. 10, a MIS (Metal Insulator Semiconductor) transistor Q is formed on the main surface of the semiconductor substrate 1. Wirings 2 formed of the same layer are arranged above the MIS transistor Q, and the respective wirings 2 are covered with an interlayer insulating film 9 made of, for example, silicon oxide and insulated and separated from each other. The wiring 2 is electrically connected to the source / drain 3 of the MIS transistor Q via the contact 4a, and is electrically connected to the gate 5 of the MIS transistor Q via the contact 4b. A gate insulating film 7 made of, for example, silicon oxide having a thickness of about 2 nm is formed under the gate electrode 5.

  In the semiconductor device of FIG. 10, for example, an insulation failure such that the interlayer insulating film 9 between the wirings 2 at the defective portion X1 surrounded by a circle causes dielectric breakdown, and the gate insulating film 7 at the defective portion X2 surrounded by a circle causes dielectric breakdown. May occur.

  For example, in the step of forming the via hole opening 8 in the interlayer insulating film 9 by plasma etching using a plasma etching apparatus, if the via hole opening 8 reaches the wiring 2 and the wiring 2 is exposed, the charged charge is increased. Flows to the semiconductor substrate 1 via the wiring 2. In FIG. 10, the flow of charge up is indicated by the symbol I. In such a case, the interlayer insulating film 9 at the defective portion X1 and the gate insulating film 7 at the defective portion X2 are formed with a dielectric breakdown voltage lower than the design standard, and the charge-up charge is in a normal manufacturing process. It is considered that dielectric breakdown occurs in the interlayer insulating film 9 at the defective portion X1 or the gate insulating film 7 at the defective portion X2 due to the presence of more instantaneously. Here, as a factor in which a large number of charges that are instantaneously charged up exist, abnormal plasma discharge in the plasma etching apparatus can be considered.

  Hereinafter, an example of factors that cause abnormal plasma discharge in the plasma manufacturing apparatus will be described with reference to FIG. FIG. 11 is an explanatory diagram showing an example of the cause of abnormal plasma discharge in the vacuum processing chamber of the plasma manufacturing apparatus. In the figure, reference numeral 21 denotes an anode electrode, reference numeral 22 denotes a cathode electrode, and reference numeral 23 denotes cooling helium. A gas supply pipe top, 24 is a gap, and 25 is a foreign object. A semiconductor wafer is placed on the cathode electrode 22 which is a wafer stage.

  As one of the factors that cause the abnormal discharge of plasma, there is a discharge that burns the frame portion 23 of the factor portion Y1 surrounded by a circle. The frame unit 23 shown in FIG. 11 is configured by overlapping three frames 23a, 23b, and 23c. A plurality of through holes are formed in each frame, and the cooling He gas passes through these through holes. By using a plurality of frames, the cooling He gas flow rate is adjusted, and the withstand voltage is adjusted so that no discharge occurs in the frame portion 23. The cooling He gas is used to cool the semiconductor wafer disposed on the cathode electrode 22 that is a wafer stage during plasma processing.

  However, for example, in a place where one of the through holes formed in the top 23a and one of the through holes formed in the top 23b overlap with each other, electrons contained in the cooling He gas are transferred to the cooling He. In some cases, the gas supply pipe is accelerated to increase energy and cause discharge, which may lower the withstand voltage of the top portion. In this case, if it is normal, discharge occurs in the frame portion 23 where no discharge occurs, and the frame portion 23 is burned as described above. In addition, a high electric field is instantaneously generated in the top portion 23 at the beginning of the rise of plasma. Therefore, such discharges cause abnormal plasma discharge in the vacuum processing chamber of the plasma manufacturing apparatus. Note that the burned-up frame portion 23 does not play a normal role.

  Also, abnormal discharge generated by the gap 24 due to poor assembly of the factor location Y2 surrounded by a circle, abnormal discharge generated when the foreign material 25 of the factor location Y3 surrounded by a circle becomes an antenna, or foreign material of the factor location Y4 surrounded by a circle The abnormal discharge generated by the pressure difference due to the pressure hole 25 closing the gas hole of the anode electrode 21 becomes a cause of the abnormal discharge of the plasma in the vacuum processing chamber of the plasma production apparatus. In addition, it is conceivable that abnormal discharge is also caused by mechanical interference caused by pusher pins, electric field balance abnormality caused by alumite deterioration, and the like.

  When plasma processing is not normally performed due to such abnormal discharge of plasma, as described above, the semiconductor device may be defective due to various defects such as dielectric breakdown of the interlayer insulating film between the wirings and dielectric breakdown of the gate insulating film. It will occur. Therefore, the termination of plasma processing by detecting an abnormal discharge of plasma does not manufacture many defective products, that is, a semiconductor device by preventing the creation of defective products due to the failure of the semiconductor manufacturing apparatus. It is considered effective to improve the manufacturing yield of

  Hereinafter, detection of abnormal discharge of plasma will be described with reference to FIG. FIG. 12 is an example of the waveform of the plasma impedance Vpp and the waveform of the reflected wave Pr of the plasma manufacturing apparatus, and the symbol T indicates a certain time from the rise of the plasma.

  As shown in FIG. 12, when plasma is first generated in the vacuum processing chamber of the plasma manufacturing apparatus, the plasma impedance Vpp is output and the reflected wave Pr is output. Next, when the plasma state is stabilized, the plasma impedance Vpp is stably output and the reflected wave Pr is not output. Next, when plasma generation is stopped, the plasma impedance Vpp is not output.

  Here, the output waveform of the plasma impedance Vpp and the output waveform of the reflected wave Pr shown in FIG. 12 show a case where the sampling is performed by sampling of about 100 ms, for example. In this case, it may be difficult to observe the abnormal discharge of the plasma generated in a shorter time.

  However, if there is no problem in the semiconductor device even if abnormal plasma discharge occurs, it is considered sufficient to detect abnormal plasma discharge from the waveform of the plasma impedance Vpp and the waveform of the reflected wave Pr by sampling for about 100 ms. . Further, if the plasma processing can be performed, it is excessive specification to use a control device having a clock frequency higher than the clock frequency capable of sampling about 100 ms, and the waveform and reflection of the plasma impedance Vpp performed by the sampling of about 100 ms. It is considered sufficient to detect abnormal plasma discharge from the waveform of the wave Pr. The sampling value of about 100 ms is determined from the clock frequency of the control device on the plasma manufacturing apparatus side that synchronizes various control signals such as pressure adjustment, gas flow rate adjustment, and temperature adjustment in order to perform plasma processing. It is.

  As described above, the waveforms of the plasma impedance Vpp and the reflected wave Pr shown in FIG. 12 are output when the plasma discharge is normally performed and output when the abnormal discharge of the plasma is generated. It is almost the same, and it is difficult to detect an abnormal discharge of plasma generated in a time shorter than sampling of about 100 ms. However, due to abnormal discharge of the plasma, for example, it is considered that a failure occurs in the semiconductor device due to a breakdown such as an insulation breakdown of an interlayer insulating film that has become difficult to ensure withstand voltage due to miniaturization, and a decrease in manufacturing yield of the semiconductor device. In order to prevent this, it is required to more accurately determine abnormal plasma discharge.

  In addition, in order to detect the abnormal discharge itself of the above-mentioned frame part, detection by the light emission monitor is difficult due to the device mechanism such as the frame part being covered. In addition, although a high electric field is instantaneously generated in the top part of the plasma at the beginning of the plasma, it is not necessary to detect abnormal discharge in the top part as long as it is an abnormal discharge of the plasma that does not cause a problem in the semiconductor device. Therefore, it is not necessary to provide an abnormality determination interlock mechanism. However, when abnormal discharge occurs in the top part, the use of the top part in the burned-in state cannot perform normal plasma processing, and the manufacturing yield of the semiconductor device is lowered.

  An object of the present invention is to provide a technique capable of improving the manufacturing yield of a semiconductor device using a plasma manufacturing apparatus.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In the method of manufacturing a semiconductor device according to the present invention, first, an insulating film is formed on a semiconductor substrate. Next, a plasma impedance waveform and a reflected waveform of the plasma etching apparatus are detected. Next, the detected waveform is set on the insulating film while monitoring abnormal discharge by setting a threshold value of abnormal discharge in each time division unit for plasma rising, plasma stable, and plasma falling. An opening is formed by an etching apparatus.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the semiconductor device manufacturing technique of the present invention, the manufacturing yield of a semiconductor device using a plasma manufacturing apparatus can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  First, a case where an example of a plasma manufacturing apparatus used for manufacturing a semiconductor device according to the present invention is applied to a plasma etching apparatus will be described with reference to FIGS. FIG. 1 is an explanatory view showing an example of a plasma manufacturing apparatus used for manufacturing a semiconductor device according to the present invention. FIG. 2 is an explanatory diagram showing a plasma impedance waveform and a reflected waveform of the plasma manufacturing apparatus of FIG.

  As shown in FIG. 1, a plasma manufacturing apparatus 31 used for manufacturing a semiconductor device according to the present invention includes a plasma abnormal discharge detection system (abnormal discharge detection mechanism) 32, for example, outside. In the vacuum processing chamber 33 of the plasma manufacturing apparatus 31, an anode electrode 21 and a cathode electrode 22 serving as a wafer stage are disposed so as to face each other. On the cathode electrode 22, a semiconductor wafer 1 </ b> W that is also a semiconductor substrate is disposed. Has been placed. The plasma manufacturing apparatus 31 is a plasma etching apparatus that performs plasma etching, which is plasma processing, on the semiconductor wafer 1 </ b> W in the vacuum processing chamber 33.

  The plasma in the vacuum processing chamber 33, the pressure of which is adjusted by the supply of the discharge gas, is supplied from the high frequency power source 35a to the anode electrode 21 through the matching box 34a. For example, the high frequency power (RF (Radio Frequency) of about 60 MHz is supplied. ) Power) and high-frequency power of, for example, about 2 MHz supplied from the high-frequency power source 35b to the cathode electrode 22 through the matching box 34b. Since a plasma composed of ions or the like is attracted by the sheath potential generated on the cathode electrode 22 side, for example, an insulating film or the like formed on the semiconductor wafer 1W can be more efficiently plasma etched (plasma treatment). In the present embodiment, high frequency power is supplied to each of the anode electrode 21 and the cathode electrode 22, but high frequency power need not be supplied to the anode electrode 21.

  A frame portion (not shown in FIG. 1) is disposed below the cathode electrode 22 on the side opposite to the side on which the semiconductor wafer 1W is disposed. The top part is configured by overlapping a plurality of tops, and is used for temperature adjustment such as cooling of the semiconductor wafer 1W by the cooling He gas passing through the plurality of through holes formed in each top. In addition, for example, by using a plurality of pieces made of Teflon (registered trademark), in addition to adjusting the cooling He gas flow rate, the dielectric strength is adjusted so that no discharge occurs in the piece part.

  The plasma impedance Vpp indicating the fluctuation of the matching box 34b, the incident wave Pf and the reflected wave Pr of the high-frequency power for plasma generation supplied from the high-frequency power source 35b are monitored (checked) by the monitoring device 36 of the plasma manufacturing apparatus 31. The monitoring device 36 is connected to a control device that performs various controls when performing plasma processing.

  The control device (sequencer) controls, for example, a signal for monitoring by the monitoring device 36, a signal for controlling the pressure in the vacuum processing chamber 33, and a high-frequency power for plasma generation in a predetermined sequence. Control for performing plasma processing in the plasma manufacturing apparatus 31 is performed, such as transmitting a signal or the like to each mechanism. The sequence for performing the plasma processing is synchronized with the clock frequency of the control device (hereinafter referred to as the first clock frequency).

  The abnormal discharge detection system 32 provided outside the plasma production apparatus 31 includes an A / D conversion unit 37, an abnormality determination data storage unit 38, a data input / display unit 39, and an abnormality notification unit 40. Yes.

  The abnormality determination data storage unit 38, which is a main unit for detecting an abnormal discharge of plasma in the plasma manufacturing apparatus 31, determines whether or not an abnormal discharge of plasma has occurred. That is, the waveform data of the normal plasma impedance and the reflected wave that are stored in the data logger of the abnormality determination data storage unit 38 and set in advance according to various plasma processing conditions, and the plasma impedance detected from the plasma manufacturing apparatus 31 are stored. The waveform data of the reflected wave and the reflected wave are compared to determine whether or not an abnormal discharge has occurred. The determination as to whether or not there is an abnormal discharge in the detected plasma impedance and reflected wave is transferred from the control device (sequencer) to the data logger of the abnormality determination data storage unit 38 via the A / D conversion unit 37. Performed in real time with a data logger. By performing in real time, abnormal discharge of plasma can be detected more rapidly.

  That is, after the semiconductor wafer 1W is placed in the plasma manufacturing apparatus 31 that performs plasma processing on the semiconductor wafer 1W by various controls synchronized with the first clock frequency, the high frequency power for generating plasma is supplied every certain time interval. In addition, abnormal plasma discharge can be detected by monitoring at least one of the plasma impedance Vpp and the reflected wave Pr.

  The waveform data of the plasma impedance Vpp and the reflected wave Pr is transmitted from the monitoring device 36 to the A / D conversion unit 37. Since the respective waveform data of the plasma impedance Vpp and the reflected wave Pr are analog data, the A / D conversion unit 37 converts the converted digital data into digital data by sampling of, for example, about 1 ms, and the abnormality determination data storage unit 38. For example, the certain time interval of about 1 ms is controlled by the clock frequency of the A / D conversion unit 37 (hereinafter referred to as the second clock frequency). The second clock frequency of the A / D conversion unit 37 is higher than the first clock frequency of the control device described above.

  Here, it is also possible to perform sampling at a constant time interval, for example, about 100 ms, according to the first clock frequency of the control device described above, detect the plasma impedance Vpp and the reflected wave Pr, and detect the abnormal discharge of the plasma. However, it is difficult to detect an abnormal discharge of plasma that occurs in a time shorter than the sampling of about 100 ms. Therefore, in the A / D conversion unit 37 of the abnormal discharge detection system 32, by controlling a certain time interval at the second clock frequency higher than the first clock frequency, for example, in about 1 ms which is shorter than about 100 ms sampling. It is possible to detect abnormal discharge of plasma more accurately by sampling. In this embodiment, it is about 1 ms, but it has been confirmed by the inventors that the abnormal discharge of the plasma is generated with a waveform having a pulse width of about 2 ms. Therefore, the time division unit is preferably at least 2 ms or less. May be 1 ms or less.

  The data input / display unit 39 can input data for conditions for plasma etching, such as the type of insulating film that is an object to be plasma processed, and displays an input waveform of an abnormality determination reference value. be able to. The data input / display unit 39 transmits / receives data to / from the abnormality determination data storage unit 38.

  A trigger signal for comparing waveform data is sent from the monitoring device 36 to the abnormality determination data storage unit 38. On the other hand, if the determination result is determined to be abnormal, an abnormal signal is sent from the abnormality determination data storage unit 38 to the monitoring device 36. If the determination result is determined to be abnormal, the abnormality notification unit 40 sends an abnormality signal from the abnormality determination data storage unit 38 and notifies the abnormality by, for example, an alarm.

  Next, detection of abnormal plasma discharge during manufacture of the semiconductor device according to the present invention will be described with reference to FIG. FIG. 2 is an example of the waveform of the plasma impedance Vpp and the waveform of the reflected wave Pr of the plasma manufacturing apparatus of FIG. 1, and the symbol T indicates a certain time from the rise of the plasma. In the plasma impedance Vpp, the regions F, A, and B when the plasma rises, the region C when the plasma is stable, the region G when the plasma falls, and the reflected wave Pr in the region H when the plasma rises. D, the region E is shown when the plasma is stable, and the region I is shown when the plasma falls.

  The waveform of the plasma impedance Vpp and the waveform of the reflected wave Pr shown in FIG. 2 are detected by sampling of about 1 ms, for example. When comparing the waveform of the plasma impedance Vpp and the reflected wave Pr shown in FIG. 12 by sampling of about 100 ms with the waveform of the plasma impedance Vpp and the waveform of the reflected wave Pr shown in FIG. 2 by sampling of about 1 ms, A short-time plasma discharge can be detected from the output waveform obtained by sampling of about 1 ms. Therefore, the detection of the abnormal discharge of the plasma can detect the discharge of the plasma for a shorter time, and therefore has high accuracy.

Determination of abnormal plasma discharge in the plasma impedance Vpp and the reflected wave Pr is performed using a threshold value. In FIG. 2, examples of the threshold values of the plasma impedance Vpp and the reflected wave Pr are respectively shown by dotted lines. In the plasma impedance Vpp, for example, the threshold value V _A can be set in the region A, the threshold value V _{B in the} region B, and the threshold value V _{C in the} region C. Further, the reflected wave Pr, for example, can be set in the region D threshold _{P D,} in the region E threshold _{P E.}

In FIG. 2, when an abnormal discharge of plasma occurs at a certain time, a waveform Z1 and a waveform Z2 indicated by dotted lines are detected in the plasma impedance Vpp and the reflected wave Pr, respectively. The waveform Z1 is because it exceeds the threshold value V _C region C, the plasma impedance Vpp, is determined to be abnormal. The waveform Z2 is because it exceeds the threshold P _E region E, the reflected wave Pr, is determined to be abnormal. Therefore, when both the plasma impedance Vpp and the reflected wave Pr detected at a certain time exceed the threshold value, it can be detected (determined) that an abnormal plasma discharge has occurred. It is also possible to detect that abnormal plasma discharge has occurred when the plasma impedance Vpp or the reflected wave Pr exceeds a threshold value.

Also, when detecting a plasma impedance Vpp of the waveform that exceeds the threshold value V _B region B, in particular, if the abnormal discharge plasma, such as coma seizure is occurring is considered. Variations in the rise of the plasma impedance Vpp of the plasma, in particular, to influence the frame portion including a plurality of frames, when the abnormal discharge plasma which exceeds the threshold value V _B, the frame is burned It is possible. An abnormal determination interlock mechanism can be provided for the case where abnormal discharge is detected in the frame section.

  Next, a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 3 to 8 are cross-sectional views schematically showing the semiconductor device during the manufacturing process of the present embodiment. FIG. 9 is a flowchart for detecting an abnormal discharge of plasma, and shows a case where an abnormal discharge is determined from a plasma impedance waveform. In addition, although description is abbreviate | omitted, it can determine similarly whether it is abnormal discharge from a reflected waveform.

  First, as shown in FIG. 3, after the element isolation 6 is formed on the main surface of the semiconductor substrate 1 made of, for example, p-type single crystal silicon, the MIS transistor Q is formed. The element isolation 6 is formed by forming a groove in a predetermined region on the semiconductor substrate 1 by a photolithography technique and an etching technique and then filling the groove with, for example, silicon oxide and planarizing the groove. The gate electrode 5 and the gate insulating film 7 of the MIS transistor Q are formed by depositing a silicon film made of, for example, about 2 nm of silicon oxide to be the gate insulating film 7 and polysilicon to be the gate electrode 5, and then photolithography and etching. It is formed by patterning so that a predetermined region remains by a technique. The source / drain 3 of the MIS transistor Q is formed by, for example, an ion implantation technique using an n-type impurity using the gate electrode 5 as a mask.

  Note that a metal film may be formed on the silicon film to be the gate electrode 5. That is, after forming, for example, silicon oxide to be the gate insulating film 7, a silicon film to be the gate electrode 5, and a metal film on the main surface of the semiconductor substrate 1, patterning is performed so that a predetermined region remains by a photolithography technique and an etching technique. Then, the gate insulating film 7 and the gate electrode 5 including a metal film on the top are formed. Here, plasma etching with detection of abnormal plasma discharge can be applied as an etching technique. That is, the plasma impedance waveform and reflection waveform of the plasma etching apparatus are patterned while monitoring the threshold value set in the time division unit that subdivides the plasma rising time, plasma stabilizing time, and plasma falling time. It is.

  Subsequently, as shown in FIG. 4, an interlayer insulating film 9 a made of, for example, silicon oxide is deposited so as to cover the main surface of the semiconductor substrate 1 and is planarized, and then, for example, in a contact opening formed in a predetermined region. A conductor such as tungsten (W) is embedded to form contacts 4a and 4b. The contact 4a is formed so as to be electrically connected to the source / drain 3 of the MIS transistor Q. The contact 4b is formed so as to be electrically connected to the gate electrode 5 of the MIS transistor Q.

  Subsequently, as shown in FIG. 5, a conductor such as aluminum (Al), for example, is deposited on the interlayer insulating film 9a, and then the wiring 2 made of the same layer is formed by a photolithography technique and an etching technique. The wiring 2 is electrically connected to a contact 4 a formed under the wiring 2.

  Subsequently, as shown in FIG. 6, an interlayer insulating film 9 b is formed and planarized so as to cover the wiring 2 formed on the main surface of the semiconductor substrate 1, and then by photolithography technique and etching technique. A resist is deposited on the interlayer insulating film 9b, and a patterned resist film 11 is formed.

  Subsequently, after detecting the abnormal discharge of the plasma described later, if the abnormal discharge of the plasma cannot be detected, the interlayer insulating film 9b is connected to the wiring 2 by the plasma 12 using the resist film as a mask as shown in FIG. Etching is performed until a via hole opening 8 is formed. This plasma etching is performed using the resist film 11 shown in FIG. 6 as a mask. Here, plasma etching with detection of abnormal plasma discharge can be applied as an etching technique. In other words, while monitoring the plasma impedance waveform and reflection waveform of the plasma etching device, while monitoring the threshold of abnormal discharge determination set in time division units that subdivide the plasma rising time, plasma stable time, and plasma falling time The via hole opening 8 is formed in the interlayer insulating film 9b.

  Subsequently, as shown in FIG. 8, the via hole 10 is formed in the interlayer insulating film 9 b by filling the via hole opening 8 formed so as to expose the wiring 2 with a conductor made of, for example, tungsten (W). To do. Therefore, the via hole 10 is electrically connected to the source / drain 3 of the MIS transistor Q via the wiring 2 and the contact 4a, or is electrically connected to the gate electrode 5 of the MIS transistor Q via the wiring 2 and the contact 4b. Connected.

  Thereafter, for example, after forming a plurality of wiring layers and the like, a protective film covering the main surface of the semiconductor substrate 1 is formed, and the semiconductor device is substantially completed.

  A description will be given of a case where determination processing for determining whether or not there is abnormal discharge (hereinafter referred to as abnormal discharge determination) from the waveform of the plasma impedance Vpp when detecting the abnormal discharge of the plasma described above. Here, the plasma impedance Vpp waveform as shown in FIG. 2 is subdivided when the plasma rises (regions F, A, and B), when the plasma is stable (region C), and when the plasma falls (region G). The time division unit is set to about 1 ms, for example. That is, the plasma impedance Vpp is monitored for every fixed time segment of about 1 ms, for example, from the time of supplying the high frequency power for generating plasma in the vacuum processing chamber of the plasma manufacturing apparatus. In this embodiment, it is set to about 1 ms. However, it has been confirmed by the inventors that the abnormal discharge of plasma occurs in about 2 ms. Therefore, the time division unit is preferably 1 ms or less. Furthermore, the monitoring sections for determining whether or not the plasma is abnormally discharged are areas A, B, and C, and the non-monitoring sections for which monitoring is not performed are the areas F and G. Although all the regions F, A, B, C, and G may be set as monitoring sections, in the present embodiment, particularly, the areas A to C where abnormal plasma discharge is likely to occur are set as monitoring sections.

First, in plasma etching, after setting plasma etching conditions such as the material of the interlayer insulating film 9b formed on the main surface of the semiconductor substrate 1 to be an object, abnormal discharge determination is started (step S10). Threshold values V _A , V _B and V _C are set according to the plasma etching conditions. These threshold values V _A , V _B , and V _C are set with reference to a plasma impedance waveform at the time of normal plasma rise, plasma stability, and plasma fall measured in advance under plasma etching conditions as a reference (reference value). . For example, the threshold value _VA can be about ± 90% of the reference value, the threshold value VB can be about 100 V to about 2500 V, and the threshold value VC can be about ± 11% of the reference value.

Subsequently, it is determined whether or not it is the monitoring section A (step S20). If it is the monitoring section A, it is determined whether or not the waveform of the detected plasma impedance Vpp is abnormal, that is, the threshold value V. _It is determined whether or not _A is exceeded (step S30). At this time, the waveform of the plasma impedance Vpp is transferred from the control device (sequencer) to the abnormality determination storage unit (data logger), and is performed in real time by the abnormality determination storage unit. On the other hand, if it is not the monitoring section A, that is, the non-monitoring section F, the determination as to whether or not it is the monitoring section A is repeated without determining whether or not the waveform of the plasma impedance Vpp is abnormal.

  Here, in the monitoring section A, when it is determined that the waveform of the plasma impedance Vpp is abnormal, it is detected that an abnormal discharge of the plasma has occurred, and for example, an abnormality warning is performed, and waveform data is accumulated for a certain period of time. Then, abnormality processing such as stopping the plasma processing is performed (step S100), and the abnormality determination processing is ended (step S90). The same applies when it is determined that there is an abnormality in the waveform of the plasma impedance Vpp in the monitoring sections B and C.

Subsequently, when it is determined that there is no abnormality in the waveform of the plasma impedance Vpp in the monitoring section A, it is determined whether or not it is the monitoring section B (step S40). If a monitoring Section B, the determination of whether there is an abnormality in the waveform of the plasma impedance Vpp detected at monitor block B, that, to determine whether or not exceeding the threshold value V _B (step S50). At that time, the waveform of the plasma impedance Vpp is transferred from the monitoring device to the abnormality determination storage unit, and is performed in real time by the abnormality determination storage unit. On the other hand, if it is not the monitoring section B, that is, the monitoring section A, the determination as to whether or not the waveform of the plasma impedance Vpp is abnormal is repeated.

Subsequently, when it is determined that there is no abnormality in the waveform of the plasma impedance Vpp in the monitoring section B, it is determined whether or not it is the monitoring section C (step S60). If a monitor block C, the determination of whether there is an abnormality in the waveform of the plasma impedance Vpp detected at monitor block B, that, to determine whether or not exceeding the threshold value V _C (step S70). At that time, the waveform of the plasma impedance Vpp is transferred from the monitoring device to the abnormality determination storage unit, and is performed in real time by the abnormality determination storage unit. On the other hand, if it is not the monitoring section C, that is, the monitoring section B, the determination as to whether or not the waveform of the plasma impedance Vpp is abnormal is repeated.

For example, when the waveform Z1 as shown by dotted lines in FIG. 2 was observed, the waveform Z1 is the fact that exceeds the threshold value V _C. Therefore, it is determined that the waveform of the plasma impedance Vpp is abnormal, and it can be detected that an abnormal discharge of plasma has occurred. When it is detected that the abnormal discharge of the plasma is generated, maintenance is performed so as to stop the abnormal discharge of the plasma etching apparatus, so that the manufacturing yield of the semiconductor device using the plasma etching apparatus can be improved.

  Subsequently, if it is determined that the waveform of the plasma impedance Vpp is not abnormal in the monitoring section C, it is determined whether or not it is the non-monitoring section G (step S80). Is finished (step S90). On the other hand, if it is not the non-monitoring section G, that is, the monitoring section C, the determination as to whether or not the waveform of the plasma impedance Vpp is abnormal is repeated.

  In addition, although the abnormal discharge determination of the plasma impedance waveform has been described, the abnormal discharge determination of the reflected waveform can be similarly performed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the case where the plasma manufacturing apparatus that performs plasma processing is applied to a plasma etching apparatus that performs plasma etching has been described, but the present invention can also be applied to, for example, a plasma CVD apparatus that forms an insulating film.

  The present invention is widely used in the manufacturing industry for manufacturing a semiconductor device using a plasma manufacturing apparatus.

It is explanatory drawing which shows an example of the plasma manufacturing apparatus used for manufacture of the semiconductor device which concerns on this invention. It is explanatory drawing which shows the plasma impedance waveform and reflection waveform of the plasma manufacturing apparatus of FIG. It is sectional drawing which shows typically the semiconductor device in the manufacturing process which concerns on embodiment of this invention. FIG. 4 is a cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 3. FIG. 5 is a cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 4. FIG. 6 is a cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 5. FIG. 7 is a cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 6. FIG. 8 is a cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 7. It is a flowchart for detecting the abnormal discharge of the plasma which concerns on embodiment of this invention. It is explanatory drawing which shows an example of the defective location generate | occur | produced in a semiconductor device. It is explanatory drawing which shows an example of the factor which the abnormal discharge of a plasma generate | occur | produces in the vacuum processing chamber of a plasma manufacturing apparatus. It is an example of the plasma impedance waveform and reflection waveform of a plasma manufacturing apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1W Semiconductor wafer 2 Wiring 3 Source / drain 4a, 4b Contact 5 Gate electrode 6 Element isolation | separation 7 Gate insulating film 8 Via-hole opening part 9, 9a, 9b Interlayer insulating film 10 Via hole 11 Resist film 12 Plasma 21 Anode electrode 22 Cathode electrode 23 Top part 23a, 23b, 23c Top 24 Clearance 25 Foreign object 31 Plasma production device 32 Abnormal discharge detection system 33 Vacuum processing chamber 34a, 34b Matching box 35a, 35b High frequency power supply 36 Monitoring device 37 A / D conversion unit 38 Abnormality determination Data storage unit 39 Data input / display unit 40 Abnormal alarm unit Q MIS transistor Vpp Plasma impedance Pf Incident wave Pr Reflected wave

Claims (11)

(A) placing the semiconductor wafer in a vacuum processing chamber of a plasma manufacturing apparatus that performs plasma processing on the semiconductor wafer by various controls synchronized with a first clock frequency;
(B) The abnormal discharge of the plasma is monitored by monitoring at least one of the impedance of the plasma or the reflected wave of the high-frequency power every certain time interval from the time of supplying the high-frequency power that generates plasma in the vacuum processing chamber. Detecting process,
A method of manufacturing a semiconductor device including:
The abnormal discharge detection mechanism provided in the plasma manufacturing apparatus performs sampling of at least one of the impedance of the plasma or the reflected wave of the high-frequency power at a second clock frequency higher than the first clock frequency, and performs the predetermined time division. A method for manufacturing a semiconductor device, wherein abnormal discharge is detected by comparing with a threshold value set separately for each. The high-frequency power is supplied to the electrode in which the semiconductor wafer is disposed in the vacuum processing chamber,
The method of manufacturing a semiconductor device according to claim 1, wherein the plasma is attracted to the electrode side, and the semiconductor wafer is subjected to plasma processing. A method for manufacturing a semiconductor device comprising the following steps:
(A) forming an insulating film on the main surface of the semiconductor substrate;
(B) With respect to the plasma impedance waveform of the plasma etching apparatus and the reflected waveform of the high frequency power for plasma generation obtained by sampling for controlling the plasma processing, when the plasma rises, when the plasma is stable, when the plasma falls The plasma is sampled in a time division unit of 2 ms or less, and the plasma is monitored while monitoring abnormal discharge with thresholds set separately for each plasma rise time, plasma stable time, and plasma fall time. Forming an opening in the insulating film by an etching apparatus;   4. The method of manufacturing a semiconductor device according to claim 3, wherein the time division unit is 1 ms or less.   4. The method of manufacturing a semiconductor device according to claim 3, wherein waveform data is accumulated only when the threshold value is exceeded.   4. The method of manufacturing a semiconductor device according to claim 3, wherein when both the plasma impedance waveform and the reflected waveform exceed the threshold value, it is determined that the plasma is abnormally discharged.   4. The method of manufacturing a semiconductor device according to claim 3, wherein when any one of the plasma impedance waveform and the reflected waveform exceeds the threshold value, it is determined that the plasma is abnormally discharged. The plasma etching apparatus includes a sequencer and a data logger,
4. The semiconductor device according to claim 3, wherein the plasma impedance waveform and the reflected waveform are transferred from the sequencer to the data logger, and the determination of abnormal discharge of the plasma is performed in real time by the data logger. Manufacturing method.   4. The method of manufacturing a semiconductor device according to claim 3, wherein the threshold value is set according to plasma etching conditions. The insulating film is formed so as to cover the wiring formed on the main surface of the semiconductor substrate,
The method of manufacturing a semiconductor device according to claim 3, wherein the opening exposes the wiring. A method for manufacturing a semiconductor device comprising the following steps:
(A) forming a gate insulating film, a silicon film and a metal film on the main surface of the semiconductor substrate;
(B) With respect to the plasma impedance waveform of the plasma etching apparatus and the reflected waveform of the high frequency power for plasma generation obtained by sampling for controlling the plasma processing, when the plasma rises, when the plasma is stable, when the plasma falls The plasma is sampled in a time division unit of 2 ms or less, and the plasma is monitored while monitoring abnormal discharge with thresholds set separately for each plasma rise time, plasma stable time, and plasma fall time. Patterning the gate insulating film, the silicon film and the metal film with an etching apparatus;

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