JP4797358B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a trench gate type semiconductor device in which a trench is formed on a silicon substrate and a field effect transistor is formed inside the trench.

  Although miniaturization is indispensable for realizing high integration and miniaturization of a semiconductor device, a U-shaped deep groove (trench) is dug in the surface of a silicon substrate, and a buried gate electrode is provided in the trench. A MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) having an element structure is known as an effective structure for realizing a short channel and high integration because the gate structure can be controlled in the depth direction.

FIG. 10 is a cross-sectional view of a conventional trench type power MOSFET.
A conventional trench type power MOSFET 800 includes an electric field relaxation region 802 formed mainly by epitaxial growth or the like on a silicon substrate 801, a diffusion layer (hereinafter referred to as a base region) 803 having a conductivity type opposite to the electric field relaxation region 802, an electric field. A diffusion layer (hereinafter referred to as a source region) 804 having the same conductivity type as that of relaxation region 802 is formed. A trench that penetrates the source region 804 and the base region 803 and reaches the electric field relaxation region 802 is formed, and a gate electrode 806 is embedded inside the trench with a gate insulating film 805 interposed therebetween.

  By forming the MOSFET in the trench in this way, when the transistor is turned on, the channel is formed in the vertical direction along the sidewall of the trench. Therefore, the channel length can be secured even when the width of the gate electrode 806, that is, the trench is reduced, and high integration can be achieved.

  High integration is possible by using the trench gate structure as described above, but etching damage occurs during trench etching for digging a groove, and the damage causes minute irregularities on the trench side wall and bottom surface. . If such minute surface irregularities are present at the interface between the region serving as the channel and the gate insulating film 805, the carrier mobility in the ON state of the MOSFET is lowered, and the performance is lowered such that the driving force of the MOSFET is lowered. In addition, the interface state density at the interface with the gate insulating film 805 increases, leading to a decrease in reliability of the gate insulating film 805, or the gate insulating film 805 is locally thinned to reduce the breakdown voltage.

Further, since the shape of the trench corner is rounded, there is a problem that electric field concentration at the corner tends to occur and the breakdown voltage of the trench gate is lowered.
Therefore, in order to remove the etching damage at the time of forming the trench, in the process after digging the trench, a method of slightly etching the inside of the trench by a method such as isotropic etching before forming the gate insulating film, or 1000 ° C. There is known a method of removing damage by rounding the corners of the trench corners by the above high-temperature oxidation and smoothing the inner walls of the trenches.

  However, isotropic etching and high-temperature oxidation processes performed to remove damage after trench etching are because the silicon on the inner wall of the trench is shaved. There was a drawback that the width would widen. Thus, isotropic etching or high-temperature oxidation as a removal of damage after trench etching leads to an increase in trench dimensions, which makes it difficult to miniaturize semiconductor elements and is an obstacle to achieving high integration. It has become.

  Therefore, hydrogen annealing treatment has been proposed as a method for removing surface irregularities due to etching damage on the inner wall of the trench without increasing the trench size after forming the trench (see, for example, Patent Document 1).

11 to 15 are cross-sectional views of the semiconductor device in each process when forming a trench gate in a conventional method for manufacturing a semiconductor device.
First, a silicon oxide film (SiO ₂ film) 812 is formed on the surface of the silicon substrate 811 (FIG. 11), and a portion to be trench-etched is opened by a photolithography technique (FIG. 12). Subsequently, a trench etching process is performed to form a trench 813 (FIG. 13). Next, a by-product 814 generated by etching remaining in the trench is removed with dilute hydrofluoric acid. Thereafter, the silicon oxide film 812 is removed with hydrofluoric acid. Then, annealing in a reducing atmosphere with hydrogen is performed to smooth the surface unevenness of the inner wall of the trench 813 by the migration effect on the silicon surface, and the upper corner portion 813a and the lower corner portion 813b are rounded. (FIG. 14) Etching damage can be removed without increasing the trench size. Thereafter, a gate insulating film 815 is formed, and the gate electrode 816 is buried in the trench 813 and etched back (FIG. 15).
JP 2003-229479 A

However, high temperature annealing in a reducing atmosphere with hydrogen has the following problems.
In order to actually cause migration of silicon atoms by hydrogen annealing, the surface of the silicon substrate must be silicon. Usually, a natural oxide film is formed on the surface of the silicon substrate. However, since the natural oxide film can be reduced and removed during this hydrogen annealing, migration of silicon atoms can be caused. However, if the thickness of the natural oxide film on the surface is not uniform, that is, if there is a locally thick natural oxide film, or if organic contamination is present, the organic contaminant must be removed. Reduction of the natural oxide film underneath occurs. For this reason, there is a time difference in the reduction of the natural oxide film within the hydrogen annealing treatment time, hindering migration, and the problem that the trench does not have the desired shape. Problem arises. If the annealing time is extended to sufficiently reduce the natural oxide film, it becomes difficult to control the trench shape to a desired shape.

  If there is even one location where shape anomalies or surface irregularities are not improved, the trench corner rounding and surface irregularity improvement effect expected in the hydrogen annealing process cannot be obtained, and the extreme shape When an abnormality occurs, a problem such as a decrease in yield also occurs.

  The present invention has been made in view of the above points, and is a semiconductor device capable of flattening surface unevenness due to etching damage on the inner wall of a trench and rounding corners of a trench corner without increasing the trench size. An object is to provide a manufacturing method.

  In the present invention, in order to solve the above problem, in the method of manufacturing a trench gate type semiconductor device, an ozone treatment step of forming an oxide film on the silicon substrate surface after the trench formation by ozone treatment, and after the ozone treatment step, And an annealing step for causing migration of silicon atoms after annealing in an atmosphere containing hydrogen and reducing and removing the oxide film on the surface of the silicon substrate. Is done.

  According to the above method, a highly uniform oxide film is formed by performing the ozone treatment process, and after the oxide film is reduced and removed by the next annealing process, migration of silicon atoms is caused. The surface unevenness of the inner wall of the trench is flattened without increasing the trench size, and the corner of the trench corner is rounded.

  In the present invention, a highly uniform oxide film is formed on the silicon substrate surface after the trench formation by the ozone treatment process before the annealing process, and the oxide film is reduced and removed by the next annealing process, and then silicon Since atomic migration occurs, the surface irregularities of the inner wall of the trench can be flattened without increasing the trench size, and the corners of the trench corners can be rounded.

  As a result, it is possible to avoid the thinning of the local gate insulating film in the trench, and to form a high-quality gate insulating film with a low interface state density, and the gate insulating film of the trench gate type semiconductor device It is possible to improve various electrical characteristics such as withstand voltage and reliability.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a flowchart showing a process flow of the method of manufacturing a semiconductor device according to the present embodiment, and particularly shows a process flow of forming a trench gate.

FIG. 2 is a configuration diagram of a processing apparatus that performs the processing of FIG.
First, the processing apparatus of FIG. 2 will be described.
The processing apparatus 100 is a vertical batch heat treatment apparatus.

A resistance heating heater (hereinafter simply referred to as a heater) 101 is for controlling the inside of the reaction tube 102 to a predetermined temperature. A thermocouple (not shown) is installed in the reaction tube 102 and is controlled by a control unit (not shown). In response to the signal, the temperature in the reaction tube 102, that is, the reaction chamber is accurately controlled. The reaction tube 102 is made of high-purity quartz, and is designed to have a shape and thickness that maintains sufficient strength even when the reaction tube 102 is evacuated, and is installed in the heater 101. An exhaust pipe 103 is connected to the reaction tube 102 via an exhaust port, and a valve 104 and a vacuum pump 105 are connected to the tip of the reaction pipe 102. Although not shown, a vacuum sensor and an N ₂ (nitrogen) ballast pipe for pressure adjustment are connected between the valve 104 and the vacuum pump 105, and a control signal is received from a control unit (not shown) in the reaction tube 102. The pressure is precisely controlled.

  In addition, a plurality of gas introduction pipes are connected to the opposite side of the exhaust port at the bottom of the reaction pipe 102. For example, an ozone supply pipe 106, a hydrogen supply pipe 107, an oxygen supply pipe 108, a nitrogen supply pipe 109, etc. are connected. Has been. An ozone generator 110 is connected to the upstream side of the ozone supply pipe 106. The ozone generator 110 generates ozone from oxygen supplied from the upstream side using plasma or the like as an excitation source, and supplies the ozone into the reaction tube 102 through the ozone supply tube 106. The other supply pipes supply oxygen and hydrogen as process gases, and also supply nitrogen for purging the inside of the furnace. In addition, a plurality of silicon substrates 112, which are objects to be processed, can be placed on a boat 111 made of high-purity quartz housed in the reaction tube 102 at a predetermined pitch (interval). Further, the boat 111 can be rotated by the rotation mechanism 113, and the uniformity in the surface of the silicon substrate 112 can be improved. The boat 111 can be moved up and down by the boat elevator 114. Normally, when the silicon substrate 112 is placed on the boat 111, the processing is performed with the boat 111 lowered from the reaction tube 102 downward. The reaction tube 102 and the supply tubes 106 to 109, the exhaust tube 103, the boat elevator 114, and the like are connected so as to keep airtightness.

  In the processing apparatus 100 of FIG. 2, the boat 111 is housed in the reaction tube 102, but an inner tube used in normal low pressure CVD (Chemical Vapor Deposition) is provided between the reaction tube 102 and the boat 111. May be arranged. In this case, the gas nozzle is disposed in the inner tube in which the boat 111 is accommodated, and the gas passes through the inner tube, exits to the external reaction tube 102, and is finally exhausted through the exhaust port.

  Further, in the processing apparatus 100 of FIG. 2, the gas flows from the lower side of the reaction tube 102, but may flow from the upper side (in this case, the inner tube is not necessarily required). A long nozzle with a structure extending to the top of the reaction tube 102 is required).

In the above description, the N ₂ ballast control is used as the pressure control method. However, for example, a combination valve described in Japanese Patent Laid-Open No. 2002-176043 (paragraph number [0046]) may be used. A method may be employed in which the pressure in the reaction tube 102 is controlled to a predetermined pressure by adjusting the degree of opening.

Next, a manufacturing method according to the present embodiment for manufacturing a trench type MOSFET will be described with reference to FIG.
FIG. 3 is a cross-sectional view of the semiconductor device before the trench gate is formed.

  As shown in this figure, an electric field relaxation region 202 mainly formed by epitaxial growth or the like on a silicon substrate 201, a base region 203 which is a diffusion layer of a conductivity type opposite to the electric field relaxation region 202, and the surface of the base region 203 A source region 204 which is a diffusion layer of the same conductivity type as that of the electric field relaxation region 202 is formed in a part thereof. Further, a silicon oxide film 205 is formed on the above structure, and a portion to be trench-etched is opened by a photolithography technique.

In the process of step S1 in FIG. 1, a trench etching process is performed to form a trench in the semiconductor device as shown in FIG.
FIG. 4 is a cross-sectional view of the semiconductor device after the trench etching process.

By trench etching, a trench 206 that penetrates the source region 204 and the base region 203 and reaches the electric field relaxation region 202 is formed.
In the process of step S2, a cleaning process is performed. Here, after by-products (SiO ₂ and SiO _x ) 207 generated in the trench 206 due to etching are removed with dilute hydrofluoric acid, wafer cleaning is performed. Wafer cleaning is RCA cleaning used in normal semiconductor cleaning (a cleaning method developed by RCA in the US that cleans wafers with chemicals such as ammonia / hydrogen peroxide, hydrochloric acid / hydrogen peroxide, and hydrofluoric acid). Is used. Thereafter, the silicon oxide film 205 is removed with hydrofluoric acid.

FIG. 5 is a cross-sectional view of the semiconductor device after the cleaning process.
The semiconductor device after the processing in step S2 is damaged by dry etching in the substrate, and the sidewall of the trench 206 also has a large surface roughness. Further, the corners of the trench 206 also have a square shape.

  The semiconductor device that has undergone such a process is loaded onto the boat 111 of the processing apparatus 100 as a silicon substrate 112 to be processed by the processing apparatus 100 shown in FIG. Subsequently, the boat 111 is raised by the boat elevator 114, loaded into the reaction tube 102, and the reaction chamber is sealed. At this time, the inside of the reaction tube 102 is controlled to 300 ° C. or less by the heater 101. The process up to this process is the loading process to the boat 111 (step S3).

  After the loading is completed, the pressure / temperature / gas flow rate adjusting step in step S4 is performed. Specifically, nitrogen is introduced for about 10 minutes after the reaction tube 102 is sealed, and the atmosphere entrained between the plurality of silicon substrates 112 as the boat 111 rises is replaced with nitrogen. When transferring the silicon substrate 112, the boat 111 may be loaded in a state in which a load lock chamber is provided and a nitrogen atmosphere is provided in advance. In that case, nitrogen may be introduced for about 5 minutes after loading the boat 111. Next, the valve 104 is opened, and the reaction chamber is evacuated. At this time, while supplying nitrogen at about 10 L / min, the gas in the reaction chamber is exhausted by the vacuum pump 105, and vacuum is applied until a predetermined pressure, for example, 1000 Pa (1 Pa (Pascal) = 0.005 Torr) or less. Continue pulling.

Next, the ozone treatment process of step S5 is performed. At this time, the nitrogen supply into the reaction tube 102 is stopped while maintaining the pressure at, for example, 1000 Pa, oxygen is supplied to the ozone generator 110 to generate ozone, and the ozone is introduced into the reaction tube 102. At this time, the ozone concentration is, for example, about 10 vol%, the supply amount is 10 L / min, and the ozone supply time is, for example, 20 minutes. For example, ozone introduced into the reaction chamber is heated to 300 ° C. and activated to generate oxygen atom radicals (O ^* ). By contacting the oxygen atom radicals with the substrate surface, organic substances adhering to the substrate surface are decomposed and removed, and a thin oxide film is formed on the surface of the silicon substrate 112. Since the oxide film thus formed is formed after the surface organic matter contamination is removed, the oxide film has a very uniform film thickness. The ozone supply time and supply amount are adjusted so that the thickness of the oxide film formed at this time is in the range of 0.8 to 1.5 nm.

FIG. 6 is a cross-sectional view of the semiconductor device after the ozone treatment.
As shown in the figure, an oxide film 208 having a very uniform film thickness of 0.8 to 1.5 nm is also formed on the substrate surface and inside the trench 206.

  The reason why the step of forming an oxide film by ozone treatment is performed at 300 ° C. or lower is as follows. During the ozone treatment, when heated to a predetermined temperature, ozone is activated and oxygen atom radicals which are active oxidizing species are generated, and organic contamination on the surface of the silicon substrate 112 is removed and an oxide film is formed. When the temperature is higher than 300 ° C., the presence or absence of organic contamination affects the uniformity of the thickness of the oxide film on the surface after the removal. This is because the portion where there is no organic matter has a longer oxidation time and becomes a thick oxide film. The temperature may be the same as or different from the temperature at the time of loading, but actually the same temperature is preferred. Although the temperature changes slightly during loading, extra time is required for stabilization due to changes in temperature conditions, resulting in reduced throughput. Because it is advantageous.

  The thickness of the oxide film formed by ozone treatment was set to 0.8 nm to 1.5 nm in terms of uniformity. The first factor is that the film thickness is within this level when organic substances are removed and oxidized, and this level of film thickness is excellent in terms of controllability at 300 ° C. Moreover, if it becomes thicker than this, the variation in the reduction effect at the time of the hydrogen annealing step described later is greatly affected.

  Next, the pressure / temperature / gas flow rate adjusting step of step S6 is performed. Following the step S5, the temperature in the reaction chamber is raised by heater control continuously. The temperature is raised to the temperature of the hydrogen annealing step for reducing the oxide film. The temperature rising rate at that time is around 100 ° C./min. Here, the temperature is raised to the hydrogen annealing temperature of 900 ° C. to 1050 ° C. (hereinafter referred to as 950 ° C.), which is the next step. At this time, the reaction chamber is evacuated while supplying nitrogen at about 5 L / min. After the temperature reaches the set temperature, the process proceeds to a hydrogen annealing process in which a subsequent oxide film is reduced through a temperature stabilization process.

  In the hydrogen annealing step (1) of step S7, after the temperature is sufficiently stabilized at 950 ° C. continuously after the step S6, the nitrogen supply is stopped and the reaction chamber is evacuated. After sufficiently evacuating, hydrogen is supplied and the following steps are performed in an inert gas atmosphere such as argon or helium containing 1% or more of hydrogen. The supply amount of hydrogen is, for example, 0.1 to 10 L / min, and the supply time is set in the range of 10 seconds to 5 minutes together with the hydrogen annealing step (2) in the next step S8. The pressure is controlled to 1 Torr to 760 Torr, for example. Here, due to the reduction effect of hydrogen, the thin oxide film formed by ozone treatment is reduced and removed, and the substrate surface becomes silicon (oxide film reduction process).

  Subsequently, in the hydrogen annealing step (2) of step S8, hydrogen is continuously supplied at a pressure of 0.1 to 10 L / min at 950 ° C. and a pressure of 1 Torr to 760 Torr following the previous step. During this hydrogen annealing, surface diffusion (migration) of silicon atoms occurs, the roughness of the sidewalls of the trench 206 is reduced and flattened, and the corners of the trench 206 are rounded.

FIG. 7 is a cross-sectional view of the semiconductor device after the hydrogen annealing step.
The oxide film formed by the ozone treatment is reduced and removed, and further migration occurs to flatten the inside of the trench 206 and round the corners.

  In the hydrogen annealing process of steps S7 and S8, the reason for setting the temperature to 900 to 1050 ° C., the pressure to 1 Torr to 760 Torr, and the time to 10 seconds to 5 minutes is as follows. First, the reason why the pressure is normal is that the etching effect of the oxide film is great. For example, Patent Document 1 describes that the etching rate is 1.4 nm for 200 Torr and 0.1 nm or less for 5 Torr. The reason why the upper temperature limit is set to 1050 ° C. is to prevent reverse taper from being formed in the trench 206 due to bowing (bow-shaped constricted side wall shape). If it becomes a bowing shape, a void (hole) will generate | occur | produce in the subsequent gate electrode embedding process. Even if the time for performing the hydrogen annealing is long, a bowing shape may be formed. Therefore, the time is desirably set in the range of 10 seconds to 5 minutes.

  Next, the process proceeds to the thermal oxidation process in step S9. In the thermal oxidation process, the process proceeds to a process of forming an oxide film continuously following the hydrogen annealing process (2) of step S8. Here, various oxidation methods can be used depending on the target gate insulating film thickness. For example, the reduced pressure oxidation method is used for a thin oxide film of 300 mm or less, and the pyrogenic oxidation method is used for a thick oxide film of more than 300 mm. As for the oxidation temperature, the same temperature as the hydrogen annealing step (2) in step S8 (here, 950 ° C.) is constant, and the temperature in the furnace is also constant. Is advantageous. However, the temperature may be further increased to oxidize at a higher temperature, or the temperature may be decreased to oxidize on the lower temperature side. Further, although pyrogenic oxidation is used, there is no problem even if an oxidation method such as a dry oxidation method or hydrochloric acid oxidation is used. In addition, after this thermal oxidation, a POA (Post Oxidation Anneal) process is also continuously performed.

FIG. 8 is a cross-sectional view of the semiconductor device after the thermal oxidation process.
A gate insulating film 209 is formed on the substrate surface by a thermal oxidation process. The interface between the gate insulating film 209 and the silicon on the inner wall of the trench 206 has a low interface state density because the inside of the trench 206 is sufficiently flattened by the hydrogen annealing step (2) in step S8 immediately before oxidation. A stable interface can be obtained, and channel mobility is not lowered even in a portion that becomes a channel of the MOSFET. Further, by rounding corners such as trench corners, local thinning of the gate insulating film 209 in the trench 206 can be avoided, so that local electric field concentration does not occur and a high interface state density is low. A quality gate insulating film 209 can be formed. Thereby, in the trench MOSFET, the reliability of the gate insulating film can be greatly improved.

After this thermal oxidation step (step S9), the process proceeds to the pressure / temperature / gas flow rate adjustment step of step S10.
In the pressure / temperature / gas flow rate adjusting step of step S10, the temperature is lowered to near the loading temperature (300 ° C.) and purged with nitrogen gas. Then, the process proceeds to a step of unloading the silicon substrate 112.

  In the step of unloading the silicon substrate 112 in step S11, the boat 111 is unloaded (lowered from the reaction tube 102), and the silicon substrate 112 is unloaded from the boat 111 and collected. Up to this point, a series of steps for forming a trench gate, which is a characteristic part of the method for manufacturing a semiconductor device of the present embodiment, has been described. The next step is a gate electrode formation step, which is the same as in the prior art and will not be described.

  Further, the thermal oxide film (the gate insulating film 209 described above) applied in the series of steps up to the thermal oxidation may be used as the sacrificial oxide film. That is, after the thermal oxidation and unloading, the oxide film is again removed with dilute hydrofluoric acid, and the oxide film that finally becomes the gate insulating film may be formed again from the same process (loading to the boat). Good.

  As described above, in the present embodiment, a thin uniform oxide film is formed by ozone treatment in a state where a silicon substrate is put in a reaction furnace after cleaning after trench etching, and the oxide film is reduced by hydrogen annealing, and further the substrate The surface is flattened at the atomic level by hydrogen annealing, the shape of the trench corner is rounded, and then the substrate surface is thermally oxidized to form an oxide film. This process is never taken out of the furnace, that is, it is not exposed to the atmosphere, and is continuously processed in the furnace, so that organic contamination adheres to the substrate surface, oxide film non-uniformity before reduction, etc. Since various problems can be avoided, it is a very excellent process.

  Next, in order to evaluate the breakdown voltage of the gate insulating film, a MOS capacitor was created in the same process as described above, and the results of investigation on the breakdown electric field of the formed 100 nm gate insulating film by the current-voltage characteristics are as follows. Show.

The trench has a width of 0.6 μm and a depth of 3 μm. Further, 160 MOS capacitors were formed on the wafer (corresponding to the silicon substrate 112 in FIG. 2).
FIG. 9 is a histogram of the breakdown voltage of the MOS capacitor formed on the wafer. FIG. 9A shows a case where a P-type substrate is used, and FIG. 9B shows a case where an N-type substrate is used.

The horizontal axis represents the breakdown electric field (MV / cm), and the vertical axis represents the number of MOS capacitors in one wafer indicating the breakdown electric field value.
In FIG. 9, data A is measured for a MOS capacitor created in the process of the method for manufacturing the semiconductor device of the present embodiment shown in FIG. In the case of data B, only the ozone treatment process is not performed in the process of FIG. 1, and in the data C, only the thermal oxidation process is performed without performing the ozone treatment process and the hydrogen annealing process (1) and (2) in the process of FIG. Is the case. These were measured for comparison with data A.

  As can be seen from this result, in the data C, the trench corner is not rounded at all, and the unevenness of the substrate surface due to the etching damage is not flattened, so that the breakdown electric field is small and the breakdown voltage is very low. . In the data B, the corner rounding effect by the hydrogen annealing process is exhibited, so that the breakdown voltage is improved as compared with the data C, but the breakdown voltage as a whole remains insufficient. On the other hand, in the data A of the MOS capacitor created by the process of the present embodiment, the pretreatment of the hydrogen annealing treatment is performed by ozone treatment, a thin and uniform oxide film is formed, and organic contamination is removed. Because it is processed continuously without being exposed to the atmosphere in the same furnace, the effect of hydrogen annealing is exhibited, the dielectric breakdown electric field is large, and the gate breakdown voltage is excellent. I found out.

As described above, according to the manufacturing method of the semiconductor device of the present embodiment, the corner rounding of the trench and the planarization at the atomic level of the surface are performed by the hydrogen annealing process, so that the local oxidation in the trench is performed. Thinning of the film can be avoided. Further, by making the SiO ₂ / Si interface an interface by thermal oxidation, the interface state density can be reduced, and various electrical characteristics such as breakdown voltage and reliability of the gate insulating film of the MOSFET can be improved. By performing ozone treatment as a pretreatment of this hydrogen annealing treatment, organic contamination can be removed and a thin oxide film can be formed uniformly, so that variations in film thickness in the hydrogen annealing treatment can be reduced. .

It is a flow which shows the flow of a process of the manufacturing method of the semiconductor device of this Embodiment, and has shown the flow of the process of forming a trench gate especially. It is a block diagram of the processing apparatus which performs the process of FIG. It is sectional drawing of the semiconductor device before forming a trench gate. It is sectional drawing of the semiconductor device after a trench etching process. It is sectional drawing of the semiconductor device after a washing process. It is sectional drawing of the semiconductor device after ozone treatment. It is sectional drawing of the semiconductor device after a hydrogen annealing process. It is sectional drawing of the semiconductor device after a thermal oxidation process. It is a histogram of the breakdown voltage of the MOS capacitor formed on a wafer, (A) is a figure which shows the case where a P-type board | substrate and (B) use an N-type board | substrate. It is sectional drawing of the conventional trench type power MOSFET. In the conventional manufacturing method of a semiconductor device, it is sectional drawing of the semiconductor device in each process at the time of forming a trench gate (the 1). In the conventional manufacturing method of a semiconductor device, it is sectional drawing of the semiconductor device in each process at the time of forming a trench gate (the 2). In the conventional manufacturing method of a semiconductor device, it is sectional drawing of the semiconductor device in each process at the time of forming a trench gate (the 3). In the conventional manufacturing method of a semiconductor device, it is sectional drawing of the semiconductor device in each process at the time of forming a trench gate (the 4). In the conventional manufacturing method of a semiconductor device, it is sectional drawing of the semiconductor device in each process at the time of forming a trench gate (the 5).

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Processing apparatus 101 Resistance heating heater 102 Reaction pipe 103 Exhaust pipe 104 Valve 105 Vacuum pump 106 Ozone supply pipe 107 Hydrogen supply pipe 108 Oxygen supply pipe 109 Nitrogen supply pipe 110 Ozone generator 111 Boat 112 Silicon substrate 113 Rotation mechanism 114 Boat elevator

Claims (7)

In the method of manufacturing a trench gate type semiconductor device,
An ozone treatment step of forming an oxide film on the surface of the silicon substrate after trench formation by ozone treatment;
After the ozone treatment step, annealing is performed in an atmosphere containing hydrogen, and after the oxide film on the surface of the silicon substrate is reduced and removed, an annealing step for causing migration of silicon atoms,
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the ozone treatment step is performed at a temperature at which ozone is activated to generate oxygen atom radicals.   The method of manufacturing a semiconductor device according to claim 2, wherein the temperature is 300 ° C. or less.   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the ozone treatment step, the thickness of the oxide film is formed in a range of 0.8 nm to 1.5 nm.   The annealing step is performed in an inert gas atmosphere containing 1% or more of hydrogen in a temperature range of 900 ° C. to 1050 ° C., a pressure range of 1 Torr to 760 Torr, and a time range of 10 seconds to 5 minutes. A method for manufacturing a semiconductor device according to claim 1.   2. The method of manufacturing a semiconductor device according to claim 1, wherein a gate insulating film forming step for forming a gate insulating film on the surface of the silicon substrate is performed after the annealing step. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the ozone treatment step, the annealing step, and the gate insulating film formation step are continuously performed in the same processing chamber without being exposed to the atmosphere. .

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