JP4806066B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine configured with a computer circuit, and more particularly, to a gaming machine capable of storing a trace of illegal modification of a gaming machine in a nonvolatile manner.

  A ball and ball game machine such as a pachinko machine has a symbol start port provided on the game board, a symbol display unit for displaying a series of symbol variation modes such as stopping a plurality of display symbols after varying a predetermined time, and an opening / closing plate It is configured with a grand prize opening that opens and closes. When the detection switch provided at the symbol start port detects the passing of the game ball, the game ball is in a winning state and the symbol display unit changes the display symbol for a predetermined time. Thereafter, when the symbol stops in a predetermined manner such as 7-7-7, a big hit state is established, and the big winning opening is repeatedly opened to generate a profit state advantageous to the player.

  Whether or not to enter the big hit state is actually determined in advance by random lottery based on, for example, a random value at the time of winning when the game ball passes through the symbol start opening. In other words, whether or not a profit state occurs for a player is originally determined fairly by a lottery process using a random value. However, there have been reports of illegal activists trying to obtain a large number of prize balls by launching illegal control programs. Therefore, each gaming machine is equipped with various security circuits. When a ROM for storing a control program or a main circuit board is inserted or removed, an alarm sound or the like sounds.

JP 2006-059138 A JP 2006-017908 A JP 2005-242081 A JP 2005-221723 A

  However, if the gaming machine is turned off, the security circuit may no longer function and illegal actions may not be detected. In particular, after the game hall is closed, all power supplies are shut down, making the security circuit infamous. In addition, if an illegal act is detected, if the time and number of times can be stored in a nonvolatile manner, the illegal act can be pursued regardless of the subsequent power-off of the gaming machine, and the same act can be reoccurred. It can be effectively prevented.

  Here, it is conceivable to use electronic paper, and various proposals have been made regarding electronic paper (Patent Documents 1 to 4), but none of them solves problems unique to gaming machines.

  The present invention has been made on the basis of such circumstances, and an object thereof is to provide a gaming machine that can monitor illegal activities regardless of whether the power is turned off. It is another object of the present invention to provide a gaming machine that can be stored in a nonvolatile manner so that the time and number of times can be specified when an illegal act is detected.

In order to achieve the above object, the present invention determines whether or not to generate a profit state advantageous to the player by a lottery determination resulting from the occurrence of a predetermined detection state related to the operation of the player. A gaming machine configured to maintain power supply of a backup power source to a predetermined electronic element even after the power supply voltage to the gaming machine is cut off. A storage display element that stores display contents in a nonvolatile manner, a nonvolatile storage unit that stores the display contents as character data of a plurality of groups, and an irregular count clock, A counting unit for identifying any one group, a writing unit for reading the group of data identified by the counting unit from the storage unit, supplying the stored data to the storage display element, and the backup power source An abnormality detection unit that monitors a power supply state and detects a change in the power supply state, and the counting unit and the writing unit operate in response to a change in the power supply state detected by the abnormality detection unit. The timing unit is initially set to specify character data in an initial state when the power reset signal is output.

  In the above invention, examples of the gaming machine are preferably a ball game machine and a slot machine.

  According to the present invention described above, it is possible to always monitor illegal activities regardless of whether the power is turned off or not. Further, even when an illegal act is detected, it can be stored in a nonvolatile manner so that the time and number of times can be specified.

It is a perspective view of the pachinko machine shown in an example. This is an example of a power line of a pachinko machine. It is the front view which illustrated in detail the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. A part of internal circuit of a power supply board is illustrated. It is a circuit diagram which shows the remaining part of the internal circuit of a power supply board, and shows the connection relation with a main control board. 1 is a circuit diagram illustrating a first embodiment of a detection and storage circuit for fraudulent activity. FIG. It is a circuit diagram which illustrates the internal structure of electronic paper. It is a circuit diagram which shows the 2nd Example of the detection preservation | save circuit of fraud. It is a circuit diagram which shows 3rd Example of the detection preservation | save circuit of fraud. It is a circuit diagram which shows the 4th Example of the detection preservation | save circuit of fraud.

  Hereinafter, the embodiment of the present invention will be described in detail based on the ball game machine according to the embodiment. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. As shown in FIG. 2, in the game hall, a large number of pachinko machines GM are continuously arranged on the island structure STR, and the AC power supply AC100V of the game hall is stepped down to 24V AC by the island structure STR. It is supplied to the machine GM ... GM. In the embodiment shown in FIG. 7, each gaming machine GM is provided with a power switch SW. However, in the embodiments shown in FIGS. 9 to 11, the power switch SW for each gaming machine can be omitted, and the power supply may be turned on / off all at once.

  The pachinko machine GM shown in FIG. 1 has a rectangular frame-shaped wooden outer frame 1 that is detachably attached to the island structure STR and a hinge 2 that is fixedly attached to the outer frame 1 before being pivotably mounted. It consists of a frame 3. A game board 5 is detachably attached to the front frame 3 from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be freely opened and closed.

  An electronic paper 72 for displaying a history of illegal activities in a non-volatile manner is disposed at the upper left part of the glass door 6. However, while the game hall is in operation, the display lamps arranged around the electronic paper 72 are lit up in a flashy manner, so that the display content of the electronic paper 72 can hardly be recognized by anyone other than the familiar hall staff. On the other hand, the display content of the electronic paper 72 can be easily recognized in a state in which the power supply to the game hall is shut off, such as after the game hall is closed or before the game starts.

  However, the arrangement position of the electronic paper is not particularly limited. Rather, it is also preferable to install the electronic paper at a position where it cannot be viewed from the front of the gaming machine. For example, it is a predetermined part on the back side of the gaming machine, and typically, it is disposed inside the power supply board case or the like.

  An upper plate 8 for storing game balls for launch is mounted on the front plate 7, and a lower plate 9 for storing game balls overflowing from or extracted from the upper plate 8 and a launch handle 10 are mounted at the bottom of the front frame 4. And are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 3, the game board 5 is provided with a guide rail 13 formed of a metal outer rail and an inner rail in an annular shape, and a liquid crystal color display DISP is provided at the approximate center of the game area 5a inside. Has been placed. In addition, at a suitable place in the game area 5a, a symbol starting port 15, a big winning port 16, a plurality of normal winning ports 17 (four on the right and left sides of the big winning port 16), and a gate 18 serving as two passing ports are arranged. Has been. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  The liquid crystal display DISP is a device that variably displays a specific symbol related to a big hit state and displays a background image and various characters in an animated manner. This liquid crystal display DISP has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. The special symbol display portions Da to Dc execute a reach effect that expects a big hit state to be invited, and the special symbol display portions Da to Dc and the surroundings perform a notice effect that informs the result of the determination indefinitely. The

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the displayed normal symbol fluctuates for a predetermined time and is extracted at the time when the game ball passes through the gate 18. The stop symbol determined by the random number for lottery is displayed and stopped.

  For example, the symbol start opening 15 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws 15a. When the stop symbol after the fluctuation of the normal symbol display unit 19 displays a winning symbol, the symbol start port 15 is opened and closed. The claw 15a is opened for a predetermined time. When a game ball wins the symbol start port 15, the display symbols of the special symbol display portions Da to Dc change for a predetermined time and are determined based on the lottery result corresponding to the winning timing of the game ball to the symbol start port 15. Stop at the stop symbol. In addition, in special symbol display parts Da-Dc and its circumference, a notice effect may be performed between a series of symbol effects.

  The big winning opening 16 is controlled to open and close by, for example, an opening / closing plate 16a that can be opened forward. When the stop symbol after the symbol change of the special symbol display portions Da to Dc is a big hit symbol such as “777”, the “big hit” Is started, and the opening / closing plate 16a is opened. A winning area 16 b is provided inside the big winning opening 16.

  After the opening / closing plate 16a of the big prize opening 16 is opened, the opening / closing plate 16a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. In such an operation, the special game is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol of the special symbols, a privilege that the game after the end of the special game is in a high probability state is given. Usually, the big hit by this specific design is called “probable big hit”.

  FIG. 4 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the operations described above. Broken lines in the figure mainly indicate DC voltage lines.

  As shown in FIG. 4, this pachinko machine GM receives AC 24V, outputs various DC voltages (5V, 12V, 32V, BU) and outputs a system reset signal SYS when power is turned on, and a game operation The main control board 21 that centrally controls the effect, the effect control board 22 that executes the lamp effect and the sound effect based on the control command CMD received from the main control board 21, and the signal received from the effect control board 22 to each part The effect interface board 23 to be transmitted, the liquid crystal control board 24 for driving the liquid crystal display DISP based on the control command CMD ′ received from the effect interface board 23, and the payout motor based on the control command CMD ″ received from the main control board 21 A payout control board 25 that controls M to pay out a game ball, and a game in response to a player's operation It is organized around a firing control board 26 of firing.

  Here, the main control board 21, the effect control board 22, the liquid crystal control board 24, and the payout control board 25 are each mounted with a computer circuit including a one-chip microcomputer. Therefore, the functions mounted on the main control board 21, the production control board 22, the liquid crystal control board 24, and the payout control board 25 and the operations realized by the circuits are functionally named. Unit 21, effect control unit 22, liquid crystal control unit 24, and payout control unit 25. All or part of the effect control unit 22, the liquid crystal control unit 24, and the payout control unit 25 are sub-control units.

  5 and 6 are block diagrams showing the internal configuration of the power supply board 20. The power supply substrate 20 includes three full-wave rectifier circuits 40 to 42 that convert AC 24 V into pulsating voltage (DC 24 V), smoothing circuits 43 a to 43 d that smooth the output voltages of the full-wave rectifier circuits 40 and 41, and three terminals Stabilized power supply circuits 44a to 44c such as a regulator, a backup power supply circuit 45 that maintains a DC voltage of 5V even after the power is shut off, and the output of the full-wave rectifier circuit 40 are short-circuited when the DC output voltage (12V, 5V) rises abnormally. Forcibly shut-off circuit 46, a power reset circuit 48 using a dedicated IC 60, a detection and storage circuit 49 for illegal activities using electronic paper 72, and the like.

  The stabilized power supply circuits 44a to 44c are circuits that output DC voltages 5V, 12V, and 12V, respectively, and a power storage unit using a capacitor and a high-pass filter unit for noise suppression are provided on the output side. In this embodiment, the same DC voltage value DC12V is generated by two systems of circuits, one of which is supplied to the main control board 21 and the payout control board 25, and the other via the power relay board 30. This is supplied to the production interface board 23 and the liquid crystal control board 24 (see FIG. 4). This prevents high-frequency noise on the effect control board 22 side from being transmitted to the main control board 21 and the payout control board 25 through the power supply line.

  The backup power supply circuit 45 is composed of a diode and a large-capacity capacitor, and a DC5V backup power supply BU, which is the output of the backup power supply circuit 45, is supplied to the main control board 21 and the payout control board 25. The backup power BU is supplied to a RAM built in the one-chip microcomputer of each control board 21 and 25 so that the stored contents of the RAM are maintained even when the power is cut off.

  The forced cutoff circuit 46 is configured by supplying two systems of direct current 12V and direct current 5V to an abnormal voltage detection unit composed of a current limiting resistor, a diode, and a Zener diode. When each voltage supplied to the abnormal voltage detection unit exceeds the reverse voltage of each chain diode and charges the capacitor to a predetermined level or more, the thyristor is energized and the pulsating voltage DC24V is short-circuited. . As a result, the energization of the main control board 21 and the payout control board 25 and the DC voltage 5V passing through the power relay board 30 are cut off at the same time, so that abnormal operation in each control board is avoided.

  As shown in the upper left column of FIG. 6, the power reset circuit 48 is mainly configured by a system reset IC 60, an input prohibition circuit 61, and an output circuit 62 configured by a Schmitt trigger. The system reset IC 60 is a dedicated IC that automatically generates a system reset signal (power reset signal) SYS when the power is turned on and a power failure signal ABN when the voltage drops. For example, M5297P (RENESAS) is used. The

When the value of the pulsating voltage DC24V supplied to the AC input terminal of the system reset IC 60 falls below the monitoring level for the monitoring time T _OFF2 or more, the abnormal signal ABN operates to drop to the L level (FIG. 6 ( c)). Here, the monitoring time T _OFF2 is proportional to the product of the capacitor C2 and the resistor R2, but in this embodiment, the monitoring time T _OFF2 is designed to be about ₃₅ mS. Therefore, if the AC24V cutoff state recovers in less than 1 to 2 cycles (16 to 33 mS at 60 Hz), the power supply abnormality signal ABN is not output. By such an operation for measures against instantaneous interruption, useless output operation of the system reset signal SYS in a state where the DC voltage (12V, 5V) is maintained is avoided.

As shown in FIG. 6C, the system reset IC 60 is configured such that the system reset signal SYS falls to the L level after a predetermined time (T _D + T _OFF3 ) has elapsed since the power supply abnormality signal ABN falls. ing. Here, the drop delay time T _OFF3 is proportional to the product of the capacitor C3 and the resistor R3. In this embodiment, the predetermined delay time (T _D + T _OFF3 ) is used to control the main control unit 21 and the payout control. The highest priority interrupt processing (non maskable interrupt) in the unit 25 is finished. Therefore, in the main control unit 21 and the payout control unit 25, each CPU core is reset by the system reset signal SYS after necessary data is saved in the RAM area. The data saved in the RAM area is maintained for at least several days by the backup power supply BU.

As shown in FIG. 6B, in this system reset IC60, when the AC input voltage AC24V is applied and the pulsating voltage DC24V is supplied to the AC input terminal of the system reset IC60, after the first delay time _TON4 . The power supply abnormality signal ABN rises, and the system reset signal SYS rises after the second delay time _TON5 . Here, the delay time _{T ON5} and the delay time _{T ON4,} respectively, is proportional to the product of the capacitor C4, C5 and the resistor R4, R5, in the present embodiment, _T ON5 _{-T ON4} the CPU can not operate normally During this time period, the watchdog timer 53 of the main control unit 21 is automatically cleared by the logic circuits 51 and 52.

This point will be described with reference to the main control board 21 shown in the right column of FIG. As shown, the main control unit 21 includes a delay circuit 50, and 2 ^N-ary counter 51, an OR gate 52, and watchdog timer 53 is cleared processed is provided in the differential pulse of the output signal of the OR gate 52 ing. The system reset signal SYS generated by the power supply board 20 is supplied to the clear terminal CLR of the counter 51 via the delay circuit 50, while the system clock Φ is supplied to the clock terminal CLK of the counter 51. Therefore, during the period of the delay time _TON5 until the system reset signal SYS rises, the 2 ^N- ary counter 51 can count up, and the differential pulse of the count-up signal S1 becomes the clear signal WD of the watchdog timer 53. Will function as. Therefore, trouble that the watchdog timer 53 is in a free-running state and resets the CPU during a time period when the CPU of the main control unit 21 does not function is avoided.

  Thus, if the count-up signal S1 prohibits the watchdog timer 53 from entering the free-running state, the system reset signal SYS will eventually rise (see FIG. 6B), and thereafter the counter The counting operation of 51 is prohibited. However, thereafter, since the CPU periodically outputs the clear pulse S2, the self-running state of the watchdog timer 53 is continuously prohibited by the clear pulse S2. However, when the clear pulse S2 is interrupted due to a program runaway state or the like and the watchdog timer 53 is in a free-running state, the reset signal XURST is output and the CPU of the main control unit 21 is reset.

  On the other hand, when the power is turned on, the system reset signal SYS is delayed by the delay circuit 50 and becomes the reset signal XSRST, so that the CPU of the main control unit 21 is reset by the supply of the reset signal XSRST. Thus, in this embodiment, the CPU is reset by the XURST signal or the XSRST signal. As shown in the figure, the reset signal XURST is also supplied to the power supply board 20, and the number of abnormal resets of the CPU is recorded in the electronic paper 72 in the embodiment of FIG.

  Now, returning to the upper left column of FIG. 6A, the description of the power reset circuit 48 of the power supply board 20 will be continued. The input prohibition circuit 61 of the power reset circuit 48 is mainly composed of two NOR gates and a switching transistor Q. Only when the system reset signal SYS is at the H level and the power supply abnormality signal ABN is at the L level, the two NOR gates output a signal at the H level to turn on the transistor Q.

The time zone of the power supply abnormality signal ABN = L and the system reset signal SYS = H is a time zone of T _D + T _OFF3 at the time of voltage drop, as shown in FIG. In this embodiment, in this transient state, the supply of the pulsating voltage DC24V to the AC input terminal of the system reset IC 60 is cut off by the ON operation of the transistor Q. Therefore, for example, an unstable signal or an unreasonable signal is output from the system reset IC 60 even when the AC input voltage AC24V is at a normal level but for some reason, only when the DC voltage 5V is cut off or dropped. This prevents the possibility of malfunction and prevents abnormal operation on each control board.

  Further, even when the power supply is cut off when the AC input voltage AC24V drops, abnormal operation of each control board is prevented. Therefore, even in the control boards 21 and 25 that execute data saving processing when the voltage drops, normal NMI Operation is guaranteed.

  Next, the illegal action detection and storage circuit 49 will be described with reference to FIG. The detection storage circuit 49 includes a power supply circuit 70 dedicated to the circuit, an extraction circuit 71 for the power supply frequency F, an electronic paper 72 that is a nonvolatile storage element, a writing circuit 73 for the electronic paper 72, and an electronic paper 72. The character ROM 74 for storing the display data, the address section 75 for generating the address signal of the character ROM 74, and the reset circuit 76 for returning the display content of the electronic paper 72 to the initial state.

  The power supply circuit 70 is a part that receives an AC power supply (AC24V) from the upstream side of the power switch SW of the gaming machine and generates a DC power supply voltage of each element constituting the detection storage circuit 49. Therefore, for example, even if an illegal person turns off the power switch SW of the gaming machine and replaces the circuit board, the detection storage circuit 49 continues to operate normally. The power supply circuit 70 includes a full-wave rectifier circuit, a smoothing capacitor, and a three-terminal regulator.

  The power supply frequency extraction circuit 71 includes a detection transformer 80 disposed on the upstream side of the power supply circuit 70 and a saturation type amplifier 81. Then, the amplifier 81 operates based on the secondary side AC voltage of the detection transformer 80 to generate a time pulse Φ corresponding to the power supply frequency F. The power supply frequency F is 50 Hz or 60 Hz depending on the region. In any case, the power frequency F is accurately calibrated by the electric power company, and thus exhibits sufficient practicality as a time measuring pulse.

  As long as the electronic paper 72 has a non-volatile memory display function, the display method is electrophoretic display (Electro-Phoretic Display), electrochromic display (ECD), twist ball display (Twist-). Various types such as Ball Display) can be used. However, in this embodiment, an electrophoretic electronic paper is used.

  As shown in FIG. 8, the electronic paper 72 is formed by arranging 8 × 8 pixels in a matrix. Each pixel includes an electrophoretic element C1, a thin film transistor (TFT) Tr that drives the electrophoretic element C1, and a capacitive element C2 that maintains the electric polarization state of the dispersion in the electrophoretic element. ing. In FIG. 8, an electrostatic capacity C1 indicates an equivalent capacity of the electrophoretic element.

  As illustrated, the source terminal of the thin film transistor Tr is connected to the drive lines L1 to L8, and the gate terminal is connected to the data lines R1 to R8. The drain terminal is connected to the electrophoretic element C1 and the capacitive element C2. A predetermined potential is commonly applied to the terminals of the electrophoretic element C1. The terminal of the capacitive element C2 is connected to the ground line GND.

  In the circuit configuration of FIG. 8, when the drive lines L1 to L8 are selectively driven and the data on the data lines R1 to R8 are changed in synchronization therewith, the 8 × 8 electrophoretic elements C1 are appropriately replaced with two. As a result, the dot pattern of 8 × 8 pixels can be formed in a nonvolatile manner.

  In this embodiment, 8 × 8 pixels are used to display any numerical value from hexadecimal 00 to FF, and this numerical value indicates the elapsed time from the start of business in the game hall. Yes. In this embodiment, the elapsed time is counted every 18.2 minutes (60 Hz region) or every 21.8 minutes (50 Hz region) from the viewpoint of simplicity in circuit configuration. Will be described later).

  The writing circuit 73 to the electronic paper 72 receives the binary data and converts it into alternative 8-bit drive data, and supplies the converted 8-bit drive data to the drive lines L1 to L8. A first driver 83; a second driver 84 for supplying dot data read from the character ROM 74 to the data lines R1 to R8; and a signal generator for generating an operation control signal CTL for the first driver 83 and the second driver 84. And 85.

  The signal generation unit 85 includes an OR gate G1 and a one-shot multivibrator MT. Although not particularly limited, in this embodiment, a re-triggerable multivibrator that can be re-triggered is used.

  As illustrated, the OR gate G1 is supplied with a power reset signal RST output from the reset circuit 76 and a system reset signal SYS output from the power reset circuit 48 of FIG. When the power reset signal RST or the system reset signal SYS changes to H level and the output of the OR gate G1 rises, the one-shot multivibrator MT functions in synchronization with the rising edge. The shot multivibrator MT outputs an active operation control signal CTL having an H level for a predetermined time.

  Both the first driver 83 and the second driver 84 have an operation permission terminal CE, and the drive operation to the electronic paper 72 is executed only when the H level operation control signal CTL is received here. It has become. Information once written in the electronic paper 72 is held regardless of the presence or absence of the power supply voltage Vcc until another information is overwritten.

  The character ROM 74 is a nonvolatile memory having at least 9-bit address terminals A0 to A8 and 8-bit data terminals D0 to D7. The chip select terminal CS, the output enable terminal OE, etc. are all fixed in an active state, and are configured so that data can always be read out.

  The data stored in advance in the character ROM 74 is divided every 8th address. For example, dot data corresponding to “00” is stored at addresses 0 to 7, and “01” is stored at addresses 8 to 15. Dot data to be stored is stored. The same applies to the following. The stored dot data continues with “02” and “03” every 8th address, and dot data corresponding to the hexadecimal number “FF” is stored at the last 8th address.

  The address unit 75 includes a first counter 86 having a 16-bit length that receives a time pulse (power pulse) Φ of 50 Hz or 60 Hz at the clock terminal CK, and a 6-bit length that receives the most significant digit MSB of the first counter 86 at the clock terminal CK. 2 counter 87 and a 3 bit length third counter 88 which receives a clock pulse Φ at a clock terminal CK. The first counter 86 to the third counter 88 are all simple ripple counters. Therefore, the first counter 86 is “65536 base counter”, the second counter 87 is “64 base counter”, and the third counter 88 is “ It functions as an “octal counter”.

  Here, since the frequency F of the time measuring pulse Φ is approximately 60 Hz or 50 Hz, the output of the second counter 87 is updated every 65536 / F (= 18.2 minutes or 21.8 minutes). On the other hand, the output of the third counter 88 is updated every 1 / F (= 16.7 msec or 20 msec). Outputs CT0 to CT2 of the third counter 88 are connected to address terminals A0 to A2 of the character ROM 74, and outputs CT0 to CT5 of the second counter 87 are connected to address terminals A3 to A8 of the character ROM 74.

  Therefore, 8-byte (8 × 8 bit) dot data read from the character ROM 74 is updated every 18.2 minutes or 21.8 minutes. For example, in the region where the power supply frequency is 60 Hz, if this game machine is 182 minutes after the start of operation (= 18.2 × 10 = approximately 3 hours later), the binary number [001010000] address of the character ROM 74 will be [001010111]. Address data] is repeatedly read out at a rate of 60 times per second. If the operation control signal CTL is at the H level at this time, the electronic paper 72 displays a hexadecimal number “0A” indicating that 10 unit hours have elapsed since the start of business.

  The reset circuit 76 is configured by connecting a parallel circuit of a clear switch CL and an electrolytic capacitor C and a parallel circuit of a resistor R and a diode D to which the power supply voltage Vcc of the dedicated power supply circuit 70 is supplied. . For this reason, the voltage across the capacitor C rises to the H level after a predetermined time at the start of operation of the game hall into which AC 24 V is input, and then rises to the H level, and the power reset signal RST is output from the capacitor C.

  Since the power reset signal RST is supplied to the clear terminal CLR of the second counter 87, the output of the second counter 87 is cleared to zero and becomes 000000B when the game hall starts business. B is a subscript meaning a binary number. The power reset signal RST is supplied to the OR gate G1, and when the game hall starts business, the one-shot multivibrator MT outputs an operation control signal CTL that is active for one pulse. As described above, since the second counter 87 outputs 000000B at this time, in this embodiment, “00” is displayed on the electronic paper 72 when the game hall starts business.

  Thus, in this embodiment, the display content of the electronic paper 72 is automatically cleared when the game hall starts business. However, when an attendant finds an illegal game during business hours and takes an appropriate action, the user may want to clear the display content of the electronic paper 72 again. Therefore, in this embodiment, a clear switch CL connected in parallel to the capacitor C is connected. The clear switch CL can be operated only by a dedicated key held only by the hall staff. When the dedicated key is operated, the clear terminal CLR of the second counter 87 becomes L level for a moment and the output of the OR gate G1 rises from L level to H level. Therefore, the active operation control signal CTL is output from the one-shot multivibrator MT, and the display content of the electronic paper 72 returns to “00”.

  Next, the operation contents of the illegal action detection display circuit 49 shown in FIG. Since the power switch SW of each gaming machine is normally maintained in the ON state, all the gaming machines are powered on at the same time when the game hall starts business. Then, the reset circuit 76 functions, the power reset signal RST is output, and the second counter 75 is cleared to zero. Further, in response to the rise of the power reset signal RST, an active operation control signal CTL is output and characters “00” are displayed on the electronic paper 72. These points are as described above.

  By the way, when the power is turned on, the system reset signal SYS is also output from the power reset circuit 48 shown in FIG. 6, and the system reset signal SYS is applied to the OR gate G1. However, even if the rising timing of either the system reset signal SYS or the power supply reset signal RST is delayed, only a wide active operation control signal CTL is output from the retriggerable one-shot multivibrator MT, causing a problem. Absent.

  Thereafter, the power switch SW is not operated until the end of business. Therefore, the power reset signal RST does not rise for the system reset signal SYS. For this reason, the display content of the electronic paper also remains “00”.

  However, for example, there is a possibility that an illegal person turns off the power switch SW in order to replace the original circuit board with an unauthorized circuit board. The purpose of turning off the power switch SW in this way is to avoid the operation of a security circuit (not shown) in the game and the generation of an alarm sound or the like. In other words, if the original circuit board is removed while the power is on, the security circuit will function, so illegal actors will shut off the power and destroy the security circuit function until the illegal circuit board is replaced. is there.

  When such an illegal action is executed, in this embodiment, when the power switch SW is subsequently turned on, a system reset signal SYS output in response thereto is added to the OR gate G1. Then, an active operation control signal CTL is output from the one-shot multivibrator MT.

  On the other hand, all of the power supply circuit 70, the extraction circuit 71, and the address unit 75 of this embodiment are operating normally even when the power switch SW is turned off and on. Therefore, the output value of the second counter 87 indicates a value of N = INT [T / 18.2] in the 60 Hz region according to the elapsed time T (minutes) from the start of operation of the game hall. . “INT” means that the numerical value in parentheses is converted into an integer.

  Since the output value of the second counter 87 is N, 8-byte dot data in the Nth group is read from the character ROM 74. Therefore, on the basis of the active operation control signal CTL, the electronic paper 72 displays the hexadecimal number “**”, which means the decimal number N, and is stored in a nonvolatile manner.

  Therefore, even if the illegal act cannot be detected immediately, the attendant may display the fact of the illegal act on the electronic paper 72 during the subsequent game (the player must have won a lot of prize balls at this time). It can be detected from the content. In addition, since the time of illegal activities can be substantially specified according to the display content of the electronic paper 72, for example, it is also possible to specify the escaped offender and their accomplices, for example, based on the stored video of the security camera.

  Even if the clerk reads out the display contents of the electronic paper 72 during business hours, the display contents of the electronic paper 72 remain after the game hall is closed and after the power supply voltage is cut off. It is possible to specify the offense time of illegal activities at any time until the power is turned on at the start of business. When the power is turned on at the start of business the next day, the display content of the electronic paper 72 is cleared to zero by the power reset signal RST and becomes “00”.

  The first embodiment shown in FIG. 7 has been described above, but various modifications can be made. FIG. 9 is a circuit diagram showing the second embodiment. Here, the crime time is not specified, but the number of crimes is specified and displayed on the electronic paper 72.

  That is, the CPU reset signal XURST (see FIG. 6) transmitted from the main control unit 21 is supplied to the input terminal of the OR gate G1 in FIG. 9 instead of the power reset signal RST. Further, the output of the OR gate G1 is supplied to the clock terminal CK of the second counter 87 without using the time clock (power supply clock) Φ. The third counter 88 is circulated by the output pulse of the self-excited oscillator OSC and repeatedly outputs 000B to 111B.

  Since the second embodiment is configured as described above, after the second counter 87 is cleared by the power reset signal RST at the start of operation of the game hall, the number of reset signals XURST and system reset signals SYS The second counter 87 is counted up. Therefore, if an illegal person turns OFF / ON the power switch SW or intentionally runs the control program of the game machine and causes the CPU to be forcibly reset, the total number of crimes is the electronic paper 72. Will be recorded. The CPU is forcibly reset in order to illegally return the jackpot lottery counter to the initial state. For example, if a high-voltage discharge pulse is generated near the gaming machine, the processing of the gaming machine becomes a runaway state. The CPU may be forcibly reset.

  Since the system reset signal SYS also rises from the L level to the H level when the game hall starts business, the second counter 87 may be counted up correspondingly. However, if the capacity of the capacitor C and the resistance value of the resistor R are increased and the L level period of the power supply reset signal RST is designed to be long, the count-up operation of the second counter 87 by the normal system reset signal SYS is avoided. be able to.

  Although FIG. 9 shows the power switch SW, it can be omitted. If the power switch SW is omitted, there is no point in counting the number of rising times of the system reset signal SYS, but the number of offenses can be specified by counting the number of rising times of the CPU reset signal XURST.

  FIG. 10 is a circuit diagram showing a third embodiment. The illegal action detection / save circuit 49 has a dedicated power supply circuit 70, electronic paper 72, a writing circuit 73 to the electronic paper 72, a character ROM 74, an address section 75 of the character ROM 74, and the electronic paper 72 in an initial state. The reset circuit 76 for returning to the center and the monitoring circuit 90 of the backup power supply BU are mainly configured. The backup power source BU is a power source that supplies a DC voltage (design value is 5 V) to the RAM of the one-chip microcomputer of the main control unit 21 or the payout control unit 22.

  The address unit 75 includes a self-excited oscillator OSC that generates a time clock Φ having a pulse period τ of about 10 minutes, a 6-bit second counter 87 that counts up in response to the time clock Φ, and a frequency 1 / τ of the time clock. A 3-bit third counter 88 is counted up in response to a higher frequency (N / τ) write pulse Φ ′. Although the self-excited oscillator OSC is used here, it is a matter of course that the power supply pulse may be divided to be a time clock as in the case of FIG.

  The monitoring circuit 90 of the backup power supply BU includes voltage dividing resistors R1 and R2, a chainer diode ZD that generates a reference voltage Vz, a current limiting resistor R3, and a comparator CP. Here, the voltage value Vcc of the backup power supply BU is designed to be 5 V in a no-load state, but when the power is supplied to the RAM of the one-chip microcomputer, the voltage value Vcc is slightly lowered.

  On the other hand, the reference voltage Vz corresponds to the voltage design value Vcc of the backup power supply and the voltage value Vcc−Δ of the backup power supply that has dropped slightly from now on, R2 × (Vcc−Δ) / (R1 + R2) <Vz <R2 × Vcc / (R1 + R2) is set. That is, during normal operation, the input voltage R2 × (Vcc−Δ) / (R1 + R2) at the non-inverting input terminal (+) of the comparator CP is slightly lower than the reference voltage Vz. Therefore, when the backup power supply BU is supplied to the one-chip microcomputer, the output voltage of the comparator CP becomes L level.

  By the way, regardless of whether or not the power switch SW is turned off, the illegal acter wants to replace the control program stored in the ROM of the main control unit 21 or the payout control unit 22 with an illegal program. However, in this embodiment, since the one-chip microcomputer is used for the main control unit 21 and the payout control unit 22 and only the ROM cannot be replaced, at least the one-chip microcomputer must be replaced.

  For this reason, the illegal person pulls out the regular one-chip microcomputer from the IC socket, or if this is impossible, the main control board 21 or the payout control board 22 is replaced. However, there is a moment when the voltage value of the backup power supply BU rises from (Vcc−Δ) to Vcc at any time of replacement.

  Then, since the voltage value of the backup power supply BU has increased to Vcc, the relationship of Vz <R2 × Vcc / (R1 + R2) is established, and the output voltage of the comparator CP changes to H level. In other words, the comparator CP detects the illegal act of replacing the illegal actor and changes the output value to the H level.

  Since the change in the output level of the comparator CP is supplied to the one-shot multivibrator MT via the OR gate G1, an active operation control signal CTL is output from the one-shot multivibrator MT, and is sent to the electronic paper 72. Write processing is executed.

  At the time of writing to the electronic paper 72, the character ROM 74 outputs dot data corresponding to the elapsed time since the power supply to the gaming machine is turned on, so that the crime time of the illegal act is determined by the data written on the electronic paper 72. It becomes possible to specify.

  FIG. 11 is a circuit diagram showing the fourth embodiment. The illegal action detection and storage circuit 49 is not provided with a dedicated power supply circuit, and each circuit element shown in the figure is operated only by the backup power supply BU. Therefore, the fourth embodiment can continue the illegal action monitoring operation regardless of whether or not the gaming machine is turned on, and the illegal action after all the power supply voltages of the gaming hall are cut off. Also works effectively.

  As shown, the detection storage circuit 49 includes an electronic paper 72, a writing circuit 73 to the electronic paper 72, a character ROM 74, an address section 75 of the character ROM 74, a reset circuit 76, and a monitoring circuit 90 for the backup power supply BU. It is structured around. As described above, the above-described units 73, 74, 75, 76, and 90 are driven by the backup power source BU and operate regardless of whether or not the game machine is powered on.

  The write circuit 73 includes a 3-8 decoder 82, a first driver 83, a second driver 84, and a signal generator 85 that generates an operation control signal CTL for the first driver 83 and the second driver 84. Yes.

  The signal generator 85 includes a one-shot multivibrator MT1 that receives the system reset signal SYS from the power reset circuit 48, a one-shot multivibrator MT2 that receives the output of the comparator CP, and an OR gate that receives the outputs of the two multivibrators MT1 and MT2. G1 and a delay circuit DLY that slightly delays the timing at which the operation control signal CTL is applied to the drivers 83 and 84.

  The address unit 75 is counted up by receiving a 6-bit second counter 87 that receives the one-shot multivibrator MT2 as a count clock, a self-excited oscillator OSC that determines the write speed of the driver 83, and an output clock of the self-excited oscillator OSC. It is composed of a 3-bit third counter 88.

  The clear circuit 76 includes an AND gate G2, a clear switch CL, and a pull-up resistor R. The clear switch CL is an ON / OFF switch that can be operated only by an attendant. This clear switch is normally in an OFF state, and is connected to the input terminal of the AND gate G2 while being pulled up. A system reset signal SYS output from the power reset circuit 48 (FIG. 6) is supplied to the other input terminal of the AND gate G2.

  On the other hand, the output of the AND gate G 2 is supplied to the clear terminal CLR of the second counter 87. For this reason, the second counter 87 is automatically cleared to zero when the power is turned on, and is also cleared to zero when the clerk operates the clear switch CL. Since the second counter is automatically cleared to zero when the power to each gaming machine is turned on, the operation of the clear switch CL is not particularly necessary. Therefore, the configuration of the clear switch CL and the AND gate G2 can be omitted. good.

  The monitoring circuit 90 of the backup power supply BU may have the same configuration as that of FIG. 10, but here, a configuration is adopted in which chattering noise superimposed on the power supply line LN of the backup power supply BU is detected. That is, if an illegal person pulls out a regular one-chip microcomputer from an IC socket or pulls out a harness of the main control board 21 or the payout control board 22, chattering noise is superimposed on the power line LN. Identify illegal activities by the presence of this chattering noise.

  In order to realize such an operation, the monitoring circuit 90 is mainly configured by a noise detection transformer 91, a noise amplification amplifier 92, a peak hold circuit 93 that detects and holds a noise peak value, and a comparator CP. . When no particular noise is superimposed on the power supply line LN, the voltage Vo across the resistor R4, which is the output of the peak hold circuit 93, is lower than the voltage Vz across the Zener diode ZD. Therefore, during normal operation, the output of the comparator CP is at L level.

  However, if chattering noise is superimposed on the power supply line LN due to an illegal action, the output Vo of the peak hold circuit 93 increases, and Vo> Vz is satisfied for a moment. Then, since the output of the comparator CP rises from the L level to the H level, the active operation control signal CTL is output from the second one-shot multivibrator MT2.

  Since this active operation control signal CTL is supplied to the clock terminal of the second counter 87, the second counter 87 is counted up and the dot data read from the character ROM is updated. Therefore, for example, the dot data corresponding to “00” is changed to dot data corresponding to “01”.

  The active operation control signal CTL output from the gate G1 is slightly delayed in the delay circuit DLY and supplied to the drivers 83 and 84. Therefore, for example, “01” corresponding to the updated dot data of the character ROM is written and displayed on the electronic paper 72.

  Therefore, even if the game hall is sneaked into the gaming hall at midnight and the gaming machine is illegally modified, the action will be stored in the electronic paper 72 in a non-volatile manner and will be grasped by the staff before the next business day starts. . When power is turned on to the gaming machine, the system reset signal SYS is output from the power reset circuit 48, so that the second counter 87 is cleared, and the active operation control signal from the first one-shot multivibrator MT1. CTL is output. As a result, the display content of the electronic paper returns to the initial state, for example, returns from “01” to “00”.

  As described above, the four examples of the illegal action detection and storage circuit have been specifically described. However, the internal configuration of each example can be applied to other examples. That is, the present invention can be realized by appropriately combining the internal circuits of the four embodiments.

  The description of the power supply board 20 is now complete. Finally, the main control board 21 will be described just in case with reference to FIG. As described above, the main control board 21 receives the power supply abnormality signal ABN output from the power supply board 20 in addition to the DC12V, DC32V, and backup power supply BU (= DC5V) (see FIG. 5) and the voltage drop. The system reset signal SYS output when the power is turned on is received (see FIG. 6). In the main control board 21, the received DC 12V is stepped down to DC 5V, and used as the power supply voltage of the computer circuit in the board. As described above, the main control unit 21 does not receive the DC power supply voltage 5V directly from the power supply board 20, and therefore may receive high-frequency noise from the other control boards 25, 23, 22, 24 through the DC5V power supply line. Is avoided.

  The main control board 21 is connected to the command relay board 29 and is connected to each game component of the game board 5 via the game board relay board 27. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. Note that the switch signal from the symbol start port 15 is received directly by the main control unit 21 without going through the game board relay board 27.

  The main control unit 21 transmits a control command CMD ″ to the payout control unit 25 in one direction, while the payout control unit 25 receives a prize ball count signal indicating a game ball payout operation and a payout operation. The status signal CON related to the abnormality is received, and the status signal CON includes, for example, a replenishment out signal, a payout shortage error signal, and a lower plate full signal.

GM gaming machine Φ timing clock 72 storage display element 74 storage section 75 timing section 73 writing section

Claims (3)

A gaming machine that determines whether or not a profit state advantageous to a player is generated by a lottery determination resulting from the occurrence of a predetermined detection state related to the player's movement, wherein a power supply voltage to the gaming machine Is configured so that the power supply of the backup power source is maintained for a predetermined electronic element even after the power is interrupted,
A storage display element having a plurality of pixels and storing its display content in a nonvolatile manner;
For the display content, a non-volatile storage unit that stores this as a plurality of groups of character data;
A counting unit that receives an irregular counting clock and identifies one group of the plurality of groups of data;
A writing unit that reads a group of data specified by the counting unit from the storage unit, supplies the data to the storage display element, and stores the data.
An abnormality detection unit that monitors a power supply state from the backup power source and detects a change in the power supply state, and
The counting unit and the writing unit are configured to operate in response to detection of a change in power supply state by the abnormality detection unit,
The gaming machine is initially set so as to specify character data in an initial state when the power reset signal is output .   The gaming machine according to claim 1, wherein the storage display element, the storage unit, the counting unit, the writing unit, and the abnormality detection unit are operated by the backup power source. The writing unit, gaming machine according to claim 1 or 2 is controlled to a predetermined write pulse running write operation.

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