JP4812186B2 - Active matrix liquid crystal display device, driving method thereof and portable information terminal device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an active matrix liquid crystal display device. More particularly, the present invention relates to an active matrix liquid crystal display device that independently drives storage capacitor lines, and more particularly to an active matrix liquid crystal display device characterized by partial display driving, a driving method thereof, and an information portable terminal device using the active matrix liquid crystal display device. .
[0002]
[Prior art]
The configuration of a conventional active matrix liquid crystal display device will be described with reference to FIG. FIG. 4 shows an equivalent circuit of a conventional liquid crystal display panel and its peripheral circuit, and shows a case where the number of pixels is VGA (horizontal 640 RGB × vertical 480). A conventional active matrix type liquid crystal display device is provided at intersections of a plurality of gate lines G1 to G480 wired in rows, a plurality of source lines S1 to S1920 wired in columns, and gate lines and source lines. An active matrix display unit composed of a pixel LC, a storage capacitor CS and a pixel driving thin film transistor TFT, and a plurality of storage capacitor lines C1 to C1 wired in parallel to the gate line and connected to the storage capacitor CS for each line. C480 is included. The source lines S1 to S1920 are connected to the source driving circuit 32 that controls the supply of the source image signal of the thin film transistor TFT, and the gate lines G1 to G480 are connected to the gate driving circuit 31 that controls the gate selection signal. Further, the storage capacitor lines C1 to C480 are connected to the pixel via the storage capacitor CS, and are connected to the storage capacitor drive circuit 33 that controls the voltage applied to the liquid crystal pixel. The thin film transistor TFT provided in each pixel is connected to the counter electrode COM through the liquid crystal capacitor LC. A certain DC voltage is applied to the counter electrode COM.
[0003]
Next, a general driving method of the active matrix liquid crystal display device having the above configuration will be described with reference to FIGS. FIG. 5 shows applied voltage waveforms at various parts in a conventional active matrix liquid crystal display device. Here, VG1 is a gate voltage waveform sequentially output from the gate drive circuit 31. When considered in pixel units, the thin film transistor TFT is turned on once per frame period 1 frame (usually 1/60 second) for 1 HS. Data is an image signal, and any voltage between the VH potential and the VL potential corresponding to the image signal is written in the liquid crystal capacitor LC by the source drive circuit 32 during the period when the gate line is selected. VC1 to VC3 are storage capacitor voltage waveforms, which are output signals from the storage capacitor drive circuit 33 to the storage capacitor lines (C1, C2, C3...). Next, Vpix indicates a voltage waveform actually applied to the liquid crystal pixel.
[0004]
In the first frame 1 frame (odd) period, when the gate voltage VG1 is ON, the voltage Vipx of the liquid crystal pixel indicated by the thick line rises to the potential of VH. Descent. Thereafter, in response to the rising of the storage capacitor voltage VC1 from the L level to the H level, the pixel potential rises by ΔVcs through the storage capacitor CS, and the voltage is held for a period until the next image data is written. . Since the image signal Data is VL in the next one frame 1 frame (even) period, the VL voltage is written to the liquid crystal pixel, and then the storage capacitor voltage VC1 corresponds to the fall from the H level to the L level. , .DELTA.Vcs, the pixel potential drops, and the voltage is similarly held until the next image data is updated.
[0005]
VCOM is a counter voltage, and a voltage difference from the pixel voltage Vpix is a voltage that is actually written into the liquid crystal pixel. Note that the liquid crystal deteriorates when a DC voltage is applied, and thus needs to be driven in an alternating manner. By setting the VCOM voltage so that the voltage difference between Vpix and VCOM, and the effective values of ΔV + and ΔV− are equal, the polarity of the voltage applied to the liquid crystal is reversed every frame and the alternating current for driving the liquid crystal Can be performed.
[0006]
By driving the storage capacitor lines C1 to C480 independently by using the driving method shown in this example, it is possible to apply a voltage sufficient for driving the liquid crystal while reducing the amplitude of the image signal data.
[0007]
Next, FIG. 6 shows a timing chart of a conventional driving method. Here, STV is a frame signal, CKV is a clock signal for transferring the shift registers of the gate drive circuit 31 and the storage capacitor drive circuit 33, LP is a latch pulse signal for controlling the output of the gate drive circuit, and a gate output signal VG1. ... VG8 are sequentially output every 1 HS in synchronization with the clock signal CKV and the latch signal. The storage capacitor output signals VC1 to VC7 are inverted every frame of the odd period and the even period, and are sequentially output in synchronization with the clock signal CKV and the latch signal LP. In FIG. 6, the storage capacitor output signals VC1 to VC7 are input with waveforms inverted every 1HS.
[0008]
[Problems to be solved by the invention]
Next, partial display in the conventional liquid crystal display device will be described with reference to FIG. The partial display is a technique that generally displays only a part of the screen of a liquid crystal panel or the like, and has recently attracted attention as one of the power saving techniques in mobile phones and the like. Since the liquid crystal panel has a capacitive load, it is necessary to charge and discharge the liquid crystal capacitor in order to display an image. Therefore, when it is not necessary to display the full screen, such as when waiting for a mobile phone, it is possible to reduce power consumption as a result by setting only one part and not displaying other areas. It becomes.
[0009]
However, the conventional liquid crystal display device as described above has a problem that display unevenness appears due to a change in the potential of the non-display area as shown in FIG. . This cause will be described below.
[0010]
FIG. 7 is a timing chart of partial display in a conventional liquid crystal display device. Here, STV is a frame signal, CKV is a clock signal, LP is a latch signal, VG1 to VG8 are gate output signals, and VC1 to VC7 are storage capacitor output signals. In the full screen display mode, the signal waveforms are exactly the same as those shown in FIG. In the partial display mode, for example, when displaying 1, 2, and 6-8 lines and not displaying 3-5 lines, first, data for refresh (for example, full screen white data) is written in the previous frame. In the next partial display mode, the latch signal LP for controlling the output of lines 3 to 5 is controlled to stop the output of the gate output signals VG3 to VG5. Therefore, the thin film transistor TFT corresponding to the above line is not selected, and the data written in the previous frame (here, white data) is continuously held.
[0011]
However, in the conventional driving method, the gate output signals VG3 to VG5 are stopped, whereas the storage capacitor output signals VC3 to VC5 corresponding to the partial display lines are synchronized with the clock signal CKV for each frame as in the full screen mode. Will be reversed. For this reason, the voltage written in the liquid crystal pixels during the refresh period changes via the storage capacitor, and the partial display portion is different from a desired potential, causing uneven display.
[0012]
In view of the above-described problems of the conventional technology, the present invention eliminates the display unevenness at the time of partial display, which has been a problem in the conventional technology, by changing the configuration of such a conventional liquid crystal display device. It is an object of the present invention to provide an active matrix liquid crystal display device having the above, a driving method thereof, and an information portable terminal device.
[0013]
[Means for Solving the Problems]
The invention according to claim 1 of the present application includes a plurality of gate lines wired in rows, a plurality of source lines wired in columns, and a plurality of storage capacitor lines wired in parallel to the gate lines. A pixel driving thin film transistor in which a source and a gate are connected to each intersection of the source line and the gate line, respectively, and a drain of the pixel driving thin film transistor and a storage capacitor line adjacent to the gate line at the intersection at each intersection. An active matrix display unit including storage capacitors connected to each other and a liquid crystal pixel connected between a drain and a common electrode of the pixel driving thin film transistor at each intersection, and the source line of the active matrix display unit through the source line A source driving circuit for controlling supply of an image signal to the pixel driving thin film transistor; and A gate drive circuit that is connected to each gate line of the active matrix display unit and outputs output to the gate line, and outputs a storage capacitor output signal that is inverted after the gate voltage of the corresponding gate line is turned off for each frame. A storage capacitor driving circuit for controlling a voltage applied to the liquid crystal pixels via the storage capacitor in the storage capacitor line, and refreshing at a previous frame in a partial display mode in which a predetermined line is not displayed. In the next frame, in the liquid crystal display device that controls to stop the gate output signal corresponding to the non-displayed line by the gate drive circuit in the next frame, from the storage capacitor drive circuit during full screen display Are output sequentially to all the storage capacitor lines, and the value is maintained for one frame period. Sequentially outputs output signals from the storage capacitor driving circuit to a storage capacitor line corresponding to a liquid crystal pixel that performs display, holds the value for one frame period, and stores a value corresponding to a liquid crystal pixel that does not perform display A partial display selection circuit is further provided which stops updating the output signal to the line and holds the voltage of the storage capacitor line already held for one frame period.
[0014]
According to a second aspect of the present invention, in the active matrix liquid crystal display device according to the first aspect, the partial display selection circuit outputs a selection signal that becomes active during a horizontal scanning period corresponding to a non-display period of the partial display. A latch pulse generation circuit; and a latch circuit having a function of stopping the update of the output signal to the storage capacitor line based on the selection signal output from the latch pulse generation circuit.
[0015]
The invention of claim 3 of the present application includes a plurality of gate lines wired in rows, a plurality of source lines wired in columns, and a plurality of storage capacitor lines wired in parallel to the gate lines, A pixel driving thin film transistor in which a source and a gate are connected to each intersection of the source line and the gate line, respectively, and a drain of the pixel driving thin film transistor and a storage capacitor line adjacent to the gate line at the intersection at each intersection. An active matrix display unit including storage capacitors connected to each other and a liquid crystal pixel connected between a drain and a common electrode of the pixel driving thin film transistor at each intersection, and the source line of the active matrix display unit through the source line A source driving circuit for controlling supply of an image signal to the pixel driving thin film transistor; and A gate driving circuit connected to each gate line of the active matrix display unit and providing an output to the gate line, and a storage capacitor output signal which is inverted after the gate voltage of the corresponding gate line is turned off for each frame. A storage capacitor driving circuit that outputs to a capacitor line and controls a voltage applied to a liquid crystal pixel via the storage capacitor, wherein the storage capacitor driving is performed during full-screen display. In the partial display mode in which the output signal from the circuit is sequentially output to all the storage capacitor lines and the value is maintained for a period of one frame, and the predetermined line is not displayed, the data for refreshing is first displayed in the previous frame. writing, in the next frame, the gate output signal corresponding to the line to be hidden by the gate driving circuit stops, line display The output signal from the storage capacitor driving circuit is sequentially output to the storage capacitor line corresponding to the liquid crystal pixel, and the value is held for a period of one frame, and the output signal to the storage capacitor line corresponding to the liquid crystal pixel not to be displayed. Is stopped, and the voltage of the storage capacitor line is held as it is for one frame period.
[0016]
An information portable terminal device according to claim 4 of the present application includes the active matrix liquid crystal display device according to claim 1 or 2.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1 of the invention)
FIG. 1 shows a circuit configuration of an active matrix liquid crystal display device according to an embodiment of the present invention. FIG. 1 shows a case where the number of pixels is VGA (horizontal 640 RGB × vertical 480). The active matrix liquid crystal display device of this embodiment includes a plurality of gate lines G1 to G480 arranged in a row, a plurality of source data lines S1 to S1920 arranged in a row, and intersections of gate lines and source lines. An active matrix display unit provided with a liquid crystal pixel LC, a storage capacitor CS, and a pixel driving thin film transistor TFT, and a plurality of storages connected in parallel to the gate line and connected to the storage capacitor CS for each line. The capacitor lines C1 to C480 are included. The source lines S1 to S1920 are connected to the source driving circuit 12 that controls the supply of the source image signal of the thin film transistor TFT, and the gate lines G1 to G480 are connected to the gate driving circuit 11 that controls the gate selection signal. The storage capacitor lines C1 to C480 are connected to the pixels via the storage capacitor CS, and are connected to the storage capacitor drive circuit 13 and the partial display selection circuit 15 that control the voltage applied to the liquid crystal pixels. The thin film transistor TFT provided in each liquid crystal pixel is connected to the counter electrode COM through the liquid crystal capacitor LC. A certain DC voltage is applied to the counter electrode COM.
[0018]
FIG. 2 shows a detailed configuration of the partial display selection circuit 15 of the active matrix type liquid crystal display device according to the embodiment of the present invention. Here, the partial display selection circuit 15 includes a latch pulse (hereinafter referred to as LP) generation circuit and a latch circuit that receives VFR1 to VFRn as input, latches the input according to LP2, and outputs as VC1 to VCn.
[0019]
Next, a driving method of the active matrix liquid crystal display device having the above configuration will be described with reference to FIG. FIG. 3 is a timing chart of partial display of the active matrix liquid crystal display device according to the embodiment of the present invention. Here, STV is a frame signal, CKV is a clock signal, LP is a latch pulse signal, VG1 to VG8 are gate output signals, VFR1 to VFR6 are output signals from the storage capacitor circuit 13 to the partial display selection circuit 15, and VC1 to VC6 are partial This is a signal that is actually output from the display selection circuit 15 to the storage capacitor lines C1 to C6. Further, SEL is a selection signal and becomes H level only during a period corresponding to partial display. LP2 is a second latch pulse signal for controlling the storage capacitor line output signals VC1 to VC6.
[0020]
The full screen display mode is the same as the conventional driving method, and the output signals VFR1, VFR2,... Output from the storage capacitor driving circuit 13 are latched by the latch circuit of the partial display circuit 15 at the next stage as they are, Is output to the storage capacitor lines C1, C2,.
[0021]
On the other hand, in the partial display mode, for example, when displaying 1, 2 and 6 to 8 lines and not displaying 3 to 5 lines, first, data for refreshing in the previous frame (for example, full screen white data) Is written. The next frame is in the partial display mode. In this mode, the latch signal LP for controlling the output of the 3 to 5 lines is stopped, and the output of the gate output signals VG3 to VG5 is stopped. Therefore, the thin film transistor TFT corresponding to the third to fifth lines is not selected, and the data written in the previous frame (here, white data) is continuously held.
[0022]
Next, the output of the storage capacitor driving circuit 13 is controlled as follows. First, the SEL signal becomes H level at a timing delayed by 2HS with respect to the gate output signal of the line, and is input to the LP generation circuit 16 together with the latch signal LP. The LP generation circuit 16 is composed of, for example, a gate circuit such as NAND or NOR, and stops the output of the second latch signal LP2 only during a period when the SEL signal is at the H level. The second latch signal LP2 generated in this way is input to the latch circuit 17.
[0023]
Next, output signals VFR1 to VFR6 from the respective storage capacitor driving circuits 13 are inputted to the latch circuit 17. Here, the second latch signal LP2 is an enable input of the latch circuit 17. For example, when the second latch signal LP2 becomes H level, the information of the input data VFR1 to VFR6 is directly transmitted to the outputs VC1 to VC6. When it becomes the L level, the immediately preceding data is held.
[0024]
As a result, as shown in FIG. 2, among the signals VFR1 to VFR6 input to the latch circuit at the timing when the second latch signal becomes L level, the data of the signals VFR3 to VFR5 is not updated, and the above data Work to hold. Therefore, among the output signals to the storage capacitor line, VC3 to VC5 continue to hold the data of the previous frame until the next refresh.
[0025]
In this way, the voltage written in the liquid crystal pixel during the refresh period via the storage capacitor does not change, and a desired potential can be kept in the partial display portion.
[0026]
As described above, by using the active matrix liquid crystal display device of the present invention, display unevenness during partial display can be improved, and advantages of both low power consumption and high image quality can be obtained.
[0027]
【The invention's effect】
The active matrix liquid crystal display device of the present invention sequentially outputs an output signal from the storage capacitor driving circuit to all the storage capacitor lines during full screen display, and corresponds to a liquid crystal pixel that does not perform display during partial display. A selection circuit for stopping the update of the output signal to the line and holding the voltage of the storage capacitor line is provided. Then, the output signal to the storage capacitor line is continuously held during partial display, and the change of the voltage written in the liquid crystal pixel through the storage capacitor during the refresh period is prevented. Accordingly, it is possible to provide an active matrix liquid crystal display device that improves display unevenness during partial display and has the advantages of both low power consumption and high image quality.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an active matrix liquid crystal display device according to a first embodiment of the present invention. FIG. 2 is a configuration diagram illustrating a partial display selection circuit according to the first embodiment of the present invention. The figure which showed the timing chart of the active matrix type liquid crystal display device in the form 1. [FIG. 4] The block diagram of the conventional active matrix type liquid crystal display device [FIG. 5] The figure of the pixel voltage waveform of the conventional active matrix type liquid crystal display device [ FIG. 6 is a timing chart of a conventional active matrix liquid crystal display device. FIG. 7 is a diagram illustrating a problem in partial display of a conventional active matrix liquid crystal display device.
11, 31 Gate drive circuit 12, 32 Source drive circuit 13, 33 Storage capacitor drive circuit 14, 34 Liquid crystal panel 15 Partial display selection circuit 16 LP generation circuit 17 Latch circuit TFT Thin film transistor CS Storage capacitor LC Liquid crystal capacitor PIX Liquid crystal pixels G1 to G480 Gate lines S1 to S1920 Source lines C1 to C480 Storage capacitor line STV Frame signal CKV Clock signal LP Latch signal LP2 Second latch signals VG1 to VG8 Gate output signals VFR1 to VFR6 Output signals VC1 to VC7 from the storage capacitor circuit Storage capacitor output Signal VH, VL Image signal potential Data Image signal 1HS 1 Horizontal scanning period 1 frame 1 Frame COM Counter electrode VCOM Counter voltage

Claims (4)

A plurality of gate lines wired in rows, a plurality of source lines wired in columns, a plurality of storage capacitor lines wired in parallel to the gate lines, and the source lines and gate lines A pixel driving thin film transistor having a source and a gate connected to the intersection, a storage capacitor connected between a drain of the pixel driving thin film transistor and a storage capacitor line adjacent to the gate line of the intersection at each intersection, and An active matrix display unit including a liquid crystal pixel connected between a drain of the pixel driving thin film transistor and a common electrode at an intersection;
  A source driving circuit for controlling supply of an image signal to the pixel driving thin film transistor through a source line of the active matrix display unit;
  A gate driving circuit connected to each gate line of the active matrix display unit and providing an output to the gate line;
  A storage capacitor that outputs a storage capacitor output signal that is inverted after the gate voltage of the corresponding gate line is turned off for each frame, and controls the voltage applied to the liquid crystal pixels through the storage capacitor to the storage capacitor line. A capacity driving circuit,
  In the partial display mode in which a predetermined line is not displayed, refresh data is first written in the previous frame, and in the next frame, the gate output signal corresponding to the non-displayed line is stopped by the gate drive circuit. In the liquid crystal display device to be controlled,
  During full screen display, the output signal from the storage capacitor driving circuit is sequentially output to all the storage capacitor lines, and the value is maintained for one frame period. During partial display, the storage capacitor corresponding to the liquid crystal pixel to be displayed is displayed. The output signal from the storage capacitor driving circuit is sequentially output to the line, the value is held for a period of one frame, and the update of the output signal to the storage capacitor line corresponding to the liquid crystal pixel not to be displayed is stopped, An active matrix type liquid crystal display device, further comprising a partial display selection circuit for holding the voltage of the storage capacitor line already held for one frame period. The partial display selection circuit includes:
  A latch pulse generation circuit that outputs a selection signal that becomes active in a horizontal scanning period corresponding to a non-display period of the partial display;
  2. An active matrix liquid crystal display according to claim 1, further comprising: a latch circuit having a function of stopping updating of an output signal to the storage capacitor line based on a selection signal output from the latch pulse generation circuit. apparatus. A plurality of gate lines wired in rows, a plurality of source lines wired in columns, a plurality of storage capacitor lines wired in parallel to the gate lines, and the source lines and gate lines A pixel driving thin film transistor having a source and a gate connected to the intersection, a storage capacitor connected between a drain of the pixel driving thin film transistor and a storage capacitor line adjacent to the gate line of the intersection at each intersection, and An active matrix display unit including a liquid crystal pixel connected between a drain of the pixel driving thin film transistor and a common electrode at an intersection;
A source driving circuit for controlling supply of an image signal to the pixel driving thin film transistor through a source line of the active matrix display unit;
A gate driving circuit connected to each gate line of the active matrix display unit and providing an output to the gate line;
A storage capacitor output signal that is inverted after the gate voltage of the corresponding gate line is turned off for each frame is output to the storage capacitor line, and the voltage applied to the liquid crystal pixels via the storage capacitor is controlled. A driving method in a liquid crystal display device comprising a capacitance driving circuit,
At the time of full screen display, the output signal from the storage capacitor driving circuit is sequentially output to all the storage capacitor lines, and the value is maintained for a period of one frame,
In the partial display mode in which a predetermined line is not displayed, first, data for refresh is written in the previous frame, and in the next frame, the gate output signal corresponding to the line to be hidden is stopped by the gate drive circuit, The output signal from the storage capacitor driving circuit is sequentially output to the storage capacitor line corresponding to the liquid crystal pixel to be displayed, and the value is maintained for a period of one frame, to the storage capacitor line corresponding to the liquid crystal pixel not to be displayed. And updating the output signal of the active matrix liquid crystal display, and holding the voltage of the storage capacitor line as it is for a period of one frame. An information portable terminal device comprising the active matrix type liquid crystal display device according to claim 1.

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