JP4813692B2 - Method for manufacturing hermetically sealed IC package - Google Patents
Method for manufacturing hermetically sealed IC package Download PDFInfo
- Publication number
- JP4813692B2 JP4813692B2 JP2001182439A JP2001182439A JP4813692B2 JP 4813692 B2 JP4813692 B2 JP 4813692B2 JP 2001182439 A JP2001182439 A JP 2001182439A JP 2001182439 A JP2001182439 A JP 2001182439A JP 4813692 B2 JP4813692 B2 JP 4813692B2
- Authority
- JP
- Japan
- Prior art keywords
- manufacturing
- photosensitive material
- package
- plate
- lid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/0198—Manufacture or treatment batch processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【0001】
【発明の属する技術分野】
本発明は気密封止ICパッケージの製造方法に関する。
【0002】
【従来の技術】
これまでの気密封止ICパッケージは図に示すように、枠47を有する個片の基板41にICチップ45をのせワイヤ46をはり、枠47にあわせるように板状のふた49をのせていた。
【0003】
【発明が解決しようとする課題】
従来の気密封止ICパッケージは、1個1個別別に製造されているため生産性が著しく低く、それゆえ非常に高価なものとなっていた。
【0004】
【課題を解決するための手段】
上記の問題点を解決するために、本発明は複数以上のICチップを載せられる基板を用い、感光性物質をICチップ間に厚く形成し、板状のふたを被せた後で、基板を切断することにより1個1個のICパッケージにする。
【0005】
【発明の実施の形態】
本発明は、ICチップの表面を空気などの気体で取り囲んだ気体封止型のパッケージの製造方法に関するものである。以下にこの発明の実施例を図面に基づいて説明する。
【0006】
図1は、本発明の製造方法の工程順を示すICパッケージの断面図を示す。
図1(a)に示すように、外部電極12と内部電極配線13を有する基板11が用意される。この基板内には複数以上のたくさんのICチップが搭載され、最終的に個片にされる。従って基板のサイズは大型であり、外部電極12も内部電極配線13も繰り返しのパターンとなっている。基板11の材料は、セラミックやガラスエポキシやポリイミドやガラスなどが挙げられる。
【0007】
次に図1(b)に示すように、ICチップ15を内部電極配線の所望の位置に接着する。尚、ICチップ15の接着する位置には、内部電極配線13はなくて良い場合もある。たとえば、ICチップの表面をできるだけ低くする必要がある場合や、ICチップを電気的に導通する必要がない場合や、ICチップを放熱する必要があまりない場合などである。次にICチップ15の表面の電極と内部電極配線とをワイヤ16で接続する。このワイヤの材料として、金(Au)、金合金、アルミニウム(Al)、アルミニウム合金、銅(Cu)、銅合金などの金属が使われる。
次に図1(c)に示すように感光性物質17を塗布する。この感光性物質17は塗布する時には液状なので、ICチップ15を移動させたり、ICチップ15にダメッジを与えたり、ワイヤ16を曲げたり、ワイヤにダメッジを与えたり、ワイヤと電極配線およびICとの接着場所にダメッジを与えたりすることはない。この感光性物質17として、ネガレジスト、ポジレジスト、感光性ポリイミドなどがある。また、塗布する感光性物質17の厚みは、最終的にワイヤ16の最も高い所より高くなるように設計されなければならない。
【0008】
次に図1(d)に示すように、ICチップ15、ワイヤ16のある部分が露出されるように作成されたマスク18を用いて光をあてる。ネガ型の感光性物質では光があたる所が硬化する。ポジ型の場合は、逆に光があたらない所が硬化する。
【0009】
次に図1(e)に示すように、現像することにより、ICチップ15のある所の感光性物質17がなくなり、ICチップ15の間にある所に厚い壁状の感光性物質17が形成される。これを熱処理することにより、感光性物質17はさらに強固になる。この熱処理により感光性物質17は縮小する場合があるが、縮小して高さが低くなってもワイヤの最高点よりも感光性物質17を高くするようにしなければならない。また、ICチップ15を先に搭載しワイヤ16をはっているので、感光性物質17とワイヤ16の位置および内部電極配線13とをかなり接近させることができる。
【0010】
次に図1(f)に示すように、板状のふた19を接着する。この場合、感光性物質17の上に接着材料を付着してからふた19を接着する方法、あるいはふた19の方に感光性物質17が来る位置に接着材を塗布してからふた19を接着する方法、あるいは感光性物質17とふた19を熱処理で接着する方法などがある。この板状のふた19として、光を通すことが必要であればガラスや透明プラスチックなどのその光に透明な物質からなる材料にする。光を通す必要がなければ、セラミックやガラスエポキシやポリイミドなどの材料を用いることができる。またテープ状のシートでも用途によって使うこともできる。
【0011】
次に図1(g)に示すように、感光性物質17の中間地点で基板を切断する。この切断の方法として、ダイシング装置を用いて行う方法やワイヤーソーを用いて行う方法やレーザーや高圧水を用いて切断する方法がある。また、ダイシングで行う場合、最初比較的幅の広いブレードを用いて浅く切断しその後幅の狭いブレードで切断することで、切断面にクラックが入ることを防止する方法を用いることもできる。
【0012】
このようにして、図1(h)に示すように、ICチップ15が気体で封止されたICパッケージを得る。
さて、ICパッケージの電気特性の測定方法として、従来と同じく1個のパッケージになった後で測定することはもちろん可能である。そのほかに、図1(g)で基板を切断する前に測定することもできる。すなわち、基板の電極に合せてプローブカードを作成しウエハ測定の時と同じ方法で測定できる。従って多数のICパッケージを1回のプロービングで測定することも可能である。
【0013】
図2は、図1(e)の平面図を示す。基板21内に多数のICチップ25が搭載されている。ICチップ25およびワイヤ26は露出している。ICチップの間には感光性物質27が壁状に形成されている。写真食刻法を用いているので感光性物質は精度良くパターニングされている。
【0014】
図3は、図1(g)の平面図を示す。点線で示す位置で切断される。感光性物質37のほぼ中間位置で切断される。
【0015】
【発明の効果】
以上、説明したように基板内に多数のICパッケージを一挙に作り込み、最後に切断して1個1個のICパッケージにするので、生産性が大幅に向上し製造費も大幅に低減する。また、切断する前に1枚の基板になっている時に電気特性を測定できるので、ウエハプローバーと同様の思想で多数のICの電気特性を一挙に測定できることになり、テストに要する費用を大幅に削減できる。
【図面の簡単な説明】
【図1】本発明のICパッケージの製造方法を示す図である。
【図2】図1(e)の平面図を示す図である。
【図3】図1(g)の平面図を示す図である。
【図4】従来のICパッケージを示す図である。
【符号の説明】
11、21、31、41 半導体基板
12、42 外部電極
13、23、33、43 内部電極配線
15、25、35、45 ICチップ
16、26、36、46 ワイヤ
17、27、37 感光性物質
18 マスク
19、49 ふた
47 枠[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a hermetically sealed IC package.
[0002]
[Prior art]
As shown in the drawing, the conventional hermetically sealed IC package has an IC chip 45 placed on a piece of substrate 41 having a frame 47, a wire 46, and a plate-like lid 49 placed on the frame 47. .
[0003]
[Problems to be solved by the invention]
Conventional hermetic sealing IC packages are manufactured individually and individually, so the productivity is remarkably low, and therefore they are very expensive.
[0004]
[Means for Solving the Problems]
In order to solve the above problems, the present invention uses a substrate on which a plurality of IC chips can be mounted, forms a photosensitive material thickly between the IC chips, covers the plate-like lid, and then cuts the substrate. By doing so, one IC package is made.
[0005]
DETAILED DESCRIPTION OF THE INVENTION
The present invention relates to a method for manufacturing a gas-sealed package in which the surface of an IC chip is surrounded by a gas such as air. Embodiments of the present invention will be described below with reference to the drawings.
[0006]
FIG. 1 is a cross-sectional view of an IC package showing the process sequence of the manufacturing method of the present invention.
As shown in FIG. 1A, a substrate 11 having external electrodes 12 and internal electrode wirings 13 is prepared. A large number of IC chips of a plurality are mounted on this substrate, and finally are made into individual pieces. Therefore, the size of the substrate is large, and both the external electrode 12 and the internal electrode wiring 13 have a repeated pattern. Examples of the material of the substrate 11 include ceramic, glass epoxy, polyimide, and glass.
[0007]
Next, as shown in FIG. 1B, the IC chip 15 is bonded to a desired position of the internal electrode wiring. In some cases, the internal electrode wiring 13 may not be provided at the position where the IC chip 15 is bonded. For example, there is a case where the surface of the IC chip needs to be as low as possible, a case where the IC chip does not need to be electrically connected, or a case where it is not necessary to dissipate the IC chip. Next, the electrode on the surface of the IC chip 15 and the internal electrode wiring are connected by a wire 16. Metals such as gold (Au), gold alloy, aluminum (Al), aluminum alloy, copper (Cu), and copper alloy are used as the material of this wire.
Next, a
[0008]
Next, as shown in FIG. 1 (d), light is applied using a mask 18 formed so that a part of the IC chip 15 and the wire 16 is exposed. With a negative photosensitive material, the area exposed to light is cured. In the case of the positive type, the place where light is not exposed is cured.
[0009]
Next, as shown in FIG. 1E, by developing, the
[0010]
Next, as shown in FIG. 1 (f), a plate-
[0011]
Next, as shown in FIG. 1G, the substrate is cut at an intermediate point of the
[0012]
In this way, as shown in FIG. 1H, an IC package in which the IC chip 15 is sealed with gas is obtained.
As a method for measuring the electrical characteristics of an IC package, it is of course possible to measure after a single package as in the prior art. In addition, the measurement can be performed before the substrate is cut in FIG. That is, a probe card can be prepared in accordance with the electrodes on the substrate, and measurement can be performed by the same method as that for wafer measurement. Therefore, it is possible to measure a large number of IC packages with a single probing.
[0013]
FIG. 2 shows a plan view of FIG. A large number of IC chips 25 are mounted in the substrate 21. The IC chip 25 and the wire 26 are exposed. A photosensitive material 27 is formed in a wall shape between the IC chips. Since the photolithography method is used, the photosensitive material is patterned with high accuracy.
[0014]
FIG. 3 shows a plan view of FIG. Cut at the position indicated by the dotted line. The photosensitive material 37 is cut at a substantially intermediate position.
[0015]
【The invention's effect】
As described above, since a large number of IC packages are formed on the substrate at a time and finally cut into one IC package, productivity is greatly improved and manufacturing costs are greatly reduced. In addition, since the electrical characteristics can be measured when a single substrate is formed before cutting, the electrical characteristics of a large number of ICs can be measured at the same time with the same idea as a wafer prober, greatly increasing the cost of testing. Can be reduced.
[Brief description of the drawings]
FIG. 1 is a diagram showing a method of manufacturing an IC package according to the present invention.
FIG. 2 is a plan view of FIG. 1 (e).
FIG. 3 is a diagram showing a plan view of FIG.
FIG. 4 is a view showing a conventional IC package.
[Explanation of symbols]
11, 21, 31, 41 Semiconductor substrate 12, 42 External electrode 13, 23, 33, 43 Internal electrode wiring 15, 25, 35, 45 IC chip 16, 26, 36, 46
Claims (9)
前記搭載接続工程の後に感光性物質を塗布する工程と、
写真食刻法を用いて前記ICチップ間に壁状の感光性物質を形成する工程と、
板状のふたを前記壁状の感光性物質の上部に接着する工程と、
平面視にて前記感光性物質の前記ICチップ間の中間位置で前記板状のふたと前記基板と前記感光性物質とを切断する工程と、
からなることを特徴とする気密封止ICパッケージの製造方法。 A mounting connecting step to a substrate having an external electrode and the internal electrode wirings put a plurality of IC chips for connecting the electrode and the inner electrode wiring in the IC chip by wire,
A step of applying a photosensitive substance after the mounting connection step ;
Forming a wall-like photosensitive material between the IC chip using a photolithographic method,
Adhering a plate-like lid on top of the wall-like photosensitive material ;
Cutting the plate-like lid, the substrate and the photosensitive material at an intermediate position between the IC chips of the photosensitive material in plan view ;
Method of manufacturing a sealed IC package willing to, characterized in that it consists of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001182439A JP4813692B2 (en) | 2001-06-15 | 2001-06-15 | Method for manufacturing hermetically sealed IC package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001182439A JP4813692B2 (en) | 2001-06-15 | 2001-06-15 | Method for manufacturing hermetically sealed IC package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002373952A JP2002373952A (en) | 2002-12-26 |
| JP4813692B2 true JP4813692B2 (en) | 2011-11-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001182439A Expired - Fee Related JP4813692B2 (en) | 2001-06-15 | 2001-06-15 | Method for manufacturing hermetically sealed IC package |
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| Country | Link |
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Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5729185A (en) * | 1996-04-29 | 1998-03-17 | Motorola Inc. | Acoustic wave filter package lid attachment apparatus and method utilizing a novolac epoxy based seal |
| WO1999026289A1 (en) * | 1997-11-18 | 1999-05-27 | T.I.F. Co., Ltd. | Semiconductor device and method for manufacturing the same |
| JP3408987B2 (en) * | 1999-03-30 | 2003-05-19 | 三菱電機株式会社 | Semiconductor device manufacturing method and semiconductor device |
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2001
- 2001-06-15 JP JP2001182439A patent/JP4813692B2/en not_active Expired - Fee Related
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| Publication number | Publication date |
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| JP2002373952A (en) | 2002-12-26 |
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