JP4830173B2 - Semiconductor switching device - Google Patents

Description

  The present invention relates to a semiconductor switching device that performs a switching operation using a semiconductor element, and more particularly to a configuration for reducing output noise of a semiconductor switching device in which a plurality of semiconductor elements are arranged in parallel.

  In power conversion equipment that performs power control, a semiconductor switch capable of high-speed on / off control is used. In particular, when high-speed operation is required, a field effect transistor (FET) is used as the switching element. As the capacity of power conversion equipment increases, the amount of current to be processed increases, and it is necessary to connect semiconductor switching elements in parallel. When switching elements are arranged in parallel in this way, problems such as generation of a loop current flowing in a loop between the switching elements occur due to the asymmetry of the element arrangement and the difference in element characteristics. Various countermeasures have been proposed in order to cope with problems caused by such differences in characteristics and the like in elements arranged in parallel.

  Patent Document 1 (Japanese Patent Laid-Open No. 10-080132) controls the gate potential of a plurality of IGBTs (insulated gate type bipolar transistors) arranged in parallel through a resistance element, and also provides each emitter terminal and driver circuit. A resistive element is disposed between the two. The gate resistance is intended to suppress an increase in the gate-emitter voltage when a short circuit accident occurs. Further, by connecting an emitter resistor to each IGBT, it is intended to prevent generation of an oscillating current in the switching element at the time of occurrence of a short circuit accident.

  In Patent Document 1, a Schottky barrier diode is further arranged in parallel with the emitter resistor, and this diode is intended to absorb current flowing through the emitter resistor at a high speed due to wiring inductance or the like at the time of turn-off.

Patent Document 2 (Japanese Patent Application Laid-Open No. 09-289442) discloses a configuration for avoiding main current imbalance caused by asymmetry of the characteristics of these IGBTs in a power conversion device in which IGBTs are connected in parallel. To do. In this Patent Document 2, the IGBT has a multi-emitter structure of a main emitter and a current sense emitter. A resistor is connected to the current sense emitter, and the voltage across the emitter resistor is compared between the IGBT elements. According to the comparison result, the gate potential of the IGBT is controlled to balance the current flowing through each IGBT.
Japanese Patent Laid-Open No. 10-080132 JP 09-289442 A

  In the configuration in which the semiconductor switching elements are provided in parallel, the semiconductor switching elements are connected in parallel to the path (main current path) through which the current to be switched flows. A main current from the power supply or output terminal flows to the output terminal or power supply via the semiconductor switching element. For simplicity of explanation, in the semiconductor switching element, the main current inflow end and the main current outflow end of each switching element are electrically connected to the first and second wiring patterns, respectively. Consider a configuration in which the main current outflow ends of the switching elements are commonly connected to the gate drive circuit.

  When the main current flows, a current flows in one direction in the second wiring pattern, so that a difference occurs in the potential at the main current outflow end of each semiconductor switching element due to the inductance of the second wiring pattern. When such a potential difference occurs due to a difference in wiring inductance in each semiconductor switching element, a current is looped between the semiconductor switching elements via the wiring of the semiconductor switching element with respect to the second wiring pattern and the wiring with respect to the gate drive circuit. Flowing. When such a loop current occurs, it becomes a new electromagnetic radiation source and a noise source for peripheral devices, which causes malfunction. Also, overcurrent flows through the wiring of the gate drive circuit, causing problems such as wiring deterioration.

  In the above-mentioned Patent Document 1, it is intended to suppress the generation of such a loop current by providing an emitter resistor in each semiconductor switching element. When a resistive element has a relatively large occupation area and a plurality of semiconductor switching elements are arranged in one module, it is required from the viewpoint of reducing the module size to efficiently arrange the resistive elements. Further, when the resistance element is actually arranged, it is required to arrange the resistance without affecting the arrangement of the switching element. In this case, it is conceivable to take measures such as disposing the resistance element in an empty area on the substrate and routing the wiring for the resistor on the substrate. However, in this case, there arises a problem that the wiring inductance increases. That is, if the arrangement of the resistors and the arrangement of the wires with respect to the resistors are not considered, problems such as an increase in circuit inductance due to the inductance of the wires, generation of noise due to coupling with the main current circuit, and a reduction in switching speed occur.

  However, this Patent Document 1 only shows an electrical equivalent circuit for connecting a resistance element to the gate and emitter of each IGBT, and how to mount and arrange the gate resistance and emitter resistance. Is not considered at all.

  Also in Patent Document 2, although a sense resistor is provided in the current sense emitter of each multi-emitter IGBT, no consideration is given to how the gate resistor and the emitter resistor are physically arranged efficiently.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor switching device that performs high-speed switching operation while reliably suppressing the generation of loop current without increasing the occupied area.

A semiconductor switching device according to the present invention includes a substrate on which a plurality of semiconductor switching elements, each of which is controlled to be turned on and off in accordance with a control signal applied to the control electrode, are arranged in parallel, and the control electrode and gate of the semiconductor switching element A plurality of gate resistors and a plurality of source resistors are connected between the drive circuits and between the first electrode of the semiconductor switching element and the gate drive circuit. These gate resistances and source resistances are arranged at opposing positions on the front surface and back surface of the connection substrate serving as a relay for electrically connecting the control electrodes of the plurality of semiconductor switching elements to the gate drive circuit.

  A resistor is disposed between the first electrode of the semiconductor switching element and the gate drive circuit, and the current amplitude of the path through which the loop current flows can be reduced. Further, the attenuation time determined by the inductance of the loop circuit and the loop resistance can be greatly improved by the reduction of the loop current amplitude. Therefore, it is possible to dramatically improve the loop current caused by the asymmetry of the current path such as the difference in wiring inductance between a plurality of semiconductor switching elements connected in parallel. Can be turned on / off.

  In addition, the gate resistance and the first electrode resistance are respectively disposed on the front surface and the back surface of the connection substrate, and an increase in the substrate area on which the semiconductor switching element is mounted can be suppressed. Further, by arranging the resistance elements on the front surface and the back surface of the connection substrate, it is possible to sufficiently secure the arrangement area of these resistance elements.

[Embodiment 1]
1 schematically shows an arrangement of switching elements of the semiconductor switching device according to the first embodiment of the present invention. In FIG. In FIG. 1, semiconductor switching elements 3 and 4 formed of MOSFETs (insulated gate field effect transistors) are arranged in parallel between wiring patterns 1 and 2 constituting a main current path. The wiring patterns 1 and 2 are formed by wiring patterns on a substrate on which the switching elements 3 and 4 are mounted.

  The semiconductor switching elements 3 and 4 have a vertical structure in which a gate electrode (control electrode) G and a source electrode (first electrode) S are formed on the front surface, and a drain electrode is formed on the back surface. The drain electrodes of the semiconductor switching elements 3 and 4 are fixed and electrically connected to the wiring pattern 1 by die bonding (not shown).

  Semiconductor switching elements 3 and 4 are also electrically connected to wiring pattern 2 via source electrode wirings 10a and 10b, respectively. Source electrode wirings 10a and 10b are bonding wires formed by wire bonding.

  Gate electrodes G of switching elements 3 and 4 are coupled to gate drive circuit 9 via gate resistors 7 and 8, respectively. Source electrodes S of semiconductor switching elements 3 and 4 are electrically connected to gate drive circuit 9 via source resistors 12 and 11, respectively. The gate driving circuit 9 generates a pulse voltage and controls the potential difference between the gate electrode G and the source electrode S of the semiconductor switching elements 3 and 4 to turn on the semiconductor switching elements 3 and 4. Control off / off.

  Next, the operation will be described. The semiconductor switching elements 3 and 4 are turned on by the pulse voltage from the gate drive circuit 9. Accordingly, current 5 flows from wiring pattern 1 to wiring pattern 2 through semiconductor switching elements 3 and 4 and source electrode wirings 10a and 10b.

  In the semiconductor switching element 3, the source electrode S is electrically connected to the wiring pattern 2 through the source electrode wiring 10a. In the semiconductor switching element 4, the source electrode S is electrically connected to the wiring pattern 2 through the source electrode wiring 10b. The current 5 flowing through these semiconductor switching elements 3 and 4 merges at a point C on the wiring pattern 2.

  As shown in FIG. 1, the distance from the source electrode S to the point C in the main current passing through the semiconductor switching element 3 and the distance from the source electrode S to the point in the main current passing through the semiconductor switching element 4 are as follows. , Different from each other. In the wiring pattern 2, there is a parasitic inductance. Therefore, the inductance at the point C from the source electrode of the semiconductor switching element 3 and the inductance at the point C from the source electrode of the semiconductor switching element 4 do not match. Therefore, when these semiconductor switching elements 3 and 4 perform a switching operation, a potential difference is generated between the source electrodes S of these semiconductor switching elements 3 and 4 due to the current change rate di / dt.

  Since the main current 5 flows in the direction from the semiconductor switching element 3 to the semiconductor switching element 4 as shown in FIG. 1, the source electrode S of the semiconductor switching element 3 has a higher potential than the source electrode of the semiconductor switching element 4. . Therefore, as indicated by an arrow in FIG. 1, a current 6 flows from the semiconductor switching element 3 through the source electrode wiring 10 a, the wiring pattern 2, the source electrode wiring 10 b, and the semiconductor switching element 4. In this case, the source electrodes S of the semiconductor switching elements 3 and 4 are connected by source resistors 12 and 11, respectively. Therefore, the loop current 6 is suppressed by the current limiting function of the source resistors 11 and 12, and the source current during the switching operation can be suppressed from oscillating.

  In the path through which the loop current flows, the time constant of the loop current 6 is determined by the inductance L of the path through which the loop current 6 flows and the resistance value Rs of the source resistances 11 and 12 (L / R (2 · Rs)). Since the loop current 6 is reduced according to the time constant, the loop current 6 is rapidly attenuated by setting the resistance value Rs to an appropriate value. Thereby, switching operation can be performed at high speed.

  The gate resistors 7 and 8 are provided to optimize the switching time of the semiconductor switching element 3, and the resistance values Rg of these gate resistors 7 and 8 are the switching time during which the switching loss is reduced and the gate voltage oscillates. The value is adjusted in consideration of the delay of

  In FIG. 1, the main current flows from the wiring pattern 1 toward the wiring pattern 2 via the semiconductor switching elements 3 and 4. The same effect can be obtained even when the main current flows in the opposite direction, that is, when the main current flows from the wiring pattern 2 toward the wiring pattern 1.

  Furthermore, the number of semiconductor switching elements is not limited to two, and more switching elements may be provided. The number of semiconductor switching elements is determined according to the current value to be driven.

  FIG. 2 is a plan view schematically showing an arrangement on the substrate of the switching element of the semiconductor switching device according to the first embodiment of the present invention. In FIG. 2, a semiconductor switching element 18 formed of a MOSFET and a Schottky barrier diode (SBD) 19 functioning as a freewheel diode for current commutation are arranged in parallel on a wiring pattern 1 on a substrate 17. In FIG. 2, a configuration in which four semiconductor switching elements (MOSFETs) 18 and three Schottky barrier diodes (SBD) 19 are arranged is shown as an example. This semiconductor device has a 1 in 1 module configuration as an example, and one module is configured by a semiconductor switching element 18 and a Schottky barrier diode 19 that perform the same operation.

  The wiring pattern 1 is connected to a terminal 13 for connection to the outside at an end thereof, and the wiring pattern 2 is similarly connected to a terminal 16 for external connection at an end facing the terminal 13. These connection terminals 13 and 16 are used for connection to an external load or power source, and the connection destination is appropriately determined according to the position in the circuit where the semiconductor switching device is used. For example, when this semiconductor switching device is used in a motor drive circuit, the connection of these connection terminals 13 and 16 depends on whether the semiconductor switching device is connected to the upper arm or the lower arm. The destination is decided.

  The gate electrode wiring pattern 14g and the source electrode wiring pattern 14s are alternately arranged in a line facing the semiconductor switching element (MOSFET, hereinafter simply referred to as MOSFET) 18. These electrode wiring patterns 14g and 14s have the same length, and are electrically connected to the gate electrode G and source electrode S of the corresponding MOSFET, respectively, by bonding wires (shown by straight lines in FIG. 2). The source electrode S of the MOSFET 18 is also electrically connected to the wiring pattern 2 extending linearly by a bonding wire.

  Corresponding to the gate pad 14, a connection pin 15 for establishing an electrical connection with an external gate driving circuit is arranged. The connection pin 15 constitutes a part of the connection wiring and is electrically connected to a connection board described later.

  The Schottky barrier diode (SBD) 19 has a cathode electrode electrically connected to the wiring pattern 1 and an anode electrode electrically connected to the wiring pattern 2 by a bonding wire.

  As an example of the semiconductor switching element 18, a square-shaped switching element having an outer dimension of 4 mm per side is used, and these are arranged, for example, at intervals of 2 mm. As shown in FIG. 2, when the gate electrode wiring pattern 14g and the source electrode wiring pattern 14s are formed in parallel to reduce the inductance, the distance between the gate electrode wiring pattern 14g and the source electrode wiring pattern 14s is 2 mm. When ensuring, the gate electrode wiring pattern 14g and the source electrode wiring pattern 14s are formed at intervals of 1 mm.

  In the following description, when these electrode wiring patterns 14g and 14s are referred to collectively, the term “gate pad” is used and “14” is used as a reference number.

  FIG. 3 is a front view of the configuration shown in FIG. In FIG. 3, connection terminals 13 and 16 are disposed on both sides of the substrate 17. A Schottky barrier diode 19 is provided in the vicinity of these connection terminals 13 and 16. A MOSFET 18 is provided between the Schottky barrier diodes 19. Corresponding to the MOSFET 18, a connection pin 15 is provided. As shown in FIG. 2, the connection pins 15 are provided corresponding to the gate electrode wiring patterns 14g and the source electrode wiring patterns 14s, respectively.

  As shown in FIG. 2 and FIG. 3, the MOSFET 17 constituting the semiconductor switching element and the Schottky barrier diode 19 for current commutation are only provided on the substrate 17. Gate resistance and source resistance are not provided.

  FIG. 4 is a front view of a relay connection board for connecting the semiconductor switching elements arranged on the board 17 to the gate drive circuit. FIG. 4 also shows a front view of the substrate 17 on which the semiconductor switching element is arranged. 4, the components of the substrate 17 are the same as those shown in FIG. 3, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the connection board 29, connection metal fittings 20r and 20l for connecting a module constituted by the semiconductor switching element 18 and the outside are provided on both sides. These mounting brackets 20r and 20l have a hollow structure, and the connection terminals 13 and 16 formed on the substrate 17 are engaged with the mounting brackets 20r and 20l.

  In the central portion of the connection board 29, a socket 21 is provided for establishing an electrical connection with the connection pins 15 arranged on the board 17. A connector 22 is provided on the surface of the connection substrate 29 so as to face the socket 21 and make an electrical connection with the gate drive circuit.

  A gate resistor 23 is provided on the surface side of the connection substrate 29 corresponding to each pin of the socket 21. A source resistor 24 is disposed on the back surface of the connection substrate 29 so as to face almost the same position as the gate resistor 23.

  As shown in FIG. 4, by arranging the gate resistor 23 and the source resistor 24 on the front and back surfaces of the connection substrate 29, respectively, the gate resistor 23 and the source resistor 24 can be arranged with a sufficient margin. Further, the gate resistor 23 and the source resistor 24 do not need to be disposed on the substrate 17 on the same substrate as the semiconductor switching element, so that the area of the substrate 17 can be reduced and the size of the module is increased accordingly. Can be suppressed. Further, since the resistance element and the switching element are provided on different substrates, the gate resistance and the source resistance can be arranged without affecting the arrangement of the MOSFET 18.

  FIG. 5 is a diagram showing a wiring pattern on the surface of the connection substrate 29. In FIG. 5, mounting brackets 20 l and 20 r are disposed on both sides of the connection substrate 29. Through holes are provided at the ends of the mounting brackets 20l and 20r, and the connection terminals 13 and 16 shown in FIGS.

  In the connection substrate 29, gate resistors 23 are arranged in parallel at predetermined intervals in the center. These gate resistors 23 are connected at one end to the connector 22 via wiring patterns 31 and 30 and connected at the other end to the pin terminal hole 21h of the socket 21 via the wiring pattern 32. The The wiring pattern 31 is provided in a straight line corresponding to each of the gate resistors 23, and the wiring pattern 30 is electrically connected in common to the wiring pattern 31 and electrically connects the wiring pattern 31 to the connector 22.

  Since the gate electrode pins and the source electrode pins are alternately arranged corresponding to the gate electrode wiring pattern and the source electrode wiring pattern, the wiring pattern 32 is connected to every other pin in the pins 21h of the socket 21. The

  FIG. 6 is a diagram illustrating a wiring pattern on the back surface of the connection substrate 29. In FIG. 6, the source resistors 24 are arranged between the mounting brackets 20 l and 20 r in parallel with each other at substantially the same pitch as the gate resistors 23. A linear wiring pattern 36 is formed for each of the source resistors 24, and these wiring patterns 36 are electrically connected to a wiring pattern 35 that extends linearly in common. 22 is connected through a connection hole.

  The other end of the source resistor 24 is electrically connected to the pin 21h of the socket 21 by a wiring pattern 37 extending linearly. Each of the source resistor wiring patterns 37 is electrically connected to every other pin of the socket pins 21h.

  The gate resistor 23 and the source resistor 24 are arranged at substantially corresponding positions on the connection substrate 29, and are electrically connected to the pins 21h of the corresponding sockets by wiring patterns having substantially the same shape and the same pitch.

  As shown in FIGS. 5 and 6, by arranging the gate resistor 23 and the source resistor 24 on the front surface and the back surface of the connection substrate 29, the gate resistor 23 and the source resistor 24 are greatly limited in size. Therefore, a low inductance resistor (wide resistor) can be arranged with a sufficient margin. Further, by using the front and back surfaces of the connection substrate 29 as wiring arrangement regions for the resistors 23 and 24, a parallel plate type wiring in which wirings for the gate resistance and the source resistance are arranged in parallel can be realized. That is, a linearly extending wiring pattern can be arranged for these resistors, the wiring length can be reduced, the wiring inductance can be reduced, and high-speed driving can be realized.

  In the first embodiment, the resistance values of the gate resistor 23 and the source resistor 24 are, for example, 1Ω. When the size of the semiconductor switching element is several mm square and the interval between these switching elements is several mm (in this embodiment, the element size is a square having a side of 4.5 mm and the interval is 2 mm), a loop The parasitic inductance of the current path wiring is about 10 nH. Since the decay time when the loop current flows is determined by the inductance / resistance value, according to the configuration of the first embodiment, the loop current is expected to decay in about 10 ns. The normal switching time is about several tens of ns, the attenuation time is sufficiently short, and the influence is small.

  As described above, according to the first embodiment of the present invention, the resistance elements are connected to the source electrodes of the semiconductor switching elements connected in parallel, and are commonly connected to the gate drive circuit. Thus, the loop current flowing between the switching elements during the switching operation can be suppressed, the decay time can be reduced, and high-speed switching can be realized.

  Further, the gate resistance and the source resistance are arranged not on the substrate on which the semiconductor switching element is mounted but on the connection substrate for connection with the gate drive circuit. Therefore, it is not necessary to provide these gate resistance and source resistance arrangement regions on the substrate, an increase in the area of the substrate on which the semiconductor switching element is mounted can be suppressed, and the size of the module can be reduced. Also, the gate resistance and the source resistance can be individually arranged, and the wiring length for these resistors can be set to the shortest, the wiring width can be sufficiently widened, and the wiring inductance is increased. Can be suppressed.

[Embodiment 2]
FIG. 7 schematically shows a wiring pattern on the substrate of the semiconductor switching element according to the second embodiment of the present invention. The arrangement of the substrate 17 shown in FIG. 7 is different from the arrangement of the substrate shown in FIG. 2 in the following points. That is, the gate electrode wiring patterns 14g and the source electrode wiring patterns 14s are alternately arranged so as to face the MOSFET 18. Although the gate electrode wiring pattern 14g and the source electrode wiring pattern 14s are formed to extend linearly, the length of the source electrode wiring pattern 14s is longer than that of the gate electrode wiring pattern 14g. Therefore, the connection pins 15g and 15s indicating the connection positions on the substrate with respect to the gate electrode wiring pattern 14g and the source electrode wiring pattern 14s are alternately arranged in a zigzag shape. These connection pins 15g and 15s are electrically connected to a socket pin 21hg for a gate electrode and a socket pin 21hs for a source electrode formed on the connection substrate. The gate electrode pins 15g are arranged in a straight line, and the connection pins 15s for the source electrode are arranged in a straight line at another position. The positions of the gate electrode connection pin 15g and the socket pin 21hg are the same in plan view, and the positions of the source electrode connection pin 15s and the socket pin 21hs are the same in plan view. .

  The distance (interval) LP between the straight line where the source electrode connection pins 15s are aligned and the straight line where the gate electrode connection pins 15g are aligned is greater than the distance Lg between the source electrode wiring pattern 14s and the gate electrode wiring pattern 14g. Increased. The socket pins 21hg and 21hs are arranged corresponding to the connection pins 15g and 15s, respectively. Therefore, the socket pins 21hg and 21hs satisfy the same relationship as the connection pins 15g and 15s.

  The other configuration of the pattern on the substrate 17 shown in FIG. 7 is the same as the configuration of the first embodiment shown in FIG. 2, and the corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted. .

  FIG. 8 is a diagram schematically showing a wiring pattern on the connection substrate 29 in the first embodiment for comparison. In FIG. 8, socket pins 21h are arranged in a line for a gate electrode and a source electrode. A solder region 40 is formed in the socket pin 21h for electrical connection to the socket.

  When the mounting density of the semiconductor switching elements is increased on the surface of the connection substrate 29, the distance between the switching elements is narrowed, and accordingly, the distance between the gate electrode wiring pattern and the source electrode wiring pattern is also narrowed. In this case, the interval between the socket pins 21h becomes extremely narrow, and there is a possibility that the solder region 40 cannot be sufficiently secured. In this case, when the interval between the wirings becomes very narrow due to the solder region 40, a high voltage is applied between the wirings, which may cause a problem such as a short circuit, which causes a problem in withstand voltage characteristics.

  When the pitch of the switching elements and the interval between the gate pads are narrowed, the lengths of the gate electrode wiring pattern 14g and the source electrode wiring pattern 14s are different as shown in FIG. 7 in order to sufficiently secure the solder region 40. Then, the pins 15 for connecting to the socket are arranged in a zigzag shape, and the socket pins 21h are accordingly arranged in a zigzag shape to secure the solder region 40.

  FIG. 9 schematically shows a wiring pattern of a connection substrate of the semiconductor switching device according to the second embodiment of the present invention. In FIG. 9, the gate resistors 23 are electrically connected to the socket pins 21 hg via the wiring patterns 32 on the surface of the connection substrate 29. Socket pins 21hg for the gate electrodes are arranged in a line. Source electrode socket pins 21hs are arranged in a line at positions different from the gate electrode socket pins 21hg.

  A solder region 40 is provided for each of the socket pins 21hg and 21hs. In this case, the distance Lp between the straight line on which the gate electrode socket pin 21hg is aligned and the straight line on which the source electrode socket pin is aligned is sufficiently larger than the distance (interval) LG between the gate pads. The pitch (L1 + L2) of the source electrode socket pins 21hs is sufficiently larger than the pitch L1 between the source electrode socket pins 21s and the gate electrode socket pins 21g. The same applies to the socket pin 21hg for the gate electrode. Therefore, the solder region 40 can be secured sufficiently even when the pitch (or interval) of the semiconductor switching elements is sufficiently small and the interval between the gate pads is small.

  The wiring pattern for the gate resistance is shorter than the wiring pattern for the source resistance. This suppresses an increase in inductance of the gate wiring of the MOSFET (semiconductor switching element) 18 and suppresses a decrease in the change rate of the gate potential of the switching element.

  In the arrangement shown in FIG. 9, the minimum distance Lgs between the solder region 40 with respect to the source electrode socket pin 21hs and the solder region 40 with respect to the gate electrode socket pin 21hg is sufficiently larger than the distance LG between the gate pads. If the distance between the semiconductor switching elements is small, the solder region 40 can be sufficiently secured, and the withstand voltage characteristic can be sufficiently ensured.

  FIG. 10 schematically shows a wiring pattern on the back surface of connection substrate 29 of the semiconductor switching device according to the second embodiment of the present invention. In FIG. 10, on the back surface of the connection substrate 29, the source resistors 24 are arranged in alignment, and wiring patterns 36 and 37 extending linearly are connected to each.

  10 differs from the wiring pattern shown in FIG. 6 in the following points. In other words, the length of the wiring pattern 37 with respect to the source resistor 24 is made longer than that in the first embodiment, passes between the socket pins 21hg for the gate electrodes, and further to the source electrode socket pins 21hs. The point of extension is different. The other configuration of the wiring pattern of the connection board 29 shown in FIG. 10 is the same as that of the wiring pattern shown in FIG. 6, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  A solder region for establishing connection with the socket is not provided on the back surface of the connection board 29. Therefore, the wiring pattern 37 for the source resistor 24 can be linearly passed between the socket pins 21hg and extended to the source electrode socket pins 21hs.

  As described above, according to the second embodiment of the present invention, the connection positions (connection pins) with the connection substrate with respect to the source electrode wiring pattern and the gate electrode wiring pattern are arranged in a zigzag pattern on the substrate. Accordingly, the socket pins are similarly arranged in a zigzag pattern on the connection board. Therefore, even when the switching elements are arranged at a high density, the interval between the switching elements is narrowed, and the interval between the gate pads (gate electrode wiring pattern and source electrode wiring pattern) is narrowed, a sufficient solder area is secured. be able to. As a result, even when the interval between the switching elements becomes narrow, it is possible to suppress the deterioration of the withstand voltage characteristics and to realize a switching device that operates stably and at high speed.

  In the first and second embodiments described above, the gate resistance is disposed on the surface of the connection substrate, and the source resistance is disposed on the back surface of the connection substrate. However, conversely, the source resistor may be disposed on the surface of the connection substrate, and the gate resistor may be disposed on the back surface.

  The present invention can be applied to a semiconductor switching device in which a plurality of semiconductor switching elements are connected in parallel to perform a switching operation, thereby realizing a semiconductor switching device that operates stably at high speed.

  In the above description, a MOSFET is used as the semiconductor switching element. However, if the source electrode is replaced with an emitter electrode, it can be applied to an IGBT (insulated gate bipolar transistor) as well.

1 schematically shows an arrangement of a semiconductor switching device according to a first embodiment of the present invention. FIG. It is a figure which shows roughly the arrangement | positioning on the element mounting board | substrate of the semiconductor switching apparatus according to Embodiment 1 of this invention. It is a front view of arrangement | positioning on the board | substrate shown in FIG. FIG. 3 is a front view of the connection board and the board according to the first embodiment of the present invention. It is a figure which shows roughly the wiring pattern on the surface of a connection board according to Embodiment 1 of this invention. It is a figure which shows roughly the wiring pattern of the back surface of the connection board according to Embodiment 1 of this invention. It is a figure which shows roughly the pattern on the element mounting board | substrate of the semiconductor switching apparatus according to Embodiment 2 of this invention. FIG. 3 is a diagram schematically showing a solder region for a gate pad on a connection substrate in the first embodiment. It is a figure which shows roughly arrangement | positioning of the solder area | region on the connection board | substrate according to Embodiment 2 of this invention. It is a figure which shows roughly the wiring pattern of the back surface of the connection board | substrate of the semiconductor switching device according to Embodiment 2 of this invention.

Explanation of symbols

  1, 2 wiring pattern, 3, 4 MOSFET, 7, 8 gate resistance, 11, 12 source resistance, 9 gate drive circuit, 18 MOSFET, 19 Schottky barrier diode, 14 gate pad, 14g gate electrode wiring pattern, 14s source electrode wiring Pattern, 15 connection pin, 17 substrate, 29 connection substrate, 21 socket pin, 21h socket pin, 21hs source electrode socket pin, 21hg gate electrode socket pin, 22 connector, 23 gate resistance, 24 source resistance, 40 solder area.

Claims (3)

A substrate on which a plurality of semiconductor switching elements having at least a control electrode for controlling on and off and a first electrode are arranged in parallel;
A gate drive circuit for supplying a control signal for controlling on and off of the semiconductor switching element to the control electrodes of the plurality of semiconductor switching elements;
A plurality of gate resistors connected between the control electrodes of the plurality of semiconductor switching elements and the gate drive circuit and connected on a first surface of a connection substrate; and the first electrodes of the plurality of semiconductor switching elements and the A plurality of source resistors provided between the gate driving circuit and connected to the second surface opposite to the first surface of the connection substrate so as to face the gate resistor via the connection substrate; A semiconductor switching device. A plurality of control electrode wiring patterns arranged in a line on the substrate and electrically connected to the control electrodes of the plurality of semiconductor switching elements;
A plurality of first electrode wiring patterns which are arranged on the substrate in alignment with and alternately with the plurality of control electrode wiring patterns and are respectively electrically connected to the first electrodes of the plurality of semiconductor switching elements;
Connection positions on the substrate with the plurality of control electrode wiring patterns are linearly defined, a plurality of gate connection wirings for electrically connecting the connection substrate and the control electrode wiring pattern, and the plurality A connection position with the first electrode wiring pattern is linearly defined on the substrate, and includes a plurality of first electrode connection wirings for electrically connecting the connection substrate and the first electrode wiring pattern, The interval between the control electrode wiring pattern and the first electrode wiring pattern is shorter than the interval between the connection position of the control electrode wiring pattern and the connection position of the first electrode wiring pattern. Semiconductor switching device. The control electrode wiring pattern and the first electrode wiring pattern are formed in different lengths and are alternately arranged on the substrate,
The semiconductor switching device according to claim 2, wherein the connection position of the control electrode wiring pattern and the connection position of the first electrode wiring pattern are arranged in a zigzag shape on the substrate.

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