JP4848959B2 - Power circuit - Google Patents

Description

  The present invention relates to a power supply circuit that controls an output voltage to a target value by controlling driving of a main transistor interposed in a power supply path between a power supply input terminal and a power supply output terminal.

  With the recent miniaturization of LSI, the power supply voltage of the internal digital circuit is being lowered to 1.5 V, for example. On the other hand, for example, in an LSI used in an automobile, a 5V signal is required for the interface portion. For this reason, a 1.5V system element and a 5V system element may be mixed in the same chip. In such an LSI, when a power supply circuit for generating a power supply voltage to be supplied to the digital circuit is built in the LSI, the power supply circuit is configured using the 5V system element. As this type of power supply circuit, for example, a series regulator type disclosed in Patent Document 1 is often used.

FIG. 11 shows an example of the structure of an LSI incorporating a series regulator type power supply circuit. The LSI 1 has a power supply circuit 2 and a digital circuit 3. The power supply circuit 2 includes a P-channel type MOSFET (hereinafter referred to as a transistor) M1 connected between a power supply input terminal 4 and a power supply output terminal 5, a voltage detection circuit 6 comprising resistors R1 and R2, and a reference voltage generation The control amplifier 8 is configured to control the driving of the circuit 7 and the transistor M1.

As shown in FIG. 12 , the control amplifier 8 operates by receiving power supply from the power supply line 9 and the power supply line 10, and includes a differential amplifier circuit 11 including transistors M2 to M6, a transistor M7, and a resistor R3. A constant current circuit 12 and an output circuit 13 composed of transistors M8 to M11. The power supply circuit 2 configured as described above has a power supply output terminal 5 as an output voltage obtained by stepping down an input voltage of 5 V (VDD) supplied from the outside via the power supply input terminal 4 to a target value of 1.5 V (Vout). To output. On the other hand, the digital circuit 3 is configured by a 1.5 V-type element that operates by receiving a power supply voltage of 1.5 V (Vout) from the power input terminal 14 connected to the power output terminal 5 of the power circuit 2. Yes.
Japanese Patent Laying-Open No. 2005-165379 (FIG. 11)

  However, since the 5V element constituting the power supply circuit 2 is not miniaturized like the 1.5V element, the threshold voltage of the transistor is high. For this reason, the control amplifier 8 does not operate normally because the operating current does not flow unless the voltage between the power lines 9 and 10 (input voltage VDD) rises to a certain level, for example, 2.0 V (minimum operating voltage: VDDmin). . The same applies to the reference voltage generation circuit 7.

FIG. 13 shows waveforms of the input voltage VDD and the output voltage Vout during the power-on process of the power supply circuit 2. As shown in FIG. 11, until the input voltage VDD reaches VDDmin (time t0 to time t2) after the power is turned on, the control amplifier 8 cannot operate normally as described above, and the output of the power circuit 2 The voltage Vout becomes indefinite.

  Further, when the input voltage VDD exceeds the target value of the output voltage Vout of 1.5 V (between time t1 and time t2) in the power-up process in which the input voltage VDD is less than VDDmin, the output voltage Vout is There is a risk of overshoot, and the output voltage Vout may temporarily exceed 1.5V. As a result, an excessive voltage may be applied to the 1.5 V system element of the digital circuit 3.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a power supply circuit that can prevent an overshoot of an output voltage when an input power supply voltage is a low voltage during a power-on process.

  According to the power supply circuit of the first aspect, the voltage control circuit and the reference voltage generation circuit operate normally when the current flowing in their circuits exceeds a predetermined value, and these circuits operate normally. The drive of the main transistor is controlled, and an output voltage that is a target value is output from the power supply output terminal. When the current flowing in at least one of the voltage control circuit and the reference voltage generation circuit is smaller than a predetermined value, the output cutoff circuit outputs a cutoff signal to control the main transistor to a current cutoff state.

  According to this configuration, when at least one of the voltage control circuit and the reference voltage generation circuit is not operating normally in a state where the input power supply voltage is low, such as in the power-on process, the output from the power supply output terminal is Since it is cut off, an indefinite state of the output voltage can be prevented. In addition, by preventing an indefinite state of the output voltage, the output voltage overshoots and temporarily exceeds the target value when the input power supply voltage is higher than the target value of the output voltage during the power-on process. Thus, there is no adverse effect on the output voltage supply destination circuit.

  According to the power supply circuit of the second aspect, the voltage control circuit actually applies the predetermined current supplied from the current source to the pair of differential input transistors and the pair of differential input transistors when operating normally. The sum of the flowing currents matches. Therefore, each current flowing through the pair of differential input transistors is detected by the pair of detection transistors, and the output cutoff circuit outputs a cutoff signal when the sum of the detected currents is smaller than a predetermined current. According to this configuration, since the output from the power supply output terminal is shut off when the voltage control circuit is not operating normally, an indefinite state of the output voltage and overshoot can be prevented.

  According to the power supply circuit of the third aspect, each current flowing in the differential input transistor flows in each detection transistor. Then, a common resistor is connected between the first power supply line and the output node of the cutoff signal, and a pair of detection transistors are connected in parallel between the output node of the cutoff signal and the second power supply line.

  With this configuration, the potential at the output node of the cutoff signal changes according to the sum of the currents flowing through the pair of differential input transistors, that is, the operating state of the voltage control circuit. Therefore, if the output cutoff circuit controls the main transistor to the current cutoff state based on the potential of the output node of the cutoff signal, the output from the power supply output terminal can be cut off based on the operating state of the voltage control circuit.

  According to a fourth aspect of the present invention, the cutoff signal is output when the sum of the currents flowing through the pair of detection transistors is smaller than the predetermined current, and the sum of the currents flowing through the pair of detection transistors is the predetermined current. The resistance value of the common resistor is set so as to invalidate the cut-off signal when it is equal to. Therefore, it is possible to reliably output the cutoff signal or invalidate the cutoff signal in accordance with the sum of the currents flowing through the pair of detection transistors.

  According to the power supply circuit of the fifth aspect, instead of the common resistor, a constant current circuit set to flow a constant current smaller than a predetermined current supplied to the pair of differential input transistors is provided. Thus, without performing a design that requires high accuracy such as tolerance design of the resistance value, the output of the cutoff signal or the invalidation of the cutoff signal is surely performed according to the sum of the currents flowing through the pair of detection transistors. be able to.

  According to the power supply circuit of claim 6, the output cut-off circuit detects a current flowing through the reference voltage generation circuit, and the cut-off signal is detected when the detected current is smaller than the operation current during normal operation (when the reference voltage is generated). Was configured to output. With this configuration, since the output from the power supply output terminal is cut off when the reference voltage generation circuit is not operating normally, an indefinite state of the output voltage and overshoot can be prevented.

  According to the power supply circuit of the seventh aspect, when the reference voltage generation circuit is operating normally, a predetermined operating current flows through the first resistor through the fourth transistor. Therefore, the current flowing through the fourth transistor is configured to flow to the output detection transistor via the current mirror circuit. Then, an output detection transistor is connected between the first power supply line and the output node of the cutoff signal, and an output detection resistor is connected between the output node of the cutoff signal and the second power supply line.

  With this configuration, the potential at the output node of the cutoff signal changes according to the operating state of the reference voltage generation circuit. Therefore, if the output cutoff circuit controls the main transistor to the current cutoff state based on the potential of the output node of the cutoff signal, the output from the power supply output terminal can be cut off based on the operating state of the reference voltage generation circuit.

  According to the power supply circuit of claim 8, the reference voltage generation circuit provided with the startup circuit operates normally when a current flows in the start-up transistor and the reference voltage generation circuit generates the reference voltage during the power-up process. After starting, the starting transistor is turned off. Therefore, a start-up transistor and a start-up detection transistor in which the control terminals are connected are connected between the first power supply line and the output node of the cut-off signal, and between the cut-off signal output node and the second power supply line. A start detection resistor was connected to

  With this configuration, the potential at the output node of the cutoff signal changes according to the current flowing through the starting transistor, that is, the operating state of the reference voltage generation circuit. Therefore, if the output cutoff circuit controls the main transistor to the current cutoff state based on the potential of the output node of the cutoff signal, the output from the power supply output terminal can be cut off based on the operating state of the reference voltage generation circuit.

  According to the power supply circuit of the ninth aspect, even when the main transistor cannot be directly driven, the main transistor can be reliably driven off based on the cutoff signal by driving through the cutoff transistor.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
Figure 1 shows a schematic configuration of an LSI having a built-in power supply circuit of the series regulator type, the same symbols are the same components as in FIG. 11. In FIG. 1, the LSI 21 has a power supply circuit 22 and a digital circuit 3.

  The power supply circuit 22 includes a transistor M1 (corresponding to a main transistor) connected between the power supply input terminal 4 and the power supply output terminal 5, a voltage detection circuit 6 including resistors R1 and R2, a reference voltage generation circuit 7, and a transistor M1. The control amplifier 23 (corresponding to a voltage control circuit) for controlling the driving of the output, and an output cut-off unit 24 comprising transistors M21 and M22 (corresponding to cut-off transistors) and a resistor R21. The transistors M1 and M22 are P-channel MOSFETs, and the transistor M21 is an N-channel MOSFET.

  An input voltage VDD (5 V in this embodiment) is externally applied between the power input terminal 4 and a ground terminal (not shown). The digital circuit 3 is composed of 1.5V elements, and a power supply voltage is supplied from a power supply input terminal 14 connected to the power supply output terminal 5 by external connection.

  The resistors R 1 and R 2 of the voltage detection circuit 6 are connected between the power output terminal 5 and the power line 10. The common connection point between the resistor R1 and the resistor R2 is connected to the non-inverting input terminal of the control amplifier 23, and the detection voltage Vdet obtained by dividing the output voltage Vout at the power supply output terminal 5 by the resistors R1 and R2 is the control amplifier 23. Has been entered. The reference voltage generation circuit 7 is a band gap reference voltage circuit, for example, and generates a reference voltage Vref (1.0 V in this embodiment) for instructing a target value of the output voltage Vout. The output terminal of the reference voltage Vref of the reference voltage generation circuit 7 is connected to the inverting input terminal of the control amplifier 23.

  The control amplifier 23 has two output terminals, the output terminal of the error amplification signal Aout is connected to the gate of the transistor M1, and the output terminal of the voltage signal Vcut1 is connected to the gate of the transistor M21. The source of the transistor M21 is connected to the power supply line 10, and the drain is connected to the power supply line 9 via the resistor R21. The drain of the transistor M21 is connected to the gate of the transistor M22 connected between the gate and source of the transistor M1.

  FIG. 2 shows the electrical configuration of the control amplifier 23. The control amplifier 23 operates by receiving power supply from power supply lines 9 and 10 (corresponding to first and second power supply lines), and an input voltage VDD is applied between the power supply lines 9 and 10. The The control amplifier 23 includes a differential amplifier circuit 11 including transistors M2 to M6, a constant current circuit 12 including a transistor M7 and a resistor R3, an output circuit 13 including transistors M8 to M11, and transistors M23 and M24 and a resistor R22. It has the interruption signal output part 25 which becomes.

  In the present embodiment, the cutoff signal output unit 25 and the output cutoff unit 24 described above constitute an output cutoff circuit. Of the above-described transistors, the transistors M2, M3, M6, M7, M10, and M11 are P-channel MOSFETs. Of these, the transistors M2 and M3 and M10 and M11 have W (gate width) / L (Gate length) is formed to have the same value. The transistors M4, M5, M8, M9, M23, and M24 are all N-channel MOSFETs formed so that W / L has the same value.

  In the constant current circuit 12, the source of the transistor M7 is connected to the power supply line 9, the gate and drain are connected in common, and are connected to the power supply line 10 via the resistor R3. In the differential amplifier circuit 11, the gates of the transistors M2 and M3 (corresponding to a pair of differential input transistors) are connected to the inverting input terminal and the non-inverting input terminal, respectively, and are supplied with the reference voltage Vref and the detection voltage Vdet. It is supposed to be. The sources of the transistors M2 and M3 are connected in common and are connected to the power supply line 9 via the transistor M6 functioning as a current source. The transistor M6 and the transistor M7 of the constant current circuit 12 constitute a current mirror circuit. The drains of the transistors M2 and M3 are connected to the power supply line 10 via transistors M4 and M5 (corresponding to a pair of load transistors), respectively.

  In the output circuit 13, the transistors M8 and M9 form a current mirror circuit with the transistors M4 and M5 of the differential amplifier circuit 11, respectively. A current mirror circuit including transistors M10 and M11 is connected between the transistors M8 and M9 and the power supply line 9. A common connection point N21 between the transistors M9 and M11 is an output terminal of the error amplification signal Aout.

  In the cutoff signal output unit 25, the transistors M23 and M24 (corresponding to a pair of detection transistors) are connected to the transistors M4 and M5 of the differential amplifier circuit 11, and the sources and gates to form a current mirror circuit, respectively. ing. The drains of the transistors M23 and M24 are connected in common and connected to the power supply line 9 via a resistor R22 (corresponding to a common resistor). A common connection point N22 (corresponding to an output node of the cutoff signal) between the resistor R22 and the transistors M23 and M24 is an output terminal of the voltage signal Vcut1.

  Note that the resistance value of the resistor R22, including the variation thereof, is equal to the current supplied to the transistors M2 and M3 (current I (M7) flowing through the transistor M7) and the current actually flowing through the transistors M2 and M3. The potential at the common connection point N22 is set to be a potential (a potential of approximately 0V) that can reliably drive the transistor M21 off.

Next, the operation of the power supply circuit 22 configured as described above will be described.
As described above, power is supplied to the control amplifier 23 from the power supply lines 9 and 10. The input voltage VDD applied between the power supply lines 9 and 10 is not less than the minimum operating voltage VDDmin shown in the following equation (1). At this time, the drain-source voltage VDS and the threshold voltage VT of the transistors M2 to M6 of the differential amplifier circuit 11 are sufficiently secured. As a result, a predetermined drain current flows through the transistors M2 and M3, and the differential amplifier circuit 11 operates normally. Note that VDS and VT in the following formula (1) indicate that the transistors are denoted by the reference numerals in parentheses.
VDDmin = VDS (M6) + VDS (M2) + VT (M4)
= VDS (M6) + VDS (M3) + VT (M5) (1)

At this time, the sum of the drain currents I (M2) and I (M3) actually flowing through the transistors M2 and M3 and the drain current I (M7) of the transistor M7 are equal as shown in the following equation (2). .
I (M7) = I (M2) + I (M3) (2)

  FIG. 3 is a waveform diagram of the input voltage VDD, the output voltage Vout, and the voltage signal Vcut1 during the power-on process. In FIG. 3, the input voltage VDD and the output voltage Vout are indicated by solid lines, and the voltage signal Vcut1 is indicated by a one-dot chain line. First, the operation in a state (state after time t3 in FIG. 3) in which the input voltage VDD rises to VDDmin and the output voltage Vout is controlled to the target voltage (1.5 V in this embodiment) will be described.

  In this state, since the input voltage VDD that can sufficiently drive the transistors M2 to M6 is applied between the power supply lines 9 and 10, the transistors M2 and M3 have a predetermined drain current I ( M2) and I (M3) flow, and the control amplifier 23 operates normally as follows.

That is, the control amplifier 23 outputs an error amplification signal Aout corresponding to the difference between the reference voltage Vref applied to the gate of the transistor M2 and the detection voltage Vdet applied to the gate of the transistor M3. The transistor M1 is driven by the error amplification signal Aout, and the output voltage Vout is controlled to a target voltage expressed by the following equation (3). In the following formula (3), the resistance values of the resistors R1 and R2 are shown as R1 and R2, respectively.
Target voltage = Vref × (R1 + R2) / R2 (3)

  On the other hand, since the drain currents I (M2) and I (M3) of the transistors M2 and M3 flow through the transistors M4 and M5 in the transistors M23 and M24 of the cutoff signal output unit 25, the potential at the common connection point N22 is The voltage drops to a potential of approximately 0 V, and an L level voltage signal Vcut1 is output. Therefore, the transistors M21 and M22 of the output shut-off unit 24 are turned off so that the drive control of the transistor M1 is not affected.

  Next, the operation in the process of raising the input voltage VDD will be described. Until the input voltage VDD reaches the minimum operating voltage VDDmin (between time t0 and time t2 in FIG. 3), the input voltage VDD that can sufficiently drive the transistors M2 to M6 is applied between the power supply lines 9 and 10. It has not been. For this reason, almost no drain current flows through the transistors M2 and M3. Therefore, the control amplifier 23 cannot operate normally, and the error amplification signal Aout that is an output thereof is indefinite.

  On the other hand, the transistors M23 and M24 of the shut-off signal output unit 25 have almost no current flowing in the same way as the transistors M2 and M3. Therefore, the potential at the common connection point N22 rises to approximately VDD, and the H level voltage signal Vcut1 is output. Is done. In the present embodiment, the H level voltage signal Vcut1 corresponds to a cutoff signal. The transistors M21 and M22 are turned on by the H level voltage signal Vcut1, and the transistor M1 is controlled to be in a current cutoff state. In this way, while the error amplification signal Aout output from the control amplifier 23 is indefinite (between times t0 and t2), the output voltage Vout at the power supply output terminal 5 does not rise from 0V and is kept constant at 0V. Be drunk.

  While the input voltage VDD is less than the threshold voltage VT (M21) of the transistor M21 (between times t0 and t1), the transistors M21 and M22 cannot be turned on by the voltage signal Vcut1. However, at this time, since the potential of the power supply line 9 is also substantially the same as the voltage signal Vcut1, even if the error amplification signal Aout is 0V, the gate-source voltage of the transistor M1 is less than the threshold voltage. Thus, the transistor M1 is not turned on. Therefore, the output voltage Vout is kept constant at 0V during this time.

As described above, according to the present embodiment, the following effects can be obtained.
In the power supply circuit 22, the sum of currents I (M2) and I (M3) actually flowing through the transistors M2 and M3 of the differential amplifier circuit 11 in the control amplifier 23 is the current I supplied from the transistor M6 to the transistors M2 and M3. When less than (M7), that is, when each of the transistors M2 to M6 of the differential amplifier circuit 11 is not sufficiently driven, the H level voltage signal Vcut1 that is a cutoff signal is output, and the transistor M1 is set in a current cutoff state. Control.

  More specifically, the drains of the transistors M23 and M24 of the cutoff signal output unit 25 are connected in common and connected to the power supply line 9 via the resistor R22, and the common connection point N22 between the resistor R22 and the transistors M23 and M24. Is the output terminal of the voltage signal Vcut1. Each current flowing in the transistors M2 and M3 is configured to flow to the transistors M23 and M24 via the current mirror circuit. Accordingly, the potential of the common connection point N22, that is, the level of the voltage signal Vcut1 changes according to the operating state of the control amplifier 23.

  As a result, when the input voltage VDD is lower than the minimum operating voltage VDDmin (2 V) of the control amplifier 23 when the power is turned on, the transistors M2 to M6 of the differential amplifier circuit 11 cannot be driven sufficiently and are output from the control amplifier 23. Even if the error amplification signal Aout becomes indefinite, the transistor M1 is controlled to be in a current cutoff state, so that a state in which the output voltage Vout becomes indefinite can be prevented.

  By preventing an indefinite state of the output voltage Vout, the output voltage Vout overshoots when the input voltage VDD is lower than the minimum operating voltage VDDmin and higher than the target voltage (1.5 V) of the output voltage Vout. It can be prevented that the voltage is temporarily higher than 1.5 V and an excessive voltage is applied to the 1.5 V system element of the digital circuit 3 to which the output voltage Vout is supplied.

  If the current supplied to the transistors M2 and M3 including the variation of the resistance value of the resistor R22 is equal to the current actually flowing through the transistors M2 and M3, the potential of the common connection point N22 becomes approximately 0V. Was set as follows. Thus, when the control amplifier 23 is operating normally, the L level voltage signal Vcut1 can be reliably output, and the error amplification signal Aout output from the control amplifier 23 can be applied to the gate of the transistor M1. The steady operation of the circuit 22 is not hindered.

  The transistor M1 is controlled to be in a current cutoff state via the transistors M21 and M22 which can be turned on by the H level voltage signal Vcut1. As a result, even when the transistor M1 cannot be directly driven, it can be reliably turned off by the H level voltage signal Vcut1.

(Second Embodiment)
FIG. 4 is an electrical configuration diagram of the control amplifier showing the second embodiment of the present invention. The control amplifier 31 (corresponding to a voltage control circuit) shown in FIG. 4 is different from the control amplifier 23 shown in FIG. 2 in that a cutoff signal output unit 32 is provided instead of the cutoff signal output unit 25. The other components are the same, and are given the same reference numerals as in FIG.

  As shown in FIG. 4, in the cutoff signal output unit 32, the drains of the transistors M23 and M24 are connected to the power line 9 via a P-channel MOS transistor M31. The transistor M31 and the transistor M7 of the constant current circuit 12 have their sources and gates connected to form a current mirror circuit 33 (corresponding to a constant current circuit). Further, the W / L of the transistor M31 is set to a smaller value than the W / L of the transistor M7.

A current I (M31) corresponding to the current I (M7) flowing through the transistor M7 flows through the transistor M31. This current I (M31) has a gate width ratio between the transistors M7 and M31 under the same gate length. When expressed as W (M31) / W (M7), it is expressed by the following equation (4).
I (M31) = I (M7) × W (M31) / W (M7) (4)

  Note that the gate widths of the transistors M7 and M31 are such that when the sum of the currents flowing through the transistors M23 and M24 is less than the current I (M7) supplied to the transistors M2 and M3, the potential at the common connection point N22 is set to the transistor M21. Is set to flow a current I (M31) required to make the transistor M31 into a potential that can be reliably turned on (approximately VDD).

According to the said structure, there exist the following effects and effects.
In the case where the transistors M2 to M6 of the differential amplifier circuit 11 are not sufficiently driven and the error amplification signal Aout becomes indefinite, the control amplifier 31 does not cause a current to flow through the transistors M23 and M24. Current I (M31) corresponding to the current I (M7) flows. Accordingly, the potential at the common connection point N22 rises to approximately VDD, and the H level voltage signal Vcut1 is output. As a result, the transistor M1 is controlled to be in a current cutoff state, so that the output voltage Vout can be kept constant at 0V while the error amplification signal Aout is indefinite.

  On the other hand, when the control amplifier 31 is operating normally, that is, the current I (M7) supplied to the transistors M2 and M3 of the differential amplifier circuit 11 and the currents I (M2) and I that actually flow through the transistors M2 and M3. When (M3) is equal, the sum of the currents flowing through the transistors M23 and M24 is equal to I (M7). Since the sum of the currents flowing through the transistors M23 and M24 is larger than the current I (M31) flowing through the transistor M31, the potential at the common connection point N22 drops to a potential of approximately 0V, and the L level voltage signal Vcut1 is output. Is done. As a result, the transistors M21 and M22 are turned off, and the drive control of the transistor M1 is not affected.

  The control amplifier 31 of the present embodiment sets the ratio of the gate widths of the transistors M7 and M31 instead of the design that requires high accuracy, that is, the resistance value design including variations in the first embodiment. Thus, the same effect as that of the first embodiment can be obtained. Further, since the area necessary for forming the transistor M31 on the LSI 21 chip is smaller than the area necessary for disposing the resistor R22 in the first embodiment, the power supply circuit 22 is included in the LSI 21 chip. The area occupied can be reduced.

(Third embodiment)
5 and 6 show a third embodiment of the present invention, and FIG. 5 is a view corresponding to FIG. 1 in the first embodiment. The power supply circuit 41 shown in FIG. 5 includes a reference voltage generation circuit 42 instead of the reference voltage generation circuit 7 with respect to the power supply circuit 22 shown in FIG. The difference is that 43 is provided. Other components are the same, and are given the same reference numerals as in FIG.

  The reference voltage generation circuit 42 is a bandgap reference voltage circuit that generates the reference voltage Vref, similarly to the reference voltage generation circuit 7, and further includes an output terminal for the voltage signal Vcutb2. The output cutoff unit 43 includes a P-channel type MOS transistor M41 (corresponding to a cutoff transistor). The transistor M41 is connected between the gate and source of the transistor M1, and a voltage signal Vcutb2 output from the reference voltage generation circuit 42 is supplied to the gate of the transistor M41.

  FIG. 6 shows the electrical configuration of the reference voltage generation circuit 42. The reference voltage generating circuit 42 shown in FIG. 6 operates by receiving power from the power lines 9 and 10, and an input voltage VDD is applied between the power lines 9 and 10. The reference voltage generation circuit 42 includes a reference voltage generation circuit 44 including transistors M42 to M48, resistors R41 and R42 and a diode D41, a startup circuit 45 including transistors M49 and M50, a resistor R43 and a capacitor C41, a transistor M51 and a resistor R44. And a cut-off signal output unit 46.

  In this embodiment, the cutoff signal output unit 46 and the output cutoff unit 43 described above constitute an output cutoff circuit. Among the transistors described above, the transistors M42 to M45 are N-channel MOSFETs, and the transistors M46 to M51 are P-channel MOSFETs. Among these, the transistors M44 and M45 and the transistors M46 to M48 and M51 are formed so that W / L has the same value. The transistors M42 and M43 have the same gate length L, but the gate width W is set so that the W of the transistor M43 is α times the W of the transistor M42.

  In the reference voltage generation circuit 44, the source of the transistor M42 (corresponding to the first transistor) is connected to the power supply line 10, and the gate and drain are connected in common. The source of the transistor M43 (corresponding to the second transistor) is connected to the power supply line 10 via the resistor R41 (corresponding to the first resistor). The drains of the transistors M42 and M43 are connected to the power supply line 9 via transistors M44 and M45 and a current mirror circuit composed of transistors M46 and M47 (corresponding to the third and fourth transistors). The gates of the transistors M42 and M43, and M44 and M45 are connected to each other.

  The transistor M48 forms a current mirror circuit with the transistor M47, and its drain is connected to the power supply line 10 via a resistor R42 (corresponding to a second resistor) and a diode D41 connected in the forward direction. . A common connection point N41 (corresponding to an output node of the reference voltage) between the transistor M48 and the resistor R42 is an output terminal of the reference voltage Vref.

  In the start-up circuit 45, the transistor M49 (corresponding to the start-up transistor) is connected between the power supply line 9 and the drain of the transistor M42 of the reference voltage generation circuit 44. Between the gate of the transistor M49 and the power supply line 10, a resistor R43 (corresponding to a starting resistor) and a capacitor C41 are connected in parallel. Further, between the gate of the transistor M49 and the power supply line 9, the transistor M47 and a transistor M50 (corresponding to an activation control transistor) constituting a current mirror circuit are connected.

  In the cutoff signal output unit 46, the source of the transistor M51 (corresponding to the output detection transistor) is connected to the power supply line 9, and the drain is connected to the power supply line 10 via the resistor R44 (corresponding to the output detection resistor). . The transistor M51 constitutes a current mirror circuit with the transistor M47 of the reference voltage generation circuit 44. A common connection point N42 (corresponding to an output node of the cutoff signal) between the transistor M51 and the resistor R44 is an output terminal of the voltage signal Vcutb2.

  It should be noted that the resistance value of the resistor R44, including the variation thereof, can reliably turn off the transistor M41 of the output cut-off unit 43 when the predetermined operating current described later flows through the transistor M51. It is set to be such a potential (approximately the potential of VDD).

The reference voltage Vref output from the reference voltage generating circuit 42 having the above configuration represents the forward voltage of the diode D41 as VF (D41), and (gate width of the transistor M43) / (gate width of the transistor M42) is expressed by a coefficient α. And (resistance value of the resistor R42) / (resistance value of the resistor R41) is generally expressed by the following equation (5). The coefficients α and β are set such that the temperature coefficient of the reference voltage Vref is zero.
Vref = VF (D41) +. Beta .. (k.T / q) .ln.alpha. (5)
Where q is the electron charge, k is the Boltzmann constant, and T is the absolute temperature

Next, the operation of the power supply circuit 41 having the above configuration will be described focusing on the operation of the reference voltage generation circuit 42.
When the supply of power to the reference voltage generation circuit 42 is started and the input voltage VDD rises to the threshold voltage of the transistor M49 of the startup circuit 45, the transistor M49 is turned on. As a result, the gate of the transistor M42 rises to a potential of approximately VDD, and the operation of the reference voltage generation circuit 44 is forcibly started. Then, the same current as the current flowing through the transistor M47 flows through the transistor M50 of the start-up circuit 45, the capacitor C41 is charged, the gate potential of the transistor M49 rises, and the transistor M49 is eventually turned off. By such an operation of the start-up circuit 45, the time until the reference voltage generation circuit 44 becomes a steady state to be described later is shortened.

  Until the reference voltage generating circuit 44 shifts to the steady state, only a smaller current flows through the transistor M47 than the predetermined operating current in the steady state, and the potential at the common connection point N41 is indefinite. Therefore, based on the reference voltage Vref from the reference voltage generation circuit 42, the control amplifier 23 that controls driving of the transistor M1 cannot operate normally.

  At this time, in the cutoff signal output unit 46, only a current smaller than that in the steady state flows through the transistor M51 as in the transistor M47 of the reference voltage generation circuit 44. Therefore, the potential at the common connection point N42 decreases to a potential of approximately 0V. Then, the L level voltage signal Vcutb2 is output. In this embodiment, the L-level voltage signal Vcutb2 corresponds to a cutoff signal. By this L level voltage signal Vcutb2, the transistor M41 of the output cut-off unit 43 is turned on, and the transistor M1 is controlled to a current cut-off state. Accordingly, during this time, the output voltage Vout at the power supply output terminal 5 does not rise from 0V and is kept constant at 0V.

  Thereafter, when the input voltage further rises and the reference voltage generation circuit 44 shifts to a steady state, the reference voltage generation circuit 44 operates as follows. That is, a predetermined operating current flows in the transistor M47 so as to control the voltage at the common connection point N41 to the reference voltage Vref shown in the above equation (5). As a result, a reference voltage Vref having a normal voltage value (for example, 1.0 V) is applied from the reference voltage generation circuit 42 to the control amplifier 23. As a result, the control amplifier 23 operates normally, and the output voltage Vout is controlled to the target voltage (1.5 V).

  At this time, in the cutoff signal output unit 46, since a predetermined operating current flowing through the transistor M47 of the reference voltage generation circuit 44 flows through the transistor M51, the potential at the common connection point N42 rises to a potential of approximately VDD and is at the H level. Voltage signal Vcutb2 is output. Accordingly, the transistor M41 of the output shut-off unit 43 is turned off, and the drive control of the transistor M1 by the control amplifier 23 is not affected.

As described above, according to the present embodiment, the following effects can be obtained.
When the current flowing through the transistor M47 of the reference voltage generation circuit 44 in the reference voltage generation circuit 42 is less than a predetermined operating current that flows when the reference voltage generation circuit 44 is in a steady state, that is, the reference voltage generation circuit 42 When each of the 44 transistors M42 to M48 is not sufficiently driven, an L level voltage signal Vcutb2 which is a cutoff signal is output to control the transistor M1 to a current cutoff state.

  More specifically, the transistor M51 and the resistor R44 of the cutoff signal output unit 46 are connected between the power supply lines 9 and 10, and the common connection point N42 between the transistor M51 and the resistor R44 is used as the output terminal of the voltage signal Vcutb2. The current flowing in the transistor M47 is configured to flow to the transistor M51 via the current mirror circuit. Accordingly, the potential of the common connection point N42, that is, the level of the voltage signal Vcutb2 changes according to the operating state of the reference voltage generation circuit 42. As a result, even if the reference voltage Vref output from the reference voltage generation circuit 42 becomes indefinite until the reference voltage generation circuit 44 shifts to a steady state at the time of power-on, the transistor M1 is set in a current cutoff state. Since the control is performed, it is possible to prevent a state in which the output voltage Vout is indefinite, and thus, application of an excessive voltage to the digital circuit 3.

(Fourth embodiment)
FIGS. 7 and 8 show a fourth embodiment of the present invention and are equivalent to FIGS. 5 and 6 in the third embodiment. The power supply circuit 61 shown in FIG. 7 includes a reference voltage generation circuit 62 instead of the reference voltage generation circuit 42 with respect to the power supply circuit 41 shown in FIG. 63 is different. The other components are the same, and are given the same reference numerals as in FIG.

  The reference voltage generation circuit 62 includes an output terminal for the voltage signal Vcut2 instead of the output terminal for the voltage signal Vcutb2 in the reference voltage generation circuit 42. The output cutoff unit 63 includes an N-channel type MOS transistor M61 (corresponding to a cutoff transistor) instead of the P-channel type MOS transistor M41 in the output cutoff unit 43. The transistor M61 is connected in parallel with the transistor M21, and a voltage signal Vcut2 output from the reference voltage generation circuit 62 is supplied to the gate of the transistor M61.

  FIG. 8 shows an electrical configuration of the reference voltage generation circuit 62. The reference voltage generation circuit 62 includes a cutoff signal output unit 64 including a P-channel type MOS transistor M62 and a resistor R61 instead of the cutoff signal output unit 46 in the reference voltage generation circuit 42 shown in FIG. In the present embodiment, the cutoff signal output unit 64 and the output cutoff unit 63 described above constitute an output cutoff circuit.

  In the cutoff signal output unit 64, the source of the transistor M62 (corresponding to the activation detection transistor) is connected to the power supply line 9, and the drain is connected to the power supply line 10 via the resistor R61 (corresponding to the activation detection resistor). . The gate of the transistor M62 is connected to the transistor M49 of the startup circuit 45. A common connection point N61 (corresponding to an output node of the cutoff signal) between the transistor M62 and the resistor R61 is an output terminal of the voltage signal Vcut2.

  Note that the resistance value of the resistor R61 includes the variation, and the potential at the common connection point N61 when the transistor M62 is in the on state can reliably drive the transistor M61 of the output cutoff unit 63 on (approximately the potential of VDD). It is set to be.

According to the said structure, there exist the following effects and effects.
The reference voltage Vref output from the reference voltage generation circuit 62 is a normal voltage value (for example, 1.0 V) while the start-up circuit 45 is operating even when current starts to flow through the reference voltage generation circuit 44. There is no possibility.

  At this time, since the transistor M62 is turned on in the cutoff signal output unit 64, the potential at the common connection point N61 rises to a potential of approximately VDD, and the H level voltage signal Vcut2 is output. In the present embodiment, the H level voltage signal Vcut2 corresponds to a cutoff signal. By this H level voltage signal Vcut2, the transistor M61 of the output cutoff unit 63 is turned on, and the transistor M1 is controlled to a current cutoff state. Accordingly, during this time, the output voltage Vout at the power supply output terminal 5 does not rise from 0V and is kept constant at 0V.

Thereafter, when the transistor M49 is turned off and the start-up operation is completed, the reference voltage generation circuit 62 outputs a normal reference voltage Vref. As a result, the control amplifier 23 operates normally and the output voltage Vout is controlled to the target voltage (1.5 V).
At this time, since the transistor M62 is also turned off in the cutoff signal output unit 64, the potential of the common connection point N61 is reduced to a potential of approximately 0 V, and the L-level voltage signal Vcut2 is output. Accordingly, the transistor M61 of the output shut-off unit 63 is turned off, and the drive control of the transistor M1 by the control amplifier 23 is not affected.

  The reference voltage generation circuit 62 of the present embodiment controls the transistor M1 to be in a current cutoff state when the reference voltage Vref output from the reference voltage generation circuit 62 is not a normal voltage value until the start-up operation is completed. Therefore, it is possible to prevent a state in which the output voltage Vout is indefinite, and thus application of an excessive voltage to the digital circuit 3.

(Fifth embodiment)
9 and 10 show a fifth embodiment of the present invention, and FIG. 9 is a view corresponding to FIG. 1 in the first embodiment. The power supply circuit 71 shown in FIG. 9 is provided with a reference voltage generation circuit 72 instead of the reference voltage generation circuit 7 with respect to the power supply circuit 22 shown in FIG. The difference is that 73 is provided. Other components are the same, and are given the same reference numerals as in FIG.

  The reference voltage generation circuit 72 includes an output terminal for the voltage signal Vcutb2 of the reference voltage generation circuit 42 in the third embodiment and an output terminal for the voltage signal Vcut2 of the reference voltage generation circuit 62 in the fourth embodiment. . The output cutoff unit 73 includes a transistor M41 of the output cutoff unit 43 in the third embodiment and a transistor M61 of the output cutoff unit 63 in the fourth embodiment (see FIGS. 5 and 7).

  FIG. 10 shows an electrical configuration of the reference voltage generation circuit 72. The reference voltage generation circuit 72 shown in FIG. 10 includes the cutoff signal output unit 46 of the reference voltage generation circuit 42 in the third embodiment and the cutoff signal output unit 64 of the reference voltage generation circuit 62 in the fourth embodiment. Provided (see FIG. 6 and FIG. 8). In the present embodiment, the cutoff signal output units 46 and 64 and the output cutoff unit 73 described above constitute an output cutoff circuit. That is, the power supply circuit 71 of the present embodiment includes both elements that constitute the output cutoff circuit of the third embodiment and elements that constitute the output cutoff circuit of the fourth embodiment.

According to the said structure, there exist the following effects and effects.
When the reference voltage generation circuit 44 has not shifted to the steady state, or when the startup circuit 45 is operating even in the steady state, the reference voltage Vref output from the reference voltage generation circuit 72 is indefinite or There is a possibility that the voltage value is not normal (for example, 1.0 V). Therefore, in this embodiment, in any of the above cases, the transistor M1 is turned on by the L level voltage signal Vcutb2 output from the cutoff signal output unit 46 or the H level voltage signal Vcut2 output from the cutoff signal output unit 64. Control to shut off. As a result, the output voltage Vout at the power output terminal 5 is kept constant at 0V without increasing from 0V.

  Since the reference voltage generation circuit 72 of the present embodiment controls the transistor M1 to be in a current cutoff state regardless of whether the output reference voltage Vref is indefinite or not a normal voltage value, the third and fourth As compared with the configuration of the embodiment, the state where the output voltage Vout becomes unstable can be prevented more reliably.

(Other embodiments)
The present invention is not limited to the embodiments described above and illustrated in the drawings, and the following modifications or expansions are possible.
A cutoff transistor is connected in series with the transistor M1 between the power input terminal 4 and the power output terminal 5, and when the cutoff signal is not output from the cutoff signal output circuit, the cutoff transistor is turned on and the cutoff signal is output. In such a case, the blocking transistor may be turned off.

As the pair of differential input transistors, P-channel type MOS transistors M2 and M3 are used. Instead, N-channel type MOS transistors are used, and the conductivity type of other transistors is changed accordingly. It is good.
Although each transistor is constituted by a MOSFET, it may be constituted by a bipolar transistor.
The reference voltage generation circuit is not limited to the band gap reference voltage circuit, and may be a reference voltage circuit having another circuit configuration.

  In the output cutoff circuits of the third to fifth embodiments, the configuration for outputting the voltage signal Vcut1 and the configuration for controlling the transistor M1 to the current cutoff state by the voltage signal Vcut1 may be omitted.

The transistor M1 may be directly controlled to be in a cutoff state by a cutoff signal without using a cutoff transistor.
The current flowing in the voltage control circuit or the reference voltage generation circuit may be detected using a configuration different from that of the current mirror circuit.

1 is a schematic configuration diagram of an LSI showing a first embodiment of the present invention. Electrical configuration of control amplifier Waveform diagram showing the relationship between input / output voltage and cutoff signal FIG. 2 equivalent view showing the second embodiment of the present invention FIG. 1 equivalent view showing a third embodiment of the present invention Electrical configuration diagram of the reference voltage generation circuit FIG. 1 equivalent view showing a fourth embodiment of the present invention 6 equivalent diagram FIG. 1 equivalent view showing a fifth embodiment of the present invention 6 equivalent diagram 1 equivalent diagram showing the prior art 2 equivalent diagram 3 equivalent figure

Explanation of symbols

  In the drawing, 4 is a power input terminal, 5 is a power output terminal, 6 is a voltage detection circuit, 7 is a reference voltage generation circuit, 9 is a first power supply line, 10 is a second power supply line, and 11 is a differential amplifier circuit. , 13 is an output circuit, 22, 41, 61, 71 are power supply circuits, 23, 31 are control amplifiers (voltage control circuits), 24, 43, 63, 73 are output cutoff units (output cutoff circuits), 25, 32, 46 and 64 are cutoff signal output units (output cutoff circuits), 33 is a current mirror circuit (constant current circuit), 42, 62 and 72 are reference voltage generation circuits, 44 is a reference voltage generation circuit, 45 is a startup circuit, and C41 is Capacitor, D41 is a diode, M1 is a main transistor, M2 and M3 are a pair of differential input transistors, M4 and M5 are a pair of load transistors, M6 is a P-channel MOSFET (current source), M21, M22, M 1 and M61 are blocking transistors, M23 and M24 are a pair of detection transistors, M42 is a first transistor, M43 is a second transistor, M46 is a third transistor, M47 is a fourth transistor, and M48 is a fifth transistor. , M49 is an activation transistor, M50 is an activation control transistor, M51 is an output detection transistor, M62 is an activation detection transistor, N22, N42, and N61 are common connection points (interrupt signal output nodes), and N41 is a reference. A voltage output node, R22 is a common resistor, R41 is a first resistor, R42 is a second resistor, R43 is a start resistor, R44 is an output detection resistor, and R61 is a start detection resistor.

Claims (9)

A main transistor interposed in a power supply path between a power supply input terminal and a power supply output terminal, a voltage detection circuit that outputs a detection voltage corresponding to an output voltage at the power supply output terminal, and a reference corresponding to a target value of the output voltage In a power supply circuit having a reference voltage generation circuit that generates a voltage, and a voltage control circuit that outputs a drive signal based on the detection voltage and the reference voltage to control driving of the main transistor,
The voltage control circuit and the reference voltage generation circuit are configured to normally operate when the current flowing in the circuit of the voltage becomes a predetermined value or more,
An output cutoff circuit for outputting a cutoff signal and controlling the main transistor in a current cutoff state when a current flowing in at least one of the voltage control circuit and the reference voltage generation circuit is smaller than the predetermined value; A power supply circuit characterized by being configured. The voltage control circuit includes a differential amplifier circuit having a pair of differential input transistors and a current source for supplying a predetermined current to the pair of differential input transistors, and the driving based on a signal from the differential amplifier circuit And an output circuit that outputs a signal,
The output cutoff circuit includes a pair of detection transistors that detect currents flowing through the pair of differential input transistors, and the sum of the currents detected by the detection transistors is smaller than the predetermined current. The power supply circuit according to claim 1, wherein the power supply circuit outputs a cutoff signal. The voltage control circuit operates by receiving power from a first power supply line and a second power supply line, and the differential amplifier circuit is provided between each differential input transistor and the second power supply line. A pair of load transistors each in the form of a diode connection,
Each of the detection transistors and each of the load transistors constitutes a current mirror circuit,
The output cut-off circuit includes a common resistor connected between the first power supply line and the output node of the cut-off signal, and each of the detection cut-off circuits is provided between the output node and the second power supply line. 3. The power supply circuit according to claim 2, wherein the transistors are connected in parallel.   The common resistor outputs the cutoff signal when the sum of the currents flowing through the pair of detection transistors is smaller than the predetermined current, and the sum of the currents flowing through the pair of detection transistors becomes the predetermined current. 4. The power supply circuit according to claim 3, wherein the resistance value is set so that the cutoff signal is invalidated if they are equal.   4. The power supply according to claim 3, further comprising a constant current circuit configured to flow a constant current smaller than a predetermined current supplied to the pair of differential input transistors in place of the common resistor. circuit. The reference voltage generation circuit includes a reference voltage generation circuit that generates the reference voltage,
The output cutoff circuit detects a current flowing through the reference voltage generation circuit, and the detected current is based on an operating current flowing through the reference voltage generation circuit in a state where the reference voltage generation circuit generates the reference voltage. 6. The power supply circuit according to claim 1, wherein the cutoff signal is output when the power is small. The reference voltage generation circuit operates by receiving power supply from the first power supply line and the second power supply line,
The reference voltage generation circuit includes a first transistor grounded to the second power supply line, a second transistor having a control terminal connected to the first transistor, the second transistor, and the second transistor. A first resistor connected between two power lines, and a third transistor constituting a current mirror circuit connected between the first power line and the first and second transistors. And a fourth transistor, a fifth transistor connected between the first power supply line and the reference voltage output node and constituting a current mirror circuit with the fourth transistor, and an output node of the reference voltage And a diode and a second resistor connected in a forward direction between the first power supply line and the second power supply line,
The output cut-off circuit is connected between the first power supply line and the output node of the cut-off signal, and an output detection transistor that forms a current mirror circuit with the fourth transistor, and an output node of the cut-off signal The power supply circuit according to claim 6, further comprising an output detection resistor connected between the second power supply line. The reference voltage generation circuit operates by receiving power supply from the first power supply line and the second power supply line,
The reference voltage generation circuit includes a first transistor grounded to the second power supply line, a second transistor having a control terminal connected to the first transistor, the second transistor, and the second transistor. A first resistor connected between two power lines, and a third transistor constituting a current mirror circuit connected between the first power line and the first and second transistors. And a fourth transistor, a fifth transistor connected between the first power supply line and the reference voltage output node and constituting a current mirror circuit with the fourth transistor, and an output node of the reference voltage And a diode and a second resistor connected in a forward direction between the first power supply line and the second power supply line,
A starting transistor connected between the first power line and the first transistor, and a starting transistor connected in parallel between the control terminal of the starting transistor and the second power line A start-up circuit comprising a resistor and a capacitor, and a fourth mirror and a start-up control transistor that forms a current mirror circuit and supplies a current to the start-up resistor and the capacitor from the first power line;
The output cut-off circuit is connected between the first power line and the output node of the cut-off signal, the start-up detection transistor connected between the start-up transistor and the control terminal, and the output node of the cut-off signal The power supply circuit according to claim 6, further comprising an activation detection resistor connected between the second power supply line.   9. The power supply circuit according to claim 1, wherein the output cutoff circuit includes a cutoff transistor that drives the main transistor off when the cutoff signal is input.

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