JP4849037B2 - Automatic frequency control method and apparatus - Google Patents

Description

  The present invention relates to an automatic frequency control method and apparatus. More particularly, the present invention relates to an automatic frequency control (AFC) method and apparatus suitable for use in a digital wireless communication receiver to follow the carrier frequency of a transmission signal.

  Recently, in digital wireless communication, linear modulation that reproduces information contained in a baseband signal as a modulated wave as it is is often used from the viewpoint of good frequency utilization efficiency. In order to demodulate a modulated wave with baseband signal information added by such linear modulation on the receiving side, generally, synchronous detection or delayed detection is used as a demodulation method. In general, the receiver is provided with an AFC circuit in order to keep the reception state optimal by following the carrier frequency.

  Therefore, a configuration example of the AFC circuit used conventionally is shown in FIG. 4 and described (conventional example 1). Here, FIG. 4 is a circuit configuration diagram showing the configuration of the AFC circuit of the receiver using the delay detection method as the demodulation method.

  In FIG. 4, the delayed detection signal 11 at the symbol identification timing from a delay detection circuit (not shown) is branched into two, one input to the phase error detection circuit 20 and the other input to the subtraction circuit 40. . In this case, when the modulation method on the transmission side is π / 4 shift QPSK (quadrature phase shift keying), the signal component included therein is quaternary, but the actual delayed detection signal 11 Is a superposition of a noise component and a component due to a deviation from the carrier frequency. In the following, the delayed detection signal 11 is represented by a phase, and is represented by θ (nT) (n is an integer, T is a symbol time length).

  As described above, the delayed detection signal 11 from the delay detection circuit is branched into two, and one is input to the phase error detection circuit 20. In the phase error detection circuit 20 to which the delay detection signal 11 is input, the phase of the delay detection signal 11 is provisionally determined, and a correspondence relationship is provided between the phase of the delay detection signal 11 and the provisional determination result of the delay detection signal 11. The phase difference from the reference phase, which is an ideal signal point when there is no frequency shift, is output as the phase error signal 21 (Δθ (nT)).

Table 1 shows an example of the relationship between the delayed detection signal 11 and an ideal signal point when the delayed detection signal 11 has an 8-bit phase expression.

  In Table 1 above, if the phase of the delayed detection signal 11 input to the phase error detection circuit 20 is “36”, for example, the signal point in the temporary determination is “32”, so the phase difference is “4”. Therefore, this phase difference is output as the phase error signal 21 from the phase error detection circuit 20, and the output phase error signal 21 is sent to the averaging circuit 30.

  In the averaging circuit 30, the averaged signal 31 obtained by averaging the input phase error signal 21 (Δθ (nT)) for a certain period is used as an estimated value of the component due to the frequency shift in the delayed detection signal 11. (Hereinafter referred to as “average phase error”.) Output as Mean [Δθ (nT)].

On the other hand, in the subtraction circuit 40 to which the delay detection signal 11 from the delay detection circuit is input, the average phase error Mean [Δθ (nT)] in the delay detection signal 11 is subtracted from the delay detection signal 11 (θ (nT)). The obtained subtraction signal 41 is output as an AFC correction signal θ _out (nT) for correcting a deviation from the carrier frequency.

  The operation of the above AFC circuit will be described in more detail using mathematical expressions. Here, it is assumed that a signal modulated by π / 4 shift QPSK is subjected to delay detection.

If the signal obtained by latching the delayed detection signal 11 expressed by the phase, which is input to the phase error detection circuit 20, with the symbol clock is θ (nT) (where n is an integer and T is the symbol time length) as described above, θ (nT) is ideally four values as shown below.
θ (nT) = ± π / 4, ± 3π / 4

Therefore, assuming that θ ₀ (nT) is a signal obtained by temporarily determining θ (nT) on the cos (Δθ) axis and sin (Δθ) axis in the phase error detection circuit 20, θ ₀ (nT) is as follows. Become.
θ ₀ (nT) = ± π / 4, ± 3π / 4
In this case, the phase error signal 21 (Δθ (nT)) is expressed by the following equation.
Δθ (nT) = θ (nT) −θ ₀ (nT)

The averaging circuit 30 that has received the phase error signal 21 performs the averaging process of the phase error signal 21 at time t = nT. As an averaging process method, for example, there is a weighted average using a forgetting factor that sequentially reduces the weight of past values. When this weighted average is used, the average at time t = (n + 1) T is calculated by the following equation using the phase error signal 21 (Δθ (nT)) and the average phase error Mean [Δθ (nT)] one symbol before. A phase error Mean [Δθ {(n + 1) T}] is obtained.
Mean [Δθ {(n + 1) T}] = (1 / N) Δθ (nT)
+ {(N−1) / N} Mean [Δθ (nT)]
The averaged signal 31 obtained by the averaging circuit 30 in this way is sent to the subtracting circuit 40.

In the subtraction circuit 40, a subtraction signal 41 obtained by subtracting the average signal 31 from the delay detection signal 11 (θ (nT)) from the delay detection circuit is used as an AFC correction signal θ _OUT (nT) in which the frequency shift is corrected. Output. The AFC correction signal θ _OUT (nT) is expressed by the following equation.
θ _OUT (nT) = θ (nT) −Mean [Δθ (nT)]
= Θ (nT) − {(N−1) / N} Mean [Δθ {(n−1) T}]
− (1 / N) [θ {(n−1) T} −θ ₀ {(n−1) T}] (1)

As described above, in the AFC circuit shown in FIG. 4, the signal obtained by subtracting the average value of the phase error from the detection signal, that is, the signal obtained by substantially subtracting the component due to the deviation from the carrier frequency is used as the AFC correction signal θ _OUT (nT ), And this signal is used for decision decoding.

  FIG. 5 is a space diagram for explaining the provisional determination by the AFC circuit shown in FIG. 4, and shows a case where the modulation method on the transmission side is π / 4 shift QPSK.

  In FIG. 5, circles (white circles) indicate ideal signal points when there is no frequency deviation from the carrier frequency, and when there is no frequency deviation, the detected signals are the points A and B on the coordinate plane. , C point, or D point.

  On the other hand, ● (black circle) indicates a detection signal when there is a frequency shift, and when there is a frequency shift, the detection signal is a point A ′ or a point B ′ shifted by a phase error due to the frequency shift. , C ′ point, and D ′ point. In this case, the points A ′, B ′, C ′, and D ′ are in the same quadrant on the coordinate plane as the points A, B, C, and D when there is no frequency shift. This is not mistaken for the determination of the code assigned to each quadrant.

  However, when the frequency deviation is large, the absolute value of the phase error exceeds π / 4 radians, and the absolute value of ΔfT (Δf is the frequency deviation and T is the symbol time length) exceeds 1/8, the operation of the AFC circuit is It will not be done correctly.

  That is, for example, it is assumed that there is a phase error of + 3π / 8 radians due to a frequency shift. In that case, looking at point A when there is no phase error in FIG. 5, the detection signal shifts + 3π / 8 radians from point A on the first quadrant due to the phase error of + 3π / 8 radians, and the second The coordinates are in the quadrant.

  In this case, the AFC circuit originally determines the phase error of the detection signal from the correspondence with point A, which is an ideal signal point in the first quadrant, as point B in the second quadrant. Therefore, the phase error is judged from the corresponding relationship. Therefore, in the code determination, a place that should be correctly determined to be a code assigned to the first quadrant is erroneously determined to be a code assigned to the second quadrant.

  FIG. 6 shows an error rate characteristic of code determination in the case of the conventional example 1 shown in FIG. Here, FIG. 6 shows a case in which Conventional Example 1 is applied to a personal handy phone system (PHS) that is a simple mobile phone, where the vertical axis represents the error rate of code determination, and the horizontal axis represents the carrier. It represents the deviation from the frequency. As can be understood from the drawing, the error rate of code determination is minimized when there is no frequency shift, and the error rate characteristic is rapidly deteriorated as the frequency is shifted.

  Therefore, in another conventional example, there is a software design that does not require the development of a new large-scale integrated circuit, and that can avoid the increase in size and cost of the receiver by using a highly stable frequency reference source. The above problem is addressed by possible means (conventional example 2).

  That is, in Conventional Example 2, as the first control stage, the frequency of the local oscillation signal is controlled based on the phase error Δθ detected by receiving the delay detection signal from the delay detection circuit. At this time, the magnitude of the power value of the intermediate frequency from the mixing circuit before and after the frequency of the local oscillation signal is changed is compared to obtain determination information K indicating whether the reception level is increasing or decreasing.

Next, as the second control stage, the phase information Δθa is calculated by the following calculation formula based on the information on the phase error Δθ detected in the first control stage and the determination information K indicating increase / decrease in the reception level. Then, the frequency is controlled by the obtained phase information Δθa.
Δθa = Δθ− (π / 2) × K × sign (Δθ)
In the above equation, when the reception level increases, K = 0, when the reception level decreases, K = 1, and sign (x) is a function representing the sign of the factor x (sign (x) = + 1: x>) 0, sign (x) = − 1: x <0, sign (x) = 0: x = 0).

  Here, when the absolute value of the phase error Δθ is smaller than π / 4 radians, the frequency of the local oscillation signal follows the frequency of the received signal and the frequency error Δf = 0 in the first control stage. Since the reception power is maximized, the reception level increases. Therefore, since K = 0, from the above formula, Δθa = Δθ. Therefore, in the second control stage, the same process as in the first control stage, that is, the frequency of the local oscillation signal is changed by -Δf corresponding to -Δθ.

On the other hand, when the absolute value of the phase error Δθ is greater than or equal to π / 4 radians and smaller than π / 2 radians, the phase error Δθ is erroneously determined to be −Δθ ′ in the first control stage, and the frequency of the local oscillation signal is Since it changes in a direction away from the frequency of the reception signal, the reception level decreases. Therefore, since K = 1, from the above formula,
Δθa = −Δθ ′ − (π / 2) × 1 × (−1) = − Δθ ′ + π / 2 = Δθ
It becomes. Therefore, in the second control stage, the frequency of the local oscillation signal is changed by −Δf corresponding to −Δθ.

  As described above, in Conventional Example 2, the power level of the intermediate frequency from the mixing circuit before and after the frequency of the local oscillation signal is changed is compared to determine the increase or decrease of the reception level. The frequency of the oscillation signal is controlled.

In addition to the conventional examples 1 and 2 that correct the frequency shift using the AFC circuit described above, the frequency shift using the pilot symbols (known symbols) inserted on the transmitter side without using the AFC circuit. There is a method to correct this. The method described in Japanese Patent Laid-Open No. 10-271179 is one example (conventional example 3), and in this conventional example 3, the receiver periodically inserts the detected base band in the transmitter side. A pilot symbol is detected, and pilot symbol timing and symbol timing are detected from the detected pilot symbol. Then, the phase fluctuation amount from the previous pilot symbol is measured at the detected pilot symbol timing to obtain the average phase fluctuation amount. Therefore, the frequency shift is estimated from the obtained average phase fluctuation amount, and the frequency shift is corrected by performing antiphase rotation by an amount corresponding to the frequency shift.
JP 2001-237906 A JP-A-10-271179

  According to the conventional example 1 shown in FIG. 4, as described with reference to FIG. 5, the provisional determination of the detection signal is performed using the cos (Δθ) axis and the sin (Δθ) axis. As a result, the noise margin in the tentative determination decreases, and the error rate characteristic deteriorates.

  In particular, in PHS, π / 4 shift QPSK is used as a modulation method on the transmission side. If a phase error of π / 4 radians or more occurs between symbols due to a frequency shift, an error occurs in provisional determination of a detection signal. However, this cannot be corrected. That is, correct frequency control can be performed only when the absolute value of the phase error is smaller than π / 4 radians.

  The limit value of the error rate in this PHS is 12.6 ppm, and when the frequency shift approaches this limit value, the error rate increases rapidly as shown in FIG. Further, according to the PHS standard, a frequency shift of up to 6 ppm can occur, but even in this case, the error rate characteristic is degraded by about 1 dB.

  As described above, in the conventional example 1 shown in FIG. 4, when the frequency shift occurs, the error rate in the temporary determination for obtaining the phase error deteriorates. Therefore, even within the frequency pull-in range of the AFC circuit, the error is about 1 dB. There was a problem to be solved that the rate characteristics deteriorated.

  On the other hand, Conventional Example 2 uses a means for correcting the frequency shift by comparing the power values of the intermediate frequency from the mixing circuit before and after the frequency is controlled. However, since the fluctuation of the power value from the mixing circuit due to the frequency shift is very small, it is not always easy to detect this, and the problem to be solved that is extremely difficult in practice is the conventional example 2. Is left behind.

  In addition, the pilot symbols periodically inserted at the transmitter side are detected at the receiver, the phase fluctuation amount is measured to obtain the average phase fluctuation amount, and the frequency deviation is estimated from the obtained average phase fluctuation amount. Thus, in the case of the conventional example 3 in which the correction is performed, it is necessary to use a configuration for periodically inserting pilot symbols in the transmitter. Therefore, when the structure of the frame format in which pilot symbols are periodically inserted on the transmitter side, such as PHS, is not used for the transmission signal, Conventional Example 3 cannot be applied. There was an unsolved problem that the application would be limited.

  Accordingly, the present invention has been made in view of the above problems. Therefore, in the present invention, the following means are used. That is, an average signal, which is an estimated value of a component due to a frequency shift from the carrier frequency of the transmission signal, is subtracted from the detection signal to obtain a subtraction signal. An error signal is obtained by detecting a difference between the obtained subtraction signal and a signal point set as a reference as an error. The obtained error signal is averaged for a predetermined period to obtain an averaged signal. The means as described above were used.

  According to the present invention, when the temporary determination for obtaining the error signal due to the frequency shift is performed using the coordinate axis, the coordinate axis is rotated by the estimated value of the frequency shift. The error rate characteristic of the judgment does not deteriorate. The error rate characteristics are almost flat within the frequency pull-in range, and even if there is a frequency shift, the error rate does not deteriorate.

  Further, the AFC circuit according to the present invention only needs to be incorporated in an LSI (Large Scale Integrated Circuit) used in the receiver, and it is not necessary to use a frame format having a different configuration for the transmission signal in the transmitter. Therefore, in the case of PHS, there is no need to change the existing frame format, and it can be used as it is.

  In addition, since a simple circuit change is sufficient, it is possible to meet the demand for low cost without increasing the circuit scale. Therefore, the effect brought about by the present invention is extremely large in practical use.

  In the frequency control according to the present invention, the subtracted signal obtained by subtracting the averaged signal, which is the estimated value of the component due to the frequency deviation from the carrier frequency of the transmission signal, from the detection signal, and the signal point set as the reference Is detected as an error signal. The detected error signal is averaged for a predetermined period to obtain an averaged signal. Hereinafter, the embodiment will be described in detail.

  A circuit configuration of an embodiment of the present invention will be described with reference to FIG. Here, FIG. 1 shows the configuration of the AFC circuit used in the receiver using the delay detection method as in the conventional example 1 shown in FIG. 4, and the same components as those in FIG. Are given the same reference numerals.

  In FIG. 1, a delay detection signal 11 at a symbol identification timing from a delay detection circuit (not shown) is input to a subtraction circuit 40. Here, the delayed detection signal 11 input to the subtraction circuit 40 is represented by a phase, and is represented by θ (nT) (n is an integer, T is a symbol time length).

The subtracting circuit 40 also receives the averaged signal 31 from the averaging circuit 30 and subtracts the averaged signal 31 from the delayed detection signal 11. The averaged signal 31 here is an estimated value of the component due to the average phase error Mean [Δθ (nT)], that is, the frequency shift in the delayed detection signal 11 (θ (nT)). The subtraction signal 41 obtained here is output from the subtraction circuit 40 as an AFC correction signal θ _OUT (nT) for correcting the frequency shift.

The AFC correction signal θ _OUT (nT) output from the subtraction circuit 40 is input to the phase error detection circuit 20. In the phase error detection circuit 20 performs temporary decision of the AFC correction signal θ _OUT (nT), and AFC correction signal θ _OUT (nT), a correspondence relation to the temporary decision result, the reference phase and an ideal signal point Is output as a phase error signal 21 (Δθ (nT)). As the phase error signal 21, for example, the lower N bits (N is a natural number) are extracted from the delayed detection signal 11, and the most significant bit (MSB) obtained by bit inversion is transmitted.

As already described, the signal component included in the detection signal when the modulation method on the transmission side is π / 4 shift QPSK is quaternary, and therefore the signal component of the AFC correction signal θ _OUT (nT) is quaternary. Thus, the actual AFC correction signal θ _OUT (nT) is obtained by superimposing a noise component and a component caused by a frequency shift thereon.

Table 2 shows an example of the relationship between the AFC correction signal θ _OUT (nT) and an ideal signal point when the AFC correction signal θ _OUT (nT) is an 8-bit phase expression.

In Table 2 above, when the phase of the AFC correction signal θ _OUT (nT) is, for example, “36”, the signal point in the temporary determination is “32”, so the phase difference is “4”. Therefore, this phase difference is output from the phase error detection circuit 20 as the phase error signal 21 (Δθ (nT)), and the output phase error signal 21 is sent to the averaging circuit 30.

The averaging circuit 30 outputs an averaged signal 31 obtained by averaging the input frequency shift signal Δθ _Offset (nT) for a certain period as an average phase error Mean [Δθ (nT)]. As an averaging method, for example, there is a weighted average using a forgetting factor.

  The operation of the AFC circuit according to the present invention will be described in more detail using mathematical expressions. In the following description, it is assumed that a signal modulated by π / 4 shift QPSK is subjected to delay detection. A signal obtained by latching the delayed detection signal 11 expressed in phase with a symbol clock is represented by θ (nT) (where n is an integer and T is a symbol time length).

The delay detection signal 11 (θ (nT)) ideally has four values as shown below.
θ (nT) = ± π / 4, ± 3π / 4

Further, the AFC correction signal θ _OUT (nT) in which the frequency shift is corrected is expressed by the following equation.
θ _OUT (nT) = θ (nT) −Mean [Δθ (nT)]

Therefore, if the signal obtained by determining the AFC correction signal θ _OUT (nT) on the cos (Δθ) axis and the sin (Δθ) axis is θ ′ ₀ (nT), θ ′ ₀ (nT) is as follows: Become.
θ ′ ₀ (nT) = ± π / 4, ± 3π / 4
In this case, the phase error signal 21 (Δθ (nT)) is expressed by the following equation.
Δθ (nT) = θ _OUT (nT) −θ ′ ₀ (nT)
= Θ (nT) −Mean [Δθ (nT)] − θ ′ ₀ (nT)

The averaging circuit 30 that has received the phase error signal 21 performs the averaging process of the phase error signal 21 at time t = nT. As an averaging process method, for example, there is a weighted average using a forgetting factor that sequentially reduces the weight of past values. When this weighted average is used, the average at time t = (n + 1) T is calculated by the following equation using the phase error signal 21 (Δθ (nT)) and the average phase error Mean [Δθ (nT)] one symbol before. A phase error Mean [Δθ {(n + 1) T}] is obtained.
Mean [Δθ {(n + 1) T}] = (1 / N) Δθ (nT)
+ {(N−1) / N} Mean [Δθ (nT)]
The averaged signal 31 obtained by the averaging circuit 30 in this way is sent to the subtracting circuit 40.

In the subtraction circuit 40, a subtraction signal 41 obtained by subtracting the average signal 31 from the delay detection signal 11 (θ (nT)) from the delay detection circuit is used as an AFC correction signal θ _OUT (nT) in which the frequency shift is corrected. Output. The AFC correction signal θ _OUT (nT) is expressed by the following equation.
θ _OUT (nT) = θ (nT) −Mean [Δθ (nT)]
= Θ (nT) − {(N−1) / N} Mean [Δθ {(n−1) T}]
− (1 / N) [θ {(n−1) T} −θ ′ ₀ {(n−1) T}] (2)

Comparing the equation (2) with the equation (1) (paragraph number 0014) shown in the description of the conventional example 1 in FIG. 4, the AFC correction signals θ _OUT of the AFC circuits in the conventional example 1 and the present embodiment are compared. The only difference in (nT) is that the signals (θ ₀ (nT), θ ′ ₀ (nT)) determined on the cos (Δθ) axis and the sin (Δθ) axis are different.

  FIG. 2 is a space diagram for explaining the provisional determination by the AFC circuit shown in FIG. 1, and shows a case where the modulation method on the transmission side is π / 4 shift QPSK.

  In FIG. 2, ◯ (white circle) indicates an ideal signal point when there is no frequency deviation from the carrier frequency, and ● (black circle) indicates a detection signal when there is a frequency deviation. In the AFC circuit according to the present invention, the phase error due to the frequency shift is subtracted from the delayed detection signal 11 to make a temporary determination using the signal after correction.

  That is, in Conventional Example 1 shown in FIG. 4, provisional determination is performed with the coordinate axes represented by solid lines, whereas in the AFC circuit in this embodiment, rotation is performed by the average phase error Mean [Δθ (nT)]. The provisional determination is performed with the coordinate axes indicated by the one-dot chain line. Therefore, even if the phase error due to the frequency deviation exceeds π / 4 radians, it is within a certain limit. It is possible to correctly perform provisional determination of the detection signal.

  FIG. 3 shows the error rate characteristics of the respective code determinations according to the embodiment shown in FIG. 1 and the conventional example 1 shown in FIG. Here, FIG. 3 shows the case where the present embodiment and the conventional example 1 are applied to the PHS, the vertical axis represents the error rate of the code determination, and the horizontal axis represents the deviation from the carrier frequency. Yes. Further, the error rate characteristics expressed using □ (squares) indicate the case according to the present embodiment, and the error rate characteristics expressed using ● (black circles) indicate the case according to Conventional Example 1.

  As described above, the limit value of the error rate in PHS is 12.6 ppm, and when this limit value is exceeded, the phase rotates by π / 4 radians or more during one symbol due to frequency shift. For this reason, when the frequency deviation approaches the limit value, the error rate increases rapidly as described in the conventional example 1 with reference to FIG.

  On the other hand, according to the AFC circuit in the present embodiment, as shown in FIG. 3, a flat characteristic is obtained up to about ± 12.6 ppm. Further, according to the PHS standard, a frequency shift of up to 6 ppm can occur. However, according to the AFC circuit in this embodiment, there is no deterioration in error rate characteristics within this range.

  In the above, the case where the detection signal is expressed by a phase has been described. However, the present invention is not limited to this, and the present invention can also be applied to the case where the detection signal is expressed by a vector.

  According to the conventional example 1 shown in FIG. 4, the frequency pull-in range is ± 1 / (8T) (T is the symbol time length) or less when the modulation method is QPSK. On the other hand, in the case of the method of controlling the voltage of the reference oscillator as in Conventional Example 2, the case of Conventional Example 3 and the case of the present invention, it is determined by the frequency range for initial supplementation of the transmission signal. That is, coarse adjustment is performed with initial supplementation, and the residual is finely adjusted. The frequency acquisition of initial supplementation is determined by the pattern of the preamble signal. In the case of PHS, it is ± 1 / (4T), which is the same in the case of the method of controlling the voltage of the reference oscillator and the case of the present invention.

  The frequency pulling accuracy is determined by phase error detection accuracy, which is determined by digital processing accuracy and phase error averaging processing. In the case of the conventional example 1 shown in FIG. 4, there is no essential difference in performance between the case of using the method of controlling the voltage of the reference oscillator, the case of the conventional example 3, and the case of the present invention. The fact that the case according to the conventional example 1 and the case according to the present invention are the same is as described using mathematical formulas.

  The frequency pull-in time is determined by the preamble signal pattern in the method of initially capturing the transmission signal, and the phase error averaging process parameter is determined in accordance with the preamble signal pattern. There is no substantial difference between the case where the voltage is controlled by the method, the case according to the conventional example 3 and the case according to the present invention.

It is a circuit block diagram of one Example of this invention. It is a space diagram for demonstrating operation | movement of the Example shown in FIG. FIG. 5 is an error rate characteristic diagram showing an error rate of each code determination in the case of the embodiment shown in FIG. 1 and the conventional example 1 shown in FIG. 4. It is a circuit block diagram of the prior art example 1. 5 is a space diagram for explaining the operation of Conventional Example 1 shown in FIG. It is an error rate characteristic figure which shows the error rate of the code determination at the time of based on the prior art example 1 shown in FIG.

Explanation of symbols

11 Delay detection signal 20 Phase error detection circuit 21 Phase error signal 30 Averaging circuit 31 Averaging signal 40 Subtraction circuit 41 Subtraction signal

Claims (2)

A subtraction signal (41) is obtained by subtracting an average signal (31), which is an estimated value of a component caused by a frequency shift from the carrier frequency of the transmission signal, from a detection signal (11) expressed by a phase in a receiver of digital wireless communication. ) To obtain a subtraction process (40)
A difference between the subtracted signal and a signal point set as a reference is detected as an error, and lower N bits (N is a natural number) are extracted from the detected signal, and the most significant bit of the lower N bits is bit-inverted an error detection process of the order to the output as an error signal (21) to (20),
An automatic frequency control method of performing an averaging process (30) for averaging the error signal for a predetermined period to obtain the averaged signal. A subtraction signal (41) is obtained by subtracting an average signal (31), which is an estimated value of a component caused by a frequency shift from the carrier frequency of the transmission signal, from a detection signal (11) expressed by a phase in a receiver of digital wireless communication. ) and subtraction means for obtaining (40),
A difference between the subtracted signal and a signal point set as a reference is detected as an error, and lower N bits (N is a natural number) are extracted from the detected signal, and the most significant bit of the lower N bits is bit-inverted and error detection means for order to output an error signal (21) to (20),
Averaging means (30) for averaging the error signal for a predetermined period to obtain the averaged signal ;
Including automatic frequency control device .

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