JP4872222B2 - Method for manufacturing heterojunction bipolar transistor - Google Patents

Description

The present invention relates to a method of manufacturing a heterojunction bipolar transistor (HBT ) .

  In a heterojunction bipolar transistor (HBT), the collector layer and the base layer formed on the sub-collector layer are formed in a mesa shape to reduce the area of the base-collector junction capacitance, thereby improving the high speed. Various structures have been proposed (see, for example, Patent Document 1).

8A and 8B are a schematic plan view of an example of an HBT having a conventional base-collector mesa structure and a cross-sectional view thereof taken along the line BB. This HBT has a subcollector layer 101 on a semi-insulating semiconductor substrate 100, for example, and a base / collector mesa 104 formed by stacking a collector layer 102 and a base layer 103 on the subcollector layer 101, The pattern is formed in a convex pattern, and an emitter mesa 107 formed by stacking an emitter layer 105 and an emitter cap layer 106 thereon is formed on the U-shaped pattern, for example, and an ohmic pattern is formed on the cap layer 106. An emitter electrode 108 to be contacted is formed.
The base electrode 109 is in ohmic contact with the base layer 103 exposed in the U-shaped putter of the emitter mesa 107. The end portion of the base electrode 109 extends to the tip of the convex protrusion of the base layer 103, and a pad portion 109P that is in contact with the wiring layer is formed, although not shown.

In the HBT having this configuration, the peripheral edge 104e of the base mesa (the base / collector mesa 104 in this example) is formed along the peripheral edge 108e of the emitter electrode 108.
In the case of this configuration, the peripheral portion 104e of the base collector mesa 104 is usually set to the emitter electrode 108e in consideration of patterning mask alignment errors in the base mesa, that is, the base collector mesa 104 forming step and the emitter electrode 108 forming step. Therefore, the shape and dimensions are increased to increase the area by a width W having a required margin.
Therefore, in this case, there are problems of an increase in the base-collector junction area and an increase in the area occupied by the base-collector mesa.
JP-A-5-136159

As described above, the present invention solves the above-described problem of increasing the base area in a method of manufacturing a heterojunction bipolar transistor having a portion in which a base peripheral portion is disposed along a peripheral portion of an emitter electrode. , it weighed a reduction in parasitic capacitance, and to enhance the high speed, to provide a method of manufacturing a heterojunction bipolar transitional scan data.

  A method of manufacturing a heterojunction bipolar transistor according to the present invention includes a step of laminating a semiconductor layer having a collector layer, a base layer, and an emitter layer on a substrate, and an emitter electrode having a required pattern on the semiconductor layer. A step of forming, an etching step of forming an emitter mesa having an undercut portion formed under the periphery of the emitter electrode using the emitter electrode as a mask, and applying a photoresist covering the inside of the undercut portion and the base mesa forming portion. A step of exposing the photoresist to pattern exposure by shielding the base mesa forming portion outside the emitter electrode, a non-exposed portion of the photoresist other than the pattern exposed portion, and the emitter A development process that leaves an unexposed portion of the undercut portion under the electrode; And etching the base layer with the emitter electrode as a mask to form a base mesa, and an etching process for forming a base mesa in which the peripheral edge along the peripheral edge of the emitter electrode is self-aligned with the peripheral edge of the emitter electrode. It is characterized by having.

  The present invention is also characterized in that, in the above-described method of manufacturing a heterojunction bipolar transistor, the collector layer is etched following the base mesa etching step to form a base collector mesa.

  This manufacturing method of the present invention is a heterojunction bipolar transistor having a configuration in which no margin of width W exists between both peripheral portions by employing a method in which the peripheral portion of the emitter electrode is formed in a self-alignment manner. And the area of the base mesa is reduced.

Further, according to the manufacturing method of the present invention, since the emitter electrode is used as a mask, a self-alignment method is performed in which the base mesa or the base collector mesa is etched to form the peripheral edge along the peripheral edge of the emitter electrode. And the area of the base mesa can be minimized.
In the etching for forming the base mesa, an undercut portion is formed under the periphery of the emitter electrode, and a photoresist layer is left in the undercut portion so as to cover the emitter and the emitter cap layer. In addition, it is possible to avoid etching of the emitter layer and the emitter cap layer under the emitter electrode during the etching for forming the base / collector mesa, and to stably achieve high speed and reduction of the occupied area and to have the desired characteristics. A heterojunction bipolar transistor can be formed.

An embodiment of a heterojunction bipolar transistor (HBT) according to the present invention is illustrated with reference to the drawings, but it goes without saying that the present invention is not limited to this.
FIG. 1 is a schematic perspective view of an embodiment of an HBT according to the present invention, and FIGS. 2A and 2B are a schematic plan view and a cross-sectional view taken along line BB of FIG. 2A.
This HBT has a sub-collector layer 1 made of InGaAs or InP and having a thickness of 300 nm on a semi-insulating semiconductor substrate 50 made of, for example, an InP substrate, and a first conductivity type, for example, n-type InP, on the sub-collector layer 1. A base-collector mesa 4 formed by stacking a collector layer 2 having a thickness of 500 nm and a base layer 3 having a thickness of 50 nm made of a second conductivity type, for example, p-type InGaAs, is formed in a pattern whose planar pattern forms a convex shape, for example. Made up.
Further, on this, for example, a U-shaped pattern, an emitter layer 5 of a first conductivity type, for example, n-type InP, having a thickness of 50 nm, and a first conductivity type, a thickness of InGaAs having a high impurity concentration, are further formed thereon. An emitter mesa 7 is formed by stacking with an emitter cap layer 6 having a thickness of 50 nm, and an emitter electrode 8 in ohmic contact is formed on the cap layer 6.

The base electrode 9 is in ohmic contact with the base layer 3 exposed between the U-shaped pattern of the emitter mesas 7. The end portion of the base electrode 9 extends to the tip of the convex protrusion of the base layer 3 to form a pad portion 9P that is in contact with the wiring layer (not shown).
Further, a collector electrode 10 is formed on the subcollector 1 outside the base / collector mesa 4 in an ohmic manner.
The emitter electrode 8, the base electrode 9, and the collector electrode 10 can be formed by electrodes having a laminated structure in which, for example, each of Ti / Pt / Au has a thickness of 50 nm / 50 nm / 200 nm.

  In the HBT having this configuration, a part of the peripheral part 4e of the base mesa (the base / collector mesa 4 in this example) has a shape along a part of the peripheral part 8e of the emitter electrode 8. Circumferential portions 8e and 4e are configured to be self-aligned.

Next, an embodiment of the manufacturing method of the present invention will be described with reference to the process diagrams of FIGS.
3, 5, and 6 are each a schematic plan view of each step of the heterojunction bipolar transistor according to the present invention, and each B diagram is a schematic cross-sectional view along the line BB of each A diagram. FIG. 4A is a schematic plan view in one step, and FIGS. B1 and B2 are schematic cross-sectional views in a modification on the B1-B1 line and the B2-B2 line in FIG.

First, as shown in FIG. 3, as described above, the subcollector layer 1, the collector layer 2, the base layer 3, the emitter layer 5, and the emitter cap layer 6 are sequentially formed on the substrate 30 by, for example, MOCVD ( The laminated semiconductor layer 31 is formed by epitaxial growth using Metal Organic Chemical Vapor Deposition) or the like.
Then, an emitter electrode 8 is formed on the laminated semiconductor layer 31, that is, on the uppermost emitter cap layer 6.
The emitter electrode 8 is formed by, for example, forming Ti / Pt / Au on the entire surface by sputtering, vapor deposition, or the like, and then using a photolithographic technique to form the required pattern, for example, a U-shaped pattern. It is formed by pattern etching.

Next, as shown in FIG. 4, by using the emitter electrode 8 as an etching mask, the emitter cap layer 6 other than the portion where the emitter electrode 8 is formed and the emitter layer 5 therebelow are removed by etching. Then, an etching process for forming the emitter mesa 7 is performed.
At this time, as shown in FIGS. 4B1 and 4B, the surface etching is performed so that the undercut portion 33 is generated below the peripheral edge portion 8e of the emitter electrode 8.
As shown in FIG. 4B1, the undercut portion 33 may be formed so that the undercut portion 33 is formed over the entire thickness of the gradiator cap layer 6 and the emitter layer 5 therebelow. As shown in FIG. 4B2, the undercut portion 33 can be formed only in the lower emitter layer 3.

The undercut portion 33 can be formed by etching that shows selectivity with respect to the emitter cap layer 6 and the emitter layer 5. For example, the etching of the emitter cap layer 6 with InGaAs is performed with an etching solution using a mixed solution of phosphoric acid, hydrogen peroxide solution, and water.
For example, the etching of the emitter layer 5 by InP can be performed by, for example, overetching with an etchant of a mixed solution of hydrochloric acid and phosphoric acid, or by crystal anisotropic etching. That is, in this case, the undercut portion 33 can be formed by selecting the <010> crystal axis direction in the width direction of the undercut portion 33 (for example, the direction orthogonal to the paper surface in FIG. 4B2).

Next, as shown in FIG. 5, a positive type photoresist 34 that covers the base mesa formation portion and is entirely exposed to light so as to fill the undercut portion 33 by spin coating is applied. .
An exposure process in which the photoresist 34 is subjected to pattern exposure outside the emitter electrode 8 while shielding the base mesa formation portion, and an unexposed portion other than the pattern exposure portion of the photoresist 34 and an emitter electrode in the undercut portion 33 A development processing step is performed to leave a non-exposed portion shielded by light 8.

Then, using this photoresist 34 and the emitter electrode 8 as a mask, the base layer 3 exposed to the outside is etched to form a base mesa. However, the base layer 3 is further etched to the outside by etching. The base collector mesa 4 is formed by
In this way, the target HBT formed by aligning the peripheral edge 8e of the emitter electrode 8 shown in FIGS. 1 and 2 with the peripheral edge 4e of the base / collector mesa 4 formed along the peripheral edge 8e is obtained. It is formed.

At this time, as shown in FIG. 4B2, when the undercut portion 33 is not formed in the emitter cap layer 6, the photoresist 34 is not formed on the peripheral surface, but the base layer 3 is etched. Since the thickness of the emitter cap layer 6 is sufficiently larger than the thickness of the base layer 3, the amount by which the emitter cap layer 6 is etched by the etching on the base layer 3 is not a problem in practice. It is.
In addition, when the collector layer 2 is etched, the collector layer 2 and the emitter cap layer 6 are made of different materials. Therefore, the collector layer 2 is etched with the above-described etching solution of hydrochloric acid and phosphoric acid having selectivity for InP, for example. Etching can avoid erosion of the emitter cap layer 6.

As described above, according to the manufacturing method of the present invention, the base mesa, in the above-described example, the base collector mesa 4 is formed using the emitter electrode pattern, so that the emitter electrode of the base mesa or the base collector mesa 4 is formed. The peripheral edge portion 4 e formed along the peripheral edge portion 8 e of 8 is formed to substantially coincide with the peripheral edge portion 8 e of the emitter electrode 8.
Therefore, since the HBT according to the present invention formed in this way does not have a width W for forming a tolerance unlike the conventional HBT shown in FIG. The area can be reduced, and by reducing the parasitic capacitance, the high speed can be improved and the occupied area of the HBT can be reduced. For example, the degree of integration can be improved.

In the above-described example, a single HBT has been described. However, it can be applied to various examples such as forming and separating a plurality of HBTs at the same time, or an integrated circuit configuration. Various structures and material configurations can be selected.
For example, as shown in the plan view of FIG. 8, the above-described HBT may be arranged on both sides of the common base wiring 35 with the common base wiring 35 interposed therebetween. In FIG. 8, parts corresponding to those in FIG.

1 is a schematic perspective view of one embodiment of a heterojunction bipolar transistor according to the present invention. FIG. 2A and 2B are a schematic plan view of an embodiment of a heterojunction bipolar transistor according to the present invention and a cross-sectional view taken along line BB in FIG. FIGS. 3A and 3B are a schematic plan view and a schematic cross-sectional view taken along line BB in one step of an embodiment of a method of manufacturing a heterojunction bipolar transistor according to the present invention. FIGS. A is a schematic plan view in one step of a method for manufacturing a heterojunction bipolar transistor according to the present invention, and B1 and B2 are schematic diagrams on the B1-B1 line and the B2-B2 line in FIG. It is sectional drawing. FIGS. 3A and 3B are a schematic plan view and a schematic cross-sectional view taken along line BB in one step of an embodiment of a method of manufacturing a heterojunction bipolar transistor according to the present invention. FIGS. FIGS. 3A and 3B are a schematic plan view and a schematic cross-sectional view taken along line BB in one step of an embodiment of a method of manufacturing a heterojunction bipolar transistor according to the present invention. FIGS. FIG. 6 is a schematic plan view of another embodiment of a heterojunction bipolar transistor according to the present invention. A and B are a schematic plan view of a conventional heterojunction bipolar transistor and a schematic cross-sectional view thereof taken along the line BB.

Explanation of symbols

  30, 100... Base body, 1, 101... Sub-collector layer, 2, 102... Collector layer, 3, 103... Base layer, 4, 104 ... Base collector mesa, 4 e, 104 e. , 105... Emitter layer, 6, 106... Cap layer, 7, 107... Emitter mesa, 8, 108... Emitter electrode, 8 e, 108 e .. Peripheral portion, 9, 109. ... Pad part 31 ... Laminated semiconductor layer 33 ... Undercut part 34 ... Photoresist 35 ... Wiring

Claims (6)

On the substrate,
Laminating a collector layer, a base layer, and a semiconductor layer having an emitter layer;
Forming an emitter electrode of a required pattern on the semiconductor layer;
An etching step of forming an emitter mesa in which an undercut portion is formed under the periphery of the emitter electrode using the emitter electrode as a mask;
Applying a photoresist covering the undercut portion and the base mesa forming portion;
Exposing the photoresist to pattern exposure while shielding the base mesa forming portion outside the emitter electrode; and
A development process that leaves a non-exposed portion other than the pattern exposed portion of the photoresist and a non-exposed portion of an undercut portion under the emitter electrode;
Etching process of etching the base layer using the photoresist and the emitter electrode as a mask to form a base mesa, and forming a base mesa whose peripheral edge along the peripheral edge of the emitter electrode is self-aligned with the peripheral edge of the emitter electrode When
A method of manufacturing a heterojunction bipolar transistor having The method of manufacturing a heterojunction bipolar transistor according to claim 1, wherein the collector layer is etched following the base mesa etching step to form a base-collector mesa . Forming an emitter cap layer on the emitter layer in the step of laminating the semiconductor layers;
The formation of the undercut portion, and the emitter cap layer, method for fabricating a heterojunction bipolar transistor according to 請 Motomeko 1 you formed over the whole thickness of the emitter layer. The method for fabricating a heterojunction bipolar transistor according to the formation of the undercut portion 請 Motomeko 1 you formed only on the emitter layer. The method for fabricating a heterojunction bipolar transistor according to 請 Motomeko 3 or 4 carried out by the isotropic etching in the formation of the undercut portion. The formation of the undercut portion, method for fabricating a heterojunction bipolar transistor according the crystalline anisotropic etching in a row cormorants請 Motomeko 3 or 4.

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