JP4882711B2 - Computer operation mode control circuit - Google Patents

Description

  The present invention relates to a computer operation mode control circuit, and more particularly to transition between a sleep mode (or standby mode) and a normal mode.

  In a device such as an audio amplifier, in order to suppress disturbance to an analog circuit as much as possible to prevent noise or to reduce power consumption, a plurality of microcomputers (hereinafter referred to as “microcomputers”) inside the device. Therefore, a microcomputer that is not directly related to the current operation or function is shifted from the normal mode to the sleep mode.

  On the other hand, the microcomputer that has shifted to the sleep mode is returned to the normal mode by using the external interrupt terminal and detecting the change at the logic level by the microcomputer. The following patent document describes that the sleep mode is canceled by an interrupt instruction by detecting the operation of a key switch.

JP-A-7-13671

  Here, it is assumed that a variable resistance type volume is provided on the panel of the device, and the microcomputer performs a specific process for this volume position. That is, it is a case where the volume position is digitized and grasped using an A / D converter built in the microcomputer, and processing corresponding to the numerical value is performed. Even in this case, it may be possible to suppress noise or power consumption by shifting the microcomputer from the normal mode to the sleep mode. However, when the current volume position is taken into the microcomputer using the A / D converter. Therefore, it is necessary to continue to determine whether or not the captured numerical value has changed compared to the previous value, and there is a problem that it is not possible to shift from the normal mode to the sleep mode. Of course, it is possible to forcibly shift to the sleep mode, but the sleep mode cannot be continued. Such a problem can occur not only with the volume but also with any analog switch or analog sensor.

  An object of the present invention is to provide a circuit that can shift a computer that operates based on a detection value of an analog sensor such as a volume to a sleep mode and can return from a sleep mode to a normal mode.

The present invention is a control circuit that takes in a detection value of an analog sensor from an input port, and returns a computer that operates in accordance with the detection value from a sleep mode to a normal mode. acquiring means for supplying to the input port detection value of the analog sensor to obtain a reference value, after which the computer has shifted to the sleep mode, the detected value of the analog sensor, is set based on the reference value In addition, a comparison unit that compares a determination threshold value for determining that the detection value of the analog sensor has changed, and a normal mode for the interrupt input port of the computer according to the comparison result of the comparison unit Supply means for supplying a return signal for returning to an interrupt signal as an interrupt signal. The value has an upper threshold and a lower threshold, and at least one of the upper threshold and the lower threshold is based on the reference value when the computer enters the sleep mode. It sets and outputs from an output port, It shifts to the sleep mode after outputting, It is characterized by the above-mentioned .

Further, the present invention is a control circuit that takes in a detection value of an analog sensor from an input port and returns a computer that operates according to the detection value from a sleep mode to a normal mode, and when the computer shifts to a sleep mode said obtaining means is supplied to the input port a voltage value corresponding to the detected value of the analog sensor to obtain a reference voltage value, after which the computer has shifted to the sleep mode, corresponding to the detection value of the analog sensor And a comparison means for comparing the upper limit voltage value and the lower limit voltage value set by adding a predetermined margin to the reference voltage value, the upper limit voltage value, the lower limit voltage value, At least one of the reference voltage values is set when the computer enters the sleep mode, and the output voltage is set. Output from the bets, the is to shift to the sleep mode after the output, and comparison means, if the voltage value corresponding to the detected value of the analog sensor exceeds the upper limit voltage value, or if less than the lower limit voltage value Supply means for supplying a return signal for returning to the normal mode to the interrupt input port of the computer as an interrupt signal.

  According to the present invention, an interrupt signal can be supplied to a computer by monitoring the current state of an analog sensor with a simple configuration. Therefore, the computer does not always have to monitor the current state of the analog sensor, can shift from the normal mode to the sleep mode, and can return from the sleep mode to the normal mode.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings, taking as an example a volume provided on a panel of a device.

<First Embodiment>
FIG. 1 shows a configuration of a control circuit in the present embodiment. The control circuit is provided between the microcomputer 10 and the volume 12, and includes a low-pass filter (LPF) 14, an A / D converter 16, D / A converters 18 and 20, comparators 22 and 24, and an OR gate (OR gate) 26. It is comprised including.

  An input voltage corresponding to the position of the volume 12 is supplied to the A / D converter 16 via the LPF 14. The A / D converter 16 converts an input voltage corresponding to the volume position into a digital value and supplies the digital value to the microcomputer 10 from the input port. The microcomputer 10 shifts from the normal mode to the sleep mode by detecting a non-operation state for a certain time. However, when the microcomputer 10 shifts to the sleep mode, the digital value immediately before the shift is captured from the A / D converter 16 more accurately. . Further, the microcomputer 10 sets a voltage value that can be recognized that the volume 12 has been operated with respect to the digital value when shifting to the sleep mode. The voltage values to be set are an upper limit voltage value and a lower limit voltage value. When the immediately preceding digital value is Vx, the predetermined voltage δ is used to set the upper limit voltage value VH = Vx + δ and the lower limit voltage value VL = Vx−δ. The upper limit voltage value VH is a threshold value for determining that the volume 12 has been operated upward when the upper limit voltage value VH is exceeded, and the lower limit voltage value is determined that the volume 12 has been operated downward when it is below this value. For the threshold. When the input voltage corresponding to the position of the volume 12 is between the upper limit voltage value and the lower limit voltage value, the volume 12 is substantially regarded as not being operated. That is, the predetermined value δ is a margin for determining whether or not the volume 12 has been operated. After setting these voltage values VH and VL, the microcomputer 10 outputs VH and VL from the output port and shifts from the normal mode to the sleep mode. Since the return from the sleep mode to the normal mode is performed by an interrupt signal from the interrupt input port and not by a change in the digital value input from the input port, the microcomputer 10 always outputs the digital value from the input port. Therefore, after the upper limit voltage value VH and the lower limit voltage value VL are set and output from the output port, the normal mode can be shifted to the sleep mode.

The upper limit voltage value VH and the lower limit voltage value VL output from the output port of the microcomputer 10 are converted into analog voltage values by the D / A converters 18 and 20, respectively, and supplied to one terminal of the comparators 22 and 24. That is, the upper limit voltage value VH (analog value) is supplied to the inverting input terminal (−) of the comparator 22, and the lower limit voltage value (analog value) is supplied to the non-inverting input terminal (+) of the comparator 24. The current input voltage value of the volume 12 is supplied to the non-inverting input terminal (+) of the comparator 22 and the inverting input terminal (−) of the comparator 24. The comparators 22 and 24 always compare the upper limit voltage value VH and the input voltage value, and the lower limit voltage value VL and the input voltage value, respectively, after the microcomputer 10 shifts to the sleep mode, and OR the comparison results as the VA signal and the VB signal. 26. The comparators 22 and 24 output a signal that becomes Hi when the voltage value of the non-inverting input terminal is larger than the voltage value of the inverting input terminal and becomes Low when the voltage value is smaller. OR gate 26 calculates the logical sum of the VA signal and the VB signal, and supplies the interrupt input port of the microcomputer 10 a calculation result as an interrupt signal V _Y. One of the comparators 22 and 24 becomes Hi, that is, when the input voltage corresponding to the current position of the volume 12 exceeds the upper limit voltage value VH, or the input voltage corresponding to the current position of the volume 12 is the lower limit voltage. interrupt signal V _Y becomes Hi when it falls below the value VL which is the operation result of the OR gate 26, the microcomputer 10 returns from the sleep mode to the normal mode by an interrupt signal is Hi.

FIG. 2 shows a magnitude relationship between the input voltage value, the upper limit voltage value VH = Vx + δ and the lower limit voltage value VL = Vx−δ, and a logical value table corresponding to the magnitude relationship. If the input voltage value is between the upper limit voltage value VH and the lower limit voltage value VL, the interrupt signal V _Y remains at is the microcomputer 10 of the Low continues the sleep mode. When the user operates the volume 12 and the input voltage value exceeds the upper limit voltage value VH or falls below the lower limit voltage value VL, the interrupt signal _VY becomes Hi and the microcomputer 10 returns to the normal mode, and the volume 12 The process according to the current position is executed.

  In the present embodiment, the A / D converter 16, the D / A converter 18, and the D / A converter 20 are described as a part of the control circuit. However, the A / D converter and the D / A converter built in the microcomputer 10 are described. May be used.

Second Embodiment
FIG. 3 shows the configuration of the control circuit in this embodiment. In the first embodiment, the upper limit voltage value VH and the lower limit voltage value VL are set by the microcomputer 10, but in this embodiment, only the lower limit voltage value VL is set by the microcomputer 10 and the upper limit voltage value VH is generated in the control circuit. .

  An adder 28 is provided instead of the D / A converter 18 in the configuration of FIG. The microcomputer 10 sets the lower limit voltage value VL = Vx−δ with respect to the input voltage value Vx immediately before shifting to the sleep mode, and outputs it from the output port. The D / A converter 20 converts the lower limit voltage value VL into an analog value and supplies it to the non-inverting input terminal (+) of the comparator 24 and also supplies it to the adder 28.

  The adder 28 adds the predetermined value 2δ to the lower limit voltage value VL (analog value) to generate the upper limit voltage value VH, and supplies it to the inverting input terminal (−) of the comparator 22. Since the lower limit voltage value VL = Vx−δ, the output of the adder 28 is VH = VL + 2δ = Vx + δ. As in the first embodiment, the comparators 22 and 24 compare the upper limit voltage value VH and the lower limit voltage value VL with the input voltage value corresponding to the current position of the volume 12, and respectively compare the comparison results VA and VB with the OR gate 26. To supply.

FIG. 4 shows a logical value table of the present embodiment. Like the first embodiment, when the input voltage value is between the upper limit voltage value VH and the lower limit voltage value VL, the interrupt signal V _Y microcomputer 10 remains Low continues the sleep mode. When the user operates the volume 12 and the input voltage value exceeds the upper limit voltage value VH or falls below the lower limit voltage value VL, the interrupt signal _VY becomes Hi and the microcomputer 10 returns to the normal mode, and the volume 12 The process according to the current position is executed.

  In the present embodiment, the microcomputer 10 sets the lower limit voltage value VL and the adder 28 sets the upper limit voltage value VH using the lower limit voltage value VL. However, the microcomputer 10 sets the upper limit voltage value VH and subtracts it. The lower limit voltage value VL may be set by using the upper limit voltage value VH. That is, the subtracter sets the lower limit voltage value VL by VL = VH−2δ = Vx−δ. The upper limit voltage value VH set by the microcomputer 10 is supplied to the comparator 22, and the lower limit voltage value VL set by the subtractor is supplied to the comparator 24.

<Third Embodiment>
FIG. 5 shows the configuration of the control circuit in this embodiment. In the present embodiment, the microcomputer 10 sets the reference intermediate voltage value VM from the input voltage value Vx immediately before shifting to the sleep mode. The intermediate voltage value VM is set as VM = Vx. The microcomputer 10 outputs the set intermediate voltage value VM from the output port. The D / A converter 18 converts the intermediate voltage value VM into an analog value and supplies it to the subtracter 30.

The subtractor 30 calculates the difference between the input voltage value Vx and the intermediate voltage value VM according to the current position of the volume 12, and supplies the result Vx−VM to the comparators 22 and 24. The comparator 22 compares the difference value Vx−VM with the predetermined value δ, and the comparator 24 compares the difference value Vx−Vm with the predetermined value −δ. When the volume 12 is not operated, Vx-VM is a value between 0 and 0, and the outputs of the comparators 22 and 24 are both low. Further, when the volume 12 is operated, Vx−VM exceeds δ or falls below −δ, and the output of the comparator 22 or the comparator 24 becomes Hi.

FIG. 6 shows a logical value table of the present embodiment. When the difference between the input voltage value and the intermediate voltage value VM is between the upper limit voltage value δ and the lower limit voltage value −δ, the interrupt signal Vy remains low and the microcomputer 10 continues the sleep mode. When the user operates the volume 12 and the input voltage value exceeds the upper limit voltage value δ or lower than the lower limit voltage value −δ, unlike the voltage value immediately before the transition to the sleep mode, that is, the interrupt signal V _Y becomes Hi and the microcomputer 10 returns to the normal mode, and executes processing according to the current position of the volume 12.

  As described above in each embodiment, in this embodiment, the microcomputer 10 detects the value of the analog switch immediately before the transition to the sleep mode, generates a determination threshold value based on the detected value, and shifts to the sleep mode. After the microcomputer 10 shifts to the sleep mode, the analog switch value is compared by a comparator in the control circuit to generate an interrupt signal and supply the microcomputer 10 to the microcomputer 10 so that the microcomputer 10 can be easily changed from the sleep mode to the normal mode. Can be restored.

  In each embodiment, the volume 12 is exemplified as an analog switch or a sensor. However, the microcomputer 10 can be returned from the sleep mode to the normal mode based on a detection value from another analog sensor.

It is a block diagram of 1st Embodiment. It is a logical value table of a 1st embodiment. It is a block diagram of 2nd Embodiment. It is a logic value table of a 2nd embodiment. It is a block diagram of 3rd Embodiment. It is a logic value table of a 3rd embodiment.

Explanation of symbols

  10 microcomputer, 12 volume, 14 low pass filter (LPF), 16 A / D converter, 18, 20 D / A converter, 22, 24 comparator, 26 OR gate.

Claims (2)

A control circuit that takes in a detection value of an analog sensor from an input port, and returns a computer that operates according to the detection value from a sleep mode to a normal mode,
An acquisition unit that the computer is supplied to said input port to obtain the detected value of the analog sensor as a reference value when entering the sleep mode,
A threshold value for determining that the detection value of the analog sensor and the detection value of the analog sensor set based on the reference value have changed after the computer has entered the sleep mode; A comparison means for comparing
Supply means for supplying, as an interrupt signal, a return signal for returning to the normal mode to the interrupt input port of the computer according to the comparison result in the comparison means;
Have
The determination threshold has an upper threshold and a lower threshold,
At least one of the upper threshold and the lower threshold is set based on the reference value when the computer enters the sleep mode, and is output from the output port. After the output , the computer enters the sleep mode. An operation mode control circuit for a computer. A control circuit that takes in a detection value of an analog sensor from an input port, and returns a computer that operates according to the detection value from a sleep mode to a normal mode,
An acquisition unit that the computer is supplied to said input port to acquire a voltage value according to the detected value of the analog sensor as a reference voltage value at the time of transition to the sleep mode,
After the computer enters the sleep mode, a voltage value corresponding to a detection value of the analog sensor, and an upper limit voltage value and a lower limit voltage value set by adding a predetermined margin to the reference voltage value, Each of the upper limit voltage value, the lower limit voltage value, and the reference voltage value is set when the computer shifts to the sleep mode and is output from the output port. Comparing means which is to shift to the sleep mode later ,
When a voltage value corresponding to the detected value of the analog sensor exceeds the upper limit voltage value or falls below the lower limit voltage value, a return signal for returning to the normal mode for the interrupt input port of the computer is provided as an interrupt signal. Supply means to supply as,
An operation mode control circuit for a computer, comprising:

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