JP4887189B2 - Battery voltage detection circuit - Google Patents

Description

  The present invention relates to a battery voltage detection circuit.

In a device such as a notebook PC using a rechargeable battery, it is necessary to accurately detect the voltage of each battery in order to manage charging / discharging of batteries connected in series. FIG. 9 is a diagram showing a general configuration of a battery voltage detection circuit (see Patent Document 1). The battery voltage detection circuit 100 is for detecting the voltages of four batteries BV1 to BV4 connected in series, and includes an operational amplifier 110, resistors R1 to R4, switches SW0M to SW4M, SW0P to SW3P, and a reference voltage V. A power supply 115 that outputs _REF is included. In such a battery voltage detection circuit 100, when the voltage V _BV4 of the battery BV4 is detected, the switches SW4M and SW3P are turned on, and the other switches are turned off. As a result, a voltage V _OUT corresponding to the difference between the voltage V4 at the positive terminal of the battery BV4 and the voltage V3 at the negative terminal is output from the operational amplifier 110 to the AD converter (ADC) 120. The _{ADC 120} can detect the voltage V _BV4 of the battery BV4 by changing the voltage V _OUT to a digital value. Similarly, when the switches SW3M and SW2P are turned on and the other switches are turned off, the voltage V _BV3 of the battery BV3 can be detected. Further, when the switches SW2M and SW1P are turned on and the other switches are turned off, the voltage V _BV2 of the battery BV2 can be detected. Further, when the switches SW1M and SW0P are turned on and the other switches are turned off, the voltage V _BV1 of the battery BV1 can be detected.
JP 2002-243771 A

When lithium ion batteries are used for the batteries _{BV1 to} BV4, the voltages V _{BV1 to} V _BV4 across the batteries _{BV1 to} BV4 at the time of full charge reach close to 4.5V. If the voltages V _{BV1 to} V _BV4 of the batteries _{BV1 to BV4} are _set to 5V in consideration of the design margin, the battery _{BV1 to BV4} connected in series generates a voltage of 20V, and the battery voltage detection circuit 100 Needs to have a high breakdown voltage. On the other hand, the control system circuit including the ADC 120 generally uses a power supply voltage of about 3.3 V, and the voltage V _OUT output from the battery voltage detection circuit 100 needs to be 3.3 V or less.

Here, when the resistance values of the resistors R3 and R4 are R3 and R4, respectively, the gain G _{AMP of the} operational amplifier 110 is R4 / R3. Therefore, the voltage V _OUT output when detecting the voltage V _{BV4 of the} battery BV4 is V _OUT = V _BV4 / G _AMP + V _REF = (V 4 −V 3) R 3 / R 4 + V _REF . When V _BV4 is 5 V and V _REF is 0.2 V, the condition of the gain G _AMP of the operational amplifier 110 for V _OUT ≦ 3.3 V is G _AMP ≦ (V _OUT −V _REF ) / V _BV4 = (3.3-0.2) /5≈0.6. As a result, the voltage V _OUT output to the ADC 120 can be set to 3.3 V or less by selecting the resistance values of the resistors R3 and R4 so that the gain G _{AMP of the} operational amplifier 110 is about 0.6. it can. However, in this case, it is necessary to make the operational amplifier 110 have a high breakdown voltage, leading to an increase in the cost of the battery voltage detection circuit 100.

Therefore, in order to make the operational amplifier 110 unnecessary to have a high breakdown voltage, the voltage applied to the operational amplifier 110 needs to be 3.3 V or less. That is, in order to set the voltage V ⁺ applied to the + input terminal of the operational amplifier 110 to 3.3 V or less, it is necessary to satisfy (V3−V _REF ) R4 / (R3 + R4) + V _REF ≦ 3.3. From this, R4 / (R3 + R4) ≦ (3.3−V _REF ) / (V3−V _REF ) = (3.3−0.2) / (15−0.2) = 3.1 / 14.8 ≈0.21. Therefore, the gain G _{AMP of the} operational amplifier 110 is G _AMP = R4 / R3 ≦ 0.21 / (1−0.21) ≈0.26. Therefore, by selecting the resistance values of the resistors R3 and R4 so that the gain G _{AMP of the} operational amplifier 110 is about 0.26, it is possible to make the operational amplifier 110 unnecessary to have a high breakdown voltage. However, in this case, since the gain G _{AMP of the} operational amplifier 110 is small, the voltage V _OUT input to the ADC 120 becomes low. Therefore, in order to detect the battery voltage with high accuracy, it is necessary to make the ADC 120 highly accurate, leading to an increase in cost.

  In the battery voltage detection circuit 100, when the voltages of the batteries BV1 to BV4 are detected, current flows through the resistors R1 and R3 connected to the input terminals of the operational amplifier. Therefore, in order to suppress the discharge of the batteries BV1 to BV4 due to this current, it is necessary to use resistors R1 and R3 having a large resistance of several mega ohms. Moreover, in order to detect the voltages of the batteries BV1 to BV4 with high accuracy, it is necessary that the resistors R1 to R4 have less resistance voltage dependency. Thus, when an integrated circuit using a resistor having a large resistance value and a small voltage dependency is manufactured, it is necessary to provide a special process, resulting in an increase in cost.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a battery voltage detection circuit capable of detecting a battery voltage with high accuracy at low cost.

In order to achieve the above object, a battery voltage detection circuit of the present invention includes an operational amplifier, a first capacitor having one end connected to one input terminal of the operational amplifier, one end connected to the output terminal of the operational amplifier, and the other end. A second capacitor connected to one input terminal of the operational amplifier, a third capacitor connected at one end to the other input terminal of the operational amplifier, a first reference voltage applied to one end, and the other end connected to the operational amplifier A fourth capacitor connected to the other input terminal, a fifth capacitor having one end connected to one input terminal of the operational amplifier and the other end grounded, and a voltage at one terminal of the battery to the first capacitor. And the voltage at the other terminal of the battery is applied to the other end of the third capacitor, and then the voltage at the other terminal of the battery is applied to the first and third keys. A switch circuit that can be applied to the other end of the capacitor, and a discharge circuit that discharges the second and fourth capacitors before the voltage at the other terminal of the battery is applied to the other ends of the first and third capacitors. The first to fourth capacitors are wiring capacitances constituted by wirings in an integrated circuit, and the fifth capacitor is formed by a dummy wiring that improves the capacitance accuracy of the first to fourth capacitors. , and the voltage of the other terminal of the battery to detect a voltage of the battery based on the voltage of the output terminal of the operational amplifier after being applied to the other end of the first and third capacitor.

  A battery voltage detection circuit capable of detecting the voltage of the battery with high accuracy at low cost can be provided.

<< First Embodiment >>
== Circuit configuration ==
FIG. 1 is a diagram showing a configuration of a battery voltage detection circuit according to the first embodiment of the present invention. As shown in FIG. 1, a capacitor C1 (first capacitor) is connected to the negative input terminal of the operational amplifier 20, and a capacitor C3 is connected to the positive input terminal. That is, since no DC voltage is applied to the operational amplifier 20, the operational amplifier 20 does not need to have a high breakdown voltage.

In the present embodiment, the capacitances of the capacitors C1 to C6 are represented as C1 to C6. Further, it is assumed that the relationship of C1 / C2 = C3 / C4 is established. The capacitors C1 to C5 correspond to the first to fifth capacitors of the present invention, the switches SW0P to SW3P, SW1M to SW4M, SW6M, SW6P, and SW7 correspond to the switch circuit of the present invention, and the switches SW5M and SW5P This corresponds to the discharge circuit of the present invention. The power supply 30 is a power supply circuit that outputs a reference voltage V _REF1 , and in this embodiment, V _REF1 = 0.8V.

  The switch control circuit 35 controls on / off of the switches SW0P to SW3P, SW5P, SW6P, SW1M to SW6M, and SW7 based on a signal input from the microcomputer 45 via the terminal SW. A function equivalent to the switch control circuit 35 can be realized by software.

Here, assuming a case where lithium ion batteries are used for the batteries _{BV1 to} BV4, the voltages V _{BV1 to} V _BV4 at both ends of the batteries _{BV1 to} BV4 at the time of full charge reach close to 4.5V. If the voltages V _{BV1 to} V _BV4 of the batteries _{BV1 to BV4} are _set to 5 V in consideration of the design margin, the batteries _{BV1 to BV4} connected in series generate a voltage of 20 V, and the capacitors C1 and C3 It is necessary to have a high breakdown voltage. Therefore, in the present embodiment, the capacitors C1 to C5 are configured by wiring capacitance that generally has little voltage dependency.

  FIG. 2 is a diagram illustrating an arrangement example of the metal wiring when the capacitors C1 to C5 are configured by the wiring capacitance. Here, assuming that the capacitance of the capacitor C1 is 2 pF and the capacitance of the capacitor C2 is 10 pF, as shown in FIG. 2, the area ratio between the metal wiring C1a constituting the capacitor C1 and the metal wirings C2a to C2e constituting the capacitor C2 Should be 1: 5. Similarly, when the capacitance of the capacitor C3 is 2 pF and the capacitance of the capacitor C4 is 10 pF, as shown in FIG. 2, the area ratio of the metal wiring C3a constituting the capacitor C3 and the metal wirings C4a to C4e constituting the capacitor C4 is as follows. It may be set to 1: 5. The capacitor C6 can also be configured with a wiring capacitance in the same manner.

  By the way, in the case of the wiring capacity, the accuracy of the capacity cannot be increased unless the four conditions of the metal wiring are the same. For example, when there is no metal wiring C5a shown in FIG. 2, the metal wiring C1a has other metal wirings on the right side and the lower side, but no other metal wirings exist on the upper side and the left side. On the other hand, the metal wiring C2a has other metal wirings other than the upper side. Therefore, in order to make the situation in the four directions of the metal wiring the same, the metal wiring C5a is disposed around the metal wirings C1a, C2a to C2e, C3a, and C4a to C4e. The metal wiring C5a is a dummy metal (dummy wiring) for increasing the accuracy of capacitance of the capacitors C1 to C4, and constitutes the capacitor C5.

  As described above, by disposing the metal wiring C5a, which is a dummy metal for making the four conditions of the metal wirings C1a, C2a to C2e, C3a, and C4a to C4e the same, the capacitance accuracy of the capacitors C1 to C4 is improved. Can be made. On the other hand, the capacitor C5 is realized by using a metal wiring C5a as a dummy metal for improving the capacitance accuracy of the capacitors C1 to C4, and the dummy metal can be effectively used. In other words, it is not necessary to separately provide a wiring capacity or the like for configuring the capacitor C5, and the chip size of the battery voltage detection circuit 10A can be reduced.

  FIG. 3 is a diagram illustrating a configuration example of the ADC 40. The ADC 40 includes a comparator 50, a current source 51, a capacitor C7, an N-channel MOSFET 53, an inverter 54, and a counter 55.

In the comparator 50, the voltage V _OUT output from the battery voltage detection circuit 10A is applied to the + input terminal, the − input terminal is connected to one end of the capacitor C7, and the output signal CMP is input to the counter 55. Therefore, when the voltage V _OUT is higher than the voltage of the capacitor C7, the output signal CMP becomes H level, and when the voltage of the capacitor C7 is higher than the voltage V _OUT , the output signal CMP becomes L level.

The current source 51 has one end applied with the power supply voltage V _DD and the other end connected to one end of the capacitor C7, and supplies a constant current to the capacitor C7.

  The N-channel MOSFET 53 has a drain connected to one end of the capacitor C7, a source grounded, and a signal CHG input to the gate via the inverter 54. The signal CHG is input from, for example, the microcomputer 45. When the signal CHG becomes L level, the N-channel MOSFET 53 is turned on and the capacitor C7 is discharged.

  The counter 55 receives a signal CHG output from the microcomputer 45, a signal CMP output from the comparator 50, and a clock signal CLK having a predetermined frequency generated by, for example, an RC oscillation circuit. The counter 55 starts counting the clock signal CLK when the signal CHG changes from L level to H level, and stops counting when the signal CMP changes from H level to L level.

When converting the output voltage V _OUT that is an analog value into a digital value, the microcomputer 45 first sets the signal CHG to L level and discharges the capacitor C7. Thereafter, when the microcomputer 45 sets the signal CHG to the H level, the counter 55 starts counting and the capacitor C7 starts to be charged. When the capacitor C7 is charged and the voltage of the capacitor C7 reaches the output voltage V _OUT , the signal CMP changes to the L level, and the counting operation in the counter 55 is stopped. As a result, the counter 55 outputs a count value (digital value) corresponding to the output voltage V _OUT .

== Operation ==
Next, the operation of the battery voltage detection circuit 10A will be described. FIG. 4 is a timing chart showing an example of the operation of the battery voltage detection circuit 10A. The voltages applied to the terminals V1 to V4 are represented as V1 to V4, respectively. Further, the voltages of the batteries _{BV1 to BV4} are expressed as V _{BV1 to} V _BV4 , respectively.

First, at time T0, the switches SW4M, SW3P, SW6M, SW6P, SW5M, and SW5P are turned on, and the switches SW0P to SW2P, SW1M to SW3M, and SW7 are turned off. At this time, since the switches SW5M and SW5P are on, the operational amplifier 20 becomes a gain 1 amplifier, and the reference voltage V _REF1 = 0.8 V applied to the + input terminal is output as the output voltage V _OUT . Since the switches SW4M and SW6M are on, the voltage V _{C1 of the} capacitor _C1 is V _C1 = V4−V _REF1 . Therefore, the charge Q _C1 stored in the capacitor C1 is Q _C1 = V _C1 · C1 = (V4−V _REF1 ) · C1. Since the switch SW5M is on, the voltage V _C2 of the capacitor C2 is 0V, and the charge Q _C2 stored in the capacitor C2 is also 0. Since the switches SW3P and SW6P are on, the voltage V _{C3 of the} capacitor _C3 is V _C3 = V3−V _REF1 . Therefore, the charge Q _C3 stored in the capacitor C3 is Q _C3 = V _C3 · C3 = (V3−V _REF1 ) · C3. Since the switch SW5P is on, the voltage V _C4 of the capacitor C4 is 0V, and the charge Q _C4 stored in the capacitor C4 is also 0.

  Thereafter, the switches SW5M and SW5P are turned off at time T1, and then the switch SW6M is turned off and the switch SW7 is turned on at time T2. As a result, a voltage V3 lower than the voltage V4 is applied to the other end of the capacitor C1, and a current I1 flows from the output terminal of the operational amplifier 20 toward the capacitor C2, the capacitor C1, the switch SW7, the switch SW3P, and the terminal V3.

When the charge of the capacitor C1 becomes stable at time T3, the voltage V _C1 = V3−V _REF1 and the charge Q _C1 = V _C1 · C1 = (V3−V _REF1 ) · C1. Therefore, the change amount ΔQ _C1 of the charge Q _C1 due to the current I1 is ΔQ _C1 = (V4−V _REF1 ) · C1− (V3−V _REF1 ) · C1 = (V4−V3) · C1. Since the current I1 accumulates the same amount of charge as ΔQ _{C1 in} the capacitor C2, the charge Q _{C2 of the} capacitor C2 becomes Q _C2 = (V4−V3) · C1. Therefore, the voltage V _C2 across the capacitor C2 is V _C2 = (V4−V3) · C1 / C2 = V _BV4 · C1 / C2. In addition, since the charge Q _C4 stored in the capacitor C4 is 0, the voltage V ⁺ applied to the + input terminal of the operational amplifier 20 becomes V _REF1 , and the voltage V ⁻ applied to the _−input terminal of the operational amplifier 20 is also V ⁻ = V ⁺ = V _REF1 . Therefore, the output voltage V _OUT of the operational amplifier 20 is V _OUT = V _REF1 + V _C2 = V _REF1 + V _BV4 · C1 / C2.

Here, C1, C2 are since a known constant, the microcomputer 45, the output voltage V _{OUT (2} = V when the output voltage V _OUT and the digital value (= V _REF1), the time T3 at time T0 The voltage V _BV4 of the battery BV4 can be obtained by taking the difference from the digital value of _REF1 + V _BV4 · C1 / C2).

  Further, when the batteries BV1 to BV4 are used as, for example, a driving power source for a notebook PC, the voltages V1 to V4 may simultaneously drop to the same extent when the processing load increases. If a phenomenon occurs in which the voltage V3 drops to V3 ′ at time T4, the voltage applied to the other end of the capacitor C1 drops from V3 to V3 ′, so that the capacitor C2, the capacitor C1, the switch from the output terminal of the operational amplifier 20 Current I1 further flows toward SW7, switch SW3P, and terminal V3. Further, since the voltage applied to the other end of the capacitor C3 also drops from V3 to V3 ′, a current I2 flows from the power supply 30 toward the capacitor C4, the capacitor C3, the switch SW6P, the switch SW3P, and the terminal V3.

The change amount ΔQ _C3 of the charge Q _C3 due to the current I2 is ΔQ _C3 = (V3−V3 ′) · C3. Since the current I2 accumulates the same amount of charge as ΔQ _{C3 in} the capacitor C4, the charge Q _{C4 of the} capacitor _C4 becomes Q _C4 = (V3−V3 ′) · C3. Therefore, the voltage V _C4 across the capacitor C4 is V _C4 = (V3−V3 ′) · C3 / C4, and the voltage V ⁺ applied to the + input terminal of the operational amplifier 20 is V _REF1 −V _C4 . Further, the change amount ΔQ _C1 of the charge Q _C1 due to the current I1 is ΔQ _C1 = (V3−V3 ′) · C1. Then, since the same amount of charge as ΔQ _C1 is further accumulated in the capacitor C2 by the current I1, the charge Q _{C2 of the} capacitor _C2 is Q _C2 = (V4−V3) · C1 + (V3−V3 ′) · C1 = (V4−V3 ′) · C1. Therefore, the voltage _C2 across the capacitor C2 is V _C2 = (V4−V3 ′) · C1 / C2. The voltage V ⁻ applied to the − input terminal of the operational amplifier 20 is V ⁻ = V ⁺ = V _REF1 −V _C4 = V _REF1 − (V3−V3 ′) · C3 / C4. Therefore, the output voltage V _OUT of the operational amplifier 20 is V _OUT = V _REF1 − (V 3 −V 3 ′) · C 3 / C 4 + (V 4 −V 3 ′) · C 1 / C 2 = V _{REF 1} + (V 4 −V 3) · C 1 / C 2 = V _REF1 + V _BV4 · C1 / C2, which is the same as at time T3.

That is, even if the voltages V1 to V4 simultaneously drop by the same amount, the amount of change in the voltage at the ± input terminal of the operational amplifier 20 becomes the same because the switch SW7 is turned on, and the output voltage _VOUT does not change. The voltage V _{BV4 of the} battery BV4 can be detected with high accuracy regardless of the timing.

Thereafter, when the switches SW5M and SW5P are turned on at time T5, the capacitors C2 and C4 are discharged, V _C2 and V _C4 become 0 V, and the output voltage V _OUT = V _REF1 . At time T5, the switches SW4M, SW3P, and SW7 are turned off, and the switches SW3M, SW6M, and SW2P are turned on. As a result, a voltage V2 lower than the voltage V3 is applied to the other end of the capacitor C3, and a current I2 flows from the power supply 30 toward the switch SW5P, the capacitor C3, the switch SW6P, the switch SW2P, and the terminal V2. Then, the switches SW5M and SW5P are turned off at time T6, and then the switch SW6M is turned off and the switch SW7 is turned on at time T7. As a result, a voltage V2 lower than the voltage V3 is applied to the other end of the capacitor C1, and a current I1 flows from the output terminal of the operational amplifier 20 toward the capacitor C2, the capacitor C1, the switch SW7, the switch SW2P, and the terminal V2. Thus, it is possible to charge according to the voltage V _BV2 of the battery BV2 is accumulated in the capacitor C2, to obtain a voltage V _BV3 as in the case of the voltage V _BV4. Further, for example, even when the voltages V1 to V4 simultaneously drop at the same time at time T9, the amount of change in the voltage at the ± input terminal of the operational amplifier 20 becomes about the same because the switch SW7 is turned on, and the output voltage V _OUT Does not change.

Similarly, by turning on the switches SW5M and SW5P, turning off the switches SW3M, SW2P and SW7, turning on the SW2M, SW6M and SW1P, turning off the SW5M and SW5P, turning off the SW6M and turning on the SW7, The voltage V _BV2 can be obtained. Further, by turning on the switches SW5M, SW5P, turning off the switches SW2M, SW1P, SW7, turning on the SW1M, SW6M, SW0P, turning off the SW5M, SW5P, turning off the SW6M, and turning on the SW7, the voltage V _BV1 of the battery _BV1 Can be obtained.

Thus, the voltage V4 to the other end of the capacitor C1, V3, V2, V1, V _SS is applied in sequence, by the voltage V3 to the other end of the capacitor C3, V2, V1, V _SS is gradually applied in order, The voltages V _{BV1 to} V _BV4 of the batteries _{BV1 to BV4} are detected. As described above, when the voltage applied to the other end of the capacitor C1 drops from V4 to V3, the current I1 flows out from the terminal V3. Similarly, the current I1 flows out from the terminal V2 when the voltage applied to the other end of the capacitor C1 drops from V3 to V2, and the current I1 flows out from the terminal V1 when dropping from V2 to V1. Further, when the voltage applied to the other end of the capacitor C3 drops from V3 to V2, the current I2 flows out from the terminal V2, and when the voltage drops from V2 to V1, the current I2 flows out from the terminal V1.

After the voltages V _{BV1 to} V BV4 of the batteries _{BV1 to BV4} are detected, for example, the switch control circuit 35 applies the voltages V1, V2, and V3 to the other end of the capacitor C1 in order, for example, switch circuits SW1M to SW3M, For example, the switch circuits SW1P, SW2P, and SW6P are controlled so as to control the SW6M and sequentially apply the voltages V1 and V2 to the other end of the capacitor C3. For example, when the voltage V1 is applied to the other end of the capacitor C1 by turning on the switches SW1M and SW6M, the voltage applied to the other end of the capacitor C1 changes from V _SS to V1, and the voltage V _{BV1 of the} battery _BV1 The current corresponding to the current flows from the terminal V1. For example, when the voltage V1 is applied to the other end of the capacitor C3 by turning on the switches SW1P and SW6P, the voltage applied to the other end of the capacitor C3 is changed from V _SS to V1, and the voltage of the battery BV1 A current corresponding to V _BV1 flows from the terminal V1. That is, when viewed from the terminal V1, the electric charge flowing in due to the currents I1 and I2 is canceled out by the outflow. Similarly, for the terminals V2 and V3, the charge flowing in due to the currents I1 and I2 is canceled by the outflow. In the battery voltage detection circuit 10A, the battery voltage detection operation is repeatedly performed, for example, every few seconds. Thus, the fluctuation of the battery voltage due to the battery voltage detection operation can be suppressed by canceling the charge and the output. it can.

Next, the role of the capacitor C5 in the battery voltage detection circuit 10A will be described. It is assumed that the voltages V _{BV1 to} V BV4 of the batteries _{BV1 to BV4} are 5V, the capacitance of the capacitor C1 is 2 pF, the capacitance of the capacitor C2 is 10 pF, and the capacitance of the capacitor C5 is 20 pF.

For example, it is assumed that the state in which 20V is applied to the other end of the capacitor C1 through the switches SW4M and SW6M is changed to a state in which 15V is applied to the other end of the capacitor C1 through the switches SW3P and SW7. At this time, the response time of the operational amplifier 20 is low, the capacitor C2 does not function as a capacitor, the other end of the voltage of the capacitor C2, that is, the voltage V ^- is reduced. Here, if the capacitor C5 is not provided, since the capacitance ratio of the capacitors C1 and C2 is 1: 5, the drop amount of the voltage V ⁻ is (20−15) × 1 / (1 + 5) ≈0. .83. Therefore, for example, the voltage V ⁻ drops to about negative 0.83 V from 0.8 V, which is the same as the reference voltage V _REF1 , and becomes a negative voltage. Depending on the voltage value of the reference voltage V _REF1 and the capacitance ratio of the capacitors C1 and C2, the voltage V ⁻ is even lower.

The voltage V ^- When a negative voltage, as shown in FIG. 5, so that the flow of current I3 from the parasitic diode D1 toward capacitor C1. When the current I3 flows in this way, the amount of charge accumulated in the capacitor C1 decreases, and the battery voltage detection accuracy decreases.

Therefore, when the capacitor C5 is provided as shown in this embodiment, since the ratio of the capacitance of the capacitor C1 (2 pF) and the total capacitance of the capacitor C2, C5 (30 pF) is 1:15, the voltage V ^- the drop Becomes (20−15) × 1 / (1 + 15) ≈0.31. That is, the voltage V by the capacitor C5 is provided ^- the drop amount is small. Therefore, the voltage V ^- generation of current I3 is suppressed due to is a negative voltage, it is possible to prevent the reduction of the detection accuracy of the battery voltage. The capacitor C6 is also provided to perform the same function as the capacitor C5.

<< Second Embodiment >>
== Circuit configuration ==
FIG. 6 is a diagram showing a configuration of a battery voltage detection circuit according to the second embodiment of the present invention. In addition, the same code | symbol is attached | subjected about the component similar to 10 A of battery voltage detection circuits of 1st Embodiment, and description is abbreviate | omitted. The switches SW0P to SW3P, SW1M to SW4M, SW6M, SW6P, SW7 and SW8M correspond to the switch circuit of the present invention. In this embodiment, it is assumed that V _REF2 = 0.7V. Therefore, the output signal CMP of the comparator 80 is at the H level when the output voltage V _OUT of the operational amplifier 20 is higher than 0.7V, and is at the L level when the output voltage V _OUT is lower than 0.7V. Further, it is _assumed that V _REF3 = 2.4V.

  The counter 82 receives a signal CHG output from the switch control circuit 35 and a signal CMP output from the comparator 80, for example, a clock signal CLK having a predetermined frequency generated by an RC oscillation circuit or the like. The counter 82 starts counting the clock signal CLK when the signal CHG changes from L level to H level, and stops counting when the signal CMP changes from H level to L level.

== Operation ==
Next, the operation of the battery voltage detection circuit 10B will be described. FIG. 7 is a timing chart showing an example of the operation of the battery voltage detection circuit 10B.

First, at time T11, SW5M, SW5P, SW8M, SW0P, and SW6P are turned on, and switches SW1M to SW4M, SW1P to SW3P, SW6P, and SW7 are turned off. At this time, since the switches SW5M and 5P are on, the operational amplifier 20 becomes an amplifier having a gain of 1, and the reference voltage V _REF1 = 0.8 V applied to the + input terminal is output as the output voltage V _OUT . Therefore, the output signal CMP of the comparator 80 is at H level. Since the switch SW8M is on, the other end of the capacitor C1 is applied with the reference voltage V _REF3 output from the power supply 83, and the switches SW0P and SW6P are on, so that the other end of the capacitor C3 is turned on. Is applied with a ground voltage V _SS .

Thereafter, the switches SW5M and SW5P are turned off at time T12, and then the switch SW8M is turned off and the switch SW7 is turned on at time T13. As a result, the ground voltage V _SS is applied to the other end of the capacitor C1, and a current I1 flows from the output terminal of the operational amplifier 20 toward the capacitor C2, the capacitor C1, the switch SW7, the switch SW0P, and the terminal V _SS , and the capacitor C2 is charged. Is accumulated and the output voltage V _OUT rises.

When the charge of the capacitor C1 is stabilized, the switch control circuit 35 turns off the switches SW0P and SW7 at time T14. At this time, the output voltage V _OUT is V _OUT = V _REF1 + V _REF3 · C1 / C2. Further, when the switch control circuit 35 sets the signal CHG to H level at time T14, the P-channel MOSFET 75 is turned off, and the constant current I4 flows from the P-channel MOSFET 74 toward the capacitor C2 and the output terminal of the operational amplifier 20. The electric charge accumulated in the capacitor 26 is discharged at a constant speed by the constant current I4, and the output voltage V _OUT drops at a constant speed. Further, when the signal CHG becomes H level, the counter 82 starts counting the clock signal CLK.

Thereafter, when the output voltage V _OUT decreases to 0.7 V of the reference voltage V _REF2 applied to the − input terminal of the comparator 80 at time T15, the output signal CMP of the comparator 80 changes to L level, and the counter 82 counts. Stop. A time T _REF3 from time T14 to T15 counted by the counter 82 is a time _{corresponding} to the reference voltage V _REF3 (= 2.4 V). That is, _assuming that the slope of the output voltage V _OUT between T14 and T15 is −1 / K, T _REF3 = K · (V _REF1 + V _REF3 · C1 / C2−V _REF2 ) = K · (V _REF3 · C1 / C2 + 0.1). At time T16, when the switch control circuit 35 changes the signal CHG to L level, the P-channel MOSFET 75 is turned on and the discharge of the capacitor 26 by the constant current I4 is stopped. Further, the switch control circuit 35 turns on the switches SW4M, SW3P, SW6M, SW6P, SW5M, and SW5P at time T16. When the switches SW5M and SW5P are turned on, the output voltage V _OUT becomes the reference voltage V _REF1 = 0.8 V, and the output signal CMP of the comparator 80 becomes the H level. Further, when the switches SW4M and SW6M are turned on, the voltage V4 is applied to the other end of the capacitor C1, and when the switches SW3P and SW6P are turned on, the voltage V3 is applied to the other end of the capacitor C3. .

Thereafter, the switches SW5M and SW5P are turned off at time T17, and the switch SW6M is turned off and the switch SW7 is turned on at time T18. As a result, a voltage V3 lower than the voltage V4 is applied to the other end of the capacitor C1, and a current I1 flows from the output terminal of the operational amplifier 20 to the capacitor C2, the capacitor C1, the switch SW7, the switch SW3P, and the terminal V3, and flows to the capacitor C2. Charge is accumulated and the output voltage V _OUT rises.

Note that, after the charge of the capacitor C1 is stabilized at time T19, even if the voltages V1 to V4 drop simultaneously to the same extent due to, for example, an increase in processing load, the switch SW7 is turned on, so that the ± input of the operational amplifier 20 The amount of change in the terminal voltage is about the same, and the output voltage _VOUT does not change.

At time T20, the switch control circuit 35 turns off the switches SW4M, SW3P, and SW7. At this time, the output voltage V _OUT is V _OUT = V _REF1 + V _BV4 · C1 / C2. Further, when the switch control circuit 35 sets the signal CHG to the H level at time T20, the P-channel MOSFET 75 is turned off, and the constant current I4 flows from the P-channel MOSFET 74 toward the capacitor C2 and the output terminal of the operational amplifier 20. The electric charge accumulated in the capacitor C2 is discharged at a constant speed by the constant current I4, and the output voltage _VOUT drops at a constant speed. Further, when the signal CHG becomes H level, the counter 82 starts counting the clock signal CLK.

Thereafter, when the output voltage V _OUT decreases to 0.7 V of the reference voltage V _REF2 applied to the − input terminal of the comparator 80 at time T21, the output signal CMP of the comparator 80 changes to L level, and the counter 82 counts. Stop. Then, a time T _BV4 from time T20 to T21 counted by the counter 82 is a time _{corresponding} to the reference voltage V _BV4 . That is, if the slope of the output voltage V _OUT between T20 and T21 is −1 / K, then T _BV4 = K · (V _REF1 + V _BV4 · C1 / C2−V _REF2 ) = K · (V _BV4 · C1 / C2 + 0.1).

The microcomputer 45 can obtain the voltage V _{BV4 of the} battery BV4 based on T _REF3 and T _BV4 measured by the counter 82. Specifically, V _BV4 = (C2 / C1) · (T _BV4 −T _REF3 ) / K + V _REF3 . Thus, by obtaining the voltage V _BV4 in comparison with the count value T _BV4 when the voltage V _BV4 count value T _REF3 and cell BV4 in the case of the reference voltage V _REF3, is possible to improve the detection accuracy of the battery voltage it can. For example, when the clock signal CLK is generated by a low-accuracy circuit such as an RC oscillation circuit, the voltage V _{BV4 of the} battery BV4 is obtained based only on T _BV4 measured by the counter 82. The detection accuracy of the voltage V _BV4 decreases due to the influence of the frequency change. Therefore, as shown in this embodiment, by comparing the count value T _REF3 if the predetermined reference voltage V _REF3, cancel the effects of changes in the clock frequency, detects the voltage V _BV4 battery BV4 high precision It becomes possible.

After time T22, by controlling the switches SW0P to SW3P, SW5P, SW6P, SW1M to SW6M, and SW7 as in the first embodiment, the batteries BV1 to BV1 are discharged at a constant rate by the current I4 as described above. The voltages V _{BV1 to} V _BV3 of _BV3 can be detected.

The embodiment of the present invention has been described above. As described above, the battery voltage detection circuits 10A and 10B use capacitors C1 to C4 instead of resistors for differential amplification using the operational amplifier 20. Accordingly, the DC voltage of the batteries BV1 to BV4 is not applied to the operational amplifier 20, and the operational amplifier 20 does not need to have a high breakdown voltage. Since the voltage level of the output voltage _VOUT can be increased by adjusting the capacitance ratio of the capacitors C1 to C4, it is not necessary to use a highly accurate AD converter. Therefore, the battery voltage can be detected with high accuracy at low cost. Further, even when the voltages V1 to V4 simultaneously drop by about the same due to an increase in processing load or the like, the amount of change in the voltage at the ± input terminal of the operational amplifier 20 becomes the same because the switch SW7 is turned on. Therefore, in such a case, the output voltage V _OUT does not change, and the battery voltage can be detected with high accuracy.

Furthermore, the amount of charge flowing out from the battery can be reduced as compared with the case of differential amplification using a resistor. For example, in the battery voltage detection circuit 100 of FIG. 9, assuming that the resistance values of the resistors R1 and R3 are 5 MΩ, the voltage V _{BV4 of the} battery _BV4 is 5 V, and the conversion time at the ADC 120 is 30 ms, the voltage V _BV4 is detected. The amount of charge to be obtained is Q = IT = 5 V / 10 MΩ × 30 ms = 15 μC. On the other hand, in the battery voltage detection circuits 10A and 10B, when the capacitance of the capacitor C1 is 2 pF and the voltages V _{BV1 to} V _BV4 of the batteries _{BV1 to BV4} are 5 V, the amount of charge flowing out when the switches SW4M and SW6M are turned on is Q = CV = 2pF × 20V = 40 pC = 0.000040 μC, which is overwhelmingly less than that of the battery voltage detection circuit 100. In the battery voltage detection circuit 100, as long as the switches SW4M and SW3P are on even after the conversion time in the ADC 120 elapses, the charge continues to flow out. In the battery voltage detection circuits 10A and 10B, the capacitor C1 After the battery is charged, the charge does not flow out. Therefore, the battery voltage detection circuits 10A and 10B can suppress battery consumption due to the battery voltage detection operation.

Further, in the battery voltage detection circuits 10A and 10B, by providing the capacitor C5, the amount of decrease in the voltage V ^{− at} the −input terminal of the operational amplifier 20 is reduced, and current generation from the parasitic diode D1 is suppressed, and the battery voltage is detected. A reduction in accuracy can be prevented. The voltage V ^- descent amount is increased in accordance with the amplifier gain C1 / C2 of the operational amplifier 20, the voltage V by increasing the capacitance of the capacitor C5 ^- because it is possible to reduce the drop amount, the amplifier The gain C1 / C2 can be increased. That is, the amplifier gain C1 / C2 can be increased to increase the output voltage V _OUT , and the battery voltage detection accuracy can be increased.

  Further, the battery voltage detection circuit 10B detects the battery voltage by discharging the electric charge accumulated in the capacitor C2 with a constant current I4. That is, in the battery voltage detection circuit 10B, the capacitor C2 is used as a part of the AD converter. Thereby, for example, it is not necessary to separately provide the capacitor C7 required in the ADC 40 shown in FIG. 3, and the cost can be reduced. Further, in the case of the ADC 40, when the capacitor C7 is charged and the voltage rises, an error may occur in the constant current output from the current source 51 due to a change in the voltage across the current source 51. On the other hand, in the case of the battery voltage detection circuit 10B, since the voltage at the other end of the capacitor C2 (the negative input terminal of the operational amplifier 20) does not change, an error does not occur in the constant current I4 as the discharge time elapses. The voltage can be detected with high accuracy.

In addition, the battery voltage detection circuit 10B compares the measurement time according to the voltages V _{BV1 to} V _BV4 of the batteries _{BV1 to BV4} with the measurement time according to the reference voltage V _REF3 to thereby obtain the voltages V _{BV1 to} V _BV4 . Detected. Thereby, even if the clock frequency changes due to a temperature change or the like, the voltages V _{BV1 to} V _BV4 can be detected with high accuracy. Therefore, a low-cost oscillation circuit such as an RC oscillation circuit can be used, and the battery voltage can be detected with high accuracy at a low cost.

  Further, in the battery voltage detection circuits 10A and 10B, the capacitors C1 and C3 can be configured by the wiring capacity. Since the wiring capacity is generally less voltage-dependent than other capacitors, the battery voltage can be detected with high accuracy. Further, unlike the case where a resistor having a large resistance value and a small voltage dependency is provided, an existing process can be used, and an increase in cost can be suppressed.

In the battery voltage detection circuits 10A and 10B, the capacitors C1 to C4 are constituted by the wiring capacitance, and the capacitor C5 is constituted by using a dummy metal for improving the capacitance accuracy of the capacitors C1 to C4. Capacitor C5 is of the operational amplifier 20 - voltage V at the input terminal ^- is intended to suppress the drop, not the capacity of the accuracy affects the accuracy of detection of the battery voltage. Therefore, by using the dummy metal to configure the capacitor C5, the dummy metal can be used effectively, and the chip size can be reduced as compared with the case where the capacitor C5 is separately configured.

Further, in the battery voltage detection circuits 10A and 10B, the voltages V _BV1 to _BV1 to BV4 of the batteries _BV1 to BV4 are applied by sequentially applying to the capacitors C1 and C3 from the high potential side to the low potential side of the batteries _BV1 to BV4 connected in series. V _BV4 is detected efficiently. Similarly, the voltages V _{BV1 to} V _BV4 of the batteries _{BV1 to BV4} can be efficiently detected by applying the capacitors C1 and C3 in order from the high potential side to the low potential side.

  In the battery voltage detection circuits 10A and 10B, the voltage is applied to the capacitors C1 and C3 in order from the high potential side to the low potential side, and then applied to the capacitors C1 and C3 in order from the low potential side to the high potential side. Therefore, it is possible to cancel out the inflow of charges due to the currents I1 and I2, and it is possible to suppress the fluctuation of the battery voltage when the detection of the battery voltage is repeatedly performed.

  In addition, the said embodiment is for making an understanding of this invention easy, and is not for limiting and interpreting this invention. The present invention can be changed and improved without departing from the gist thereof, and the present invention includes equivalents thereof.

  For example, in the battery voltage detection circuits 10A and 10B, the voltages of the plurality of batteries BV1 to BV4 connected in series are detected, but the number of detection target batteries is not limited to a plurality, and FIG. As illustrated, a battery voltage detection circuit 10C capable of detecting the voltage of one battery BV1 may be configured.

It is a figure which shows the structure of the battery voltage detection circuit which is 1st Embodiment of this invention. It is a figure which shows the example of arrangement | positioning of the metal wiring at the time of comprising a capacitor with wiring capacity. It is a figure which shows the structural example of ADC. It is a timing chart which shows an example of operation | movement of a battery voltage detection circuit. It is a figure which shows the mode of the electric current which flows from a parasitic diode. It is a figure which shows the structure of the battery voltage detection circuit which is 2nd Embodiment of this invention. It is a timing chart which shows an example of operation | movement of a battery voltage detection circuit. It is a figure which shows the other structural example of a battery voltage detection circuit. It is a figure which shows the general structure of a battery voltage detection circuit.

Explanation of symbols

10A, 10B, 10C Battery voltage detection circuit 20 Operational amplifier C1-C7 Capacitor 30, 81, 83 Power supply 35 Switch control circuit 40 AD converter 45 Microcomputer 50, 80 Comparator 51, 77 Current source 53 N-channel MOSFET
54 Inverter 55, 82 Counter 71-75 P-channel MOSFET
D1 Parasitic diode SW0P to SW3P, SW5P, SW6P, SW1M to SW6M, SW7, SW8M Switch

Claims (7)

An operational amplifier,
A first capacitor having one end connected to one input terminal of the operational amplifier;
A second capacitor having one end connected to the output terminal of the operational amplifier and the other end connected to one input terminal of the operational amplifier;
A third capacitor having one end connected to the other input terminal of the operational amplifier;
A fourth capacitor having one end applied with a first reference voltage and the other end connected to the other input terminal of the operational amplifier;
A fifth capacitor having one end connected to one input terminal of the operational amplifier and the other end grounded;
A voltage at one terminal of the battery is applied to the other end of the first capacitor, and a voltage at the other terminal of the battery is applied to the other end of the third capacitor, and then a voltage at the other terminal of the battery is applied. A switch circuit that can be applied to the other ends of the first and third capacitors;
A discharge circuit for discharging the second and fourth capacitors before the voltage at the other terminal of the battery is applied to the other ends of the first and third capacitors;
With
The first to fourth capacitors are wiring capacitors configured by wiring in an integrated circuit, and the fifth capacitor is formed by a dummy wiring that improves the capacitance accuracy of the first to fourth capacitors,
Detecting the voltage of the battery based on the voltage of the output terminal of the operational amplifier after the voltage of the other terminal of the battery is applied to the other ends of the first and third capacitors;
A battery voltage detection circuit. An operational amplifier,
A first capacitor having one end connected to one input terminal of the operational amplifier;
A second capacitor having one end connected to the output terminal of the operational amplifier and the other end connected to one input terminal of the operational amplifier;
A third capacitor having one end connected to the other input terminal of the operational amplifier;
A fourth capacitor having one end applied with a first reference voltage and the other end connected to the other input terminal of the operational amplifier;
A voltage at one terminal of the battery is applied to the other end of the first capacitor, and a voltage at the other terminal of the battery is applied to the other end of the third capacitor, and then a voltage at the other terminal of the battery is applied. A switch circuit that can be applied to the other ends of the first and third capacitors;
A discharge circuit for discharging the second and fourth capacitors before the voltage at the other terminal of the battery is applied to the other ends of the first and third capacitors;
A switch control circuit for controlling the discharge circuit and the switch circuit;
With
The switch circuit is capable of applying the voltage of either terminal of the first and second batteries connected in series to the other end of the first and third capacitors,
The switch control circuit includes discharging the second and fourth capacitors, applying a voltage at one terminal of the first battery to the first capacitor, and applying a voltage at the other terminal of the first battery to the third capacitor. And sequentially applying the voltage of the other terminal of the first battery to the first and third capacitors, then discharging the second and fourth capacitors, one of the second batteries Application of a terminal voltage to the first capacitor, application of a voltage at the other terminal of the second battery to the third capacitor, and application of a voltage at the other terminal of the second battery to the first and third capacitors Controlling the discharge circuit and the switch circuit in order to sequentially apply to the switch,
Detecting the voltage of the first battery based on the voltage of the output terminal of the operational amplifier after the voltage of the other terminal of the first battery is applied to the other ends of the first and third capacitors; Detecting the voltage of the second battery based on the voltage of the output terminal of the operational amplifier after the voltage of the other terminal of the battery is applied to the other ends of the first and third capacitors;
A battery voltage detection circuit. The battery voltage detection circuit according to claim 2 ,
A fifth capacitor having one end connected to one input terminal of the operational amplifier and the other end grounded;
A battery voltage detection circuit. The battery voltage detection circuit according to claim 2 or 3 is an integrated circuit,
The first and third capacitors are wiring capacitances constituted by wiring in the integrated circuit;
A battery voltage detection circuit. The battery voltage detection circuit according to claim 3 is an integrated circuit ,
The first to fourth capacitors are wiring capacitances constituted by wirings in the integrated circuit, and the fifth capacitor is formed by a dummy wiring that improves the capacitance accuracy of the first to fourth capacitors;
A battery voltage detection circuit. The battery voltage detection circuit according to any one of claims 2 to 5,
The switch control circuit includes:
After the voltage at the other terminal of the second battery is applied to the first and third capacitors, the voltage at the one terminal of the second battery should be sequentially applied to the first and third capacitors. and Turkey to control the Ku before Symbol switch circuit,
A battery voltage detection circuit. The battery voltage detection circuit according to any one of claims 1 to 6,
A terminal to which one terminal of the battery is connected;
A terminal to which the other terminal of the battery is connected;
Battery voltage detection circuit comprising: a.

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