JP4887974B2 - Sampling apparatus and sampling method - Google Patents

Description

  The present invention relates to a sampling apparatus and a sampling method.

  2. Description of the Related Art Conventionally, a sampling device that samples a signal under measurement output from various devices under measurement to acquire and display sample value data has been implemented (see, for example, Patent Documents 1 to 3).

  In addition, a sampling device including an alternating current (AC) coupled AC coupling amplification unit and two sampling units is also considered. FIG. 14 shows an internal configuration of a conventional sampling apparatus 100f.

  As shown in FIG. 14, a conventional sampling device 100f includes a primary sampling unit 101, a DC bias unit 102, an AC coupling amplification unit 103, a secondary sampling unit 107, an AD conversion unit 108, A primary sampling signal generation unit 110 and a delay unit 129 are provided.

  The AC coupling amplification unit 103 is an AC coupling amplification unit that is AC coupled, and includes a capacitor 104, an amplifier 105, and a capacitor 106. The DC bias unit 102 supplies a voltage for adjusting the DC offset voltage included in the signal under measurement S0 to the primary sampling unit 101.

  FIG. 15 shows time characteristics of various signals of the sampling apparatus 100f. First, the signal under measurement S0 output from the device under measurement 200 is input to the primary sampling means 101. As shown in FIG. 15, the signal under test S0 is a signal that increases from 0 to a predetermined value and then becomes a constant value, for example.

  In the primary sampling means 101, the signal under measurement S0 is sampled in synchronization with the primary sampling signal S1 input from the primary sampling signal generation means 110 (at the timing of the rising edge), and the primary sampling is performed. It is output as a value signal S2. The primary sample value signal S2 is close to an impulse waveform and has a very small amplitude. For this reason, the amplitude is increased while the impulse waveform is blunted by passing the primary sample value signal S2 through the AC coupling amplification means 103.

  In the AC coupling amplification means 103, the primary sample value signal S2 is amplified to the amplitude necessary for the secondary sampling means 107 and output as an amplified value signal S3. As shown in FIG. 15, the amplified value signal S3 is delayed from the primary sample value signal S2. In the delay means 129, a delay amount corresponding to the delay at the time of amplification of the AC coupling amplification means 103 is given to the primary sampling signal S1 and output as the secondary sampling signal S21. In the secondary sampling means 107, the amplified value signal S3 is sampled in synchronization with the secondary sampling signal S21 (at the rising edge timing) and output as a secondary sample value signal S22.

The secondary sample value signal S22, which is an analog signal, is digitized (quantized) by the AD conversion means 108 in synchronization with the secondary sample signal S21, and is output as a digital secondary sample value signal S23. The digitized secondary sample value signal is output to an external device (not shown), for example. By combining the primary sampling means 101 and the secondary sampling means 107, a high-speed signal under measurement is down-converted to a low frequency region and converted into a signal suitable for waveform reproduction and the like.
Japanese Patent No. 3444904 JP 2000-199769 A Japanese Patent No. 3316583

  However, in the conventional sampling device 100f, the secondary sample value signal S23 shown in FIG. 15 decreases with time even though the signal to be measured S0 is constant, and the locus of the secondary sample value signal S23, An error has occurred between the locus of the secondary sample value signal S23 corresponding to the peak value of the primary sample value signal S2. Originally, these two trajectories should be similar.

  In the sampling device 100f, there is an AC coupling component between the primary sampling means 101 and the secondary sampling means 107, and the average value of the amplitude of the secondary sampling value signal S23 changes so as to be zero volt and is steady. Transition to the state. For this reason, when the peak value does not change as in the signal to be measured S0, or when the change is slow with respect to the time constant of the AC coupling component, an error has occurred in the secondary sample value signal S23.

  In order to eliminate the error of the secondary sample value signal S23, a configuration is possible in which the AC coupling amplification unit 103 is replaced with a DC amplifier and the AC coupling unit is deleted. However, the following four problems remain in the configuration replacing the DC amplifier. First, a mechanism for correcting the offset voltage of the DC amplifier is required, and the configuration becomes complicated in order to improve accuracy. Second, it is necessary to adopt a configuration in which the operating point does not change due to the DC bias voltage of the primary sampling means 101, which complicates the configuration. Thirdly, if the configuration becomes complicated due to the first and second points, the design man-hours and the cost of the AC coupling amplification means become unnecessary. Fourth, noise becomes large because the circuit configuration is complicated.

  The occurrence of an error in the secondary sample value signal S23 will be considered from another viewpoint. First, the first cause will be described. FIG. 16A shows the frequency characteristics of the primary sample value signal S2. FIG. 16B shows the frequency characteristics of the AC coupling amplification means 103. FIG. 16C shows the frequency characteristics of the amplified value signal S3.

  The frequency of the primary sampling signal S1 is set as a sampling frequency fs. As shown in FIG. 16A, the frequency characteristic after the Fourier transform of the primary sample value signal S2 has a spectrum in the vicinity of the harmonic of the sampling frequency fs (in the vicinity of a frequency that is an integral multiple of the sampling frequency fs). Further, as shown in FIG. 16B, the frequency characteristic of the AC coupling amplification means 103 is a characteristic of cutting the low frequency part and the high frequency part including the DC part (constant part).

  As shown in FIG. 16C, the amplified value signal S3 is cut at the low frequency part and the high frequency part including the DC part (constant part) of the primary sampling signal S1. By sampling the amplified value signal S3 by the secondary sampling means 107, the DC component is reproduced. However, since not all direct current components included in the original signal are reproduced, this difference causes an error.

  Next, the second cause will be described. FIG. 17 shows the measured signal frequency frc and the sampling frequency fs. FIG. 18A shows gain characteristics of the primary sampling means 101 with respect to the signal frequency to be measured frc. FIG. 18B shows gain characteristics of the primary sampling means 101 + AC coupling amplification means 103 with respect to the signal frequency to be measured frc.

  The gain characteristic of the primary sampling means 101 is preferably flat in the measurement frequency range. As shown in FIG. 17, when the primary sampling signal S1 is kept constant and the signal under measurement S0 is changed, a frequency at which the two signals are synchronized is generated.

As shown in FIG. 18A, since the signal under measurement S0 and the primary sampling signal S1 are synchronized with each other and appear as direct current, an error as shown in the first cause occurs. When the frequency of the signal under measurement S0 is frc and the frequency of the primary sampling signal S1 is fs, the output characteristics are lowered under the condition of the following equation (1).
frc ± fs × n = 0 (n = 0 to ∞) (1)
However, n is an integer that depends on the band of the primary sampling means 101.

  Here, the gain characteristics of the primary sampling means 101 described with reference to FIG. 18A are considered in combination with the AC coupling amplification means 103 having the characteristics shown in FIG. Then, as shown in FIG. 18B, the gain characteristics of the primary sampling means 101 + AC coupling amplification means 103 are AC coupled to the gain characteristics of the primary sampling means 101 with respect to the signal frequency to be measured frc. Attenuation characteristics that attenuate the amplitude in the low frequency region by the AC coupling amplification means 103 are added, and a dip characteristic is generated in the vicinity of the frequency of the condition of Expression (1). For this reason, for example, there is a difference in amplitude level between when the signal frequency to be measured frc is n times the sampling frequency and when it is not.

  Due to the first and second causes, the primary sampling means 101 + AC coupling amplification means 103 has a frequency characteristic in which the amplitude is attenuated in the low frequency region. FIG. 19A shows the waveform of the signal under measurement S0 of a PRBS (Pseudo Random Binary Sequence Code) signal. FIG. 19B shows an image of the amplitude attenuation of the secondary sample value signal S23 in the signal under measurement S0 of the PRBS signal. FIG. 19C shows an eye pattern of the secondary sample value signal S23 in the PRBS signal.

  As shown in FIG. 19A, when a PRBS signal is used as the signal to be measured S0, as shown in FIG. 19B, the secondary sample value signal S23 seems to attenuate in the time axis direction. Become. Further, the PRBS signal of the communication signal includes a low frequency component as the number of stages increases. For this reason, as shown in FIG. 19C, the eye pattern of the secondary sample value signal S23 has a tendency that the base line becomes thicker and the eye pattern is crushed.

  An object of the present invention is to easily reduce an error of a sample value generated by AC coupling amplification.

In order to solve the above-mentioned problem, the sampling device of the invention according to claim 1
Primary sampling signal generating means for generating a primary sampling signal;
Primary sampling means for sampling a signal under measurement in synchronization with the primary sampling signal to obtain a primary sample value signal;
AC coupled amplifying means for amplifying the primary sample value signal and outputting an amplified value signal;
Secondary sampling signal generating means for generating a secondary sampling signal having timings of the peak value and base value of the amplified value signal;
Secondary sampling means for sampling the amplified signal in synchronization with the secondary sampling signal to obtain a secondary sample signal;
Computing means for subtracting the base value from the peak value of the secondary sample value signal to obtain a sample value signal;
The secondary sampling signal generating means includes:
First delay means for giving a delay corresponding to a peak value of the amplified signal to the primary sampling signal to be a first delay signal;
Second delay means for providing a delay corresponding to a base value of the amplified signal to the primary sampling signal to be a second delay signal;
And an exclusive OR means for calculating an exclusive OR of the first and second delayed signals and making the second sampling signal .

The sampling device of the invention according to claim 2 comprises:
Primary sampling signal generating means for generating a primary sampling signal;
Primary sampling means for sampling a signal under measurement in synchronization with the primary sampling signal to obtain a primary sample value signal;
AC coupled amplifying means for amplifying the primary sample value signal and outputting an amplified value signal;
Secondary sampling signal generating means for generating a secondary sampling signal having timings of the peak value and base value of the amplified value signal;
Secondary sampling means for sampling the amplified signal in synchronization with the secondary sampling signal to obtain a secondary sample signal;
Computing means for subtracting the base value from the peak value of the secondary sample value signal to obtain a sample value signal;
The secondary sampling signal generating means includes:
Delay means for giving a delay corresponding to a peak value of the amplified signal to the primary sampling signal to be a delay signal;
First pulse width signal generating means for generating a first pulse width signal having a predetermined pulse width in synchronization with the rising edge of the delay signal;
Second pulse width signal generating means for generating a second pulse width signal having a predetermined pulse width in synchronization with a fall of the delay signal;
Logical OR means for calculating a logical sum of the first and second pulse width signals to obtain the second sampling signal .

The invention according to claim 3 is the sampling apparatus according to claim 1 or 2,
Quantization means for quantizing the secondary sample value signal;
The calculating means subtracts a base value from the peak value of the quantized secondary sample value signal to obtain a sample value signal.

The invention according to claim 4 is the sampling apparatus according to claim 1 or 2,
Quantization means for quantizing the sample value signal is provided.

The sampling device of the invention according to claim 5 is:
Primary sampling signal generating means for generating a primary sampling signal;
Primary sampling means for sampling a signal under measurement in synchronization with the primary sampling signal to obtain a primary sample value signal;
AC coupled amplifying means for amplifying the primary sample value signal and outputting an amplified value signal;
Secondary sampling signal generating means for generating a secondary sampling signal having timings of the peak value and base value of the amplified value signal;
Secondary sampling means for sampling the amplified signal in synchronization with the secondary sampling signal to obtain a secondary sample signal;
Computing means for subtracting the base value from the peak value of the secondary sample value signal to obtain a sample value signal;
The secondary sampling signal generating means includes:
First delay means for providing a delay corresponding to a peak value of the amplified signal to the primary sampling signal to be a first secondary sampling signal;
Second delay means for providing a delay corresponding to a base value of the amplified value signal to the primary sampling signal to be a second secondary sampling signal;
The secondary sampling means includes:
First secondary sampling means for sampling the amplified value signal in synchronization with the first secondary sampling signal to obtain a first secondary sample value signal;
A second secondary sampling means for sampling the amplified value signal in synchronization with the second secondary sampling signal to obtain a second secondary sample value signal;
The computing means subtracts the second secondary sample value signal from the first secondary sample value signal to obtain a sample value signal.

The invention according to claim 6 is the sampling apparatus according to claim 5 ,
A quantized signal generating means for generating a quantized signal in which the value of the sample value signal subtracted by the calculating means has a correct timing;
Quantizing means for quantizing the sample value signal in synchronization with the quantized signal.

The invention according to claim 7 is the sampling apparatus according to any one of claims 1 to 6 ,
Comprising at least one of display means for displaying information and recording means for recording information on a recording medium,
Control means for performing at least one of control for displaying the sampling signal on the display means and control for recording on the recording means.

The sampling method of the invention according to claim 8 is:
A primary sampling signal generating step for generating a primary sampling signal;
A primary sampling step of sampling a signal under measurement in synchronization with the primary sampling signal to obtain a primary sample value signal;
An AC coupled amplification step of amplifying the primary sample value signal and outputting an amplified value signal;
A secondary sampled signal generating step for generating a secondary sampled signal having a timing of a peak value and a base value of the amplified value signal;
A secondary sampling step of sampling the amplified signal in synchronization with the secondary sampling signal to obtain a secondary sample signal;
And subtracting the base value from the peak value of the secondary sample value signal to obtain a sample value signal,
The secondary sampling signal generation step includes:
A first delay step of giving a delay corresponding to a peak value of the amplified signal to the primary sampling signal to be a first delayed signal;
A second delay step of giving a delay corresponding to a base value of the amplified signal to the primary sampling signal to be a second delayed signal;
And an exclusive OR step of calculating an exclusive OR of the first and second delay signals to obtain the second sampling signal .

The sampling method of the invention according to claim 9 is:
A primary sampling signal generating step for generating a primary sampling signal;
A primary sampling step of sampling a signal under measurement in synchronization with the primary sampling signal to obtain a primary sample value signal;
An AC coupled amplification step of amplifying the primary sample value signal and outputting an amplified value signal;
A secondary sampled signal generating step for generating a secondary sampled signal having a timing of a peak value and a base value of the amplified value signal;
A secondary sampling step of sampling the amplified signal in synchronization with the secondary sampling signal to obtain a secondary sample signal;
And subtracting the base value from the peak value of the secondary sample value signal to obtain a sample value signal,
The secondary sampling signal generation step includes:
A delay step of giving a delay corresponding to a peak value of the amplified signal to the primary sampling signal to be a delay signal;
A first pulse width signal generating step for generating a first pulse width signal having a predetermined pulse width in synchronization with a rising edge of the delay signal;
A second pulse width signal generating step for generating a second pulse width signal having a predetermined pulse width in synchronization with a fall of the delay signal;
A logical sum step of calculating a logical sum of the first and second pulse width signals to obtain the second sampling signal .
The sampling method of the invention according to claim 10 comprises:
A primary sampling signal generating step for generating a primary sampling signal;
A primary sampling step of sampling a signal under measurement in synchronization with the primary sampling signal to obtain a primary sample value signal;
An AC coupled amplification step of amplifying the primary sample value signal and outputting an amplified value signal;
A secondary sampled signal generating step for generating a secondary sampled signal having a timing of a peak value and a base value of the amplified value signal;
A secondary sampling step of sampling the amplified signal in synchronization with the secondary sampling signal to obtain a secondary sample signal;
And subtracting the base value from the peak value of the secondary sample value signal to obtain a sample value signal,
The secondary sampling signal generation step includes:
A first delay step of providing a delay corresponding to a peak value of the amplified signal to the primary sampling signal to be a first secondary sampling signal;
A second delay step of providing the primary sampling signal with a delay corresponding to the base value of the amplified value signal to form a second secondary sampling signal;
The secondary sampling process includes:
A first secondary sampling step of sampling the amplified value signal in synchronization with the first secondary sampling signal to obtain a first secondary sample value signal;
A second secondary sampling step of sampling the amplified value signal in synchronization with the second secondary sampling signal to obtain a second secondary sample value signal;
In the calculating step, the second secondary sample value signal is subtracted from the first secondary sample value signal to obtain a sample value signal.

Claim 1, according to the invention described in 2, 8, 9, and samples the peak value and the base value of the amplification value signal of the signal to be measured, can subtract the base value from the peak value, generated by the AC coupling amplifier The error of the sample value to be reduced can be reduced. Further, a secondary sampling signal having the timing of the peak value and the base value of the amplified value signal can be easily generated.

  According to the third aspect of the invention, the error of the quantized sample value can be reduced.

  According to the fourth aspect of the invention, the error of the sample value can be reduced and the quantization can be performed.

According to the fifth and tenth aspects of the present invention, the peak value and the base value of the amplified signal of the signal under measurement can be sampled, the base value can be subtracted from the peak value, and the error of the sample value generated by the AC coupling amplification Can be reduced. Further, the sample value signal can be easily obtained by subtracting the second secondary sample value signal from the first secondary sample value signal.

According to the invention described in claim 6 , a correct value can be quantized from the sample value signal.

According to the seventh aspect of the invention, the sample value signal can be displayed at least one of display and recording on a recording medium.

  The first and second embodiments of the present invention and modifications thereof will be described in detail below with reference to the accompanying drawings. However, the scope of the invention is not limited to the illustrated examples.

(First embodiment)
A first embodiment according to the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 shows an internal configuration of the sampling apparatus 100a of the present embodiment. As shown in FIG. 1, the sampling apparatus 100a includes a primary sampling unit 101, a DC bias unit 102, an AC coupling amplification unit 103, a secondary sampling unit 107, and an AD conversion unit as a quantization unit. 108, a calculation means 109, a primary sampling signal generation means 110, delay means 111 and 112, and an exclusive OR means 113. The secondary sampling signal generating unit 301 includes a delay unit 111 as a first delay unit, a delay unit 112 as a second delay unit, and an exclusive OR unit 113.

  The AC coupling amplification means 103 includes a capacitor 104, an amplifier 105, and a capacitor 106. The device under measurement 200 is a device that outputs various signals under measurement S0 to be measured.

  The primary sampling means 101 samples the signal under measurement S0 input from the device under measurement 200 in synchronization with the primary sampling signal S1 input from the primary sampling signal generation means 110, and performs the primary sampling. Output as the value signal S2. Further, the primary sampling means 101 adjusts the DC offset voltage included in the signal under measurement S 0 according to the DC bias input from the DC bias means 102. The DC bias means 102 outputs a DC bias for adjusting the DC offset voltage included in the signal under measurement S0.

  The AC coupling amplification means 103 is an AC coupling amplification means. The capacitor 104 removes the DC component of the primary sample value signal S2 input from the primary sampling means 101. The amplifier 105 amplifies the signal input from the capacitor 104. The capacitor 106 removes the direct current component of the signal input from the amplifier 105 and outputs it as an amplified value signal S3.

  The secondary sampling means 107 samples the amplified value signal S3 input from the AC coupling amplification means 103 in synchronization with the secondary sampling signal S6 input from the exclusive OR means 113, and outputs a secondary sample value. Output as signal S7. The AD conversion means 108 digitizes the analog secondary sample value signal S7 input from the secondary sampling means 107 in synchronization with the secondary sampling signal S6 input from the secondary sampling means 107. The next sample value signal S8 is output. The calculation means 109 subtracts the base value from the temporally adjacent peak values based on the secondary sample value signal S8 input from the AD conversion means 108. The sample value signal (data) as the calculation result of the calculation means 109 is transmitted to an external device after various signal processing is performed by a control means (signal processing means) (not shown), for example.

  The primary sampling signal generation unit 110 outputs a primary sampling signal S1 having a sampling interval set in advance to the primary sampling unit 101. The delay means 111 gives a delay D1 corresponding to the delay generated by the amplification of the AC coupling amplification means 103 to the primary sampling signal S1 input from the primary sampling signal generation means 110, and outputs it as a delay signal S4. To do. The delay means 112 gives a predetermined delay D2 to the delay signal S4 input from the delay means 111, and outputs it as a delay signal S5. The delay D1 is a delay amount such that the peak portion of the amplified value signal S3 becomes the rising edge of the delay signal S4. The delay D2 is a delay amount for setting the duty ratio of the secondary sampling signal S6.

  The exclusive OR unit 113 performs an exclusive OR on the delay signal S4 input from the delay unit 111 and the delay signal S5 input from the delay unit 112 to obtain a secondary sampled signal S6 as a secondary signal. The data is output to the sampling means 107 and the AD conversion means 108.

  Next, the operation of the sampling apparatus 100a will be described with reference to FIG. FIG. 2 shows time characteristics of various signals of the sampling apparatus 100a.

  First, the signal under measurement S0 output from the device under measurement 200 is input to the primary sampling means 101. As shown in FIG. 2, the signal under measurement S0 is, for example, a signal that increases from 0 to a predetermined value and then becomes a constant value.

  In the primary sampling means 101, the signal under measurement S0 is sampled in synchronization with the primary sampling signal S1 input from the primary sampling signal generation means 110 (at the timing of the rising edge), and the primary sampling is performed. It is output as a value signal S2.

  In the AC coupling amplification means 103, the primary sample value signal S2 is amplified to the amplitude necessary for the secondary sampling means 107 and output as an amplified value signal S3. As shown in FIG. 2, the amplified value signal S3 has a delay D1 from the primary sample value signal S2. In the delay means 111, the delay D1 is given to the primary sampling signal S1 and output as the delay signal S4. In the delay means 112, the delay D2 is given to the delay signal S4 and output as the secondary sampling signal S5. The exclusive OR means 113 performs exclusive OR on the delayed signals S4 and S5 and outputs the result as a secondary sampling signal S6.

  As shown in FIG. 2, the secondary sampling signal S6 is a signal whose timing rises alternately between the peak value of the amplified value signal S3 and the base value of the amplified value signal S3. In the secondary sampling means 107, the amplified value signal S3 is sampled in synchronization with the secondary sampling signal S6 (at the rising edge timing) and output as the secondary sampling value signal S7.

  The secondary sample value signal S7, which is an analog signal, is digitized (quantized) by the AD conversion means 108 and output as a digital secondary sample value signal S8. The secondary sample value signal S8 is a signal in which the digital peak values ai and base values bi (i = 1 to n..., N: integer) of the amplified value signal S3 are alternately arranged over time. Then, the calculation means 109 calculates (ai−bi) using the peak value ai and the base value bi of the secondary sample value signal S8, and acquires the sample value signal as the calculation result.

  As shown in FIG. 2, it can be seen that the data of the calculation result of (ai−bi) does not cause attenuation (error from the peak value) due to the passage of time of the secondary sample value signal.

  As described above, according to the present embodiment, the signal under test S0 is sampled by the primary sampling unit 101 and amplified by the AC coupling amplification unit 103, and then includes the timing of the peak value and the base value of the amplified value signal S3. Since the amplified value signal S3 is sampled by the secondary sampling means 107 based on the secondary sampling signal S6, and the base value is subtracted from the peak value of the secondary sampling value signal S8 by the computing means 109 to obtain a sample value signal. The error of the sample value generated by the AC coupling amplification means 103 can be easily reduced.

  Further, the AD sampler 108 can quantize the secondary sample value signal. Further, the secondary sampling signal generating means 301 can easily generate the secondary sampling signal S6 having the timing of the peak value and base value of the amplified value signal S3.

(First modification)
With reference to FIG. 3, a first modification as a modification of the first embodiment will be described. FIG. 3 shows the internal configuration of the sampling apparatus 100b. In the present modification, parts different from those in the first embodiment will be mainly described, and the same means as those in the first embodiment are denoted by the same reference numerals and description thereof will be omitted.

  The sampling apparatus 100b of this modification functions as an oscilloscope. As shown in FIG. 3, the sampling apparatus 100b includes a primary sampling unit 101, a DC bias unit 102, an AC coupling amplification unit 103, a secondary sampling unit 107, an AD conversion unit 108, and a calculation unit. 109, primary sampling signal generation means 110, secondary sampling signal generation means 301 (delay means 111, 112, exclusive OR means 113), trigger signal generation means 114, control means 115, recording Means 116 and display means 117 are provided.

  The trigger signal generation means 114 outputs a trigger signal S30 synchronized with the signal under measurement S0 input from the device under measurement 200 to the primary sampling signal generation means 110 and the control means 115. The primary sampling signal generation unit 110 generates a primary sampling signal in synchronization with the trigger signal S30 input from the trigger signal generation unit 114 and outputs the primary sampling signal to the primary sampling unit 101 and the delay unit 111.

  The calculation means 109 subtracts the base value bi from the peak value ai of the secondary sample value signal S8 and outputs the calculation result as a sample value signal (data) S9. The control unit 115 performs various signal processing on the sample value signal S9 input from the calculation unit 109 using the trigger signal S30 input from the trigger signal generation unit 114 as a trigger, and the recording unit 116 and the display unit 117 together with the control signal. Output to at least one.

  The recording unit 116 includes a printing unit that records an image on a recording medium (recording paper), and prints a graph of the waveform of the sample value on the recording paper based on the control signal and the sample value signal transmitted from the control unit 115. To do. The display unit 117 includes a display unit such as an LCD (Liquid Crystal Display), and displays a waveform graph of the sample value based on the control signal and the sample value signal transmitted from the control unit 115.

  As described above, according to the present modification, the same effect as that of the first embodiment is obtained, and at least one of the display of the sample value signal and the recording on the recording medium is performed by the recording unit 116 and the display unit 117. It can be carried out. Further, the trigger signal generation means 114 can generate the primary sampling signal S1 in synchronization with the signal under measurement S0.

(Second modification)
A second modification as a modification of the first embodiment will be described with reference to FIGS. 4 and 5. In the present modification, parts different from those in the first embodiment will be mainly described, and the same means as those in the first embodiment are denoted by the same reference numerals and description thereof will be omitted.

  FIG. 4 shows the internal configuration of the secondary sampling signal generating means 302. As shown in FIG. 4, the sampling apparatus according to the present modification has a configuration in which the secondary sampling signal generation means 301 is replaced with a secondary sampling signal generation means 302 in the sampling apparatus 100a of the first embodiment. It is.

  The secondary sampling signal generation means 302 includes a delay means 118, a monostable multivibrator 119 as a first pulse width signal generation means, a monostable multivibrator 120 as a second pulse width signal generation means, And summing means 121. The delay means 118 gives a delay D3 corresponding to the delay generated by the amplification of the AC coupling amplification means 103 to the primary sampling signal S1 inputted from the primary sampling signal generation means 110, and outputs it as a delay signal S10. .

  The monostable multivibrator 119 is means for outputting a pulse having a predetermined width with the rising edge of the input signal as a trigger. The monostable multivibrator 119 generates and outputs a pulse width signal S11 having a pulse width necessary for sampling by the secondary sampling unit 107 in synchronization with the rising edge of the delay signal S10 input from the delay unit 118. The monostable multivibrator 120 is a means for outputting a pulse having a predetermined width triggered by a falling edge of an input signal. The monostable multivibrator 120 is synchronized with the falling edge of the delay signal S10 input from the delay means 118, and has a pulse width necessary for sampling by the secondary sampling means 107 (for example, the same pulse width as the pulse width signal S11). ) Is generated and output.

  The logical sum means 121 performs a logical sum (OR operation) on the pulse width signal S11 input from the monostable multivibrator 119 and the pulse width signal S12 input from the monostable multivibrator 120, and performs secondary sampling. The signal S13 is output to the secondary sampling means 107 and AD conversion means 108. The secondary sampling means 107 and the AD conversion means 108 generate and output secondary sample value signals S7 and S8, respectively, using the secondary sampling signal S13 input from the logical sum means 121.

  FIG. 5 shows the time characteristics of various signals in the secondary sampling signal generating means 302. As shown in FIG. 5, the delay signal S10 is given a delay D3 by the delay means 118 to the primary sampling signal S1. The pulse width signal S11 has a predetermined pulse width high in response to the rising edge of the delay signal S10. The pulse width signal S12 has a predetermined pulse width high in response to the falling edge of the delay signal S10. The secondary sampling signal S13 is a signal obtained by adding high of the pulse width signals S11 and S12.

  As described above, according to the present modification, the secondary sample having the same effect as the first embodiment and having the timing of the peak value and the base value of the amplified value signal S3 by the secondary sampling signal generation means 302 is obtained. The signal S6 can be easily generated.

(Third Modification)
With reference to FIG.6 and FIG.7, the 3rd modification as a modification of the said 1st Embodiment is demonstrated. It should be noted that in the present modification, the differences from the first embodiment and the first modification will be mainly described, and the same reference numerals are given to the same means as those in the first embodiment and the first modification. The description is omitted.

  FIG. 6 shows the internal configuration of the sampling apparatus 100c. As shown in FIG. 6, the sampling apparatus 100c includes a primary sampling unit 101, a DC bias unit 102, an AC coupling amplification unit 103, and a secondary sampling unit 122 as a first secondary sampling unit. Secondary sampling means 123 as second secondary sampling means, calculation means 124, AD conversion means 108, primary sampling signal generation means 110, secondary sampling signal generation means 303, , A delay unit 127 as a quantized signal generation unit, a trigger signal generation unit 114, a control unit 115, a recording unit 116, and a display unit 117. The secondary sampling signal generation unit 303 includes a delay unit 125 as a first delay unit and a delay unit 126 as a second delay unit.

  The secondary sampling means 122 samples the amplified value signal S3 input from the AC coupling amplification means 103 in synchronization with the secondary sampling signal S14 input from the delay means 125, and obtains it as a secondary sample value signal S17. Output. The secondary sampling means 123 samples the amplified value signal S3 input from the AC coupling amplification means 103 in synchronization with the secondary sampling signal S15 input from the delay means 126, and obtains it as a secondary sample value signal S18. Output.

  The calculation means 124 subtracts the secondary sample value signal S18 input from the secondary sampling means 123 from the secondary sample value signal S17 input from the secondary sampling means 122, and outputs the result as a subtraction value signal S19. To do. The AD conversion means 108 digitizes the analog subtraction value signal S19 input from the calculation means 124 in synchronization with the quantized signal S16 input from the delay means 127, and outputs it as a sample value signal S20. The control unit 115 performs various signal processing on the sample value signal S20 input from the AD conversion unit 108 using the trigger signal S30 input from the trigger signal generation unit 114 as a trigger, and the recording unit 116 and the display unit 117 together with the control signal. To at least one of the

  The delay unit 125 gives a delay D4 corresponding to the delay generated by the amplification of the AC coupling amplification unit 103 to the primary sampled signal S1 input from the primary sampled signal generation unit 110, thereby providing a secondary sampled signal. Output as S14. The delay means 126 gives a predetermined delay D5 to the primary sampling signal S1 input from the primary sampling signal generation means 110, and outputs it as a secondary sampling signal S15. The delay unit 127 gives a predetermined delay D6 to the primary sampled signal S1 input from the primary sampled signal generation unit 110, and outputs it as a quantized signal S16. The delay D4 is a delay amount such that the peak portion of the amplified value signal S3 becomes the rising edge of the secondary sampling signal S14. The delay D5 is a delay amount such that the base portion of the amplified value signal S3 becomes the rising edge of the secondary sampling signal S15.

  The subtraction value signal S19 has the correct value (ai-bi) for the peak value ai and the base value bi of the amplified value signal S3, but (ai-b (i-1)) and (ai-bi) They are lined up alternately over time. For this reason, the delay D6 is a delay amount such that the value of the subtraction value signal S19 of the calculation means 124 rises at the right timing when the quantized signal S16 rises.

  Next, the operation of the sampling apparatus 100c will be described with reference to FIG. FIG. 7 shows time characteristics of various signals of the sampling apparatus 100c.

  The process until the generation of the amplified value signal S3 is the same as that in the first embodiment. In the delay means 125, the delay D4 is given to the primary sampling signal S1 and output as the secondary sampling signal S14. In the delay means 126, the delay D5 is given to the primary sampling signal S1 and output as the secondary sampling signal S15. In the delay means 127, the delay D6 is given to the primary sampling signal S1 and output as the quantized signal S16.

  As shown in FIG. 7, the secondary sampling signal S14 is a signal having a timing at which each rising edge of the signal coincides with the peak value of the amplified value signal S3. As shown in FIG. 7, the secondary sampling signal S15 is a signal having a timing at which each rising edge of the signal coincides with the base value of the amplified value signal S3. As shown in FIG. 7, the quantized signal S <b> 16 becomes a signal at a timing at which each rising edge of the signal becomes the correct value of the subtraction value signal S <b> 19.

  In the secondary sampling means 122, the amplified value signal S3 is sampled in synchronization with the secondary sampling signal S14 (at the timing of the rising edge) and output as the secondary sampling value signal S17. In the secondary sampling means 123, the amplified value signal S3 is sampled in synchronization with the secondary sampling signal S15 (at the timing of the rising edge) and output as the secondary sample value signal S18. The secondary sample value signals S17 and S18 are calculated by the calculation means 124 as the secondary sample value signal S17-secondary sample value signal S18 and output as the subtraction value signal S19.

  The subtraction value signal S19, which is an analog signal, is digitized (quantized) in synchronization with the quantized signal S16 by the AD conversion means 108 and output as a digital sample value signal S20. As shown in FIG. 7, it can be seen that the data of the sample value signal S20 is not attenuated (error from the peak value) over time of the secondary sample value signal.

  As described above, according to the present modification, the same effects as those of the first embodiment can be obtained, and the secondary sampling signals S14 and S15 including the timing of the peak value and the base value of the amplified value signal S3 can be used. The amplified value signal S3 is sampled separately by the sampling means 122, 123, and the secondary sample value signal S18 is subtracted from the secondary sample value signal S17 by the calculating means 124 to obtain the sample value signal. The sample value signal can be easily obtained by subtracting the secondary sample value signal S18 from S17.

  Further, since the AD conversion means 108 quantizes the subtraction value signal S19 based on the quantization signal S16, a correct value can be quantized from the subtraction value signal S19 (sampled signal).

(Second Embodiment)
A second embodiment according to the present invention will be described with reference to FIGS. In the present embodiment, portions different from those in the first embodiment will be mainly described, and the same means as those in the first embodiment are denoted by the same reference numerals and description thereof will be omitted.

  FIG. 8 shows an internal configuration of the sampling apparatus 100d of the present embodiment. As shown in FIG. 8, the sampling apparatus 100d includes a primary sampling unit 101, a DC bias unit 102, an AC coupling amplification unit 103, a secondary sampling unit 107, an AD conversion unit 108, and a filter 128. And a primary sampling signal generation means 110, a delay means 129, and a control means 115.

  The secondary sampling means 107 samples the amplified value signal S3 input from the AC coupling amplification means 103 in synchronization with the secondary sampling signal S21 input from the delay means 129, and obtains it as a secondary sample value signal S22. Output. The AD conversion means 108 digitizes the analog secondary sample value signal S22 input from the secondary sampling means 107 and outputs it as a secondary sample value signal S23. The filter 128 is a digital filter having a filter characteristic that cancels the attenuation of the secondary sample value signal S23. The filter 128 filters the secondary sample value signal S23 input from the secondary sampling means 107 and outputs it as the sample value signal S24.

  The control means 115 performs various signal processes on the sample value signal S24 input from the filter 128. The sample value signal S24 subjected to various signal processing is transmitted to, for example, an external device. The delay means 129 gives a delay D7 generated by the amplification of the AC coupling amplifying means 103 to the primary sampling signal S1 input from the primary sampling signal generation means 110, and gives a secondary as the secondary sampling signal S21. Output to the sampling means 107. The delay D7 of the delay means 129 is a delay amount such that the peak portion of the amplified value signal S3 becomes the rising edge of the secondary sampling signal S21.

  Next, the operation of the sampling apparatus 100d will be described with reference to FIG. FIG. 9 shows time characteristics of various signals of the sampling apparatus 100d.

  The process until the generation of the amplified value signal S3 is the same as that in the first embodiment. In the delay means 129, a predetermined delay is given to the primary sampling signal S1 and output as the secondary sampling signal S21. As shown in FIG. 9, the secondary sampling signal S21 is a signal having a timing at which each rising edge of the signal coincides with the peak value of the amplified value signal S3.

  In the secondary sampling means 107, the amplified value signal S3 is sampled in synchronization with the secondary sampling signal S21 (at the rising edge timing) and output as a secondary sample value signal S22. The secondary sampling signal S21, which is an analog signal, is digitized (quantized) by the AD conversion means 108 and output as a digital secondary sampling value signal S23. Then, the filter 128 filters the digital secondary sample value signal S 23 so as to cancel the attenuation, and outputs the sample value signal S 24 to the control means 115. As shown in FIG. 2, it can be seen that the data of the sample value signal S20 is not attenuated (error from the peak value) over time of the secondary sample value signal.

  Here, an example of the filter 128 will be described with reference to FIGS. 10 and 11. FIG. 10 shows the time characteristics of each signal related to the filter 128. FIG. 11 shows the internal configuration of the filter 128.

As shown in FIG. 10, it is assumed that a signal under measurement S0 is given. The waveform of the secondary sample value signal S23 is a step response (continuous signal), and values A and B and a sampling time interval Δt are set as shown in FIG. Then, the secondary sample value signal S23 is
x (t) = (Ae ^{(−Δt / T)} + B) · u (t) (2)
And can be put. Where T is the time constant of the step.

When the time interval is constant and the time constant is known, Ae ^{(−Δt / T)} in equation (2) can be replaced with Ak ^m by the bottom conversion formula, and equation (2) can be expressed by the following equation (3): It is expressed as
^{x (t) = (Ak m} + B) · u (t) ... (3)
However, “m = 0, 1, 2... N” and “0 <k <1”.

When this signal x (t) is Z-transformed (discrete signal), it can be transformed as in the following equation (4).

Furthermore, by differentiating the equation (4), the transfer function F (z) can be obtained by the following equation (5).

Equation (5) becomes the transfer function F (z) in the Z region. Correction is performed by multiplying the waveform of the secondary sample value signal S23 by the reciprocal characteristic transfer function (digital filter) of the equation (5), and the original DC and low frequency components can be restored. This filter characteristic F (Z) ′ is shown in the following equation (6).

  An example of the filter 128 having the filter characteristic shown in Expression (6) is shown in FIG. The filter 128 shown in FIG. 11 includes a delay element 130, a −k coefficient multiplier 131, an adder 132, an A + B coefficient multiplier 133, an adder 134, a delay element 135, and (A + kB) / (A + B) multiplier 136.

  FIG. 12A shows an eye pattern of the signal under measurement S0. FIG. 12B shows an eye pattern of the secondary sample value signal S23. FIG. 12C shows an eye pattern of the sample value signal S24. As shown in FIG. 12A, the signal under test S0 has an eye pattern with a thin line. As shown in FIG. 12B, the signal under measurement S0 is subjected to primary sampling means 101 and AC coupling amplification means. Through 103, the base line of the eye pattern of the secondary sample value signal S23 becomes thicker. For this reason, by filtering the secondary sample value signal S23 with the filter 128, the eye pattern of the sample value signal S24 has a narrow base line, and the sample value signal can be reproduced without destroying the eye pattern.

  As described above, according to the present embodiment, the signal under test S0 is sampled by the primary sampling means 101, amplified by the AC coupling amplification means 103, and then the amplified value signal S3 is sampled by the secondary sampling means 107, Since filtering for reducing the attenuation characteristic of the amplified value signal S3 is performed on the secondary sample value signal S22 by the filter 128, the error of the sample value generated by the AC coupling amplification means 103 that is AC coupled can be easily reduced. Further, the AD conversion means 108 can quantize the sample value signal.

(Fourth modification)
A fourth modification as a modification of the second embodiment will be described with reference to FIG. It should be noted that in the present modification, the differences from the second embodiment and the first modification will be mainly described, and the same reference numerals are given to the same means as those in the second embodiment and the first modification. The description is omitted.

  FIG. 13 shows an internal configuration of the sampling apparatus 100e. The sampling apparatus 100e according to this modification functions as an oscilloscope. As shown in FIG. 13, the sampling device 100e includes a primary sampling unit 101, a DC bias unit 102, an AC coupling amplification unit 103, a secondary sampling unit 107, an AD conversion unit 108, and a primary unit. The sampling signal generation means 110, the trigger signal generation means 114, the delay means 129, the filter 128, the control means 115, the recording means 116, and the display means 117 are configured.

  The control means 115 performs various signal processings on the sample value signal S24 input from the filter 128, and outputs it to at least one of the recording means 116 and the display means 117 together with the control signal.

  According to this modification, the same effects as those of the second embodiment can be obtained, and the recording means 116 and the display means 117 can display the sampled sample value signal, record it on the recording medium, and display the sample value signal. At least one of recording on the recording medium can be performed. Further, the trigger signal generation means 114 can generate the primary sampling signal S1 in synchronization with the signal under measurement S0.

  Note that the descriptions in the above embodiments and modifications are examples of the sampling apparatus and the sampling method according to the present invention, and the present invention is not limited thereto. For example, it is good also as comprising combining at least 2 of the structure of each embodiment and each modification.

  In the first embodiment, the calculation unit 109 is provided. However, the present invention is not limited to this. The sampling device 100a outputs the secondary sample value signal S7 to the outside, The secondary sample value signal S7 may be configured to perform an AD conversion or a calculation by subtracting the base value from the peak value.

  In the first embodiment and the first and second modifications, the secondary sample value signal S7 is subjected to arithmetic processing after AD conversion. However, the present invention is not limited to this. It may be configured to perform AD conversion later.

  In the first embodiment and the first and second modifications, the secondary sampling signal generating means is configured as the secondary sampling signal generating means 301 and 302. However, the present invention is not limited to this. Instead, it may be realized by another configuration.

  In the third modification, the secondary sampling signals S14 and S15 and the quantized signal S16 are generated by the delay units 125 to 127 connected in parallel. However, the present invention is not limited to this. It may be realized by other configurations. For example, the delay units 125 to 127 may be connected in series.

  In the second embodiment and the fourth modification, the secondary sample value signal S22 is subjected to filtering after AD conversion. However, the present invention is not limited to this, and AD conversion after filtering is performed. It is good also as a structure to perform. In this case, the AD converter 108 may be provided outside the sampling apparatus 100d.

  In addition, the detailed configurations and detailed operations of the sampling apparatuses 100a to 100e in the above embodiments and modifications can be appropriately changed without departing from the spirit of the present invention.

It is a block diagram which shows the internal structure of the sampling apparatus 100a of 1st Embodiment which concerns on this invention. It is a timing chart which shows the various signals of sampling apparatus 100a. It is a block diagram which shows the internal structure of the sampling apparatus 100b. 3 is a block diagram showing an internal configuration of secondary sampling signal generation means 302. FIG. 4 is a timing chart showing various signals in secondary sampling signal generating means 302. It is a block diagram which shows the internal structure of the sampling apparatus 100c. It is a timing chart which shows various signals of sampling device 100c. It is a block diagram which shows the internal structure of the sampling apparatus 100d of 2nd Embodiment which concerns on this invention. It is a timing chart which shows various signals of sampling device 100d. 3 is a timing chart showing signals related to a filter 128. 2 is a diagram showing an internal configuration of a filter 128. FIG. (A) is a figure which shows the eye pattern of measured signal S0. (B) is a diagram showing an eye pattern of the secondary sample value signal S23. (C) is a diagram showing an eye pattern of the sample value signal S24. It is a block diagram which shows the internal structure of the sampling apparatus 100e. It is a block diagram which shows the internal structure of the conventional sampling apparatus 100f. It is a timing chart which shows various signals of sampling device 100f. (A) is a figure which shows the frequency characteristic of the primary sample value signal S2. FIG. 6B is a diagram illustrating frequency characteristics of the AC coupling amplification unit 103. (C) is a figure which shows the frequency characteristic of amplified value signal S3. It is a figure which shows the to-be-measured signal frequency frc and the sampling frequency fs. (A) is a figure which shows the gain characteristic with respect to the to-be-measured signal frequency frc of the primary sampling means 101. FIG. (B) is a diagram showing gain characteristics of the primary sampling means 101 + AC coupling amplification means 103 with respect to the signal frequency to be measured frc. (A) is a figure which shows the waveform of measured signal S0 of a PRBS signal. (B) is a figure which shows the image of the attenuation | damping of the amplitude of the secondary sample value signal S23 in the to-be-measured signal S0 of a PRBS signal. (C) is a figure which shows the eye pattern of the secondary sample value signal S23 in a PRBS signal.

Explanation of symbols

100a, 100b, 100c, 100d, 100e, 100f Sampling apparatus 101 Primary sampling means 102 DC bias means 103 AC coupling amplification means 104, 106 Capacitor 105 Amplifiers 107, 122, 123 Secondary sampling means 108 AD conversion means 109 , 124 arithmetic means 110 primary sampling signal generation means 301, 302, 303 secondary sampling signal generation means 111, 112, 118, 125, 126, 127, 129 delay means 113 exclusive OR means 114 trigger signal generation means 115 control means 116 recording means 117 display means 119, 120 monostable multivibrator 128 filter 130, 135 delay element 131, 133, 136 coefficient multiplier 132, 134 adder 200 device under test

Claims (10)

Primary sampling signal generating means for generating a primary sampling signal;
Primary sampling means for sampling a signal under measurement in synchronization with the primary sampling signal to obtain a primary sample value signal;
AC coupled amplifying means for amplifying the primary sample value signal and outputting an amplified value signal;
Secondary sampling signal generating means for generating a secondary sampling signal having timings of the peak value and base value of the amplified value signal;
Secondary sampling means for sampling the amplified signal in synchronization with the secondary sampling signal to obtain a secondary sample signal;
Computing means for subtracting the base value from the peak value of the secondary sample value signal to obtain a sample value signal;
The secondary sampling signal generating means includes:
First delay means for giving a delay corresponding to a peak value of the amplified signal to the primary sampling signal to be a first delay signal;
Second delay means for providing a delay corresponding to a base value of the amplified signal to the primary sampling signal to be a second delay signal;
A sampling apparatus comprising: exclusive OR means for calculating an exclusive OR of the first and second delayed signals and using the exclusive OR as the second sampling signal . Primary sampling signal generating means for generating a primary sampling signal;
Primary sampling means for sampling a signal under measurement in synchronization with the primary sampling signal to obtain a primary sample value signal;
AC coupled amplifying means for amplifying the primary sample value signal and outputting an amplified value signal;
Secondary sampling signal generating means for generating a secondary sampling signal having timings of the peak value and base value of the amplified value signal;
Secondary sampling means for sampling the amplified signal in synchronization with the secondary sampling signal to obtain a secondary sample signal;
Computing means for subtracting the base value from the peak value of the secondary sample value signal to obtain a sample value signal;
The secondary sampling signal generating means includes:
Delay means for giving a delay corresponding to a peak value of the amplified signal to the primary sampling signal to be a delay signal;
First pulse width signal generating means for generating a first pulse width signal having a predetermined pulse width in synchronization with the rising edge of the delay signal;
Second pulse width signal generating means for generating a second pulse width signal having a predetermined pulse width in synchronization with a fall of the delay signal;
A sampling device comprising: OR means for calculating a logical sum of the first and second pulse width signals to obtain the second sampling signal. Quantization means for quantizing the secondary sample value signal;
The sampling apparatus according to claim 1 or 2, wherein the arithmetic means subtracts a base value from the peak value of the quantized secondary sample value signal to obtain a sample value signal. Sampling apparatus according to claim 1 or 2, characterized in that it comprises a quantization unit for quantizing the sampled value signal. Primary sampling signal generating means for generating a primary sampling signal;
Primary sampling means for sampling a signal under measurement in synchronization with the primary sampling signal to obtain a primary sample value signal;
AC coupled amplifying means for amplifying the primary sample value signal and outputting an amplified value signal;
Secondary sampling signal generating means for generating a secondary sampling signal having timings of the peak value and base value of the amplified value signal;
Secondary sampling means for sampling the amplified signal in synchronization with the secondary sampling signal to obtain a secondary sample signal;
Computing means for subtracting the base value from the peak value of the secondary sample value signal to obtain a sample value signal;
The secondary sampling signal generating means includes:
First delay means for providing a delay corresponding to a peak value of the amplified signal to the primary sampling signal to be a first secondary sampling signal;
Second delay means for providing a delay corresponding to a base value of the amplified value signal to the primary sampling signal to be a second secondary sampling signal;
The secondary sampling means includes:
First secondary sampling means for sampling the amplified value signal in synchronization with the first secondary sampling signal to obtain a first secondary sample value signal;
A second secondary sampling means for sampling the amplified value signal in synchronization with the second secondary sampling signal to obtain a second secondary sample value signal;
The sampling device according to claim 1, wherein the arithmetic means subtracts the second secondary sample value signal from the first secondary sample value signal to obtain a sample value signal. A quantized signal generating means for generating a quantized signal in which the value of the sample value signal subtracted by the calculating means has a correct timing;
6. The sampling apparatus according to claim 5 , further comprising: a quantization unit that quantizes the sample value signal in synchronization with the quantization signal. Comprising at least one of display means for displaying information and recording means for recording information on a recording medium,
According to any one of claims 1 to 6, characterized in that and a control means for performing at least one control to record the control and the recording device displays the sampled signals to said display means Sampling device. A primary sampling signal generating step for generating a primary sampling signal;
A primary sampling step of sampling a signal under measurement in synchronization with the primary sampling signal to obtain a primary sample value signal;
An AC coupled amplification step of amplifying the primary sample value signal and outputting an amplified value signal;
A secondary sampled signal generating step for generating a secondary sampled signal having a timing of a peak value and a base value of the amplified value signal;
A secondary sampling step of sampling the amplified signal in synchronization with the secondary sampling signal to obtain a secondary sample signal;
And subtracting the base value from the peak value of the secondary sample value signal to obtain a sample value signal,
The secondary sampling signal generation step includes:
A first delay step of giving a delay corresponding to a peak value of the amplified signal to the primary sampling signal to be a first delayed signal;
A second delay step of giving a delay corresponding to a base value of the amplified signal to the primary sampling signal to be a second delayed signal;
A sampling method comprising: calculating an exclusive OR of the first and second delay signals and using the exclusive OR as the second sampling signal . A primary sampling signal generating step for generating a primary sampling signal;
A primary sampling step of sampling a signal under measurement in synchronization with the primary sampling signal to obtain a primary sample value signal;
An AC coupled amplification step of amplifying the primary sample value signal and outputting an amplified value signal;
A secondary sampled signal generating step for generating a secondary sampled signal having a timing of a peak value and a base value of the amplified value signal;
A secondary sampling step of sampling the amplified signal in synchronization with the secondary sampling signal to obtain a secondary sample signal;
And subtracting the base value from the peak value of the secondary sample value signal to obtain a sample value signal,
The secondary sampling signal generation step includes:
A delay step of giving a delay corresponding to a peak value of the amplified signal to the primary sampling signal to be a delay signal;
A first pulse width signal generating step for generating a first pulse width signal having a predetermined pulse width in synchronization with a rising edge of the delay signal;
A second pulse width signal generating step for generating a second pulse width signal having a predetermined pulse width in synchronization with a fall of the delay signal;
And a logical sum step of calculating a logical sum of the first and second pulse width signals to obtain the second sampling signal. A primary sampling signal generating step for generating a primary sampling signal;
A primary sampling step of sampling a signal under measurement in synchronization with the primary sampling signal to obtain a primary sample value signal;
An AC coupled amplification step of amplifying the primary sample value signal and outputting an amplified value signal;
A secondary sampled signal generating step for generating a secondary sampled signal having a timing of a peak value and a base value of the amplified value signal;
A secondary sampling step of sampling the amplified signal in synchronization with the secondary sampling signal to obtain a secondary sample signal;
And subtracting the base value from the peak value of the secondary sample value signal to obtain a sample value signal,
The secondary sampling signal generation step includes:
A first delay step of providing a delay corresponding to a peak value of the amplified signal to the primary sampling signal to be a first secondary sampling signal;
A second delay step of providing the primary sampling signal with a delay corresponding to the base value of the amplified value signal to form a second secondary sampling signal;
The secondary sampling process includes:
A first secondary sampling step of sampling the amplified value signal in synchronization with the first secondary sampling signal to obtain a first secondary sample value signal;
A second secondary sampling step of sampling the amplified value signal in synchronization with the second secondary sampling signal to obtain a second secondary sample value signal;
In the sampling method, the calculation step subtracts the second secondary sample value signal from the first secondary sample value signal to obtain a sample value signal.

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