JP4890396B2 - Staff multiplex transmission equipment - Google Patents

Description

  The present invention relates to a stuff multiplex transmission apparatus, and more particularly to a stuff multiplex transmission apparatus that can suppress a speed change amount (jitter amount) of low-speed side transmission line data due to insertion of stuff bits.

  In a stuff multiplex transmission device, a low-speed data signal to be multiplexed is bit-multiplexed with an asynchronous clock that is slightly faster than an integer multiple of the speed, and stuff bits are inserted if there is no signal to be transmitted. The transmission path frame is configured, and the transmission path frame is sent to the transmission path.

  On the receiving side, the transmission path frame received by the transmission path clock is disassembled to extract a low-speed data signal, valid data is stored in the speed conversion memory, and stuff bits are discarded. The clock source of the low-speed data signal on the receiving side uses an oscillator capable of frequency control, and reads the data from the address of the speed conversion memory specified by the counter value that is incremented by the clock signal output from the oscillator. To output a low-speed data signal.

  The frequency of the above oscillator is controlled according to the phase difference between the write cycle and the read cycle of the speed conversion memory, and the write speed is higher than the read speed with the specified clock frequency defined as the speed of the low-speed data signal as the center frequency. When the speed is high, the frequency is increased, and when the writing speed is slower than the reading speed, the frequency is controlled to be low, thereby reproducing the clock of the low-speed data signal of the transmission source. Using the clock of the low-speed data signal reproduced in this way, data is read from the speed conversion memory, and data transmission is performed by outputting a low-speed data signal.

  A specific configuration of the reception side of the conventional stuff multiplex transmission apparatus will be described below with reference to FIG. The stuff multiplex transmission apparatus receives a transmission line frame from a high-speed transmission line by a receiver 10-8, performs frame synchronization detection on the transmission line frame by a frame synchronization detection circuit 10-9, and performs a frame synchronization detection circuit 10-. 9 outputs a high-speed transmission path clock, stuff information indicating insertion of stuff bits, an enable signal for separating multiplexed transmission data, and transmission data to a circuit corresponding to each channel.

  The circuit corresponding to each channel includes an AND gate 10-1 for generating a write enable signal for writing only valid transmission data excluding stuff bits from the stuff information extracted from the transmission path frame and the enable signal, and a high speed Phase for comparing write address and read address with write address counter 10-2 operating with side transmission path clock, speed conversion memory 10-3, read address counter 10-4 operating with low speed side transmission path clock Comparing circuit 10-5, voltage controlled crystal oscillator (VCXO) 10-6 having a low-speed transmission line clock as a center frequency, and driver 10-7 for generating a low-speed transmission line signal. The

  The figure shows the configuration of the first channel corresponding circuit for the stuff multiplex transmission apparatus having four channel corresponding circuits, but the configuration of the other second to fourth channel corresponding circuits is the first one. The configuration is the same as that of the channel corresponding circuit.

  FIG. 11 shows a detailed configuration of each channel corresponding circuit. In each channel corresponding circuit, a memory that performs writing and reading asynchronously is used as the speed conversion memory 10-3. The write address counter 10-2 counts up every time transmission data is written in the speed conversion memory 10-3, and is a ring counter that advances cyclically up to a value equal to the address space of the speed conversion memory 10-3. This count value becomes the write address of the speed conversion memory 10-3.

  The read address counter 10-4 counts up every time transmission data is read from the speed conversion memory 10-3 and cyclically advances with a value equal to the address space of the speed conversion memory 10-3 as an upper limit. This count value becomes the read address of the speed conversion memory 10-3.

  The phase comparison circuit 10-5 compares the write address value and the read address value of the speed conversion memory 10-3, detects the phase difference between the write timing and the read timing of the same transmission data, and The frequency of the oscillator that generates the read clock is controlled according to the phase difference.

  In order to detect the phase difference, the phase comparison circuit 10-5 includes a decoder 10-51 that decodes the count value of the write address counter 10-2 and a decoder 10- that decodes the count value of the read address counter 10-4. 52 and a reset set flip-flop (RS-FF) circuit 10-53.

  In the phase comparison circuit 10-5, the count value of the write address counter 10-2 is decoded by the decoder 1-51 to generate a pulse signal indicating that the write address serving as the reference point for phase comparison has appeared, and the read address counter 10 -4 is decoded by a decoder 10-52 to generate a pulse signal indicating that a read address serving as a reference point for phase comparison has appeared.

  The reset set flip-flop (RS-FF) circuit 10-53 is set by the input of the pulse signal on the write side and is reset by the input of the pulse signal on the read side, and from the write phase reference point to the read phase reference point. A high level control signal is output during the period, and a low level control signal is output during the period from the read phase reference point to the write phase reference point.

  For example, the decoder 10-51 detects that the value of the write address of the speed conversion memory 10-3 has become “0”, and outputs a pulse that goes to a high level as a reset set flip-flop (RS-FF) circuit 10-53. The decoder 10-52 detects that the value of the read address of the speed conversion memory 10-3 has become "0", and outputs a pulse that goes high to the reset set flip-flop (RS-FF ) Input to the reset side of the circuit 10-53.

  As a result, when the read phase approaches the write phase, the high-level region becomes narrower and the low-level region becomes wider and the read phase becomes the write phase from the reset set flip-flop (RS-FF) circuit 10-53. When the control signal is separated from the control signal, a control signal is generated in which the high level region is widened and the low level region is narrowed, and the control signal is input to the control terminal of the voltage controlled crystal oscillator (VCXO) 10-6. By generating a read clock from (VCXO) 10-6, the frequency of the read clock is controlled.

  Since the transmission frequency on the high speed side is slightly higher than an integral multiple of the transmission frequency on the low speed side, the interval between the write phase and the read phase in the speed conversion memory 10-3 is gradually increased, and the voltage controlled crystal oscillator ( The high level region of the control signal of (VCXO) 10-6 becomes gradually longer. As a result, the voltage controlled crystal oscillator (VCXO) 10-6 is controlled so as to gradually increase the frequency.

  When the stuff bit is inserted next to the transmission data, the write operation of the speed conversion memory 10-3 is not performed, the write address step is delayed by one clock, and the read phase approaches the write phase by one clock. However, the high level region of the control signal of the voltage controlled crystal oscillator (VCXO) 10-6 is shortened. As a result, the frequency of the output signal of the voltage controlled crystal oscillator (VCXO) 10-6 is controlled to be lowered.

  FIG. 12 shows an operation example of frequency control based on the phase difference between the conventional write phase and read phase. 4A is a write address value, FIG. 2B is a pulse indicating a write phase (position where the write address is “0”), FIG. 3C is a control signal to the voltage controlled crystal oscillator (VCXO), and FIG. ) Indicates a pulse indicating the read phase (position where the read address is “0”), (e) indicates the value of the read address, and (f) indicates a change in the frequency of the voltage controlled crystal oscillator (VCXO).

  As shown in FIG. 12, in the conventional stuff multiplex transmission apparatus, the read frequency gradually increases around the specified frequency of the low-speed data signal. Control is performed so as to rapidly decrease, and thereafter the operation of slowly increasing the read frequency is periodically repeated, so that the average read frequency becomes equal to the transmission clock of the low-speed data signal of the transmission source. .

  When the stuff bit is inserted, the read frequency is drastically lowered, so that the reproduced low-speed data signal transmission clock has a large jitter. In order to eliminate this point, a method is conceivable in which the phase comparison period is made longer and the ratio of the frequency change amount due to the insertion of one stuff bit is reduced.

  FIG. 13 shows a configuration example in which the period of phase comparison is made longer. In the configuration example shown in the figure, the write address counter 10-2 of the octal counter in the configuration example shown in FIG. The memory 10-3 is a 12-address area speed conversion memory 13-2, and the octal counter read address counter 10-4 in the configuration example of FIG. 11 is a binary read address counter 13-3. Other configurations are the same as those shown in FIG.

  FIG. 14 shows an operation example of frequency control based on the phase difference between writing and reading when the phase comparison period is lengthened. In the figure, (a) is the value of the write address, (b) is a pulse indicating the write phase (position where the write address is “0”), (c) is a control signal to the voltage controlled crystal oscillator (VCXO), ( d) shows a pulse indicating the read phase (position where the read address is “0”), (e) shows the value of the read address, and (f) shows the change in the frequency of the voltage controlled crystal oscillator (VCXO).

  As can be seen from a comparison between FIG. 12 and FIG. 14, the frequency of the voltage controlled crystal oscillator (VCXO) at the time of inserting the stuff bit, that is, the reading frequency is gradually reduced by the length of the phase comparison period. Accordingly, the jitter of the low-speed data signal is reduced.

As a prior art document related to the present invention, the following Patent Document 1 discloses that the positive stuff threshold value and the negative stuff threshold value used in the staff execution determination are set to the optimum threshold values in accordance with the signal speed, so A transmission signal processing circuit that stores the minimum necessary data in the memory and minimizes the transmission delay time regardless of the signal speed is described.
JP-A-8-186556

  In the conventional stuff multiplex transmission apparatus, the decode value of the read address counter 13-3 and the decode value of the write address counter 13-1 in the phase comparison circuit 10-5 are set to the same value. In this state, the address point for phase comparison and the address point for reading data are the same. This is a configuration based on the principle that phase comparison is performed by comparing the write timing and read timing of the same data.

  At the center frequency of the low-speed signal, the ratio (duty) of the high-level section of the control signal of the voltage-controlled crystal oscillator (VCXO) 10-6 is 50%, and reading of data from the speed conversion memory 13-2 is speed conversion. From the time when the same data is written to the memory 13-2, the access time of all addresses of the speed conversion memory 13-2, which is one cycle of phase comparison, is delayed by about half.

  When the stuff bit is inserted, the write phase is delayed by one clock in the low-speed transmission path clock. That is, the minimum unit of the phase control amount by the stuff insertion of the phase comparison circuit 10-5 is one clock of the low-speed transmission path clock. Since the phase comparison is performed at a period equal to the access time to all the addresses in the speed conversion memory 13-2, in order to reduce the phase control amount when inserting the stuff bits, as shown in FIG. It is only necessary to increase the address space of the conversion memory 13-2, that is, the memory capacity.

  However, the transmission delay time from the data write timing to the speed conversion memory 13-2 to the data read timing is the length of the high level section of the signal output as the phase comparison result of the phase comparison circuit 10-5. For example, it is 50% of the phase comparison period at the center frequency.

  That is, the transmission delay time by the speed conversion memory 13-2 at the center frequency is equal to half of the access time to all the address areas of the speed conversion memory 13-2, and the phase control amount (variation at the time of stuff bit insertion) If the address area of the speed conversion memory 13-2 is increased in order to reduce the amount, the transmission delay time increases as a result. The present invention provides a stuff multiplex transmission apparatus that can reduce the fluctuation amount of the read frequency when inserting stuff bits without increasing the transmission delay time.

  The stuff multiplex transmission apparatus according to the present invention includes a speed conversion memory for writing and reading transmission line data, a write address counter for generating a write address of the speed conversion memory, operating with a high-speed transmission line clock, and a low speed A read address counter that operates on the side transmission line clock and generates a read address of the speed conversion memory; a first decode circuit that detects a predetermined address value of the write address counter; and a predetermined address of the read address counter A second decoding circuit that detects an address value, a flip-flop circuit that is set by an output signal of the first decoding circuit, and is reset by an output signal of the second decoding circuit; The output signal is input as a clock frequency control signal, A voltage-controlled oscillator that outputs a clock signal for the read address counter, and when the stuff bit is inserted in the transmission path data, the write address counter stops counting up and writing to the speed conversion memory is stopped In the stuff multiplex transmission apparatus provided with the write enable signal stop means, the address value of the read address counter detected by the second decode circuit is determined from the address value of the write address counter detected by the first decode circuit. The value is set as a large value.

  Further, the write enable signal stop means, when a stuff bit is inserted in the transmission line data, outputs one stuff bit for one clock of the low-speed transmission line clock to a plurality of one clock of the high-speed transmission line clock. And the divided stuff bits are distributed and generated in the section where the stuff bits are inserted into the transmission line data, and when the divided stuff bits are generated, the write address counter Counting up is stopped, and writing to the speed conversion memory is stopped.

  According to the present invention, in a configuration in which a low-speed data signal is separated on the reception side of a stuff multiplex transmission apparatus and a transmission source clock is regenerated, a read for performing phase comparison between a write phase and a read phase of a speed conversion memory By providing an offset between the position and the writing position, even if the phase of the phase comparison is lengthened, the transmission delay time does not increase, the amount of jitter is small, and a low-speed data signal with a short transmission delay time is output. be able to.

  In addition, in the configuration where the low-speed data signal is separated on the reception side of the stuff multiplex transmission apparatus and the source clock is regenerated, when the stuff bit is inserted, the stuff bit is generated by dividing it into a plurality of speed conversions. By gradually delaying the write phase of the memory for a plurality of times, a low-speed data signal with a small amount of jitter can be output.

  That is, in the conventional apparatus, when the stuff bit processing is performed, the amount of change in the write phase of the speed conversion memory 13-2 is one clock of the low-speed transmission path clock. On the other hand, in the present invention, the stuff bit is divided into a plurality of stuff bits for one clock of the high-speed side transmission line clock, the amount of phase fluctuation per time is set to one clock of the high-speed side transmission line clock, and By dividing and inserting the divided stuff bits at regular intervals, that is, by distributing the frequency control of the voltage controlled crystal oscillator (VCXO) by stuff bits multiple times, the phase control amount per time can be reduced. As a result, the amount of frequency fluctuation can be kept small, and a low-speed data signal with a small amount of jitter can be output.

  FIG. 1 shows a circuit configuration example of a stuff multiplex transmission apparatus of the present invention. The circuit device corresponding to the channel of the stuff multiplex transmission apparatus of the present invention generates an AND signal that generates a write enable signal for writing only valid transmission data excluding stuff bits from the stuff information extracted from the transmission path frame and the enable signal. Gate 1-1, write address counter 1-2 operating with high-speed transmission path clock, speed conversion memory 1-3, read address counter 1-4 operating with low-speed transmission path clock, and write address counter A phase comparison circuit 1-5 including a decoder 1-51 for decoding the value of the read address, a decoder 1-52 for decoding the value of the read address counter, a reset set flip-flop (RS-FF) circuit 1-53, and a low-speed side Voltage controlled crystal oscillator (VCXO) 1-centered on transmission line clock 6 and a driver 1-7 for generating a low-speed transmission path signal.

  The AND gate 1-1 masks the enable signal when a stuff bit is inserted, thereby generating a write enable signal for writing only valid transmission data into the speed conversion memory 1-3. Further, the write enable signal is applied to the write address counter 1-2 as a count enable signal to count up the write address counter 1-2, and an address to be written next time is determined.

  The read side of the speed conversion memory 1-3 continuously continues the stepping operation of the read address counter 1-4 in accordance with the low-speed transmission path clock generated by the voltage controlled crystal oscillator (VCXO) 1-6. The low-speed signal data is read from the speed conversion memory 1-3 in the order of the addresses, using the count value of the read address counter 1-4 as a read address.

  In the phase comparison circuit 1-5, the count value of the write address counter 1-2 is decoded by the decoder 1-51 to generate a pulse signal indicating that the write address serving as the reference point for phase comparison has appeared, and the read address counter Similarly, the count value of 1-4 is decoded by the decoder 1-52 to generate a pulse signal indicating that a read address serving as a reference point for phase comparison has appeared.

  The reset set flip-flop (RS-FF) circuit 1-53 is set by the input of the pulse signal on the write side, and is reset by the input of the pulse signal on the read side, from the write phase reference point to the read phase reference point. A high level control signal is output during the period, and a low level control signal is output during the period from the read phase reference point to the write phase reference point.

  The voltage control crystal oscillator (VCXO) 1-6 controls the oscillation frequency of the voltage control crystal oscillator (VCXO) 1-6 with a control signal output from the reset set flip-flop (RS-FF) circuit 1-53. The low-speed transmission path clock of the transmission source is reproduced and output.

  In the present invention, the decode value for phase comparison of the read address counter 1-4 is set to an offset value with respect to the decode value of the write address counter 1-2, so that the phase comparison is performed before the point where the phase comparison is performed. By reading the transmission data, even if the address space of the speed conversion memory 1-3 is enlarged (that is, even if the phase comparison period is lengthened and the phase fluctuation amount at the time of inserting the stuff bit is reduced), It becomes possible to output a low-speed data signal with a short delay time.

  For example, when the address space of the speed conversion memory 1-3 is increased by 4 addresses as compared with the conventional apparatus, the decode value of the read address decoder 1-52 is increased by half of the increased address. That is, when the decode value is “0” in the conventional apparatus, the transmission delay time at the center frequency can be made equal to that of the conventional apparatus by setting the decode value to “2”, and the speed is As the address space of the conversion memory 1-3 is increased, that is, the phase comparison period is lengthened, the phase fluctuation amount due to the stuff bit insertion can be made moderate.

  FIG. 2 shows an operation example of frequency control based on the phase difference between the write phase and the read phase according to the present invention. 4A is a write address value, FIG. 2B is a pulse indicating a write phase (position where the write address is “0”), FIG. 3C is a control signal to the voltage controlled crystal oscillator (VCXO), and FIG. ) Indicates a pulse indicating the read phase (position where the read address is “0”), (e) indicates the value of the read address, and (f) indicates a change in the frequency of the voltage controlled crystal oscillator (VCXO).

  As shown in FIG. 2, since the phase comparison is performed between the write address “0” and the read address “2”, the phase of the read address “2” is about the phase comparison period at the center frequency of the low-speed data signal. Appears at half the position. Therefore, the transmission data at the read address “0” is read two clocks earlier than the transmission data at the read address “2”, and the transmission delay amount is reduced accordingly.

  Next, FIG. 3 shows a configuration example of the embodiment of the divided stuffing insertion according to the present invention. This figure shows a circuit configuration for one channel of the stuff multiplex transmission apparatus. The stuff multiplex transmission apparatus that performs division stuff insertion includes a latch circuit 3-1 for separating multiplexed low-speed data by an enable signal extracted from a transmission path frame, and a division stuff generation circuit 3 for generating division stuff bits. -2, a write enable counter 3-3 that is enabled according to the output signal of the divided stuff generation circuit 3-2, a predetermined count value of the write enable counter 3-3, and a speed conversion memory 1-3 A write enable decoder 3-4 that generates a write enable signal, a write address counter 1-2 that operates with a high-speed transmission line clock, a speed conversion memory 1-3, and a read address that operates with a low-speed transmission line clock. Decode the values of counter 1-4 and write address counter 1-2 A phase comparison circuit 1-5 comprising a decoder 1-51, a decoder 1-52 for decoding the value of the read address counter 1-4, a reset set flip-flop (RS-FF) circuit 1-53, and low-speed transmission A voltage controlled crystal oscillator (VCXO) 1-6 having a path clock as a center frequency and a driver 1-7 for generating a low-speed transmission path signal are configured.

  The low-speed data signal is multiplexed for a plurality of channels on the high-speed transmission line, and when the synchronization of the high-speed transmission line frame is established, an enable signal indicating the position where data exists for each channel of the low-speed data signal is generated. The enable signal is input to this circuit. When the enable signal becomes high level, the transmission line data is latched by the latch circuit 3-1, thereby separating the data for one channel of the low-speed data signal.

  A write enable counter 3-3 for generating a write enable signal of the speed conversion memory 1-3 operates with a high-speed transmission line clock, and in a normal case (insertion of divided stuff bits from the divided stuff generation circuit 3-2) When there is no instruction), the operation of counting up to a count value corresponding to the number of multiplexed channels is repeated.

  When a signal indicating a split stuff bit insertion instruction is output from the split stuff generation circuit 3-2 and a disable signal is input to the write enable counter 3-3 as its inverted logic signal, the write enable counter 3-3 Stops the count-up operation, and continues the count-up operation again when the enable signal is input.

  The write enable decoder 3-4 decodes the output of the write enable counter 3-3, generates a pulse signal when the count value of the upper limit value (that is, the number of multiplexed channels) is input, and outputs the pulse signal. The write enable signal for the speed conversion memory 1-3 and the enable signal for the write address counter 1-2 are used.

  For example, in the case of a stuff multiplex transmission apparatus that multiplexes four low-speed data signals, the write enable counter 3-3 becomes a quaternary counter, and values from 0 to 3 are counted up and output cyclically. At this time, the write enable decoder 3-4 generates a pulse signal when the upper limit value 3 is input.

  The operations of the write address counter 1-2, the speed conversion memory 1-3, the read address counter 1-4, the phase comparison circuit 1-5, the voltage controlled crystal oscillator (VCXO) 1-6, and the driver have been described with reference to FIG. Operates in the same way as the operation.

  The division stuff generation circuit 3-2 operates with the high-speed transmission line clock, and writes the stuff information extracted from the transmission line frame, the enable signal, and the speed conversion memory 1-3 output from the write enable decoder 3-4. Divided stuff bits are generated based on the enable signal.

  FIG. 4 shows a state transition diagram of the operation of the divided stuff generation circuit 3-2. The divided stuff generation circuit 3-2 enters an idle state (4-1) after initialization. When the high-speed transmission path is out of synchronization or is in a state where synchronization is established, the state waits in the idle state (4-1) when there is no stuff bit insertion. In the idle state (4-1), control is performed so that the write enable signal of the speed conversion memory 1-3 is always enabled.

  When the division stuff generation circuit 3-2 recognizes the insertion of the stuff bit based on the stuff information, the division stuff generation circuit 3-2 transitions to a state (4-2) in which the insertion interval of the division stuff bit is counted. In this state, the timing at which the divided stuff bits are inserted is monitored by counting the clock with a division cycle counter (timer) (not shown) in the division stuff generation circuit 3-2, and the division cycle counter (timer) times out. Then, a transition is made to the division stuff insertion timing state (4-3).

  In the division stuffing insertion timing state (4-3), the phase of the enable signal extracted from the transmission line frame is compared with the phase of the division stuffing insertion timing. In order to determine the divided stuff insertion interval count state (4-2) again.

  In the divided stuff insertion interval count state (4-2), when the above-described operation is repeatedly executed and the division cycle counter (timer) times out, the state again shifts to the divided stuff insertion timing state (4-3). In the division stuff insertion timing state (4-3), the phase of the enable signal extracted from the transmission path frame is compared with the phase of the division stuff insertion timing. Transition to the idle state (4-1).

  The divided stuff generation circuit 3-2 inserts the first divided stuff bit when shifting from the idle state (4-1) to the divided stuff insertion interval count state (4-2), and the speed conversion memory 1-3. The write enable counter 3-3 is disabled so as to stop the count-up operation for one clock with the high-speed transmission line clock.

  Further, when shifting from the divided stuff insertion timing state (4-3) to the divided stuff insertion interval count state (4-2), divided stuff bits are inserted, and a high-speed transmission line is transmitted to the write enable counter 3-3. The disable control for one clock is performed by the clock to stop the advance, the write enable signal of the speed conversion memory 1-3 output from the write enable decoder 3-4 is disabled, and the speed conversion memory 1- 3 is stopped, and the stepping of the address counter 1-2 is also stopped.

  5 to 8 show specific operation examples of inserting the divided stuff bits. In this example, it is assumed that four low-speed data signals are multiplexed in the transmission path frame. Therefore, the write enable counter 3-3 is a quaternary counter. The address area of the speed conversion memory 1-3 is 12 addresses, and the write address counter 1-2 and the read address counter 1-4 are 12-bit counters.

  The insertion interval of the divided stuff bits is set to every 36 clocks in the low-speed transmission path clock. It is assumed that the stuff bit insertion interval on the transmission path is larger than the product of the stuff bit division number (here, equal to the multiplexing number 4) and the division stuff bit insertion interval (36 clocks here).

  5 to 8, (a) shows the timing of the stuff bit inserted in the transmission path frame, and a signal indicating the timing is input to the divided stuff generation circuit 3-2 as stuff information. Further, (b) is an enable signal for extracting a low-speed data signal of one channel from four multiplexed transmission path data.

  Further, (c) in the figure shows four-multiplexed transmission line data. The shaded portion in the figure stores data of other channels, and the data of the channel has the enable signal (b) being high. At the timing when the level is reached, data 2, data 3, and data 4 are taken into the latch circuit 3-1.

  Further, (d) in the figure shows data taken into the latch circuit 3-1 and later written into the speed conversion memory 1-3, and (e) shows the count value of the write enable counter 3-3 of the quaternary counter. (F) is an output signal of the write enable decoder 3-4, and shows a write enable signal which becomes high level when the count value of the write enable counter 3-3 becomes 3.

  Further, (g) represents transmission data written in the speed conversion memory 1-3, and the transmission data is lower than the data taken in the latch circuit 3-1 shown in (d) of the low-speed transmission path clock. The data is written into the speed conversion memory 1-3 with a delay of one clock.

  FIG. 5 shows an initial state in which stuff bits are inserted into a transmission path frame. FIG. 5 shows an example in which stuff bits are inserted after data 2 is transmitted and then data 3 is transmitted. The division stuff generation circuit 3-2 generates division stuff bits in response to the input of stuff information. As a result, the write enable counter 3-3 of the quaternary counter generates the division stuff bits as shown in (e). Thus, the count-up is stopped for one clock of the high-speed transmission path clock.

  As a result, as shown in FIG. 5F, the timing at which the count value of the write enable counter 3-3 reaches 3 is also delayed by one clock of the high-speed side transmission line clock, and as shown in FIG. A divided stuff bit S1 corresponding to one clock of the high-speed transmission path clock is inserted between 2 ′ and data 3 ′.

  At this time, since the phase of the divided stuff bit S1 does not match the phase of the enable signal of (b), it is determined that the next divided stuff bit needs to be inserted (the last divided stuff bit has not been reached). , Transition to the divided stuffing insertion interval count state (4-2).

  When the divided stuff generation circuit 3-2 that has shifted to the divided stuff insertion interval count state (4-2) transitions to the next divided stuff insertion timing state (4-3) after 36 clocks, as shown in FIG. After the data 38 ', divided stuff bits are generated, and as shown in (e), the write enable counter 3-3 of the quaternary counter delays the count-up operation by one clock of the high-speed transmission line clock, thereby As shown in (g), a divided stuff bit S2 for one clock of the high-speed transmission path clock is inserted between the data 39 ′ and the data 40 ′.

  At this time, since the phase of the divided stuff bit S2 and the phase of the enable signal in (b) do not match, it is determined that the next divided stuff bit needs to be inserted (the last divided stuff bit has not been reached). , Transition to the divided stuffing insertion interval count state (4-2).

  Similarly, when the next divided stuff insertion timing after 36 clocks is reached, as shown in FIG. 7, divided stuff bits are generated next to the data 74 ′, and as shown in FIG. The write enable counter 3-3 delays the count-up operation by one clock of the high-speed transmission line clock, and thereby, as shown in (g), between the data 75 ′ and the data 76 ′, the high-speed transmission line clock The divided stuff bits S3 for one clock are inserted.

  At this time, since the phase of the divided stuff bit S3 does not match the phase of the enable signal in (b), it is determined that the next divided stuff bit needs to be inserted (the last divided stuff bit has not been reached). , Transition to the divided stuffing insertion interval count state (4-2).

  When the next division stuff insertion timing after 36 clocks is reached as the last division stuff insertion timing, division stuff is generated next to the data 110 ′ as shown in FIG. 8, and as shown in FIG. The write enable counter 3-3 of the hex counter delays the count-up operation by one clock of the high-speed side transmission path clock, and thereby, as shown in (g), between the data 111 ′ and the data 112 ′, Divided stuff bits S4 for one clock of the transmission path clock are inserted.

  At this time, it is recognized that the phase of the divided stuff bit S3 matches the phase of the enable signal of (b) and the insertion of the last divided stuff bit is completed, and the divided stuff generation circuit 3-2 is in the idle state ( 4-1). In this way, the stuff bit is divided into a plurality of divided stuff bits by the high-speed side transmission line clock, the phase fluctuation amount per time is made the high-speed side transmission line clock, and the divided stuff bits are distributed at regular intervals. Insert.

  FIG. 9 shows a circuit configuration of the embodiment of the present invention. This embodiment shows a configuration example of a stuff multiplex transmission apparatus that multiplexes four low-speed data signals. As a specific example of such a stuff multiplex transmission apparatus, there is a stuff multiplex transmission apparatus having a low-speed data signal of 1.544 MHz and a high-speed side transmission line clock of 6.312 MHz.

  The stuff bit insertion interval of the transmission path data is 288 bits. The write enable counter 3-3 of the speed conversion memory 1-3 is a quaternary counter, and the decode value of the decoder 3-4 for generating the write enable signal is 3. The address capacity of the speed conversion memory 1-3 is 12, and the write address counter 1-2 and the read address counter 1-4 are binary counters.

  The division staff insertion interval is 36 clocks. In the phase comparison circuit 1-5, the decode value of the write address decoder is “0”, and the decode value of the read address decoder is “2”.

  If the capacity of the speed conversion memory 1-3, which was an 8-address area in the conventional apparatus, is set to a 12-address area, the amount of phase fluctuation per stuff bit becomes 2/3 (= 8 ÷ 12). The transmission delay time in the speed conversion memory 1-3 is equivalent to 4 clocks as in the prior art.

  This is because, if the ratio (duty) of the high level section of the control signal of the voltage controlled crystal oscillator (VCXO) 1-6 is 50%, in the prior art, the first four addresses are high and the latter four addresses are the same. Becomes low level, and the delay is 4 clocks.

  In contrast, according to the present invention, the first six addresses are high level and the latter six addresses are low level. However, an offset is added to the address value for phase comparison, and two addresses from the point for phase comparison. By previously reading data, it is possible to suppress the delay time to the same as the conventional one without increasing the delay time.

  However, if the amount of offset is increased, the delay time can be reduced, but the margin of jitter compensation is reduced, so an optimum value is selected as the amount of offset.

  When it is detected that stuff bits are inserted into the transmission line data, the stuff information is notified to the division stuff generation circuit 3-2, and divided stuff insertion control is divided into one high-speed side transmission line clock. Is performed four times every 36 clocks. That is, insertion control of one stuff bit is distributed and performed over a period of 144 clocks.

  During this period, the frequency of the voltage controlled crystal oscillator (VCXO) 1-6 is controlled to a gradually lower frequency every time the divided stuff bit is inserted. Since there is no stuffing during the subsequent 144 clocks, the frequency of the voltage controlled crystal oscillator (VCXO) 1-6 is gradually controlled to a higher frequency.

  As described above, according to the present invention, after the frequency of the voltage controlled crystal oscillator (VCXO) 1-6 is greatly lowered in the period of one clock of the low-speed transmission line clock as in the prior art, the frequency is gradually increased to a higher frequency. Compared to the operation, the frequency can be controlled more gently, and the jitter can be kept low.

It is a figure which shows the circuit structural example of the stuff multiplex transmission apparatus of this invention. It is a figure which shows the operation example of the frequency control based on the phase difference of the write phase by this invention, and a read phase. It is a figure which shows the structural example of embodiment of the division | segmentation staff insertion by this invention. It is a figure which shows the state transition of the operation | movement of the division | segmentation stuffing production | generation circuit of this invention. It is a figure which shows the specific operation example of the division | segmentation stuff bit insertion of this invention. It is a figure which shows the specific operation example of the division | segmentation stuff bit insertion of this invention. It is a figure which shows the specific operation example of the division | segmentation stuff bit insertion of this invention. It is a figure which shows the specific operation example of the division | segmentation stuff bit insertion of this invention. It is a figure which shows the circuit structure of the Example of this invention. It is a figure which shows the structure of the receiving side of the conventional stuff multiplex transmission apparatus. It is a figure which shows the structure of each channel corresponding | compatible circuit of the receiving side of the conventional stuff multiplex transmission apparatus. It is a figure which shows the operation example of the frequency control based on the phase difference of the conventional writing phase and reading phase. It is a figure which shows the conventional structure which lengthened the period which performs a phase comparison. It is a figure which shows the operation example of the frequency control based on the phase difference of writing and reading when the period which performs a phase comparison is lengthened.

Explanation of symbols

1-1 AND Gate 1-2 Write Address Counter 1-3 Memory for Speed Conversion 1-4 Read Address Counter 1-51, 1-52 Decoder 1-53 Reset Set Flip-Flop (RS-FF) Circuit 1-5 Phase Comparison Circuit 1-6 Voltage controlled crystal oscillator (VCXO)
1-7 Driver

Claims (2)

A speed conversion memory for writing and reading transmission path data;
A write address counter that operates with a high-speed transmission path clock and generates a write address of the speed conversion memory;
A read address counter that operates with a low-speed transmission path clock and generates a read address of the speed conversion memory;
A first decoding circuit for detecting a predetermined address value of the write address counter;
A second decoding circuit for detecting a predetermined address value of the read address counter;
A flip-flop circuit that is set by the output signal of the first decoding circuit and is reset by the output signal of the second decoding circuit;
A voltage-controlled oscillator that inputs an output signal of the flip-flop circuit as a control signal of a clock frequency and outputs a clock signal of the read address counter;
In a stuff multiplex transmission device having a write enable signal stop means for stopping counting up of the write address counter and stopping writing to the speed conversion memory when a stuff bit is inserted in transmission path data,
Stuff multiplex transmission characterized in that the address value of the read address counter detected by the second decode circuit is set to be larger than the address value of the write address counter detected by the first decode circuit apparatus.   The write enable signal stop means divides one stuff bit for one clock of the low-speed side transmission line clock into a plurality of clocks for one clock of the high-speed side transmission line clock when the stuff bit is inserted into the transmission line data. Dividing into stuff bits, and generating the divided stuff bits in a section where stuff bits are inserted into the transmission line data, and when the divided stuff bits are generated, the write address counter is incremented The stuff multiplex transmission apparatus according to claim 1, wherein the stuff multiplex transmission apparatus is stopped and writing into the speed conversion memory is stopped.

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