JP4419670B2 - Digital signal processing circuit and digital signal processing method - Google Patents

Description

  The present invention relates to a digital signal processing circuit and a digital signal processing method, and more particularly, to a digital signal in a digital communication system that receives a digital signal in which an auxiliary signal is synchronously multiplexed with data in a predetermined cycle by a stuff operation and separates the auxiliary signal. The present invention relates to a processing circuit and a digital signal processing method.

  FIG. 3 is a block diagram showing an example of a conventional digital signal processing circuit. This conventional digital signal processing circuit includes a separation circuit 1, a storage circuit 2, a phase comparator 11, a voltage controlled oscillator 12, and a clock frequency dividing circuit 13, and performs a destuffing operation. Here, when an auxiliary signal is transmitted by a generally known stuffing technique, the auxiliary signal allocation capacity and the auxiliary signal capacity in the transmission signal are usually different. Is synchronously multiplexed. It is known that a digital signal processing circuit on the receiving side performs a destuffing operation when auxiliary signal data is separated from a received signal (see, for example, Patent Document 1).

  The operation of this conventional digital signal processing circuit will be described. The transmission signal transmitted from the transmission side is composed of data and a clock in which the auxiliary signal is synchronously multiplexed as described above. It is received and input to the separation circuit 1 as reception data and a reception clock. The separation circuit 1 receives the reception data and the reception clock multiplexed on the transmission side, separates the auxiliary signal in the reception data, generates a clock having the same period as the auxiliary signal, and generates the separated auxiliary signal and the generated clock. While being input to the storage circuit 2, the separated reception clock is input to the phase comparator 11 as a phase comparison clock used by the phase comparator 11.

  The phase comparator 11 detects the phase difference between the received clock from the separating circuit 1 and a clock described later from the clock frequency dividing circuit 13 and outputs a phase difference signal corresponding to the phase difference to the voltage controlled oscillator 12 as a control voltage. To do. The voltage controlled oscillator 12 oscillates and outputs a clock having a frequency corresponding to the phase difference signal from the phase comparator 11 and outputs the clock to the memory circuit 2 and the clock divider circuit 13. The clock divider circuit 13 divides the frequency signal supplied from the voltage controlled oscillator 12, and the phase comparator 11 generates a clock for phase comparison with the received clock from the separation circuit 1. To supply.

  The storage circuit 2 receives the auxiliary signal and the clock from the separation circuit 1 and writes the auxiliary signal using the input clock as a write clock. Further, the memory circuit 2 is supplied with a frequency signal output from the voltage controlled oscillator 12 and phase-synchronized with the reception clock as a readout clock, and reads out the written auxiliary signal. As a result, the received auxiliary signal is read from the memory circuit 2 in synchronization with the read clock, and the clock of the auxiliary signal is also output.

  Here, in the conventional digital signal processing circuit, a transmission signal in which the auxiliary signal is synchronously multiplexed is received and supplied on the transmission side. The transmission signal is synchronized with the synchronization staff depending on the frequency relationship between the transmission signal frequency and the auxiliary signal. There are time slots in which the auxiliary signal is multiplexed in bits and time slots in which the auxiliary signal is not multiplexed.

  When the auxiliary signal is not multiplexed on the stuff bit, data cannot be separated because the useless bit is inserted in the stuff bit, and the data of the previous time slot is continuously output. Accordingly, there is no auxiliary signal clock. Therefore, when the separation circuit 1 separates the auxiliary signal from the received data, the clock corresponding to the data becomes the missing clock. Therefore, in the above conventional digital signal processing circuit, the voltage control oscillator 12 is used to smooth the read clock and output it to the apparatus interface and the external device.

JP 2003-134076 A

  However, the conventional digital signal processing circuit has several problems. The first problem is that when the voltage-controlled oscillator 12 of the digital signal processing circuit fails, the data output and clock output of the auxiliary signal are stopped.

  The second problem is that the circuit configuration is complicated and the price is high. The cause of this problem is that the voltage controlled oscillator 12 is used.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a digital signal processing circuit that solves the above-described problems by performing clock smoothing in a configuration that does not use a voltage-controlled oscillator.

  The digital signal processing circuit according to the present invention receives as input a digital signal composed of data multiplexed with an auxiliary signal having a predetermined period and a first clock synchronized with the data, and separates the auxiliary signal from the data. Separating means for generating an auxiliary signal clock having the same predetermined period as that of the first embodiment, storage means for writing the auxiliary signal separated by the separating means based on the auxiliary signal clock generated by the separating means, and a first clock in the digital signal Frequency dividing means for generating a second clock having a predetermined period by dividing the frequency, reading the auxiliary signal from the storage means using the second clock as a read clock, and outputting the second clock as an auxiliary signal clock through the storage means It is characterized by having.

  The digital signal processing method of the present invention receives as input a digital signal composed of data in which an auxiliary signal having a predetermined period is multiplexed and a first clock synchronized with the data, and separates the auxiliary signal from the data. A first step of generating an auxiliary signal clock having the same predetermined period as the auxiliary signal, and a second step of writing the auxiliary signal separated in the first step into the storage means based on the auxiliary signal clock generated in the first step A third step of dividing the first clock in the digital signal to generate a second clock having a predetermined period, and reading out the auxiliary signal from the storage means using the second clock as a read clock, And a fourth step of outputting the second clock as an auxiliary signal clock through the storage means.

  According to the digital signal processing circuit and the digital signal processing method of the present invention, the first clock having no missing teeth in the supplied digital signal is divided to generate a second clock having a predetermined period, and the second clock is generated. Since the auxiliary signal is read from the storage means using the clock as the read clock, the second clock used as the read clock can be generated as the smoothing clock.

  Here, the frequency of the first clock is a natural number times the clock frequency of the auxiliary signal. In addition, the data in which the auxiliary signal is multiplexed is synchronously multiplexed with the data by the stuff operation, the time slot in which the auxiliary signal is multiplexed in the stuffing bit for synchronization, and the time that is not multiplexed. It has a slot. In the present invention, the transmission signal clock uses a frequency that is a natural multiple of the auxiliary signal clock, and the auxiliary signal data in which the presence / absence of data occurs in the time slot of the stuff bit is written in the storage circuit, and the smoothing generated from the reception transmission clock The auxiliary signal data can be read from the memory circuit using the clock.

  According to the present invention, a first clock having no missing teeth in a supplied digital signal is divided to generate a second clock having a predetermined period, and the second clock is read from the storage means as a read clock. By reading the auxiliary signal, the second clock used as the read clock can be generated as the smoothed clock, and thus has the following features.

  The first effect is that since a smoothing clock can be generated without using a voltage-controlled oscillator that has been used in the past, it is possible to output stable auxiliary signal data and auxiliary signal clock that do not fluctuate in phase. Since it is possible to prevent the auxiliary signal data and the auxiliary signal clock (second clock) from being stopped when the voltage controlled oscillator fails, the reliability can be improved.

  The second effect is that the voltage controlled oscillator is not used, so that the circuit configuration is simplified and an inexpensive circuit can be provided.

  Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of a digital signal processing circuit according to the present invention. As shown in the figure, the present embodiment includes a separation circuit 1, a storage circuit 2, and a clock frequency dividing circuit 3. The clock frequency dividing circuit 3 is a normal frequency dividing circuit having the same configuration as the clock frequency dividing circuit 13 shown in FIG.

  The separation circuit 1 receives the reception data and the reception clock as inputs, separates the auxiliary signal from the reception data, generates an auxiliary signal clock having the same period as the auxiliary signal (for example, the reciprocal of 64 kHz), and stores them in the memory circuit 2 Supply. The memory circuit 2 writes the auxiliary signal from the separation circuit 1 with the auxiliary signal clock from the separation circuit 1.

  On the other hand, the clock frequency dividing circuit 3 divides the reception clock to generate a smoothing clock for the auxiliary signal, supplies it to the memory circuit 2 as a read clock, and reads the auxiliary signal from the memory circuit 2. The memory circuit 2 outputs the read auxiliary signal and the smoothed clock.

  Therefore, in this embodiment, the separated auxiliary signal is written in the storage circuit 2 with the toothless clock and the auxiliary signal is read out from the storage circuit 2 with the smoothing clock, so that stable auxiliary signal data and auxiliary signal clock without fluctuation are output. can do.

  Next, the operation of the digital signal processing circuit of this embodiment will be further described with reference to the timing chart of FIG. 2A is a reception clock of a transmission signal that is an input of the separation circuit 1 that separates the auxiliary signal from the transmission signal, FIG. 2B is a reception data of the transmission signal that is an input of the separation circuit 1, and FIG. 2E and FIG. 2E show auxiliary signal data separated by the separation circuit 1, and FIG. 2D and FIG. 2F show auxiliary signal clocks having the same period as the auxiliary signal generated by the separation circuit 1.

  Here, in the case where the auxiliary signal is transmitted by a generally known stuffing technique, a case where the frequency of the transmission signal is 12.8 MHz and the frequency of the auxiliary signal is 64 kHz is considered. Usually, since the auxiliary signal allocation capacity and the auxiliary signal capacity in the transmission signal are different, the auxiliary signal is synchronously multiplexed on the transmission signal by the stuff operation on the transmission side. On the receiving side, the destuffing operation is performed when the auxiliary signal data is separated from the received signal, but the time slot in which the auxiliary signal data is multiplexed on the synchronization stuff bits depending on the frequency relationship between the transmission signal and the auxiliary signal. And there are timeslots that are not multiplexed.

  When the auxiliary signal data is multiplexed on the synchronization stuff bit, the auxiliary signal data is separated from the stuff bit time slot as shown in FIG. 2C, and the auxiliary signal clock is shown in FIG. As shown, a clock without missing teeth is generated. However, when the auxiliary signal data is not multiplexed on the stuff bits (when the auxiliary signal is not multiplexed on the stuff bits indicated by cross-hatching in FIG. 2B), useless bits are inserted in the stuff bits. Therefore, the auxiliary signal data cannot be separated, and the auxiliary signal data of the previous time slot is continuously output as shown in FIG. Along with this, there is no auxiliary signal clock. Therefore, as shown in FIG. 2F, the separated auxiliary clock is in a state where the time slot of the stuff bit is missing.

  However, the present embodiment is similar to the conventional point in that the auxiliary signal data and the auxiliary signal clock which are the outputs of the separation circuit 1 are supplied to the storage circuit 2 and the auxiliary signal data is written by the auxiliary signal clock. In this embodiment, the clock dividing circuit 3 directly divides the 12.8 MHz reception clock by 200 to generate a 64 kHz clock having the same period as the auxiliary signal. Since there is no missing teeth, a 64 kHz smooth clock without missing teeth can be generated from the clock frequency dividing circuit 3 even when the auxiliary signal is not multiplexed on the stuff bits.

  In the present embodiment, auxiliary signal data is read from the memory circuit 2 using this smoothed clock, and the smoothed clock is output as an auxiliary signal clock through the memory circuit 2. As a result, the auxiliary signal data and the auxiliary signal clock output are in a stable state without missing teeth.

  Thus, according to this embodiment, it is possible to output the auxiliary signal data and the auxiliary signal clock that have been smoothed with a simple circuit configuration that does not use the voltage controlled oscillator. Further, since the voltage controlled oscillator is not used, the reliability of the circuit can be improved.

  In the above embodiment, the clock frequency of the transmission signal is 12.8 MHz, and the clock frequency of the auxiliary signal is 64 kHz that is 1/200 times that, but the present invention is not limited to this. If the clock frequency of the transmission signal is a natural number multiple of the clock frequency of the auxiliary signal, the present invention can be applied.

  In the above-described embodiment, the hardware configuration has been described. However, the present invention includes a computer program and a processing method for realizing each unit of the above-described embodiment by a computer.

  A field of application of the present invention is a digital signal processing circuit of a digital transmission apparatus.

It is a block diagram of one embodiment of the present invention. 2 is a timing chart for explaining the operation of FIG. 1. It is a block diagram of an example of the conventional digital signal processing circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Separation circuit 2 Memory circuit 3, 13 Clock division circuit 11 Phase comparator 12 Voltage controlled oscillator

Claims (6)

A digital signal composed of data multiplexed with an auxiliary signal of a predetermined period and a first clock synchronized with the data is received as an input, the auxiliary signal is separated from the data, and the same predetermined period as the auxiliary signal Separating means for generating an auxiliary signal clock of
Storage means for writing the auxiliary signal separated by the separating means based on the auxiliary signal clock generated by the separating means;
The first clock in the digital signal is divided to generate a second clock of the predetermined period, and the auxiliary signal is read from the storage means using the second clock as a read clock, and the second clock And a frequency dividing means for outputting the above clock as an auxiliary signal clock through the storage means.   2. The digital signal processing circuit according to claim 1, wherein the frequency of the first clock is a natural number multiple of the clock frequency of the auxiliary signal.   In the data multiplexed with the auxiliary signal, the auxiliary signal is synchronously multiplexed with the data by the stuff operation, and the time slot in which the auxiliary signal is multiplexed in the stuff bit for synchronization and the time slot in which the auxiliary signal is not multiplexed The digital signal processing circuit according to claim 1, wherein: A digital signal composed of data multiplexed with an auxiliary signal of a predetermined period and a first clock synchronized with the data is received as an input, the auxiliary signal is separated from the data, and the same predetermined period as the auxiliary signal A first step of generating an auxiliary signal clock of
A second step of writing the auxiliary signal separated in the first step into a storage means based on the auxiliary signal clock generated in the first step;
A third step of dividing the first clock in the digital signal to generate a second clock of the predetermined period;
And a fourth step of reading the auxiliary signal from the storage means using the second clock as a read clock and outputting the second clock as an auxiliary signal clock through the storage means. Processing method.   5. The digital signal processing method according to claim 4, wherein the frequency of the first clock is a natural number multiple of the clock frequency of the auxiliary signal. In the data multiplexed with the auxiliary signal, the auxiliary signal is synchronously multiplexed with the data by the stuff operation, and the time slot in which the auxiliary signal is multiplexed in the stuffing bit for synchronization and the time slot in which the auxiliary signal is not multiplexed The digital signal processing method according to claim 4 or 5, wherein:

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