JP4890950B2 - Method for calculating pattern loop shape on printed circuit board, apparatus therefor, computer-readable recording medium and program - Google Patents

Description

  The present invention relates to a calculation method of a loop shape of a pattern on a printed circuit board, an apparatus thereof, a computer-readable recording medium, and a program, and more specifically, a pattern formed by a power supply net or a GND (ground) net on the printed circuit board. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for calculating a loop shape of a pattern on a printed circuit board suitable for use in evaluating the loop shape of the apparatus, its apparatus, a computer-readable recording medium, and a program. Electromagnetic compatibility) A method for calculating a loop shape of a pattern on a printed circuit board that can be used as a countermeasure, an apparatus thereof, a computer-readable recording medium, and a program Is shall.

  Conventionally, a pattern on a printed circuit board, that is, a pattern formed by a power supply net or a GND net may have a large loop shape on the outer periphery of the printed circuit board, and this may become an antenna and cause problems due to noise interference. It was.

  For example, in the example shown in FIG. 1, the pattern formed by the GND net has a loop shape on the outer periphery of the printed circuit board. For this reason, in such a printed circuit board, the pattern formed by the GND net functions as an antenna and may cause noise interference.

  Therefore, in general, when designing a printed circuit board, a pattern on the printed circuit board, that is, a loop shape of a pattern formed by a power supply net or a GND net on the printed circuit board has been inspected.

Here, in the conventional printed circuit board design, the inspection of the pattern on the printed circuit board, that is, the loop shape of the pattern formed by the power supply net or the GND net on the printed circuit board, is performed on the power supply net or the GND net drawn on the paper surface. It has been performed exclusively by a method in which an operator visually observes a power supply net or a GND net displayed on the screen.

  For this reason, inspecting the loop shape of patterns formed by complicated power supply nets and GND nets on multilayer boards and the like has the problem that the work is very troublesome and troublesome, and errors are likely to occur. there were.

  Further, as described above, the inspection of the loop shape of the pattern formed by the power supply net or the GND net on the printed circuit board is performed by relying on the operator's visual inspection of the paper surface or the screen, and the following problems are pointed out. It was.

  In other words, even if the loop shape is discovered by the problem that the work time is extended by performing multiple inspections for the discovery of the loop shape, the work time is long, and therefore the work efficiency becomes inefficient. There is a problem that it is difficult to perform uniform correction because there are various pattern correction methods.

  Therefore, as a result, there is a possibility that the loop shape may be overlooked in the inspection of the operator, and this overlook of the loop shape causes an EMC problem. There was a problem that reworking the actual machine frequently occurred.

  In other words, in the past, the EMC problem can be determined only after actually prototyping the substrate and actually measuring it. Therefore, when the EMC problem occurs, it is necessary to repeat the design many times until the problem is solved. Expenses such as development costs and manufacturing costs were increasing.

The prior art that the applicant of the present application knows at the time of filing a patent is as described above and is not an invention related to a known literature, so there is no prior art information to be described.

  The present invention has been made in view of the various problems of the prior art as described above, and its purpose is to generate various expenses such as development costs and manufacturing costs associated with the production of printed circuit boards. It is intended to provide a method for calculating the loop shape of a pattern on a printed circuit board that suppresses the occurrence of EMC problems, its apparatus, a computer-readable recording medium, and a program.

  In order to achieve the above object, the present invention makes it possible to detect a pattern shape by performing calculation processing using design data of a printed circuit board, thereby generating various expenses such as development costs and manufacturing costs associated with the production of the printed circuit board. It is possible to suppress the occurrence of EMC problems and suppress the occurrence of EMC problems.

  Therefore, according to the present invention, it becomes possible to extract and evaluate the loop shape of the power supply net and the GND net, and the noise caused by the loop shape antenna of the power supply net and the GND net, which has been a problem until now, can be obtained. Occurrence and malfunction of equipment can be suppressed.

  In addition, according to the present invention, it is possible to save labor for pattern inspection that has been performed visually after pattern design, and it is also possible to display a guidance for a correction method according to the detection result. Shortening can also be achieved, and therefore the development risk of design due to EMC problems can be reduced.

That is, the invention described in claim 1 of the present invention includes a net selection unit, a net determination unit, a target layer determination unit, a loop extraction unit, a loop selection unit, a calculation unit, and a first display unit. When, by the computing device of a loop shape of the pattern in the printed circuit board and a second display means, the pattern in the printed circuit board for evaluating the loop shape of the pattern power net or GND nets in printed circuit board to form a loop-shaped In the calculation method, the above-mentioned net selection means is used for layout design data including part information, which is information on various parts, and wiring information indicating wiring states between various parts, for the power supply net or the GND net. a first processing of selecting a net serving target net to be subjected to detection of loop-inside, the net When the confirmation means gives an instruction to artificially combine the target net selected in the first process in order to process different power supply nets or GND nets connected by one-point ground as one net Determines a loop shape that combines power supply nets or GND nets connected by one point ground as a pseudo net, and if a single power source or GND net is not connected by one point ground, and if a different power net or GND net connected by one point ground is one In the case where an instruction for pseudo synthesis is not performed for processing as a net, the second process for determining the power source net or the GND net as the target net as it is and the target layer determining unit Of the layout design data, the wiring pattern for the printed circuit board area in each layer Based on the condition value of the excluded layer set in advance from the occupancy rate of the target, a third process for determining a target layer as a layer for detecting a loop, and the third process is determined by the loop extraction unit. A fourth process for extracting a loop part for each target net determined in the second process on the target layer, and an area of a figure constituting the target net of each loop and the target net by the loop selection unit the size of the shapes that constitute the fifth to select the loop to be detected from the area, and based on the value calculated by using the size of the loop, the loop portion extracted by the fourth process of the loop and processing, by the calculation means, and a sixth process for calculating the compliance ratio between the fifth loop and predetermined conditions selected by the process of, by the first display means, said sixth A seventh process for displaying a calculation result by the process, and an eighth process for displaying guidance for EMC countermeasures according to the calculation result by the sixth process by the second display means; It is what I did.

Further, the invention according to claim 2 of the present invention is a net selection means, a net determination means, a target layer determination means, a loop extraction means, a loop determination means, a loop selection means, a calculation means, In a printed circuit board for evaluating a loop shape of a pattern formed by a power supply net or a GND net in a printed circuit board by a calculation device of a pattern loop shape in the printed circuit board having a first display unit and a second display unit In the pattern loop shape calculation method, the net selection means supplies power to the layout design data including part information, which is information on various parts, and wiring information indicating the wiring state between the various parts. A first net for selecting a target net that is a target for detecting a loop in the net or the GND net An instruction to artificially synthesize the target net selected in the first process by the process and the net determining means to process different power supply nets or GND nets connected by one point ground as one net. If it is performed, a loop shape that combines power nets or GND nets connected by one-point grounding is determined as a pseudo net, and if not connected by one-point grounding or different power nets connected by one-point grounding or A second process for determining a power supply net or a GND net as a target net as it is and a target layer when there is no instruction to synthesize the pseudo net to process the GND net as a single net; The printed circuit board surface in each layer of the layout design data by the determining means A third process for determining a target layer as a layer for detecting a loop based on a condition value of an exclusion layer set in advance based on a wiring pattern occupancy ratio for the line pattern, and the third process by the loop extraction unit In the case where the target layer does not exist above and below the target layer, the loop portion is extracted from the target net determined in the second process on the target layer, and the target layer has two layers. In the case where there is an overlap, a fourth process for creating a figure by superimposing and synthesizing the target nets determined in the second process on each target layer, and extracting a loop portion from the superposed and synthesized figure, When the shape of the loop part extracted in the fourth process by the loop determining means is an open shape, it is determined as an open loop, and the shape of the loop part extracted in the fourth process is Close If it is a closed loop, it is determined as a closed loop, and among the loop locations determined as the closed loop, if there is a via connection between layers, it is determined as a closed loop, and the loop determined as the closed loop If there is no via connection between the layers, the area of the figure constituting the target net of each loop and the target net are configured by the fifth processing to be determined as not being a closed loop and the loop selection means. Detected based on the determination made in the fifth process from the loop location extracted by the fourth process, based on the figure size and the value calculated using the loop area and the loop size A sixth process for selecting a loop to be processed, and the loop selected by the sixth process by the calculating means and a predetermined loop When calculating the matching ratio with the conditions, the matching ratio for the predetermined condition is changed between the loop determined to be an open loop in the fifth process and the loop determined to be a closed loop in the fifth process. A seventh process for calculating the ratio, an eighth process for displaying the result of the calculation by the seventh process by the first display means, and a process for the seventh process by the second display means. And a ninth process for displaying guidance for EMC countermeasures according to the result of the calculation .

The invention of claim 3 of the present invention, in the calculation device of the loop shape of the pattern in the printed circuit board for evaluating the loop shape of the pattern power net or GND nets in printed circuit board is formed, various components of the For the layout design data configured to include component information, which is information related to wiring, and wiring information indicating the wiring state between various components, a target net that is a target for detecting a loop in a power supply net or a GND net An instruction to artificially synthesize the net selection means for selecting the network and the target net selected by the net selection means to process different power supply nets or GND nets connected by one point ground as one net is issued. In the case of a power supply network or GND network The loop shape that combines them is determined as a pseudo net, and the pseudo-synthesizing instruction is used to process different power supply nets or GND nets that are not connected by one point ground and one point ground as one net. In the case where the power supply net or the GND net is left as it is, the net determination means for determining the target net as it is and the layout design data based on the occupation ratio of the wiring pattern with respect to the printed circuit board area in each layer are set in advance. Based on the condition value of the excluded layer determined, the target layer determining means for determining the target layer as a layer for detecting the loop, and the net determining means on the target layer determined by the target layer determining means are determined. a loop extraction means for extracting a loop portion for each target nets, target net of each loop The size of the shapes that constitute the area and target net shapes constituting, on the basis of a value calculated by using the size of the area and the loop of the loop, and the target detected from the loop portion extracted by the loop extraction means Loop selection means for selecting a loop to be obtained, calculation means for calculating a matching ratio between the loop selected by the loop selection means and a predetermined condition, first display means for displaying a result of the calculation, and the calculation And a second display means for displaying guidance for EMC countermeasures according to the result .

According to a fourth aspect of the present invention, there is provided an apparatus for calculating a loop shape of a pattern on a printed circuit board for evaluating a loop shape of a pattern formed by a power supply net or a GND net on the printed circuit board. For the layout design data configured to include component information, which is information related to wiring, and wiring information indicating the wiring state between various components, a target net that is a target for detecting a loop in a power supply net or a GND net An instruction to artificially synthesize the net selection means for selecting the network and the target net selected by the net selection means to process different power supply nets or GND nets connected by one point ground as one net is issued. In the case of a power supply network or GND network The loop shape that combines them is determined as a pseudo net, and the pseudo-synthesizing instruction is used to process different power supply nets or GND nets that are not connected by one point ground and one point ground as one net. In the case where the power supply net or the GND net is left as it is, the net determination means for determining the target net as it is and the layout design data based on the occupation ratio of the wiring pattern with respect to the printed circuit board area in each layer are set in advance. The target layer determining means for determining the target layer that is a layer for detecting a loop based on the condition value of the excluded layer, and the target layer determined by the target layer determining means are the target layers above and below the target layer. If it does not exist, the loop number is determined from the target net determined by the above net determining means on the target layer. If two or more target layers overlap, a figure is created by overlaying and synthesizing the target nets determined by the net determining means on each target layer, and a loop location is created from the superimposed and synthesized figure. When the shape of the loop part extracted by the loop extraction means is an open shape, it is determined as an open loop, and the shape of the loop part extracted by the loop extraction means is In the case of a closed shape, it is determined as a closed loop, and among the loop locations determined as the closed loop, if there is a via connection between the layers, it is determined as a closed loop and also determined as the closed loop. If there is no via connection between layers in the loop location, the loop determination means to determine that the loop is not closed and the target net of each loop The loop determining means from the loop location extracted by the loop extracting means, based on the values calculated using the area of the figure and the size of the figure constituting the target net, and the area of the loop and the size of the loop When the loop selection means for selecting a loop to be detected based on the determination made in step (b) and the matching ratio between the loop selected by the loop selection means and a predetermined condition are calculated by the loop determination means. For the loop determined to be a loop and the loop determined to be a closed loop by the loop determination means, a calculation means for calculating a matching ratio by changing the matching ratio for the predetermined condition, and a calculation result by the calculation means are displayed. a first display means, second display hands for displaying guidance for EMC measures according to the result of calculation by the calculating means It is obtained so as to have the door.

According to a fifth aspect of the present invention, a computer executes calculation of a loop shape of a pattern on a printed circuit board for evaluating a loop shape of a pattern formed by a power supply net or a GND net on the printed circuit board. In a computer-readable recording medium in which a program for recording is recorded , a power supply network is provided for layout design data including part information that is information on various parts and wiring information that indicates wiring states between the various parts. Alternatively, a first process for selecting a target net that is a net for which a loop is to be detected in the GND net, and a different power supply net or GND connected by one point ground for the target net selected in the first process. In order to process a net as a single net, When the instruction to do so is made, the loop shape obtained by combining the power supply nets or GND nets connected by one-point grounding is determined as a pseudo net, and when not connected by one-point grounding or different by one-point grounding A second process for determining a power supply net or a GND net as a target net in a state where the power supply net or the GND net is not instructed to be processed in a pseudo manner in order to process the power supply net or the GND net as a single net; Of the layout design data, a third process for determining a target layer that is a layer for detecting a loop based on a condition value of an exclusion layer set in advance based on an occupation ratio of a wiring pattern with respect to a printed circuit board area in each layer; third on the target layer that is determined in the process, the second the determined target each net in the process A fourth process of extracting the loop location, and size of graphics constituting the area and target net shapes constituting the target net for each loop, the value calculated by using the size of the area and the loop of the loop based, said a fifth process of selecting a target loop that detects the fourth loop portion extracted by the processing by the calculation means, the loop and the predetermined conditions selected by the fifth processing A sixth process for calculating the matching ratio, a seventh process for displaying the result of the calculation by the sixth process, and a guidance for EMC countermeasures according to the result of the calculation by the sixth process The eighth process is a computer-readable recording medium on which a program for causing a computer to execute is recorded.

According to a sixth aspect of the present invention, there is provided a method for calculating a loop shape of a pattern on a printed circuit board for evaluating a loop shape of a pattern formed by a power supply net or a GND net on the printed circuit board. For the layout design data configured to include component information, which is information related to wiring, and wiring information indicating the wiring state between various components, a target net that is a target for detecting a loop in a power supply net or a GND net And an instruction to artificially combine the target net selected in the first process in order to process different power supply nets or GND nets connected by one point ground as one net. If done, connect power nets or GND nets connected by a single point ground. The formed loop shape is determined as a pseudo net, and an instruction to synthesize pseudo is given in order to process different power nets or GND nets that are not connected by one point ground and one point ground as one net. If not, the power supply net or the GND net is determined in advance from the second processing for determining the target net as it is and the occupation ratio of the wiring pattern to the printed circuit board area in each layer in the layout design data. Based on the condition value of the excluded layer, the third process for determining the target layer as a layer for detecting the loop, and the target layer determined in the third process are present above and below the target layer. If not, the loop part is extracted from the target net determined in the second process on the target layer, and the target layer In the case where two or more layers are overlapped, a fourth process for creating a figure by superposing and synthesizing the target nets determined in the second process on each target layer and extracting a loop portion from the superposed figure When the shape of the loop portion extracted in the fourth process is an open shape, it is determined as an open loop, and the shape of the loop portion extracted in the fourth process is a closed shape. In some cases, it is determined as a closed loop, among the loop locations determined as the closed loop, if there is a via connection between the layers, it is determined as a closed loop, and among the loop locations determined as the closed loop, If there is no via connection between layers, the fifth process is determined to be not a closed loop, and the area of the figure and the target net constituting the target net of each loop are configured. Based on the determination made in the fifth process from the loop location extracted by the fourth process, based on the value calculated using the size of the figure to be formed, the area of the loop, and the size of the loop When calculating the matching ratio between the sixth process for selecting the loop to be detected and the loop selected by the sixth process and a predetermined condition, the loop is determined to be an open loop in the fifth process. The seventh processing for calculating the matching ratio by changing the matching rate for the predetermined condition and the result of the calculation by the seventh processing are displayed for the loop that has been determined to be a closed loop by the fifth processing. competent for the processing of the eighth, and ninth processing for displaying a guidance for EMC measures according to the result of calculation by the process of the seventh, recording a program to be executed by a computer to It is obtained by the chromatography data readable recording medium.

The invention according to claim 7 of the present invention is a program used for a calculation device for a pattern loop shape on a printed circuit board for evaluating a pattern loop shape formed by a power supply net or a GND net on the printed circuit board. The computer detects loops in the power supply net or GND net for layout design data that includes part information that is information about various parts and wiring information that indicates the wiring status between various parts. In order to process a net selection means for selecting a target net as a target net to be processed, and different power supply nets or GND nets connected by one-point ground as one net for the target net selected by the net selection means. If an instruction to combine is given, In order to determine a loop shape obtained by combining power supply nets or GND nets as a pseudo net, and to process different power supply nets or GND nets connected by one point ground as a single net when they are not connected by one point ground. In the case where there is no instruction to artificially synthesize, the net determining means for determining the power net or the GND net as the target net as it is, the wiring pattern for the printed circuit board area in each layer of the layout design data Based on the condition value of the excluded layer set in advance from the occupation ratio of the target layer, target layer determining means for determining a target layer as a layer for detecting a loop, and the net on the target layer determined by the target layer determining means loop extraction for extracting a loop location each target net which is determined by the determining means Stage, the size of the shapes that constitute the area and target net shapes constituting the target net for each loop, based on the value calculated by using the size of the area and the loop of the loop, is extracted by the loop extraction means A loop selection means for selecting a loop to be detected from the loop location, a calculation means for calculating a matching ratio between the loop selected by the loop selection means and a predetermined condition, and a result of the calculation by the calculation means is displayed. And a program for functioning as second display means for displaying guidance for EMC countermeasures according to the result of the calculation by the calculation means .

The invention according to claim 8 of the present invention is a program used for a calculation device for a pattern loop shape on a printed circuit board for evaluating a pattern loop shape formed by a power supply net or a GND net on the printed circuit board. The computer detects loops in the power supply net or GND net for layout design data that includes part information that is information about various parts and wiring information that indicates the wiring status between various parts. In order to process different power supply nets or GND nets connected by one-point ground as one net for the net selection means for selecting the target net to be the target net and the target net selected by the net selection means. If an instruction to synthesize is given, it will be grounded at one point. A loop shape obtained by synthesizing power supply nets or GND nets is determined as a pseudo net, and different power supply nets or GND nets connected by one-point grounding or not connected by one-point grounding are processed as one net. Therefore, in the case where an instruction for pseudo synthesis is not given, net determining means for determining the power net or the GND net as the target net as it is, wiring among the layout design data for the printed circuit board area in each layer Based on the condition value of the excluded layer set in advance from the pattern occupancy rate, target layer determining means for determining the target layer as a layer for detecting a loop, and the target layer determined by the target layer determining means is the target layer If the target layer does not exist above and below the target layer, the net determining means on the target layer Loop portions are extracted from the target nets created, and if there are two or more target layers, a figure is created by overlaying and synthesizing the target nets determined by the net determining means on each target layer, Loop extraction means for extracting a loop part from the superimposed figure, and when the shape of the loop part extracted by the loop extraction means is an open shape, it is determined as an open loop, and is extracted by the loop extraction means. When the shape of the loop portion is a closed shape, it is determined as a closed loop, and among the loop locations determined as the closed loop, if there is a connection by a via between layers, it is determined as a closed loop, Of the loops determined as closed loops, if there is no via connection between the layers, the loop decision factor is determined as not being a closed loop. The loop extraction means based on the values calculated using the area of the figure constituting the target net of each loop, the size of the figure constituting the target net, and the area of the loop and the size of the loop. A loop selection means for selecting a loop to be detected based on a determination made in the loop determination means from the loop location, and calculating a matching ratio between the loop selected by the loop selection means and a predetermined condition The calculation means for calculating the adaptation ratio by changing the adaptation ratio with respect to the predetermined condition between the loop determined to be an open loop by the loop determination means and the loop determined to be a closed loop by the loop determination means, by the calculation means First display means for displaying the calculation result, and guidance for EMC countermeasures according to the calculation result by the calculation means It is obtained by the program for functioning as a second display means for displaying.

  Since the present invention is configured as described above, it is possible to suppress the occurrence of various expenses such as development costs and manufacturing costs associated with the production of printed circuit boards, and to suppress the occurrence of EMC problems. There is an excellent effect of being able to.

  Hereinafter, an example of an embodiment of a method for calculating a loop shape of a pattern on a printed board according to the present invention, an apparatus thereof, a computer-readable recording medium, and a program will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram showing a system configuration of an example of an embodiment of a calculation device for a pattern loop shape on a printed circuit board according to the present invention.

  That is, the calculation device for the loop shape of the pattern on the printed circuit board according to the present invention (hereinafter simply referred to as “calculation device” as appropriate) controls the overall operation using the central processing unit (CPU) 10. It is configured.

  The CPU 10 has a random access via the bus 12 including a read-only memory (ROM) for storing a program for controlling the CPU 10 and various information described later, a storage area used as a working area for the CPU 10, and the like. An internal storage device 14 composed of a memory (RAM), a display device 16 having a screen such as a CRT or a liquid crystal panel for performing various displays based on the control of the CPU 10, and an arbitrary on the screen of the display device 16 A pointing device 18 such as a mouse for designating a position, a character input device 20 such as a keyboard for inputting an arbitrary character, and various information can be stored under the control of the CPU 10, and various stored information is read out. Hard disk that can be transferred to the internal storage device 14 And an external storage device 22 is connected.

  In this computing device, the pointing device 18 and the character input device 20 constitute an input unit IN (see FIG. 3), and the display device 16 forms an output unit OUT (see FIG. 3). It is configured.

  As described above, the external storage device 22 stores various types of information. As information related to the implementation of the present invention, it is connected by layout design data, which is design data of a printed circuit board, and one point ground. Information indicating whether or not to synthesize different nets (power supply or GND) as a single net, information indicating whether or not to synthesize, a layer not to be detected as a loop in the printed circuit board layer Information indicating the condition value of the excluded layer, information indicating the maximum and minimum loop size to be excluded (maximum and minimum loop size to be excluded), information indicating the allowable value (warning, caution) and the specified value of the judgment threshold, and guidance for improvement methods Information to be shown is stored.

  Here, as described above, the net synthesis enable / disable condition is a condition for setting whether to synthesize in a pseudo manner in order to process different nets (power supply or GND) connected by one point ground as one net. Yes, the user can selectively input information indicating the condition for determining whether or not to synthesize the net.

  That is, as shown in FIG. 7C, when the user checks the check box labeled “Consideration of synthesis of one-point ground connection GND” on the display device 16 using the pointing device 18, the condition for whether or not to synthesize the net is set. If the check box is not checked, the information indicating the net composition enable / disable condition is NO.

  When the information indicating the condition for enabling / disabling the net is YES, different nets (power supply or GND) connected by one-point ground are combined as one net. More specifically, when the information indicating whether or not to synthesize a net is YES, if there is no one-point ground on the board, there is no net to be synthesized, so the net cannot be synthesized and the net is synthesized. I will not. Therefore, when at least one point ground exists on the substrate and a plurality of nets, for example, two nets are connected by one point ground, a process of combining them as one net is performed.

  On the other hand, if the information indicating whether or not the net can be combined is NO, the net is not combined regardless of whether there is a one-point ground.

  The exclusion maximum / minimum loop size is set to omit loops that are too large and loops that are too small, and is set by the user inputting an arbitrary numerical value using the character input device 20 or the like.

That is, in setting the maximum exclusion loop, the relationship between the area of the loop to be detected (detection loop area) X and the maximum area of the loop to be excluded (designated maximum area) is “detection loop area X ≦ Enter a value for the specified maximum area so that it is "specified maximum area". Note that the actual input is performed by inputting an arbitrary numerical value using the character input device 20 or the like at the location of “XX” where “excludes“ XX mm ² or less ”” is displayed on the display device 16.

On the other hand, when setting the exclusion minimum loop, the relationship between the area of the loop to be detected (detection loop area) X and the minimum area of the loop to be excluded (designated minimum area) is “specified minimum area ≦ detection The value of the designated minimum area is input so as to be “loop area X”. Note that the actual input is performed by inputting an arbitrary numerical value using the character input device 20 or the like at the location of “XX” where “excludes XX mm ² or more” is displayed on the display device 16.

Here, the layout design data is composed of component information that is information on various components, wiring information that indicates the wiring state between the various components, and the like.

  Further, the component information includes arrangement position information indicating the arrangement position of the component, and terminal information that is information related to the terminal of the component.

  On the other hand, the wiring information includes net information, which is connection information between component pins, and wiring layout information, which is position information of wirings that constitute the printed circuit board.

  In this embodiment, the condition value of the excluded layer means a value indicating the area ratio of the layer (GND and power supply are set on the net). Here, the area ratio of the layer is the occupation ratio of the wiring pattern with respect to the printed circuit board area of the target layer, and is calculated by the areas of the power supply pattern and the GND pattern.

  In setting the condition value of the exclusion layer, the exclusion area ratio is set so that the relationship between the power supply GND area of the layer, the substrate area, and the exclusion area ratio is “layer power supply GND area / substrate area ≦ exclusion area ratio”. Enter a value. Note that the actual input is performed by inputting an arbitrary numerical value using the character input device 20 or the like to the portion of XX where “exclude area ratio XX or more” is displayed on the display device 16.

In the above configuration, an outline of processing executed by the calculation apparatus will be described with reference to the flowchart shown in FIG.

  In this calculation apparatus, a user can input a desired instruction by operating the pointing device 18 or the character input device 20 as the input unit IN. For example, the user operates the pointing device 18 or the character input device 20 as the input unit IN to instruct to read layout design data from the external storage device 22, or information indicating whether or not to synthesize the net, Information indicating the condition value, information indicating the maximum and minimum exclusion loop size, information indicating the allowable value (warning, caution) and the specified value of the judgment threshold, information indicating the guidance of the improvement method, etc. are set, and the reading is instructed You can do it.

  Then, when the user operates the pointing device 18 or the character input device 20 as the input unit IN to instruct reading of the layout design data and the like from the external storage device 22, the layout design data and the like are read from the external storage device 22. And transferred to the internal storage device 14.

  Then, the CPU 10 reads predetermined information from the layout design data transferred to the internal storage device 14 and stores it, and selects a target net that is a target for detecting a loop in the power supply net and the GND net. Target net selection process A, loop location extraction calculation process B for each target net, loop selection process C to be detected, tolerance calculation process D, and loop improvement technique guidance display Process E is executed simultaneously in parallel by time sharing.

  The intermediate result and final result of the processing are appropriately displayed on the display device 16 as the output unit OUT.

Next, processing executed by the above-described computing device will be described in detail with reference to the flowcharts shown in FIGS.

  That is, the CPU 10 reads the wiring information from the layout design data (Step S402), acquires the net information from the wiring information (Step S404), and acquires the wiring layout information (Step S406) from the wiring information.

  Further, the CPU 10 reads information indicating whether or not the net composition is possible (step S408), reads information indicating the condition value of the excluded layer (step S410), reads information indicating the maximum excluded and minimum loop size (step S412), and allows Information indicating the value (warning, caution) and the specified value of the determination threshold is read (step S414), and information indicating the guidance of the improvement method is read (step S416).

  Then, the wiring information acquired in step S404 and the wiring layout information acquired in step S406 are sent to the target net selection process (step S418).

  That is, the target net selection process (step S418) for selecting the target net that is the target of the loop detection is performed using the wiring information and the wiring layout information obtained by the above processing. Reading of wiring information and wiring layout information used in the target net selection process is performed in steps S404 and S406, and the read wiring information and wiring layout information are sent to the target net selection process (step S418).

  Here, the nets selected as the target net in the target net selection process in step S418 are the power supply net and the GND net. That is, in step S418, a net whose net attribute is set as “power supply” or “GND” on the board is selected as a target net, and nets of other signals are excluded from the target net (see FIG. 6). . In selecting target nets, lines, faces, and pads are targeted.

  Next, if the information indicating the net composition availability condition read in step S408 is YES, the power supply net selected as the target net in step S418, GND using the wiring information and wiring layout information acquired in step S418. It is determined whether or not one point ground exists on the net (step S420). The determination condition process (hereinafter referred to as “one-point ground inspection” as appropriate) performed in step S420 is a determination condition process performed to treat different nets like the same potential net.

  In the one-point ground inspection in step S420 described above, when it is determined that one-point ground exists in the selected target net, a process of combining a plurality of nets connected to the one-point ground (step S422) was performed. Later, the target net is determined in the wiring layout (step S424).

  On the other hand, if it is determined in the one-point ground inspection in step S420 described above that the one-point ground does not exist in the selected target net, the target net is determined in the wiring layout as it is (step S424).

  Further, when the information indicating the net composition availability condition read in step S408 is NO, the process of step S424 is performed without performing the processes of step S420 and step S422. That is, if the information indicating whether or not the net composition is read in step S408 is NO, the target net is determined in the wiring layout as it is regardless of the presence or absence of one-point ground in the power supply net or the GND net ( Step S424).

  Specifically, using the layout shown in FIG. 7A, in the layout shown in FIG. 7A, there are one power supply pattern and two GND patterns (GND1 and GND2). Therefore, if the information indicating the net composition enable / disable condition read in step S408 is YES, it is determined that one point ground exists in the one point ground inspection in step S420.

  For this reason, the process proceeds to step S422, and GND1 and GND2, which are two GND patterns connected to one-point ground, are synthesized to form a pseudo net. FIG. 7B shows an image diagram of the pseudo net when these two GND patterns GND1 and GND2 are synthesized.

  As shown in FIG. 7C, when the user checks the check box labeled “Consideration of synthesis of one-point ground connection GND” on the display device 16 by using the pointing device 18, the condition for whether or not to synthesize the net is set. If the check box is not checked, the information indicating the net composition enable / disable condition is NO.

  Here, the contents of the target net determined in step S424 will be described together for each condition. First, in the case where the information indicating the net composition enable / disable condition is YES, the target net selected in step S418 is displayed. If there is no one-point ground connection, the target net selected in step S418 is determined as the target net as it is.

  On the other hand, if the information indicating whether or not the net can be combined is YES, if the target net selected in step S418 has a single point ground connection, the single point ground connected net is combined to form one pseudo net. The pseudo net formed in this way is determined as the target net together with the unsynthesized net (see FIG. 8).

  If the information indicating the condition for determining whether or not to synthesize a net is NO, the target net selected in step S418 is determined as the target net as it is.

  When the target net is thus determined in step S424, the area of the graphic constituting the determined target net is acquired (step S426), and the size of the graphic is acquired (step S428).

On the other hand, when the condition value of the excluded layer is read in step S410 and the wiring layout information is acquired in step S406, the condition value and wiring layout information of the excluded layer are the target layer for determining the target layer that is the layer for detecting the loop. To the confirmation process (step S430), and the target layer is confirmed by the determination process of step S432 described below. Here, the target layer as a layer for detecting the loop is determined by excluding the layer from the loop detection target when the GND area is large, and not performing the loop location extraction calculation process for each target net. This is to omit processing.

  That is, the target layer determination process for determining the target layer as a layer for detecting a loop is performed using the condition value of the exclusion layer and the wiring layout information obtained by the above processing. In step S410, the exclusion layer condition value used in the determination process is read and the wiring layout information is acquired in step S406. The read exclusion layer condition value and the acquired wiring layout information are used. Are processed.

  Then, using the read condition value of the excluded layer and the acquired wiring layout information, it is determined whether the area ratio of the layer is equal to or less than the condition value of the excluded layer (step S432).

  In the determination process of step S432, if it is determined that the area ratio of the layer is not less than or equal to the condition value of the excluded layer, the layer is determined as an excluded layer (step S434). Thereby, loop extraction when the GND area is large in the substrate layer can be omitted.

  On the other hand, if it is determined in step S432 that the area ratio of the layer is equal to or less than the condition value of the excluded layer, the layer is determined as the target layer (step S436).

  Then, using the target layer determined in step S436 and the target net determined in step S424, a loop location extraction calculation process for each target net is performed (step S438).

  Here, the processing for determining the target layer described above will be described with reference to the example of the four-layer substrate shown in FIG. 9. In the first layer, the third layer, and the fourth layer, the area ratio of the layers is not more than the condition value of the excluded layer. As a result, the target layer is determined, and the two layers are determined as the excluded layer because the area ratio of the layers exceeds the condition value of the excluded layer.

  Next, the loop part extraction calculation process for each target net executed in step S438 is a process for extracting a loop for each net.

  Here, as shown in FIGS. 10A and 10B, for example, when the same net is in one layer and two layers, a loop surrounded by the wiring pattern is referred to as a closed loop (CLOSE) (FIG. 10). 10 (a)), a loop that is surrounded by the wiring pattern but has a portion that is not closed but is open is referred to as an open loop (OPEN) (see FIG. 10B).

  In the loop location extraction calculation process for each target net in step S438, first, the target layer is overlapped to create a figure for loop extraction of the target net.

  FIG. 11 shows an example of a two-layer substrate in which both the first layer and the second layer are the target layers. In this two-layer substrate, two layers of the first layer and the second layer are overlaid and synthesized. A loop figure is extracted as a pattern.

  FIG. 12 shows an example of a four-layer substrate in which only two layers are excluded as in the example shown in FIG. 9. In this four-layer substrate, one layer is not overlaid. A loop figure is extracted by a single layer single pattern, and a loop figure is extracted as a pattern obtained by superposing two layers of layers 3 and 4 and combining them.

  If the extracted loop graphic is a closed loop graphic surrounded by a pattern as shown in FIG. 10 (a), it is determined as a closed loop, and surrounded by a pattern as shown in FIG. 10 (b). If it is a loop figure that is open but not closed, it is determined to be open loop.

  Here, in the extraction of the loop figure as a superposed pattern, if the pattern connection between the first layer and the second layer is not considered only by simple overlapping, the loop 1 and the loop pattern as shown in FIG. Since loop 2 is surrounded by the pattern, it is determined as a closed loop.

  On the other hand, in extracting a loop figure as a superposed pattern, when considering the connection of patterns between the first and second layers, as shown in FIG. If connected by vias, loop 3 and loop 4 are determined as closed loops. However, as shown in FIG. 13A, if there is no connection by vias, loop 1 is not determined as a closed loop, and only loop 2 is determined as a closed loop. Is done.

  The setting as to whether or not to consider the connection between the layers can be appropriately performed by the user using the pointing device 18 or the character input device 20.

In addition, when the exclusion maximum / minimum loop size is read in step S412, and the loop location extraction calculation processing for each target net is performed in step S438, the exclusion maximum / minimum loop size and the loop location extraction calculation processing result for each target net are obtained as a loop. It is sent to the determination process of the loop to be determined (step S440), and the target loop (target loop) is determined by the processes of steps S442 to S452 described below.

  That is, using the exclusion maximum / minimum loop size obtained by the above-described processing and the loop part extraction calculation processing result for each target net, the loop determination processing (step S440) for determining the loop is performed. The exclusion maximum / minimum loop size used in the loop determination process is read in step S412, and the loop location extraction calculation process for each target net is performed in step S438. The read exclusion maximum / minimum loop size and each target net are read. The processing is performed using the loop location extraction calculation processing result.

  Then, using the read exclusion maximum / minimum loop size and the loop location extraction calculation result for each target net, it is determined whether or not the size of the loop is within the exclusion maximum / minimum loop size range (step S442). If the loop size does not fall within the range of the excluded maximum / minimum loop size, the loop is excluded (step S444).

  That is, whether or not the area of the loop extracted in step S438 is within the range between the designated maximum area as the maximum loop size set in the excluded maximum and minimum loop sizes and the designated minimum area as the minimum loop size is determined in step S442. If the area of the loop is smaller than the specified maximum area, the loop is excluded, and if the area of the loop is larger than the specified minimum area, the loop is also excluded (step S444).

  On the other hand, if it is determined in step S442 that the loop size is within the range of the maximum excluded minimum loop size, it is determined whether there is one net for the loop (step S446). ).

  If it is determined in step S446 that the number of nets in the loop is not one, a plurality of net flags are set (step S448), and then the process in step S450 is performed.

  On the other hand, if it is determined in step S446 that there is only one net in the loop, the process in step S450 is performed as it is.

  In the process of step S450, it is determined whether or not the loop is a closed loop.

  If it is determined in the determination processing in step S450 described above that the loop is not a closed loop, that is, an open loop, a flag indicating open loop is set and the number of nets is set (step S452). ), The process proceeds to step S454, and the loop is determined as the target loop.

  On the other hand, if it is determined in step S450 described above that the loop is a closed loop, the process proceeds to step S454 and the loop is determined as the target loop.

  When the target loop is thus determined in step S454, the determined area of the target loop is acquired (step S456) and the size of the loop is acquired (step S458).

Then, the area of the figure constituting the confirmed target net acquired in step S426, the size of the figure constituting the confirmed target net obtained in step S428, the area of the confirmed target loop acquired in step S456, and step The size of the determined target loop acquired in S458, the allowable value (warning, caution) read in step S414, and the specified value of the determination threshold are sent to the allowable value calculation process (step S460).

  In other words, the degree of compliance described later is within an allowable value using the area of the figure constituting the target net, the size of the figure constituting the target net, the area of the target loop, and the size of the target loop obtained by the above processing. An allowable value calculation process (step S460) for determining whether or not the allowable value (warning, caution) used in the allowable value calculation process and a specified value for the determination threshold are read in step S414. The read allowable value (warning, caution) and the specified value of the determination threshold value are sent to the allowable value calculation process (step S460).

  Here, as the determination threshold (hereinafter simply referred to as “threshold” as appropriate), two types of warning setting value (%) as threshold 1 and attention setting value (%) as threshold 2 are set. These two types of threshold values are read.

  The specified values of the two types of threshold values, the warning setting value (%) and the caution setting value (%), can be set to arbitrary values by the user using the character input device 20 or the like.

  The allowable value calculation process (step S460) will be described in detail with reference to FIG.

  First, the calculation formula used in the allowable value calculation processing (step S460) is defined by “evaluation value = surface area / (surface area + loop area)”. Using this calculation formula, individual target nets are defined. To evaluate.

  Here, the evaluation value is an evaluation of the loop of the target net actually searched by this computing device in terms of EMC. In other words, it represents the matching ratio between the loop of the target net actually searched for by this computing device and the ideal loop in consideration of problems related to EMC, and the maximum value is “1”.

  Therefore, when “evaluation value = 1”, the loop of the target net actually searched for by this computing device has a low possibility of occurrence of a problem relating to EMC, and if the evaluation value becomes smaller than “1”. Indeed, the possibility of occurrence of problems with the EMC increases.

  Further, “evaluation value × 100 [%]” is defined as “compliance”. Therefore, the “compliance degree” means a matching rate with respect to an ideal loop standard for each target net with respect to the loop of the target net.

  When a loop is detected across layers, the degree of compliance is calculated as shown in FIG. 15 depending on whether the loop is a closed loop or an open loop.

  That is, if the loop is a closed loop, calculation is performed as “compliance = surface area / (surface area + closed loop area) / 2 × 100 [%]”. If the loop is an open loop, the calculation is performed as “compliance degree = (surface area / (surface area + open loop area) /2+0.5) × 100 [%]”.

  Here, the “surface area” is the area of the graphic that the net forming the loop has. The “loop area” is an area where a loop is detected.

In the example of the error list shown in FIG. 14, “net name” indicates the name of the target net, and “one point ground” indicates the presence / absence of one point ground, and there is no one point ground. "-" Is shown in the case, while "+" is shown when there is a one-point ground.

  The “number of nets” indicates the synthesis of nets, and there is a loop that crosses one point ground when the number of nets is “2” or more.

  Next, “loop shape open / close” indicates a determination result of whether the loop is closed or open, and indicates “CLOSE” when the loop is closed, and when the loop is open. Indicates “OPEN”.

  The “layer position” indicates the position of the layer where the loop exists. For example, when there is a loop in one layer, “1” is indicated, and there are three and four layers. When there is a loop from the figure, “3-4” is indicated.

  In the allowable value calculation process (step S460), in order to determine whether the compliance level corresponds to “warning”, “caution”, or “pass”, Comparison processing with a threshold value is performed (see FIG. 16).

  Here, if “compliance level (%) <warning setting value (%)”, it corresponds to “warning” and “warning setting value (%) ≦ compliance level (%) <caution setting value (%)” In this case, it corresponds to “Caution”, and in the case of “Caution setting value (%) ≦ compliance degree (%)”, it corresponds to “Pass (within tolerance)”.

When the process of step S460 described above is completed, it is determined whether the result of the comparison process between the compliance level and the threshold is within the warning range (step S462), and the result of the comparison process is determined to be within the warning range. If it is determined, the highlighting process (step S468) for highlighting when displaying on the screen of the display device 16 is performed, and if it is determined that the result of the comparison process is not within the warning range, the above-described process is performed. It is determined whether or not the result of the comparison process is within the caution range (step S464).

  Then, in the determination process of step S464, when it is determined that the result of the comparison process described above is within the attention range, the highlight display process (step S468) for highlighting when displaying on the screen of the display device 16 is performed. When it is determined that the result of the comparison process is not within the caution range, the result of the comparison process is within the allowable value and is accepted (step S466), and is emphasized when displayed on the screen of the display device 16. The highlighting process to be displayed (step S468) is performed.

  Based on the processing result of the highlighting process (step S468), the screen of the display device 16 is displayed (step S472).

  Here, it is possible to arbitrarily set the display color when displaying on the screen of the display device 16 in the case of “Warning”, “Caution” and “Pass” in conjunction with the setting of the warning setting value and the caution setting value. It is.

  For example, when the warning set value is 70%, the warning display color is red, the caution set value is 80%, the caution display color is yellow, and the acceptable display color is green, FIG. As shown in FIG. 16, when the compliance level is 50%, a warning is displayed in red (see pattern 1 indicating Line 1 indicated by hatching in FIG. 16), and when the compliance level is 75%, attention is displayed in yellow (see FIG. In FIG. 16, when the compliance level is 85%, attention is displayed in green (see pattern 3 indicating Line 3 shown in white in FIG. 16).

  17, 18 and 19 are display examples of screen display showing the result of the allowable value calculation process (step S 460). For each “net name” (name of the target net) of each net, “ 1-point ground ”,“ Number of nets ”,“ Loop shape closed / open ”,“ Layer position ”,“ Surface area ”,“ Loop area ”,“ Compliance ”and evaluation. "Warning" or "Pass") is displayed.

Also, as described above, the guidance for the improvement technique is read in step S416 and sent to the process for guidance for the improvement technique for the loop (step S470).

  The processing result of the allowable value calculation process (step S460) is also sent to the loop improvement technique guidance process (step S470).

  Then, as a result of the loop improvement technique guidance process (step S470), a guidance screen is displayed on the display device 16.

  Thereby, the designer can be prompted to change the design, and the designer can easily change the design by confirming the guidance display. For this reason, the shape of the loop formed on the printed circuit board is verified, and sufficient EMC measures can be taken.

  FIG. 20 shows an example of a screen display by the guidance process of the loop improvement method. In the example shown in FIG. 20, on the screen of the display device 16, as a guidance display, “1. Make the pattern without the loop shape” and “2. Please reinforce the connection with vias, etc. "and a graphic display showing these countermeasures.

  In addition, “rule contents” and “SI & EMC problems” are also displayed in text on the screen of the display device 16.

21 to 25 and FIG. 19 conceptually show images of display examples displayed on the screen of the display device 16. The screen display of the display device 16 transitions from FIG. 21 to FIG. 22 to FIG. 23 to FIG. 24 to FIG.

  In FIG. 21, the GND of the actual pattern is displayed, and a layout of one layer and two layers is shown. That is, in FIG. 21, the state where the layers of the target net are superimposed on the substrate is displayed.

  FIG. 22 shows a figure in which the first layer and the second layer are overlapped and transmitted through the process up to the loop location extraction calculation process for each target net in step S438. That is, FIG. 22 shows a figure in which the GND patterns in the first layer and the second layer are overlapped and transmitted.

  Next, FIG. 23 shows a state in which the target loop is specified by the process up to confirmation as the target loop in step S454. That is, in FIG. 23, a loop graphic of the target loop is detected and a state in which the target loop is specified is displayed.

  Further, FIG. 24 shows a state in which the identified target loops are sorted into A loop, B loop, C loop, and D loop. That is, in FIG. 24, a state in which the loop graphic of the target loop is detected and divided for each shape is displayed.

  Then, as shown in FIG. 25, details about the A loop, B loop, C loop, and D loop will be shown.

  Further, FIG. 25 shows a state where details of each loop serving as a target loop are tabulated, and FIG. 26 shows an actual display image on the screen of the display device 16.

FIG. 19 shows a loop evaluation result when calculation is performed using the loop area. According to this loop evaluation result, Loop A and Loop B passed, and Loop C, Loop D and Loop E warned.

The embodiment described above may be modified as described in (1) to (4) below.

  (1) In the above-described embodiment, the evaluation value is obtained from the loop area. However, the evaluation value is not limited to this, and may be obtained from the loop size. In this case, as shown in FIG. 27, the calculation formula used in the allowable value calculation process (step S460) is defined by “evaluation value = surface size / (surface size + loop size)”. .

  When a loop is detected across layers, the degree of compliance is calculated as shown in FIG. 28 depending on whether the loop is a closed loop or an open loop.

  That is, if the loop is a closed loop, calculation is performed as “compliance degree = surface size / (surface size + closed loop size) / 2 × 100 [%]”. Further, if the loop is an open loop, it is calculated as “compliance degree = (surface size / (surface size + open loop size) /2+0.5) × 100 [%]”.

  Further, when obtaining the loop evaluation result, both the method obtained by the surface area shown in FIG. 14 and the method obtained by the surface size shown in FIG. 27 may be used.

  FIG. 18 shows a loop evaluation result when calculation is performed with the loop size. According to this loop evaluation result, Loop A and Loop B passed, and Loop C, Loop D and Loop E warned.

  Further, FIG. 19 shows a loop evaluation result in the case where both the method of obtaining by the loop area and the method of obtaining by the loop size are used. According to this loop evaluation result, Loop A and Loop B passed, and Loop C, Loop D and Loop E warned.

  (2) In the above-described embodiment, both the text display and the graphic display are performed in the guidance process of the improvement method (step S472). Only one of the display and the display may be performed.

  (3) In the above-described embodiment, the improvement method guidance is displayed in the improvement method guidance process (step S472) to prompt the designer to change the design. However, the present invention is limited to this. It is also possible to automatically change the design and display the contents of the change.

  (4) You may make it combine suitably the embodiment shown above and the modification shown in said (1)-(3).

  The present invention can be used for EMC countermeasures on a printed circuit board and can suppress the occurrence of EMC problems.

FIG. 1 is an explanatory diagram illustrating an example of a printed circuit board in which a pattern formed by a GND net has a loop shape. FIG. 2 is a block configuration diagram showing a system configuration of an example of an embodiment of a pattern loop shape calculation apparatus on a printed circuit board according to the present invention. FIG. 3 is a flowchart showing an outline of processing executed by the pattern loop shape calculation apparatus on the printed circuit board according to the present invention. FIG. 4 is a flowchart showing details of the processing executed by the pattern loop shape calculation apparatus on the printed circuit board according to the present invention. FIG. 5 is a flowchart showing details of the processing executed by the pattern loop shape calculation apparatus on the printed circuit board according to the present invention. FIG. 6 is an image diagram showing a display example displayed on the display device when the target net is selected. FIG. 7A is an explanatory diagram showing an example of the layout of the printed circuit board, and FIG. 7B is an image diagram when the two GND patterns GND1 and GND2 in FIG. 7A are synthesized. FIG. 7C is an image diagram showing a message displayed on the display device. FIG. 8 is an explanatory diagram of the process for determining the target net. FIG. 9 is an explanatory diagram of the target layer determination process. FIG. 10A is an explanatory diagram related to a closed loop, and FIG. 10B is an explanatory diagram related to an open loop. FIG. 11 is an explanatory diagram of a loop graphic extraction process in a two-layer substrate. FIG. 12 is an explanatory diagram of a loop graphic extraction process on a four-layer board. FIGS. 13A and 13B are explanatory diagrams of the process of extracting a loop graphic as a superimposed pattern. FIG. 14 is an explanatory diagram regarding the calculation process of the allowable value. FIG. 15 is an explanatory diagram regarding the calculation processing of the compliance level. FIG. 16 is an explanatory diagram regarding threshold values and allowable values. FIG. 17 is a display example in which the loop evaluation result when calculated by the loop area is displayed on the screen of the display device. FIG. 18 is a display example in which the loop evaluation result when calculated with the loop size is displayed on the screen of the display device. FIG. 19 is a display example in which the loop evaluation result when the calculation is performed using both the loop area and the loop size is displayed on the screen of the display device. FIG. 20 is an explanatory diagram illustrating an example of a screen display by the guidance of the loop improvement method. FIG. 21 is an explanatory diagram conceptually illustrating a display example displayed on the screen of the display device. FIG. 22 is an explanatory diagram conceptually illustrating a display example displayed on the screen of the display device. FIG. 23 is an explanatory diagram conceptually illustrating a display example displayed on the screen of the display device. FIG. 24 is an explanatory diagram conceptually illustrating a display example displayed on the screen of the display device. FIG. 25 is an explanatory diagram conceptually showing a display example in a state where the details of each loop serving as a target loop are tabulated. FIG. 26 is an explanatory diagram showing an actual display image on the screen of the display device. FIG. 27 is an explanatory diagram of another example related to the allowable value calculation process. FIG. 28 is an explanatory diagram of another example regarding the calculation processing of the compliance level.

Explanation of symbols

10 Central processing unit (CPU)
12 Bus 14 Internal storage device 16 Display device 18 Pointing device 20 Character input device 22 External storage device

Claims (8)

Net selection means,
Net confirmation means,
Target layer determination means;
Loop extraction means;
Loop selection means;
A calculation means;
First display means;
Second display means and
In the calculation method of the pattern loop shape in the printed circuit board for evaluating the loop shape of the pattern formed by the power supply net or the GND net in the printed circuit board by the calculation device of the pattern loop shape in the printed circuit board having
By the net selection means , a loop is generated in the power supply net or the GND net for the layout design data including the part information which is information on various parts and the wiring information indicating the wiring state between the various parts. A first process of selecting a target net that is a target to be detected;
The net determining means gives an instruction to artificially synthesize the target net selected in the first process in order to process different power supply nets or GND nets connected at one point ground as one net. In this case, a loop shape obtained by synthesizing power nets or GND nets connected by one point ground is determined as a pseudo net, and different power nets or GND nets connected by one point ground and when not connected by one point ground A second process for determining a power source net or a GND net as a target net as it is when an instruction to perform a pseudo synthesis for processing as one net is not given;
The target layer determining means determines a target layer as a layer for detecting a loop based on a condition value of an exclusion layer set in advance from the occupation ratio of the wiring pattern with respect to the printed circuit board area in each layer in the layout design data. A third process;
A fourth process of extracting a loop part for each target net determined in the second process on the target layer determined in the third process by the loop extraction unit ;
Based on the values calculated by the loop selection means using the area of the figure constituting the target net of each loop and the size of the figure constituting the target net, and the area of the loop and the size of the loop, the fourth A fifth process of selecting a loop to be detected from the loop location extracted by the process;
A sixth process for calculating a matching ratio between the loop selected by the fifth process and a predetermined condition by the calculation means ;
A seventh process of displaying a result of calculation by the sixth process by the first display means;
A method for calculating a loop shape of a pattern on a printed circuit board , comprising: an eighth process for displaying guidance for EMC countermeasures according to a calculation result of the sixth process by the second display unit . Net selection means,
Net confirmation means,
Target layer determination means;
Loop extraction means;
Loop determination means;
Loop selection means;
A calculation means;
First display means;
Second display means and
In the calculation method of the pattern loop shape in the printed circuit board for evaluating the loop shape of the pattern formed by the power supply net or the GND net in the printed circuit board by the calculation device of the pattern loop shape in the printed circuit board having
By the net selection means, a loop is generated in the power supply net or the GND net for the layout design data including the part information which is information on various parts and the wiring information indicating the wiring state between the various parts. A first process of selecting a target net that is a target to be detected;
The net determining means gives an instruction to artificially synthesize the target net selected in the first process in order to process different power supply nets or GND nets connected at one point ground as one net. In this case, a loop shape obtained by synthesizing power nets or GND nets connected by one point ground is determined as a pseudo net, and different power nets or GND nets connected by one point ground and when not connected by one point ground A second process for determining a power source net or a GND net as a target net as it is when an instruction to perform a pseudo synthesis for processing as one net is not given;
The target layer determining means determines a target layer as a layer for detecting a loop based on a condition value of an exclusion layer set in advance from the occupation ratio of the wiring pattern with respect to the printed circuit board area in each layer in the layout design data. A third process;
When the target layer determined in the third process by the loop extraction unit does not exist above and below the target layer, the target layer is determined from the target net determined in the second process on the target layer. If the loop part is extracted and two or more target layers are overlapped, a figure is created by superposing and synthesizing the target nets determined in the second process on each target layer, and the superposed figure A fourth process of extracting loop points from
When the shape of the loop portion extracted in the fourth process by the loop determining means is an open shape, it is determined as an open loop, and the shape of the loop portion extracted in the fourth process is In the case of a closed shape, it is determined as a closed loop, and among the loop locations determined as the closed loop, when there is a via connection between layers, it is determined as a closed loop, and also determined as the closed loop If there is no via connection between the layers in the loop location, a fifth process for determining that the loop is not closed,
Based on the values calculated by the loop selection means using the area of the figure constituting the target net of each loop and the size of the figure constituting the target net, and the area of the loop and the size of the loop, the fourth A sixth process for selecting a loop to be detected based on the determination made in the fifth process from the loop location extracted by the process;
When calculating the matching ratio between the loop selected by the sixth process and a predetermined condition by the calculating means, a loop determined to be an open loop in the fifth process and a closed loop in the fifth process In the determined loop, a seventh process of calculating a matching ratio by changing a matching ratio with respect to the predetermined condition;
An eighth process for displaying the result of the calculation by the seventh process by the first display means;
A method for calculating a loop shape of a pattern on a printed circuit board , comprising: a ninth process for displaying guidance for EMC countermeasures according to a calculation result of the seventh process by the second display unit . In the calculation device of the loop shape of the pattern on the printed circuit board for evaluating the loop shape of the pattern formed by the power supply net or the GND net on the printed circuit board,
A net that is a target for detecting a loop in a power supply net or a GND net for layout design data that includes part information that is information on various parts and wiring information that indicates wiring states between various parts. Net selection means for selecting a target net,
When the target net selected by the net selection means is instructed to synthesize a different power supply net or GND net connected by one-point grounding as one net, one-point grounding is performed. In order to determine a loop shape that combines power supply nets or GND nets connected together at a single point as a pseudo net, and to treat different power supply nets or GND nets connected at one point grounding as one net In the case where an instruction to synthesize pseudo is not given, net determining means for determining the power net or the GND net as a target net as it is,
Among the layout design data, based on the condition value of the exclusion layer set in advance from the occupation ratio of the wiring pattern with respect to the printed circuit board area in each layer, target layer determination means for determining a target layer as a layer for detecting a loop;
Loop extraction means for extracting a loop part for each target net determined by the net determination means on the target layer determined by the target layer determination means ;
The loop extracted by the loop extraction means based on the area calculated by using the area of the figure constituting the target net of each loop, the size of the figure constituting the target net, and the area of the loop and the size of the loop Loop selection means for selecting a loop to be detected from a location;
Calculation means for calculating a matching ratio between the loop selected by the loop selection means and a predetermined condition;
First display means for displaying a result of calculation by the calculation means;
An apparatus for calculating a loop shape of a pattern on a printed circuit board , comprising: second display means for displaying guidance for EMC countermeasures according to a result of calculation by the calculation means . In the calculation device of the loop shape of the pattern on the printed circuit board for evaluating the loop shape of the pattern formed by the power supply net or the GND net on the printed circuit board,
A net that is a target for detecting a loop in a power supply net or a GND net for layout design data that includes part information that is information on various parts and wiring information that indicates wiring states between various parts. Net selection means for selecting a target net,
When the target net selected by the net selection means is instructed to synthesize a different power supply net or GND net connected by one-point grounding as one net, one-point grounding is performed. In order to determine a loop shape that combines power supply nets or GND nets connected together at a single point as a pseudo net, and to treat different power supply nets or GND nets connected at one point grounding as one net In the case where an instruction to synthesize pseudo is not given, net determining means for determining the power net or the GND net as a target net as it is,
Among the layout design data, based on the condition value of the exclusion layer set in advance from the occupation ratio of the wiring pattern with respect to the printed circuit board area in each layer, target layer determination means for determining a target layer as a layer for detecting a loop;
If the target layer determined by the target layer determination means has no target layer above and below the target layer, a loop location is extracted from the target net determined by the net determination means on the target layer, and When two or more target layers are overlapped, loop extraction is performed to create a figure by overlapping and synthesizing the target nets determined by the net determination means on each target layer, and to extract a loop portion from the overlapped figure Means,
When the shape of the loop location extracted by the loop extraction means is an open shape, it is determined as an open loop, and when the shape of the loop location extracted by the loop extraction means is a closed shape, If the connection between the layers is determined as a closed loop among the loop locations determined as the closed loop, it is determined as a closed loop, and the vias between the layers are determined as the closed loop. If there is no connection by, loop determining means for determining that it is not a closed loop,
The loop extracted by the loop extraction means based on the area calculated by using the area of the figure constituting the target net of each loop, the size of the figure constituting the target net, and the area of the loop and the size of the loop Loop selection means for selecting a loop to be detected based on a determination made in the loop determination means from a location;
When calculating the matching ratio between the loop selected by the loop selection unit and a predetermined condition, the loop determined by the loop determination unit as an open loop and the loop determined by the loop determination unit as a closed loop, A calculation means for calculating a matching ratio by changing a matching ratio for a predetermined condition;
First display means for displaying a result of calculation by the calculation means;
An apparatus for calculating a loop shape of a pattern on a printed circuit board , comprising: second display means for displaying guidance for EMC countermeasures according to a result of calculation by the calculation means . In a computer-readable recording medium recording a program for causing a computer to execute calculation of a loop shape of a pattern on a printed circuit board for evaluating a loop shape of a pattern formed by a power supply net or a GND net on the printed circuit board,
A net that is a target for detecting a loop in a power supply net or a GND net for layout design data that includes part information that is information on various parts and wiring information that indicates wiring states between various parts. A first process for selecting a target net,
If the target net selected in the first process is instructed to be artificially combined to process different power supply nets or GND nets connected by one point ground as one net, one point is given. A loop shape that combines power nets or GND nets connected by ground is determined as a pseudo net, and different power nets or GND nets that are connected by one point ground and when not connected by one point ground are processed as one net. Therefore, in the case where an instruction for pseudo synthesis is not performed, a second process for determining the power net or the GND net as the target net as it is,
Of the layout design data, a third process for determining a target layer as a layer for detecting a loop based on a condition value of an exclusion layer set in advance from an occupation ratio of a wiring pattern with respect to a printed circuit board area in each layer;
A fourth process for extracting a loop part for each target net determined in the second process on the target layer determined in the third process;
Based on the values calculated using the area of the figure constituting the target net of each loop and the size of the figure constituting the target net, and the area of the loop and the size of the loop, it was extracted by the fourth process. A fifth process for selecting a loop to be detected from the loop part;
A sixth process for calculating a matching ratio between the loop selected by the fifth process and a predetermined condition;
A seventh process for displaying a calculation result of the sixth process;
A computer-readable recording medium recording a program for causing a computer to execute an eighth process of displaying guidance for EMC countermeasures according to the calculation result of the sixth process . In the calculation method of the loop shape of the pattern on the printed circuit board for evaluating the loop shape of the pattern formed by the power supply net or the GND net on the printed circuit board,
A net that is a target for detecting a loop in a power supply net or a GND net for layout design data that includes part information that is information on various parts and wiring information that indicates wiring states between various parts. A first process for selecting a target net,
If the target net selected in the first process is instructed to be artificially combined to process different power supply nets or GND nets connected by one point ground as one net, one point is given. A loop shape that combines power nets or GND nets connected by ground is determined as a pseudo net, and different power nets or GND nets that are connected by one point ground and when not connected by one point ground are processed as one net. Therefore, in the case where an instruction for pseudo synthesis is not performed, a second process for determining the power net or the GND net as the target net as it is,
Of the layout design data, a third process for determining a target layer as a layer for detecting a loop based on a condition value of an exclusion layer set in advance from an occupation ratio of a wiring pattern with respect to a printed circuit board area in each layer;
In the case where the target layer determined in the third process has no target layer above and below the target layer, the loop portion is extracted from the target net determined in the second process on the target layer, When two or more target layers overlap, a figure is created by superimposing and synthesizing the target nets determined in the second process on each target layer, and a loop portion is extracted from the superposed and synthesized figure. A fourth process;
When the shape of the loop location extracted in the fourth process is an open shape, it is determined as an open loop, and the shape of the loop location extracted in the fourth process is a closed shape. In the case where there is a via connection between layers among the loop locations determined as the closed loop, and determined as a closed loop, and among the loop locations determined as the closed loop, If there is no connection by via in the fifth process,
Based on the values calculated using the area of the figure constituting the target net of each loop and the size of the figure constituting the target net, and the area of the loop and the size of the loop, it was extracted by the fourth process. A sixth process of selecting a loop to be detected based on the determination made in the fifth process from the loop part;
A loop determined to be an open loop in the fifth process and a loop determined to be a closed loop in the fifth process when calculating a matching ratio between the loop selected by the sixth process and a predetermined condition; Then, a seventh process of calculating the matching ratio by changing the matching ratio with respect to the predetermined condition;
An eighth process for displaying a result of the calculation by the seventh process;
A computer-readable recording medium recording a program for causing a computer to execute a ninth process for displaying guidance for EMC countermeasures according to the calculation result of the seventh process . A program used for a calculation device for a loop shape of a pattern on a printed circuit board for evaluating a loop shape of a pattern formed by a power supply net or a GND net on the printed circuit board,
Computer
A net that is a target for detecting a loop in a power supply net or a GND net for layout design data that includes part information that is information on various parts and wiring information that indicates wiring states between various parts. Net selection means to select the target net,
When the target net selected by the net selection means is instructed to synthesize a different power supply net or GND net connected by one-point grounding as one net, one-point grounding is performed. In order to determine a loop shape that combines power supply nets or GND nets connected together at a single point as a pseudo net, and to treat different power supply nets or GND nets connected at one point grounding as one net A net determining means for determining a power source net or a GND net as a target net as it is,
Of the layout design data, a target layer determining means for determining a target layer that is a layer for detecting a loop based on a condition value of an excluded layer set in advance from an occupation ratio of a wiring pattern with respect to a printed circuit board area in each layer,
Loop extraction means for extracting a loop part for each target net determined by the net determination means on the target layer determined by the target layer determination means;
The loop extracted by the loop extraction means based on the area calculated by using the area of the figure constituting the target net of each loop, the size of the figure constituting the target net, and the area of the loop and the size of the loop Loop selection means for selecting a loop to be detected from a location,
Calculation means for calculating a matching ratio between the loop selected by the loop selection means and a predetermined condition;
First display means for displaying a result of calculation by the calculation means;
The program for functioning as a 2nd display means to display the guidance for EMC countermeasures according to the calculation result by the said calculation means . A program used for a calculation device for a loop shape of a pattern on a printed circuit board for evaluating a loop shape of a pattern formed by a power supply net or a GND net on the printed circuit board,
Computer
A net that is a target for detecting a loop in a power supply net or a GND net for layout design data that includes part information that is information on various parts and wiring information that indicates wiring states between various parts. Net selection means for selecting a target net,
When the target net selected by the net selection means is instructed to synthesize a different power supply net or GND net connected by one-point grounding as one net, one-point grounding is performed. In order to determine a loop shape that combines power supply nets or GND nets connected together at a single point as a pseudo net, and to treat different power supply nets or GND nets connected at one point grounding as one net A net determining means for determining a power source net or a GND net as a target net as it is,
Of the layout design data, a target layer determining means for determining a target layer that is a layer for detecting a loop based on a condition value of an excluded layer set in advance from an occupation ratio of a wiring pattern with respect to a printed circuit board area in each layer,
If the target layer determined by the target layer determination means has no target layer above and below the target layer, a loop location is extracted from the target net determined by the net determination means on the target layer, and When two or more target layers are overlapped, loop extraction is performed to create a figure by overlapping and synthesizing the target nets determined by the net determination means on each target layer, and to extract a loop portion from the overlapped figure means,
When the shape of the loop location extracted by the loop extraction means is an open shape, it is determined as an open loop, and when the shape of the loop location extracted by the loop extraction means is a closed shape, If the connection between the layers is determined as a closed loop among the loop locations determined as the closed loop, it is determined as a closed loop, and the vias between the layers are determined as the closed loop. Loop determination means for determining that the connection is not a closed loop when there is no connection by
The loop extracted by the loop extraction means based on the area calculated by using the area of the figure constituting the target net of each loop, the size of the figure constituting the target net, and the area of the loop and the size of the loop Loop selection means for selecting a loop to be detected based on a determination made in the loop determination means from a location;
When calculating the matching ratio between the loop selected by the loop selection unit and a predetermined condition, the loop determined by the loop determination unit as an open loop and the loop determined by the loop determination unit as a closed loop, A calculation means for calculating the conformity ratio by changing the conformity ratio for a predetermined condition;
First display means for displaying a result of calculation by the calculation means;
The program for functioning as a 2nd display means to display the guidance for EMC countermeasures according to the calculation result by the said calculation means .