JP4901538B2 - Data transfer method, data transfer device, electronic device, and image forming apparatus - Google Patents

Description

  The present invention relates to a data transfer method and apparatus in which a program stored in a second storage unit is transferred to a first storage unit, and a control unit executes the program stored in the first storage unit. The present invention can be applied to, for example, personal computers, workstations, servers, printers, copiers, facsimiles, and all other electronic devices and data processing devices equipped with a CPU and various memories.

JP 2006-72989 A.

  In recent electronic devices, Linux is installed even for embedded devices, and IP (Intelligent Peripheral: high-performance peripheral circuits) and already developed source code are ported to run advanced applications. However, there are no factors that reduce the amount of programs, and there is no factor to reduce the amount of programs. Since development man-hours that reduce the amount cannot be secured, the amount of programs installed or loaded on various electronic devices is increasing. However, since the cost of electronic equipment must be kept low, the CPU power that can be used (CPU function and processing capacity including processing speed) is limited, and high performance can be achieved with less CPU power and real-time processing can be performed. In order to do this, it is necessary to load a program into a RAM having a relatively high access speed and to perform hardware control or data processing based on the RAM program. However, in order to execute such a RAM program, firmware stored in a large-capacity ROM (implementing various hardware functions, input control, signal processing, calculation (data processing), output control, display, etc.) The program and reference data) need to be once transferred to the RAM. Cited Document 1 describes a data transfer device that resets a CPU and transfers firmware onto a RAM while the CPU is reset.

  One of the representative electronic devices is a digital copying machine having an MFP (Multi Function Printer) function. An example is shown in FIG. A copying machine MF1 shown in FIG. 10 includes an engine 20 including a scanner 17 that reads an image on a document, a printer 18 that writes an image on a sheet, and a process controller 19 that controls these processes. The system controller 10 that performs system control and image processing control is connected to a general-purpose bus such as a PCI bus. The above-described data transfer device can be installed in the system controller 10, for example.

  The system controller 10 includes an ASIC (Application Specific IC) 2, a RAM 4 that stores programs and image data, and holds state information of each part of the copier 3, and a ROM 4 that stores a boot program and an application program. Connected to the ASIC 2 are an NVRAM 5 that holds setting data and registration data, and an HDD 11 that mainly stores document information. The controller ASIC 2 performs transmission control for controlling the exchange of image data, control data, synchronization signals and the like among the controller 10, engine 20 and I / O interface 14, data read / write control for the memories 3 to 5 and the HDD 11, text data Is converted into image data, and read image data output from the scanner 17 is converted into recording color image data of the printer 18.

  The I / O interface 14 of the copying machine MF1 includes an operation board I / F (interface) 15 to which an operation board 9 is connected, a USB Host I / F 6, an SD card I / F 8, a MAC 16 to which a personal computer or a network is connected, and There is a line I / F 21 or the like connected to a facsimile communication line.

  A main controller unit including the system controller 10 and the I / O interface 14 performs overall control of the composite processing system, that is, system control. The CPU 1 of the system controller 10 can easily access not only the RAM 4 but also the internal registers in the I / O interface 14.

  A USB memory 12 that is one of the external storage media can be inserted into a cable terminal receiving slot having a USB cable connector of the USB Host I / F 6 to be electrically connected to the USB Host I / F 6. . Similarly, an SD card 13 as another external storage medium is inserted into the card insertion slot for guiding the SD card to the external connection connector of the SD card I / F 8 and electrically connected to the SD card I / F 8. can do.

  CPU1, which is a system control means, reads out images, prints, copies, facsimile transmissions, receptions, document information based on programs read from the ROM 4 and written to the RAM 3, and programs read from the USB memory 12 or the SD card 13 and written to the RAM 3. Control of document accumulation and transmission / reception of document information to / from the outside.

  By the way, in the data transfer apparatus, if the CPU (for example, CPU 1) is reset until all firmware is transferred to the RAM (for example, RAM 3), the larger the firmware capacity to be transferred, the longer the CPU starts to operate. Since this takes a long time, there is a demerit that the startup of the system is delayed. In Cited Document 1, the CPU reset is canceled after a part of the firmware is transferred to the RAM, and the CPU executes the program of the transferred part, while the remaining part controls the hardware by the CPU. The method of transferring while being described. However, the operation is not guaranteed when the RAM is referred to in the program first transferred to the RAM. In recent years, the capacity of the RAM mounted on the electronic device is increasing day by day. Execute the initialization process of the RAM and the initialization of the ASIC (for example, ASIC2) as soon as possible, but the ASIC cannot be initialized and the RAM can be accessed only after the transfer of all the programs to the RAM is completed. It has a structure, and since the transfer of firmware to the RAM and the initialization processing at the time of various boots by the CPU are not performed in parallel, the speed cannot be increased. Further, the present invention cannot be applied to a system using a SoC (System On Chip: a system made into a chip or a module) or a dedicated Chip Set (a dedicated chip or module) incorporating a CPU and peripheral circuits in recent years.

  As described above, there is still room for improvement in the prior art from the viewpoint of high-speed startup, and the effect is significant for electronic devices equipped with a huge OS (Operating System) as in recent years. Appear.

  In addition, due to advances in semiconductor technology in recent years, rather than selling semiconductors as conventional single CPU products, CPU peripheral circuits, USB (Universal Serial Bus), LAN (Local Area Network), PCI (Peripheral Component Interconnect), PCI Express In order to develop products that have many I / O (input / output ports) and buses compliant with various standards such as SoC with low cost, relatively high performance, and a short development period Such a SoC product must be adopted, or a system configuration with a particularly high-speed CPU and a peripheral chip set dedicated to the CPU as a core must be employed. In that case, the reset sequence of the CPU and the dedicated chip set is often specified, or the CPU and the memory controller are often built in as the SoC. There is no degree of freedom to apply, and it is necessary to consider means for realizing high-speed startup while utilizing SoC and Chip Set procured externally.

  The present invention has been made in view of the above-described problems, and has as its first object to achieve high-speed startup and high-speed execution with limited resources. A second object of the present invention is to provide a system capable of high-speed start-up and high-speed execution even in a system in which a peripheral circuit and CPU are integrated in recent years or a system in which a specific chip set must be used. To do.

  One embodiment of the present invention is a data transfer device for realizing low-cost and high-speed operation. For high-speed operation, all or firmware (program body) of electronic equipment equipped with the data transfer device is provided. In addition to control means (CPU) that executes a part of the program on the RAM, a volatile memory (a part of the nonvolatile memory (ROM, etc.) in which the firmware is stored is connected to the system). RAM) having a program transfer means that can be transferred to a part of the area, and by setting the transfer source ROM address, the transfer source program capacity, and the start address of the transfer destination RAM in the program transfer means, the ROM During the program transfer operation from the RAM to the RAM, the ROM access from the CPU and the RAM access are permitted or arbitrated. When the transfer from the CPU to the access area of the RAM of the transfer destination is not completed, the CPU is waited for, that is, waiting for the completion of the transfer, so that the fast start-up with limited resources, Achieve fast execution. Means employed for this purpose are as follows.

(1) The program stored in the second storage means (4) is transferred to the first storage means (3), and the program stored in the first storage means (3) is transferred to the control means (1). A data transfer method to execute,
Program transfer step (102) for transferring the program in the second storage means (4) to the first storage means (3) while the control means (1) is reading the program from the second storage means (4). )
A first arbitration step (103) for deferring a read / write step from the control means (1) to the first storage means (3) ;
A second arbitration step (104) for arbitrating reading of the second storage means (4) by the program transfer step (102);
The second storage means stores a boot program and other programs in a plurality of sections, and the program transfer step transfers a plurality of sections to the first storage means in the same order as the control means executes the programs. Program transfer steps,
The control means starts the execution of the boot program in the second storage means using the second arbitration step (104), and the first storage means in each section of the other program by the plurality of program transfer steps (102) When the transfer of the boot program is finished, each section of the other program is read from the first storage means and executed after the transfer from the second storage means to the first storage means, If the transfer from the second storage means to the first storage means has not ended, execute after waiting for the end using the first arbitration step,
A data transfer method characterized by the above.

  In addition, in order to facilitate understanding, symbols in parentheses are added for reference to the correspondence of the embodiment shown in the drawings or the corresponding elements or the corresponding or equivalent matters for reference. The same applies to the following.

  According to (1) above, simultaneous access to the second storage means (4) is possible. For example, the RAM access from the CPU (1) can be executed during the program transfer operation to the RAM (3).

  By transferring the program transfer destination from the start address by the program transfer amount, it becomes easy to manage the addresses where the program transfer has been completed, and even if the transfer of all programs is not completed, If the transfer is completed, the program on the RAM (3) of that part can be executed. If the address accessed by the CPU (1) is not completed, the program is suspended until the transfer is completed. That is, it is possible to make the CPU (1) wait. For example, when the RAM (3) access from the CPU (1) can be executed even during the program transfer operation to the RAM (3), the CPU (1) before the transfer of the program to the area to transfer the program in advance is completed. ), The RAM (3) access from the CPU (1) can be suspended until the moment when the program transfer is completed.

  If the ROM (4) cannot be accessed from the CPU (1) during the program transfer from the ROM (4) to the RAM (3), the CPU (1) performs code fetch (reading of the instruction code) until the transfer is completed. It is not possible to perform initialization processing such as initialization of ASIC (2). However, according to this embodiment, by providing the second arbitration means (104) in the preceding stage of the ROM (4), the ROM (4) can be accessed by the CPU (1) even during the program transfer operation, and high-speed startup can be performed. . The boot process program can be executed.

Second storage means of a plurality of regions at a time (4) -> completion of the transfer operation in each divided area during the transfer operation to the first memory means (3), the control means according to incomplete (1), Wait, or permission, it is possible to judgment. In the case of this configuration, it is not possible to determine whether or not the transfer is completed for the area where the program transfer operation is not currently performed, but the transfer is performed from the second storage means (4) to the first storage means (3). Since the order in which the programs are executed is the order in which the program in the first storage means (3) is executed (RAM execution), there should be no access to an area where the program is not transferred in the first place, and this is not a problem.

( 2 ) The program stored in the second storage means (4) is transferred to the first storage means (3), and the control means (1) transfers the program stored in the first storage means (3). A data transfer device to execute,
A boot program stored in the second storage means and other programs in a plurality of sections;
While the control means (1) is reading the boot program from the second storage means (4), the other program in the second storage means (4) is transferred to the first storage means (3). Program transfer means (102);
A first arbitration means (103) for holding a-out first read and write to the storage means (3) from said control means (1),
Second arbitration means (104) for arbitrating reading of the second storage means (4) by the program transfer means (102);
With
The program transfer means (102) includes a plurality of program transfer means for transferring each section of the other program to the first storage means in the same order as the order in which the control means executes the program,
The control means starts execution of the boot program in the second storage means using the second arbitration means (104), and transfers the other program sections to the first storage means by the plurality of program transfer means. When the execution of the boot program is finished, each section of the other program is read from the first storage means and executed when the transfer from the second storage means to the first storage means is finished, and the second storage If the transfer from the means to the first storage means is not completed, execute after waiting for the end using the first arbitration means,
A data transfer method characterized by the above.

( 3 ) The program transfer means (102) uses the transfer source start address of the second storage means (4) and the transfer destination start address to the first storage means (3) as input information, and programs the transfer source start address. was transferred to the transfer destination start address, and ends the transfer by the transfer completion signal from the first arbitration means (103), the data transfer apparatus according to (2), characterized in that.

  The transfer destination start address, the transfer source start address, and the amount of program to be transferred are items that must be managed, but if the same is managed by both the program transfer means (102) and the first arbitration means (103) This may cause problems, increase the degree of congestion of the wiring, increase the circuit scale, increase the power consumption, and increase the cost. According to this embodiment, it is possible to minimize the transfer destination start address, the transfer source start address, and the location for managing the amount of program to be transferred, and to develop a product with low power consumption and low cost. Become.

( 4 ) The data transfer according to ( 2) above, wherein the second arbitration means (104) arbitrates reading / writing from the control means (1) and reading from the program transfer means (102) apparatus.

  By providing the second arbitration means (104) before the second storage means (4), the CPU (1) accesses the storage means (4) and the storage means (4) from the program transfer means (102). Simultaneous access to is possible. For example, when a program executed by accessing the RAM (3) and a boot program executed by the CPU (1) are stored in the same storage means (4), the storage means (4 ) And simultaneous access to the storage means (4) from the program transfer means (102).

(12) The first arbitration means (103) is a final transfer address based on a program amount that the control means (1) transfers from the transfer completion address supplied from the program transfer means (102) to the transfer destination start address. The data transfer device according to ( 2) above, wherein when the read / write is attempted within the range, the read / write of the control means (1) is suspended.

  An address comparison circuit is provided in the first arbitration means (103), and the CPU (1) is compared with the address on the RAM (3) where the transfer of the program has been completed at this time. When the address requested by 1) is not the address at which the program transfer has been completed, the CPU (1) can wait for access. That is, when the CPU (1) accesses the address on the RAM (3) where the transfer of the program to be executed has not been completed, only the CPU access can be made to wait.

( 6 ) The first arbitration means (103) compares the transfer end address with the transfer end address, and when the transfer end address is the same as the transfer end address or exceeds the transfer end address, The data transfer apparatus according to ( 2), wherein a transfer completion signal is generated.

  Data transfer to the DRAM requires data transfer with a fixed burst length, but since the program transfer means (102) does not manage the burst length of the DRAM, the data transfer to the far end can be transferred to any extent. Can't judge whether to stop. According to the present embodiment, the first arbitration means (103) compares the transfer completion address that has just been transferred with the transfer end address obtained from the transfer amount of the program to be transferred, and is equal to or exceeded Thus, data transfer can be stopped at a timing when the burst length of the DRAM is just right.

( 7) An electronic device comprising the data transfer device according to any one of (2) to (6) above . In all electronic devices equipped with the CPU (1), RAM (3), and ROM (4), the effects described in ( 2) to (6 ) can be expected.

( 8 ) External data reading means (6, 8) for reading the program of the external storage medium is provided, and the program transfer means (102) transfers the program of the external storage medium to the first storage medium (3). 7 ) Electronic equipment described in the above.

( 9 ) Image forming means (18); communication means (14) communicating with the outside; and the data transfer apparatus according to any one of ( 2) to (6 ) above, wherein the data transfer apparatus 2 Based on the program of the first storage means (3) transferred from the storage means (4) to the first storage means (3), the communication means (14) is controlled to receive print information and the image forming means An image forming apparatus comprising: a system controller (10) for controlling and printing (18).

( 10 ) An image reading means (17); an image forming means (18); and the data transfer device according to any one of ( 2) to (6 ), wherein the data transfer device is a second storage means. Based on the program of the first storage means (3) transferred from (4) to the first storage means (3), the image reading means (17) is controlled to read the read image. An image forming apparatus comprising: a system controller (10) for controlling and printing.

( 11 ) An image reading means (17); an image forming means (18); a communication means (14) communicating with the outside; and the data transfer device according to any one of ( 2) to (6 ) above. Based on the program of the first storage means (3) transferred by the data transfer device from the second storage means (4) to the first storage means (3), the image reading means (17) is controlled and read. A system controller (10) for controlling the image forming means (18) to print, and controlling the communication means (14) to receive print information and controlling the image forming means (18) for printing. An image forming apparatus.

( 12 ) External data reading means (6, 8) for reading the program of the external storage medium is provided, and the program transfer means (102) transfers the program of the external storage medium to the first storage medium (3). 9) The image forming apparatus according to any one of (11 ).

  Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

FIG. 1 shows a data transfer apparatus according to a first embodiment of the present invention. The data transfer apparatus is to form part of the system controller 10 shown in FIG. 10. The other part of the system controller 10, that is, the part other than the data transfer device (for example, the document information processing / transfer part in the ASIC 2) is not shown in FIG.

  This data transfer apparatus does not use a general-purpose chip set, but uses an ASIC 101 having a built-in CPU 1 or an ASIC 2 to which the CPU 1 is externally attached. In this embodiment, the RAM 3 in FIG. 1 is the first storage means, the ROM 4 is the second storage means, the RAM arbitration 103 is the first arbitration means, the ROM arbitration 104 is the second arbitration means, and the CPU 1 is the control means. It corresponds. Although the memory controller 105 and the ROM controller 106 are illustrated, the memory controller 105 and the ROM controller 106 are not necessarily required.

Programs required for the system such as a boot program, OS, device driver, and various applications are usually stored in a nonvolatile storage device such as a ROM 4. However, it is not necessary that all of the programs are stored in the ROM4, boot program portion and, only the portion of the program you want to run at CPU1 before completing the transfer of the program from the ROM4 into RAM 3 R O M4 The OS, device driver, various applications, and the like may be stored in an external storage medium such as the USB memory 12, the SD card 13 (FIG. 10), or a CD-ROM.

  For ease of explanation, it is assumed that all programs below are stored in the ROM 4, and the boot program portion (initialization of various ASICs, etc.) is transferred to the RAM 3 and then executed on the RAM 3. To explain. A ROM arbitration 104 that arbitrates a boot program read request from the CPU 1 and a program read request other than the boot program from the program copy 102 is prepared in the preceding stage of the ROM controller 106. For ease of explanation, the ROM access is limited to read access for both the CPU 1 and the program copy 102 as program transfer means. However, as ROM arbitration 104, write access arbitration is naturally possible. Normally, the CPU 1 jumps to the boot vector after reset release, and the boot vector points to the address of the ROM 4 where the boot program is stored.

  Therefore, when the ROM arbitration 104 receives a boot program read request from the CPU 1 and reads the boot program from the ROM 4 and transfers it to the CPU 1, the ROM arbitration 104 receives a program read request for the RAM execution part to be transferred onto the RAM by the program copy 102. The program requested by the program copy 102 has a function of transferring the program to the program copy 102 at the same time.

  The term “simultaneous” here means that the requested data on the ROM 4 is transferred while arbitrating when read access from both the CPU 1 and the program copy 102 occurs at time 0, not at time 0. It is.

  The arbitration here means that when an access request from the CPU 1 and the program copy 102 occur simultaneously, one of the accesses is performed, and the other waits until the access is completed. The access of the one that has been in the waiting state is performed.

  Normally, the CPU 1 has a CPU bus, and is connected to peripheral devices via the CPU bus. In FIG. 1, considering the case where the CPU 1 is externally attached, the CPU bus is conscious of the multiplex type in which the address and data are transferred by time division multiplexing. However, in the SoC or the like incorporating the CPU 1, the address bus and the data bus are It is common that it is divided. For ease of explanation, the CPU bus and other buses are assumed to be a multiplex type, but are not necessarily a multiplex type.

  A program copy 102 is prepared between the ROM arbitration 104 and the RAM arbitration 103. The program copy 102 includes a transfer source address indicating an address on the ROM 4 where a program to be transferred to the RAM 3 supplied from the outside is stored after the reset is released (at the same time as the execution of the boot program of the CPU 1), and the transfer Based on the transfer destination address information indicating the address on the RAM 3 where the program to be stored is to be stored, a read request with the transfer source address as the start address is generated to the ROM arbitration 104. When the data of the requested transfer source address is transferred from the ROM arbitration 104, data transfer of the program to be transferred is performed to the RAM arbitration 103 using the transfer destination address as the start address.

  For ease of explanation, when data is received from the ROM arbitration 104, a write request to the RAM arbitration 103 is immediately made. Normally, however, the memory controller 105 performs burst access to the memory 3 in order to improve performance. Therefore, a write request to the RAM arbitration 103 is made after data for the burst transfer size can be secured. Further, the program copy 102 is transferred to the RAM arbitration 103 on the RAM 3 that has completed the transfer to the copy completion determination 103c, which is a transfer completion determination means, in the RAM arbitration 103 at the time when the write data transfer at that time is completed. The transfer completion address indicating the address is passed.

  The transfer completion address indicates an address on the RAM 3, and is calculated by increasing the transfer destination address by the amount of transferred data. This calculation process is performed in the program copy 102. The program copy 102 is unaware of the capacity (size) of the program that is actually transferred. The operation of reading the program to be transferred from the transfer source address and transferring it to the transfer destination address is indicated by the transfer completion signal from the copy completion determination 103c as the transfer completion determination means of the RAM arbitration 103 being Active (significant level; transfer completion). Repeat until the indicated level is reached.

  When the transfer completion signal from the transfer completion determination unit of the RAM arbitration 103 becomes Active, the program copy 102 immediately stops the read request to the ROM arbitration 104, remains in the program copy 102, and is still in the RAM arbitration 103. The data (program) of the portion not transferred to is not transferred. However, if data transfer is being performed to the RAM arbitration 103 at the moment when the transfer completion signal is active, data transfer is performed until the data transfer is completed.

  Normally, the data transfer to the RAM arbitration 103 is a burst transfer. For example, when a 16-byte transfer of a 64-byte burst transfer is completed, if the transfer completion signal becomes active, the data transfer is stopped at that moment. Since the arbitration circuit 103b and the memory controller 105 both hang up in a state waiting for the subsequent data transfer, if a 64-byte burst transfer request is issued, for example, the transfer completion signal is active. However, the data transfer is performed until the 64-byte burst transfer is completed, and the next data transfer is not performed when the data transfer is completed. This also applies to access to ROM arbitration 104. In other words, if further data transfer from the ROM is required to complete the 64-byte data transfer, a new ROM read request is sent to the ROM arbitration 104 even if the transfer completion signal is active. May be issued.

  A RAM arbitration 103 is prepared before the memory controller 105. The main function of the RAM arbitration 103 is the RAM access from the CPU 1, the DMA (Direct Memory) from the RAM initialization circuit that zero-fills (writes zero data; clears) a specific address of the RAM 3 or fills arbitrary data. Access) request and DMA access request from USB, Ethernet (registered trademark) or PCI. The above-mentioned types of DMA requests are merely examples, and this is not all and does not have to be included. This means that access from the CPU 1 and access from other circuits are arbitrated.

  In the present invention, in addition to the above functions, arbitration of a memory write request from the program copy 102 is added to the RAM arbitration 103, and an address comparison 103a serving as an address comparison unit is provided in the preceding stage of the RAM arbitration 103. In the address comparison 103a, an address comparison is prepared for each resource that requires RAM access. However, address comparison is not necessary for the request from the program copy 102.

  In the address comparison 103a, the address at the time of RAM access from the CPU 1 and other various DMACs does not fall between the current transfer completion address and the transfer final address (the program final storage address that can be determined as the completion of the program transfer). If the access is to an address outside the range, an access request is given to the RAM arbitration 103. However, if the address that the CPU 1 or various DMACs are trying to access is between the current transfer completion address and the transfer final address, the access from that resource is not made to the RAM arbitration 103, and the access from that resource is not made. Let Wait.

  However, since the transfer completion address changes every moment and increases, a request is issued to the RAM arbitration 103 when the transfer completion address exceeds the address requested by the resource. By preparing this address comparison circuit for CPU1 + the number of DMACs, even if the RAM access request from any one resource is in the Wait state, the access from another resource is the transfer completion address. If it is not between the transfer address and the final transfer address, the RAM access is permitted, and the state where the RAM access of all resources is set to Wait can be prevented.

  When the transfer completion signal of the copy completion determination 103c, which is the transfer completion determination means, becomes active, the address comparison 103a cancels the Wait of the RAM access request currently set to Wait, and the RAM access from each resource generated thereafter When a request occurs, the requested address is not compared.

  Next, the copy completion determination 103c calculates a transfer end address from the transfer destination address and the transferred program amount, and notifies the address comparison 103a of the transfer end address. The transfer end address calculated here is always compared with the current transfer end address, and when the transfer end address> = transfer end address, the transfer end signal is asserted and notified to the program copy 102 and the address comparison 103a. To do. The operation of the program copy 102 when the transfer completion signal becomes Active is as described above.

  FIG. 2 shows a configuration when the SoC 101 in FIG. 1 is a 1-chip SoC. The details of the functions and connections of the RAM arbitration 103, program copy 102, and ROM arbitration 104 are the same as those in FIG. A program copy 102, a first arbitration 103, a memory controller 105, a second arbitration 104, and a ROM controller 106 are incorporated in the SoC 101 incorporating the CPU 1, and SDRAM, DDR SDRAM, DDR2 SDRAM are externally provided as first storage means. A RAM 4 such as a DRAM and a ROM 4 such as a flash ROM are connected as second storage means. The bus connecting the ROM 4 and the ROM controller 106 may be a local bus specific to the chip, PCI, USB, or the chip for the bus may be connected in front of the ROM 4.

  FIG. 3 shows a configuration when the present invention is applied to the CPU 1 + peripheral circuit built-in SoC (ASIC) 107. Since the function of each means in the detailed part of the configuration is basically the same as that shown in FIG. 1, the configuration of the different part will be described. In this case, a system that employs a SoC 107 equipped with a commercially available CPU 1 + memory controller 105 + ROM controller 106 is assumed. SoC 2 which is an ASIC or FPGA (Field Programmable Gate Array) with built-in program copy 102, ROM arbitration 104, RAM arbitration 103, memory controller 105, ROM controller 106 is arranged outside, and compared with a normal system, The external RAM 3 (DRAM) and the external ROM 4 are arranged so as to enter.

  When the CPU 1 in the commercially available SoC 107 accesses the RAM 3, the memory controller 105 accesses the RAM 3 according to the protocol and timing for accessing the RAM 3. Therefore, the RAM arbitration 103 needs to behave like the RAM 3. This is different from the second embodiment of FIG. Although it may seem useless when viewed as a system, a memory controller 105 is provided after the RAM arbitration 103 of the external ASIC 2 in order to enable access to the RAM 3 (DRAM) from the external ASIC or FPGA 2. Is prepared.

  When the RAM 3 is an SDRAM, CAS latency (Column Address Strobe Latency) is determined for SDRAM access, and it is necessary to prepare data by the determined timing. Therefore, the CAS latency of the memory controller 108 on the commercial SoC 107 side is set larger than the CAS latency set in the memory controller 105 of the external ASIC or FPGA 2, and the read data from the SDRAM via the external ASIC or FPGA 2 is Use CAS Latency in time. For example, CAS Latency = 2.5 between SoC107 <-> ASIC2 and CAS Latency = 2 between ASIC2 <-> SDRAM3.

  In the case of the external ASIC or FPGA 2, various DMAC accesses are also made via the memory controller 108 in the SoC 107, so that the RAM arbitration 103 is configured to perform access from the SoC 107 and arbitration of the program copy 102. When the CPU 1 on the commercially available SoC 107 accesses the ROM 4 according to the protocol and timing for the ROM 4, the ROM arbitration 104 needs to behave as if it is the ROM 4 in the second embodiment of FIG. Is different.

  Although it may seem useless when viewed as a system, a ROM controller 106 is provided after the ROM arbitration 104 of the external ASIC 2 to enable access to the ROM 4 from the external ASIC or FPGA 2. Has been. Since the timing for ROM access is also determined, and ASIC or FPGA 2 is inserted between the accesses from CPU 1, the timing of SoC 107 <-> ASIC or FPGA 2 is the timing of ASIC or FPGA 2 <-> ROM 4. It is necessary to set the access timing later than that.

  By setting the timing relationship between RAM access and ROM access as described above, ROM4 and RAM3 can be correctly accessed even if ASIC or FPGA 2 is mediated between SoC107 <-> RAM3 and SoC107 <-> ROM4. In addition, a system capable of high-speed startup and high-speed execution can be achieved. When the RAM 3 is an SDRAM (including DDR and DDR2), it is necessary to set the operation mode before executing memory write / read to the RAM 3.

  Since the external ASIC 2 performs a program transfer operation from the ROM 4 to the RAM 3 before the CPU 1 completes booting, the operation mode setting (mode register setting) to the SDRAM (RAM 3) Performed after reset release by ASIC or FPGA 2. After the CPU 1 boots, the CPU 1 executes mode register setting from the memory controller 108 in the SoC 107, but the mode register setting is ignored by the RAM arbitration 103. The reason why the CPU 1 intentionally executes the mode register setting in the memory controller 108 in the SoC 107 is that the mode register setting must be performed before the first access to the DRAM (RAM 3), and the memory controller 108 executes the mode register setting. This is because it is common for the read / write operation to be performed only afterwards. The reason why the mode register setting command issued by the memory controller 108 of the SoC 107 has to be ignored by the external ASIC or FPGA 2 is that the SDRAM (RAM 3) causes the memory element itself to be changed by issuing the mode register setting command. This is to avoid erasing the program transferred from the ROM 4 to the RAM 3 in the program copy 102 before the SDRAM to be cleared.

  FIG. 4 shows that a BIOS (Basic Input / Output System) is mounted on the external CPU 1 and two dedicated chip sets 110 and 111 (the memory controller 108 and the ROM controller 109 are mounted separately). 1 shows an embodiment of the present invention for a simple system. As the difference in configuration, the difference between the fact that the BIOS is mounted and the BIOS is mounted will be described.

  Since the BIOS and the boot code are not necessarily separated if they are ordinary electronic devices, the BIOS part is included in the boot code and mounted in the same ROM 4, but in the case of a system using a specific CPU, Since the detailed specification of the CPU and the detailed specification of the peripheral chip set are not disclosed, the BIOS part for performing the initial setting of the chip set and the CPU may not be developed in-house. In such a case, a general method is to construct a high-performance system by entrusting a BIOS development company to a company that specializes in BIOS development.

  However, the device in which the BIOS is stored is often a device with a low access speed such as an LPC (Low Pin Count) I / F (Inter Face) and the boot code is executed after the BIOS is executed. Tends to be slower. The Chip Set 111 described as SB (South Bridge) is equipped with a ROM controller 109. However, the ROM controller 109 is merely used as a ROM controller for ease of explanation, and is not necessarily a ROM controller. For example, a general-purpose bus such as a PCI bus may be used. Since it is possible to put Wait in the bus protocol in the case of a PCI bus, the ROM arbitration 104 may behave as a PCI device, not as a ROM. Other configurations are the same as those of the third embodiment shown in FIG.

  Next, details of the operation of the embodiment will be described. In order to simplify the description, the description will be made on the premise of the configuration of the first embodiment of FIG. If there are different parts depending on the configuration, they will be described additionally.

  FIG. 5 shows an outline of the operation of the program copy 102, and FIG. 6 shows an outline of the operation of the RAM arbitration 103. In the following description, steps S1 to S7 are those on FIG. 5, and steps S11 to S20 are those on FIG. First, when the reset is released (S1), the program copy 102 generates a read request for the program to be transferred to the RAM 3 to the ROM arbitration 104 based on the transfer destination address and the transfer source address information (S2). The transfer destination address and the transfer source address information will be described on the premise that they are acquired by an external Pin during the reset period. First, store these information at specific addresses on the ROM 4, The operation of acquiring the information may be performed.

  Simultaneously with the reset release, the copy completion determination 103c sets the transfer completion signal to an inactive state (unintentional state; a level not indicating transfer completion), calculates transfer final address information from the transfer destination address and the transferred program amount, and transfers The final address and transfer completion signal are transmitted to the address comparison 103a, and the transfer completion signal is transmitted to the program copy 102. In parallel, the CPU 1 jumps to the reset vector and issues a boot code read request to the ROM arbitration 104 (S11).

  In FIG. 1, it is assumed that the reset vector of the CPU 1 is designed to be on the ROM 4, but when the BIOS part is not a ROM but another Device (another ROM) as shown in FIG. , Access to a device such as a ROM on which a BIOS is mounted is the first. In this case, after the code execution of the BIOS portion is finished, the CPU 1 issues a read request to the ROM arbitration 104 for executing the program on the ROM 4. At this time, a read request from the CPU 1 and a read request from the program copy 102 are generated at the same time, but which access should be given priority depends on the implementation, and no arbitration policy is mentioned. . However, the ROM arbitration 104 sets the arbitration policy so that ROM access from the CPU 1 and ROM access from the program copy 102 are permitted in the same way, thereby executing boot code execution in the program ROM-> RAM. Maximizes the efficiency of parallel execution of transfers.

  The memory controller 105 issues a mode register setting command to the SDRAM 4 (S12). Actually, a precharge command and a refresh command are also necessary, but since they are not the gist of the present invention, description thereof will be omitted. It is assumed that the precharge command and the refresh command requested by each DRAM are also issued before setting the mode register. In this description, the mode register setting is performed by the memory controller 105. However, a method in which the RAM arbitration 103 triggers is issued to the memory controller 105, and the memory controller 105 performs mode register setting in response to the command. But it ’s okay.

  Next, the program copy 102 repeats the read request to the ROM arbitration 104 until data of a size that can be transferred to the memory controller 105 is prepared (S2, S3). During this time as well, the CPU 1 is executing the boot program on the BIOS or ROM. Then, the program copy 102 issues a memory write request to the RAM control means when data of a size that can be transferred to the memory controller 105 is prepared (S4). Normally, burst transfer is used to make use of the performance of DRAM. Therefore, data read from ROM 4 is read a plurality of times as described above, and then data transfer to RAM arbitration 103 is performed. Can be read in large quantities at a time or when burst access to the RAM arbitration 103 is not performed, data can be transferred to the RAM arbitration 103 when data is read from the ROM 4, or all data is completely read from the ROM 4 If it is determined, data transfer to the RAM arbitration 103 may be started before all the data is read. When the data transfer to the RAM arbitration 103 is completed, the program copy 102 updates the transfer completion address. The program copy 102 repeats the above operation until the transfer completion signal becomes active (S2 to S5).

  Next, the RAM arbitration 103 constantly monitors whether or not a RAM access request is generated. When a memory access request from the CPU 1, each DMAC or the program copy 102 is generated, it is determined which resource the access request is from. However, the subsequent processing differs depending on the determination result. When the memory access request source is either the CPU 1 or each DMAC, it is determined whether or not the address requested by the access request can be permitted by the address comparison 103a in the RAM arbitration 103 (S13 to S16).

  If the requested address is within the range for storing the transfer result of the program and the program has not been transferred yet, the access from the resource is made to wait (S16). It is premised that a flow control method is adopted in which an authorization response is not made when there is an access request from each resource, so that data transfer from the request source resource can be made to wait. By preparing this address comparison for the number of CPUs 1 and each DMAC, the memory access from other resources can be performed even if any resource is in the Wait state.

  In the wait state, the address comparison 103a always compares the transfer completion address updated appropriately with the address indicated by the access request (S15), and when the address indicated by the access request <= transfer completion address. Then, a memory access request is issued to the subsequent arbitration circuit 103b as an access permission state. If the access request is the program copy 102, the memory access request to the arbitration circuit 103b is issued immediately without going through the address comparison 103a (S17). When the memory access is completed, the transfer completion address is compared with the transfer end address, and when the transfer completion address> = transfer end address, the transfer completion signal is set to Active (S19, S20). Otherwise, it waits for the next access request (S13). In the arbitration circuit 103b in the RAM arbitration 103, access requests from the CPU 1, each DMAC, and the program copy 102 may be generated at the same time. However, the arbitration circuit 103b arbitrates appropriately and accesses from all resources without delay. The mediation rules that can be used are set.

  Thus, even during the program transfer operation, memory access by the CPU 1 or various DMACs is possible, so that time-consuming processing such as initialization of the RAM 3 and inspection of the RAM 3 is performed before the program moves to RAM execution. It can be executed at the timing.

  When the above operation is repeated and the transfer signal becomes Active, the program copy 102 performs all operations when the data transfer is completed, regardless of whether a ROM read request is issued or a memory write request is issued. Stop (S7). This is shown in FIGS. 7A and 7B. When the transfer completion signal becomes active, the address comparison 103a does not perform any address comparison at the time of memory access from the CPU 1 and various DMACs generated thereafter.

  Even during the operation as described above, the CPU 1 is executing the BIOS or the boot code, and after the execution of the boot code is completed, it is possible to shift to RAM execution. In the case of the prior art, in order to move to the RAM execution, it is impossible only after all the programs are expanded on the RAM. However, in the present invention, the execution of the boot code in the ROM execution part is even finished. Thus, if even one part of the RAM execution part of the program has been transferred, the RAM can be executed. As a result, it is possible to realize a system that can be started at high speed without the need for troublesome adjustment setting (Tuning) at the boundary between ROM execution and RAM execution in order to exhibit maximum performance characteristics (Performance). 3 and 4, when the memory controller 8 and the ROM controller 109 are mounted on the commercially available SoC 107 and the dedicated chip sets 110 and 111, the memory controller 105 is connected to the DRAM 4 before starting the RAM execution. The mode register setting command is executed. The RAM arbitration 103 does not issue the mode register setting command to the DRAM 4, but discards the command, thereby preventing the mode register setting command from being repeatedly issued to the DRAM 4 at the time of activation.

  Next, the CPU operation, the program transfer operation, and the timing for switching to RAM execution after reset release are shown in FIGS. 7 (c), (d) and (e).

  (C) shows the timing of switching to RAM execution when the execution of the boot code (sometimes referred to as BIOS) ends earlier than the transfer from the ROM 4 to the RAM 3 and the CPU 1 is kept waiting by the address comparison 103a. . In this case, since the timing when the CPU 1 tries to execute the RAM is early, it is better to add a CPU process based on the boot code of the ROM 4.

  (D) shows the switching timing to RAM execution when the program transfer from the ROM 4 to the RAM 3 is completed earlier than the execution of the boot code. In this case, it is possible to start up at a higher speed by reducing the number of ROM execution portions and moving to RAM execution a little earlier.

  (E) is a case where RAM execution after boot code execution and program transfer from the ROM 4 to the RAM 3 overlap. Even if the transfer time of the enlarged program to the RAM 3 becomes long, it is possible to switch to RAM execution at an early timing, and since the portion transferred to the RAM 3 is sequentially executed in RAM, high-speed startup and high-speed execution are possible. It becomes possible.

  Next, the access timing when the memory controller 108 and the ROM controller 109 are mounted on the commercially available SoC 107 and the dedicated chip sets 110 and 111 as shown in FIGS. 3 and 4 will be described. If the memory controller 108 and the ROM controller 109 are general-purpose buses (for example, PCI, PCI Express, USB, etc.) and Wait can be inserted (transfer control = Flow control is possible), the access timing need not be considered. In the case of using general SDRAM, DDR SDRAM, DDR2 SDRAM, NOR Flash ROM, etc., the access timing is determined, and an external ASIC or FPGA 2 is provided between the memory controller 108, ROM controller 109 and SDRAM 3, ROM 4. Due to the timing shift caused by the occurrence of the error, correct RAM and ROM access cannot be performed.

  Therefore, in the present invention, in the case of DRAM 4 such as SDRAM, CAS Latency between commercially available SoC 107 or dedicated Chip Set 110, 111 and external ASIC or FPGA 2 is greater than CAS latency between external ASIC or FPGA 2 and SDRAM 4. Always make it bigger. By doing so, when viewed from the commercially available SoC 107 or the dedicated chips 110 and 111, the external ASIC or the FPGA 2 can be handled as an SDRAM 4 having a larger CAS latency.

  The same concept applies to the ROM controller 109. Usually, in the case of ROM devices such as Nor Flash ROM, Access Speed is determined. Therefore, the access speed between the external ASIC or FPGA 2 from the commercially available SoC 107 or the dedicated chip set 110, 111 is about 1 cycle slower than the Access Speed of the device, and the access speed of the device is between the external ASIC or FPGA 2 and the ROM 4. By setting to Speed, the external ASIC or FPGA 2 can be handled as a slightly slower ROM 4 from the commercially available SoC 107 or the dedicated chip sets 110 and 111.

  Next, a case where the program on the ROM 4 is divided into a plurality of areas and transferred in order on the RAM 3 will be described. An example of program division is shown in FIG. In the case of FIG. 8, the boot code is stored at the youngest address, and this part is an example on the premise of ROM execution. In the case of a general program, it is started while processing various subroutines in the middle of execution. Therefore, a program to be executed is not necessarily stored in ascending order of the addresses of the ROM 4. Therefore, the program on the ROM 4 is divided into a plurality of areas, and the program is transferred onto the RAM 3 in the same order as the order in which the programs are executed. Transfer order 1-> 2-> 3-> 4-> 5. FIG. 8 is an example, and which space in the ROM space is what number may be freely set.

  FIG. 9 shows a functional configuration for realizing this mechanism. The major difference from FIG. 1 is that the program amount data to be transferred is not connected to the RAM arbitration 103 but is connected to the program copy 102, the transfer destination addresses 0 to n, the transfer source addresses 0 to n, and the transfer program The amount 0 to n is the point supplied to the program copy 102. Program transfer amount 0. . The reason why n (0 to n) is supplied to the program copy 102 is to efficiently switch a plurality of transfer areas. One set consists of the transfer destination address 0, the transfer source address 0, and the transfer program amount 0. If the program areas to be transferred are divided so that the areas of the respective programs have the same size, only one program amount to be transferred needs to be supplied, and n is not required. In that case, the program amount to be transferred directly from the outside may be designated. The order selection means in the program copy 102 supplies the RAM arbitration 103 with the subscripts in ascending order from 0 to n transfer destination addresses, transfer source addresses, and the transferred program amount.

  By doing this, it is possible to determine whether the CPU Wait or the access is permitted when the transfer operation is completed or not completed in each divided area during the transfer operation to the ROM 4-> RAM 3 for each of the plurality of areas. In the case of this configuration, it is not possible to determine whether or not the transfer has been completed for the area where the program transfer operation is not currently performed, but since the order of transfer from the ROM to the RAM itself is the order in which the RAM is executed, the program is originally Access to an area that is not being transferred should not occur and is not a problem.

  As described above, in the description of the embodiment of the present invention, the program that the CPU 1 transfers to the RAM 3 for executing the program stored in the RAM 3 and the boot program of the CPU 1 are stored in the same storage means (ROM 4). Although the description is based on the premise, both may be stored in separate third storage means. In that case, the ROM arbitration 104 is not necessary, and the program copy 102 transfers the program stored in the third storage means storing the program to be executed on the RAM 3 to the RAM 3.

It is a block diagram which shows the function structure of 1st Example of this invention. It is a block diagram which shows the structure of 2nd Example of this invention. It is a block diagram which shows the structure of 3rd Example of this invention. It is a block diagram which shows the structure of 4th Example of this invention. It is a flowchart which shows the outline | summary of the data transfer operation | movement of the program copy 102 of 1st-5th Example of this invention. It is a flowchart which shows the outline | summary of the arbitration operation | movement of RAM arbitration 103 of the 1st-5th Example of this invention. It is a time chart which shows the CPU operation | movement after reset cancellation | release, the program transfer operation | movement, and the switching timing to RAM execution of 1st-5th Example of this invention. It is a block diagram which shows an example of the division of the program stored in ROM4 shown in FIG. It is a block diagram which shows the function structure of 5th Example of this invention. 1 is a block diagram showing a configuration of an information processing system of a multi-function copying machine MF1 equipped with first to fifth embodiments of the present invention.

MF1: Multifunction copier

Claims (12)

A data transfer method in which a program stored in the second storage means is transferred to the first storage means, and the control means executes the program stored in the first storage means,
A program transfer step of transferring the program in the second storage means to the first storage means while the control means is reading the program from the second storage means;
Providing a first arbitration step for deferring a read / write step from the control means to the first storage means ;
Providing a second arbitration step for arbitrating reading of the second storage means by the program transfer step;
The second storage means stores a boot program and other programs in a plurality of sections, and the program transfer step transfers a plurality of sections to the first storage means in the same order as the control means executes the programs. Program transfer steps,
The control means starts execution of the boot program of the second storage means using the second arbitration step, and starts transfer of each section of the other program to the first storage means by the plurality of program transfer steps. When the execution of the boot program is finished, each section of the other program is read from the first storage means and executed when the transfer from the second storage means to the first storage means is finished, and the second storage means If the transfer to one storage means has not ended, wait for the end using the first arbitration step,
A data transfer method characterized by the above. A data transfer device that transfers a program stored in the second storage means to the first storage means, and the control means executes the program stored in the first storage means,
A boot program stored in the second storage means and other programs in a plurality of sections;
Program transfer means for transferring the other program in the second storage means to the first storage means while the control means is reading the boot program from the second storage means;
A first arbitration means for holding a-out read and write to the first memory means from said control means,
Second arbitration means for arbitrating reading of the second storage means by the program transfer means;
With
The program transfer means includes a plurality of program transfer means for transferring each section of the other program to the first storage means in the same order as the control means executes the program,
The control means starts execution of the boot program of the second storage means using the second arbitration means, and starts transfer of each section of the other program to the first storage means by the plurality of program transfer means. When the execution of the boot program is finished, each section of the other program is read from the first storage means and executed when the transfer from the second storage means to the first storage means is finished, and the second storage means If the transfer to one storage means has not ended, the first arbitration means is used to wait for the end,
A data transfer device. The program transfer means uses the transfer source start address of the second storage means and the transfer destination start address to the first storage means as input information, transfers the program of the transfer source start address to the transfer destination start address, 3. The data transfer apparatus according to claim 2 , wherein the transfer is terminated by a transfer completion signal from the arbitrating means. The data transfer apparatus according to claim 2 , wherein the second arbitration unit arbitrates reading / writing from the control unit and reading from the program transfer unit. When the control means tries to read / write within the range of the transfer destination start address and the transfer end address based on the program amount to be transferred from the transfer completion address supplied from the program transfer means, the control means The data transfer apparatus according to claim 2 , wherein reading and writing of the data is suspended. The first arbitration means generates a program transfer completion signal when the transfer completion address is the same as or exceeds the transfer final address by comparing the transfer final address with the transfer completion address. The data transfer apparatus according to claim 2 , wherein: An electronic device comprising the data transfer device according to claim 2 . The electronic apparatus according to claim 7 , further comprising an external data reading unit that reads a program in an external storage medium, wherein the program transfer unit transfers the program in the external storage medium to a first storage medium. An image forming means; a communication means for communicating with the outside; and the data transfer device according to any one of claims 2 to 6 , wherein the data transfer device transfers the data from the second storage means to the first storage means. An image forming apparatus comprising: a system controller that controls the communication unit to receive print information and controls the image forming unit to print based on a program in a first storage unit. An image reading means; an image forming means; and a first memory comprising the data transfer device according to any one of claims 2 to 6 , wherein the data transfer device transfers the data from the second storage means to the first storage means. An image forming apparatus comprising: a system controller that controls the image reading unit to print the image read by controlling the image reading unit based on a program of the unit. An image reading unit; an image forming unit; a communication unit communicating with the outside; and the data transfer device according to any one of claims 2 to 6 , wherein the data transfer device is changed from the second storage unit to the first storage unit. Based on the program stored in the first storage means, the image reading means is controlled to print the read image, the image forming means is controlled to print, the communication means is controlled to receive print information, and An image forming apparatus comprising: a system controller that controls and prints image forming means. The image forming apparatus according to claim 9 , further comprising an external data reading unit that reads a program in an external storage medium, wherein the program transfer unit transfers the program in the external storage medium to a first storage medium. .

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