JP4912658B2 - Semiconductor memory device and operation method thereof - Google Patents

Description

  The present invention relates to a semiconductor memory device and an operation method thereof. In particular, the present invention relates to a semiconductor memory device that records information by holding charged particles in a charge holding portion and an operation method thereof.

  Conventionally, an EEPROM (Electric Erasable Programmable Read Only Memory) called a flash memory has been widely used as a semiconductor memory device. A flash memory is a memory transistor that includes a charge holding portion called a floating gate surrounded by an insulator on a tunnel insulating film. The flash memory stores information by holding charged particles in the floating gate, and the information is stored by utilizing the fact that the threshold voltage of the transistor varies depending on the number of charged particles stored in the floating gate. It has a structure for reading (see, for example, Patent Document 1).

  Specifically, as shown in FIG. 8, the flash memory includes a P-type semiconductor substrate 106, a tunnel insulating film 101 formed on the P-type semiconductor substrate 106, and a conductive material covered with the tunnel insulating film. Floating gate 102 made of polysilicon, a control gate 107 made of a conductor formed on the floating gate 102, and a source region which is a first N-type diffusion region formed near the surface of the P-type semiconductor substrate 106 103, a drain region 104 which is a second N-type diffusion region, and an element isolation region 105 made of an insulator.

  Information is stored in the flash memory by holding electrons (charged particles) in the floating gate 102. That is, information is written by injecting electrons into the floating gate 102 through the tunnel insulating film 101. On the other hand, information is erased by extracting electrons from the floating gate 102. Information is read using the fact that the threshold voltage varies depending on the number of electrons held in the floating gate 102.

  Next, a method for writing, erasing and reading information in the flash memory will be described in detail.

  For example, information is written by a method called channel hot electron injection. This writing method is explained as follows. For example, by applying + 8V to the control gate 107, + 5V to the drain region 104, and 0V to the source region 103 and the P-type semiconductor substrate 106, hot electrons (hot electrons) are generated in the vicinity of the drain region 104. The hot electrons are injected into the floating gate 102 according to the electric field generated by the positive voltage applied to the control gate 107. In this way, information is written to the flash memory.

  Next, information is erased by utilizing a phenomenon called Fowler-Nordheim tunneling. This erasing method is explained as follows. For example, by applying −8 V to the control gate 107 and +8 V to the source region 103 and the P-type semiconductor substrate 106, a strong electric field is generated in the floating gate 102. Electrons are extracted from the floating gate 102 in accordance with this strong electric field. In this way, information is erased from the flash memory.

  Next, reading of information is performed by operating the flash memory as a transistor. This reading method is described as follows. For example, a voltage of +3 V is applied to the control gate 107, a voltage of +1 V is applied to the drain region 104, a voltage of 0 V is applied to the P-type semiconductor substrate 106, and a voltage of 0 V is applied to the source region 103. In the control circuit, the drain current is compared with the drain current of the reference memory cell as a memory signal, and the magnitude of the current value is detected. Usually, the memory signal has different values depending on the number of electrons held in the floating gate 102. Therefore, information can be read using this.

  However, in the flash memory using the above-described conventional technique, since a conductor such as polysilicon is used as the floating gate 102, it is difficult to reduce the thickness of the tunnel insulating film 101. Therefore, it is difficult to miniaturize the memory. Therefore, when the memory is miniaturized and the surrounding tunnel insulating film 101 is thinned, there is a possibility that leakage occurs in the tunnel insulating film 101. If there is even a slight leak in the tunnel insulating film 101, the charged particles cannot be held in the floating gate 102 for a long time.

In order to solve this problem, a substance containing many trap levels may be used as the charge holding portion. If a substance containing a large amount of trap levels is used as the charge holding portion, electrons injected into the charge holding portion by the write / erase operation are captured at the trap level, so there is a slight leak in the insulating film. However, there is an advantage that electrons are not easily leaked from the charge holding portion and can be held for a long time. Among the semiconductor memory devices using the substance containing many trap levels as the charge holding portion as described above, the semiconductor memory device using the silicon oxide film as the insulating film and the silicon nitride film as the charge holding portion is particularly MONOS. It is called (Metal Oxide Nitride Oxide Semiconductor) type memory.
JP 2003-173690 A (publication date: June 20, 2003)

  However, conventional semiconductor memory devices such as flash memory and MONOS type memory have the following problems.

  Specifically, when a write operation or an erase operation is performed on a conventional semiconductor memory device, a positive or negative voltage is applied to the control gate to inject charged particles such as electrons and holes into the charge holding portion. At this time, since charged particles pass through the semiconductor substrate interface and the insulating film, the interface level at the semiconductor substrate interface and the trap level in the insulating film increase.

  When the interface state at the semiconductor substrate interface increases, the charge mobility of charged particles on the semiconductor substrate surface decreases, and the transistor characteristics deteriorate. Therefore, the amount of current at the time of reading information is reduced as compared with the case where there is no interface state. Moreover, since the leakage current increases as the interface state increases, the memory signal at the time of reading further decreases. For this reason, the difference between the memory signal in the written state and the memory signal in the erased state is smaller than in the state without the interface state, so that it is difficult to distinguish between the written state and the erased state.

  On the other hand, when the trap level in the insulating film increases, when charged particles are injected into the charge holding portion, the charged particles are easily trapped not only in the charge holding portion but also in the insulating film. When charged particles are trapped in both the charge holding part and the insulating film, the memory signal at the time of reading changes as in the case where the charged particles are trapped only in the charge holding part, but trapped in the insulating film. Since charged particles are very unstable, they flow out to the semiconductor substrate in a short time. That is, when the trap level in the insulating film increases, it becomes difficult to hold information for a long time.

  Therefore, in a semiconductor memory device that records information by changing the amount of charged particles in the charge holding unit, such as a flash memory or a MONOS type memory, charged particles are generated in the semiconductor substrate interface and in the insulating film during the write / erase operation. Therefore, if the write / erase operation is performed a plurality of times, it becomes difficult to hold and read information.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor memory device capable of improving information storage characteristics and an operation method thereof.

  In order to solve the above problems, a semiconductor memory device of the present invention includes a channel region formed on a semiconductor substrate, a pair of diffusion layer regions formed so as to sandwich the channel region, and a first region on the channel region. A charge holding portion formed via the insulating film and a gate electrode formed on the charge holding portion via the second insulating film, and the charge holding portion holds charged particles therein. In addition, it is possible to store information according to different distribution states of the charged particles held therein.

  In order to solve the above problems, a semiconductor memory device of the present invention includes a channel region formed on a semiconductor substrate, a pair of diffusion layer regions formed so as to sandwich the channel region, and the channel region. A charge holding portion formed via a first insulating film; and a gate electrode formed on the charge holding portion via a second insulating film, wherein the charge holding portion is an internal charged particle at room temperature. Is formed of an insulator capable of maintaining a distribution state of one of the diffusion layer regions when a voltage is applied to the gate electrode according to the distribution state of the charged particles held in the charge holding portion. It is characterized in that the amount of current that flows to the point changes.

  In the present invention, unless otherwise specified, “charged particle” means a metal ion such as sodium ion, an ion having positive or negative charge (movable ion), a hole or an electron. “Normal temperature” means 25 ° C.

  According to the configuration of the present invention, for example, when a voltage is applied to the gate electrode, the drain current that flows between the diffusion layer regions (for example, the source region and the drain region) in which the source electrode or the drain electrode is electrically connected, respectively. Changes according to the distribution state of the charged particles in the charge holding portion.

  Therefore, in order to record information as in the prior art, it is not necessary to inject or extract charged particles from the charge holding unit. Therefore, it is possible to suppress an increase in the interface state at the semiconductor substrate interface, and the stored information can be read with high accuracy. In addition, since the trap level can be prevented from increasing in the insulating film between the semiconductor substrate and the charge holding portion, the amount of charged particles held in the insulating film can be reduced. Accordingly, it is possible to prevent the deterioration of stored information caused by the charged particles escaping from the insulating film to the semiconductor substrate, and thus the information can be retained for a long time. As a result, it is possible to provide a semiconductor memory device that can improve information storage characteristics.

  Further, since the charge holding unit records information while holding the distribution state of charged particles, it is possible to store binary or higher information. As a result, it is possible to provide a more highly integrated multilevel memory device. Further, the charge holding unit can store continuous information, and a highly integrated analog memory device can be provided.

  In the semiconductor memory device of the present invention, the insulator is preferably a silicon oxide film, a silicon nitride film, or a stacked film in which two or more silicon oxide films and silicon nitride films are stacked.

  According to the above configuration, since a large number of trap levels exist in the silicon oxide film or silicon nitride film, it is difficult to move charged particles in the charge holding portion at room temperature. Accordingly, since the distribution state of charged particles does not substantially change, information can be retained for a long time.

  The semiconductor memory device of the present invention preferably further includes an excitation device that excites charged particles in the charge holding unit.

  According to said structure, since charged particle can be excited, it becomes easy to move a charged particle in a charge holding part. Therefore, it is not necessary to apply a high voltage to generate a high electric field in order to move the charged particles, and the charged particles can be moved in the charge holding portion with a low voltage of about 8 V, for example.

  In the semiconductor memory device of the present invention, the excitation device is preferably a heat generating device or an electromagnetic wave generator.

  According to said structure, the charged particle in a charge holding part can be excited by heating or irradiation of electromagnetic waves. As a result, the charged particles held in a certain trap level of the charge holding unit easily move to another trap level.

  In order to solve the above problems, an operation method of a semiconductor memory device according to the present invention is an operation method of the semiconductor memory device, in which charged particles held in a charge holding portion are excited and applied to a gate electrode. Information is rewritten by applying a voltage to change the distribution state of the charged particles.

  According to the above configuration, when a voltage is applied to the gate electrode in a state where the charged particles held in the charge holding unit are excited, the charged particles easily move from the trap level and are charged in the charge holding unit. Will be localized. When localization of charged particles occurs, for example, when a drain current flows from the source electrode to the drain electrode, the threshold value changes. Therefore, it is possible to read the distribution state of charged particles, that is, the recorded information, from the change in threshold value.

  As described above, since it is not necessary to inject charged particles into the charge holding portion during the writing or erasing operation, that is, the information rewriting operation, the deterioration of the semiconductor substrate interface as in the conventional configuration is suppressed. be able to. Therefore, the information rewriting operation can be endured more times than before. In addition, it is possible to reduce read defects at the time of reading after the information rewriting operation.

  As described above, in the semiconductor memory device of the present invention, the charge holding unit can hold charged particles therein and store information according to different distribution states of the held charged particles. is there.

  In addition, as described above, the semiconductor memory device of the present invention is configured so that when a voltage is applied to the gate electrode according to the distribution state of the charged particles held in the charge holding portion, The amount of current flowing to the diffusion layer region changes.

  Therefore, an increase in the interface state at the semiconductor substrate interface can be suppressed, and stored information can be read with high accuracy. In addition, since the trap level can be prevented from increasing in the insulating film between the semiconductor substrate and the charge holding portion, the amount of charged particles held in the insulating film can be reduced. Therefore, it is possible to prevent the deterioration of stored information due to the charged particles escaping from the insulating film to the semiconductor substrate, and thus the information can be retained for a long time. As a result, it is possible to provide a semiconductor memory device that can improve information storage characteristics.

  In addition, the operation method of the semiconductor memory device of the present invention changes the distribution state of the charged particles by applying a voltage to the gate electrode in a state where the charged particles held in the charge holding portion are excited as described above. This is a method for rewriting information.

  Therefore, it is not necessary to inject charged particles into the charge holding portion during the information rewriting operation, so that deterioration of the semiconductor substrate interface as in the conventional configuration can be suppressed. Therefore, the information rewriting operation can be endured more times than before. In addition, there is an effect that it is possible to reduce read defects at the time of reading after the information rewriting operation.

  An embodiment of the present invention will be described below with reference to FIGS.

  The semiconductor memory device of this embodiment stores information by holding the distribution state of charged particles in the charge holding unit, and can store binary or more information in one charge holding unit It functions as a memory. The configuration will be described in detail below.

  FIG. 1 is a cross-sectional view of the semiconductor memory device in this embodiment. In the semiconductor memory device of this embodiment, as shown in FIG. 1, a first insulating film 10, a charge holding unit 1, and a second insulating film 11 are formed on a P-type well region 5 formed on the surface of a semiconductor substrate. The gate electrode 4 is laminated in this order. The charge holding unit 1 includes a plurality of charged particles 6 whose positions are fixed at room temperature. An excitation device 7 is provided on the gate electrode 4. In the semiconductor substrate, a source region 2 made of an N-type diffusion layer and a drain region 3 made of an N-type diffusion layer are provided so as to face each other with a P-type well region 5 interposed therebetween. FIG. 1 shows the state of the semiconductor memory device immediately after formation, and the distribution state of the charged particles 6 is different from the distribution state in use. “Normal temperature” means 25 ° C.

  The semiconductor substrate is not particularly limited as long as it is generally used for a semiconductor device. For example, substrates composed of elemental semiconductors such as silicon and germanium, substrates composed of compound semiconductors such as gallium arsenide, gallium nitride, gallium phosphide, and indium phosphide, SOI (Silicon on Insulator) substrates, and multilayer SOI substrates Etc. can be used. Note that a substrate electrode is electrically connected to the semiconductor substrate so that a voltage can be applied.

  The semiconductor substrate may have a P-type or N-type conductivity type. Preferably, at least one well region is formed on the surface of the semiconductor substrate, and a memory device is formed on the surface of the well region.

  Further, an element isolation region is preferably formed on the surface of the semiconductor substrate. As a result, current leakage can be prevented. The method for forming the element isolation region is not particularly limited as long as it is a method generally used in a semiconductor device. For example, LOCOS (Local Oxidation of Silicon), trench oxidation, STI (Shallow Trench Isolation), etc. The method can be used.

  The gate electrode 4 is not particularly limited as long as it is generally used in a semiconductor device. For example, a semiconductor such as polysilicon, a metal such as aluminum, tungsten, titanium, and molybdenum, a metal silicide such as tungsten silicide, titanium silicide, or molybdenum silicide, and a stacked film of a semiconductor and a metal silicide can be used.

  The charged particles 6 are metal ions such as sodium ions, ions having positive or negative charges (movable ions), holes or electrons.

  The charge holding unit 1 holds a plurality of charged particles 6 and maintains the distribution state of the charged particles 6 at room temperature. The charge holding unit 1 is preferably a substance that changes the distribution state of charged particles inside by an external electric field during heating or electromagnetic wave irradiation, and that maintains the distribution at room temperature. For example, a silicon oxide film, a silicon nitride film, and a silicon oxide film and a silicon nitride film stacked in multiple layers can be used.

  A first insulating film 10 is provided between the charge holding portion 1 and the well region 5, and a second insulating film 11 is provided between the charge holding portion 1 and the gate electrode 4. ing. That is, the charge holding unit 1 is insulated. Therefore, the charged particles 6 are prevented from moving from the charge holding unit 1 to the gate electrode 4 or the well region 5. The first insulating film 10 and the second insulating film 11 are not particularly limited as long as they are insulating films that are generally used in semiconductor devices. For example, silicon oxide films can be used.

  The excitation device 7 excites (activates) the charged particles 6, and is, for example, an electromagnetic wave generation device or a heat generation device. The electromagnetic wave generator is an apparatus that excites the charged particles 6 by irradiating the electric charge holding unit 1 with an electromagnetic wave. For example, a solid state laser such as a YAG laser or a titanium sapphire laser, a semiconductor laser element such as a DH semiconductor laser, or a surface emitting laser. Alternatively, a light emitting element such as a light emitting diode element or an electroluminescent element can be used. Further, the heating device applies heat to the charge holding unit 1 to excite the charged particles 6, and for example, a resistance element can be used. The resistance element may be provided, for example, in an element isolation region or a semiconductor substrate. In FIG. 1, among the reference numerals, an arrow 8 represents an electromagnetic wave applied to the charge holding unit 1 or applied heat.

  For the source region 2 and the drain region 3, a P-type well region 5 formed in the semiconductor substrate or a diffusion region having a conductivity type opposite to that of the semiconductor substrate when the P-type well region 5 is not formed is used. It is done. Further, the junction depth of the source region 2 and the drain region 3 in the semiconductor substrate is not particularly limited as long as it is a junction depth used when a general semiconductor device is manufactured. Further, part of the source region 2 and the drain region 3 may be formed at a position higher than the height of the lower surface of the first insulating film 10 (the surface in contact with the P-type well region 5 in the first insulating film 10). Absent. The source region 2 and the drain region 3 are electrically connected to a source electrode and a drain electrode (not shown), respectively.

  In addition, an impurity that is generally used in a semiconductor device for adjusting a threshold voltage is implanted into a channel region formed above the P-type well region 5 between the source region 2 and the drain region 3. It doesn't matter.

  In the semiconductor memory device of the present embodiment, the gate electrode 4, the source region (source electrode) 2, the drain region (drain electrode) 3, and the semiconductor substrate (substrate electrode) are provided with four terminals under the above-described configuration. As described above, operations such as writing, erasing and reading of information are performed by applying a voltage between these terminals.

  In the above configuration, information writing, erasing and reading operations of the semiconductor memory device will be described with reference to FIGS. In the present embodiment, an operation when the charge of the charged particles 6 in the charge holding unit 1 is positive (for example, holes) will be described.

  FIG. 2 is a cross-sectional view showing a distribution state of holes in the charge holding portion when the semiconductor memory device is in an erased state. FIG. 3 is a cross-sectional view showing a distribution state of holes in the charge holding portion when the semiconductor memory device is in a write state.

  First, as shown in FIG. 2, “erasing” is a region in which the distribution state of the charged particles 6 in the charge holding unit 1 is sparse in the region close to the gate electrode 4 and close to the P-type well region 5. Is to change to a dense state. That is, the erased state is a state in which the charged particles 6 are concentrated in a region close to the P-type well region 5 in the charge holding unit 1 (the charged particles 6 are localized in a region close to the P-type well region 5. State) and represents the state of the semiconductor memory device after erasing.

  On the other hand, “writing” means that the distribution state of the charged particles 6 in the charge holding portion 1 is dense in the region close to the gate electrode 4 and close to the P-type well region 5 as shown in FIG. Is to change to a sparse state. In other words, the writing state is a state where the charged particles 6 are concentrated in a region close to the gate electrode 4 in the charge holding unit 1 (a state where the charged particles 6 are localized in a region close to the gate electrode 4). In addition, the state of the semiconductor memory device after writing is represented.

  As shown in FIG. 2, in a state where the charged particles 6 are distributed in a region close to the P-type well region 5, that is, in the erased state, the P-type well region 5 is used for the charged particles 6 in the charge holding unit 1. The inner holes move away from the interface with the charge holding unit 1. Therefore, in the erased state, even when the charged particles 6 shown in FIG. 3 are distributed in a region close to the gate electrode 4, that is, in the erased state, that is, even when the applied gate voltage is smaller than the written state, the first The P-type well region 5 under the insulating film 10 is inverted, and a channel layer (channel region) is formed between the source region 2 and the drain region 3. Therefore, the threshold voltage as a transistor is lowered.

  FIG. 4 shows the gate voltage-drain current characteristics of the semiconductor memory device when the drain voltage is constant. The horizontal axis represents the gate voltage, and the vertical axis represents the drain current. Curve 12a shows the gate voltage-drain current characteristic in the erased state, and curve 12b shows the gate voltage-drain current characteristic in the written state. From FIG. 4, it can be seen that in the erased state compared to the written state, the drain current starts to flow with a small gate voltage, and the threshold voltage as a transistor decreases.

  When the charge of the charged particles 6 in the charge holding unit 1 is negative (for example, electrons), a state where the charged particles 6 are distributed in a region close to the gate electrode 4 is an erased state, and the transistor characteristics are curved. 12b. In addition, a state where many charged particles 6 are distributed in a region close to the P-type well region 5 is referred to as a writing state, and the transistor characteristic is a curve 12a.

  FIG. 5 is a cross-sectional view for explaining a method of erasing information from the semiconductor memory device. In the semiconductor memory device in which the charged particles 6 in the charge holding unit 1 have a positive charge, in order to perform erasing, a state in which heat is applied to the semiconductor memory device or an electromagnetic wave is irradiated as shown by an arrow 8 in FIG. Thus, a positive voltage, for example, +8 V may be applied to the gate electrode 4 and 0 V may be applied to the substrate electrode, the source electrode, and the drain electrode, respectively. That is, by applying heat or irradiating electromagnetic waves, the charged particles 6 in the charge holding unit 1 are excited from a certain trap level and can easily move in the charge holding unit 1. When a positive voltage is applied to the gate electrode 4 in this state, the positive charged particles 6 in the charge holding unit 1 are close to the P-type well region 5 according to the electric field 14 generated by the positive voltage applied to the gate electrode 4. The region is densely distributed, and the region close to the gate electrode 4 is sparsely distributed. That is, the charged particles 6 are localized in a region close to the P-type well region 5. If the application of heat or irradiation of electromagnetic waves is stopped in this state, the charged particles 6 are captured again at the trap level, and the charged particles 6 are fixed as shown in FIG. In this manner, the distribution state of the charged particles 6 in the charge holding unit 1 can be changed and erasing can be performed.

  FIG. 6 is a cross-sectional view for explaining a method of writing information to the semiconductor memory device. In the semiconductor memory device in which the charged particles 6 in the charge holding unit 1 have a positive charge, as shown in FIG. 6, in a state where heat is applied to the semiconductor memory device or an electromagnetic wave is irradiated, as shown in FIG. A negative voltage, for example, −8 V may be applied to the gate electrode 4, and 0 V may be applied to the substrate electrode, the source electrode, and the drain electrode. By applying heat or irradiating electromagnetic waves, the charged particles in the charge holding unit 1 are excited from the trap level and can easily move in the charge holding unit 1. When a negative voltage is applied to the gate electrode 4 in this state, the positive charged particles 6 in the charge holding unit 1 follow the electric field 15 generated by the gate electrode, and are sparse near the P-type well region 5 and close to the gate electrode 4. Then it will be densely distributed. That is, the charged particles 6 are localized near the gate electrode 4. When the application of heat or the irradiation of electromagnetic waves is stopped, the charged particles 6 are captured again at the trap level, and the distribution state of the charged particles is fixed as shown in FIG. In this way, the writing state can be changed by changing the distribution state of the charged particles in the charge holding unit 1.

  In the present embodiment, the charge holding unit 1 is made of, for example, a silicon nitride film, and has a thickness of 1 nm to 20 nm, for example, and a relative dielectric constant of 7.0. The first insulating film 10 is made of, for example, a silicon oxide film, and has a thickness of 0.5 to 10 nm, for example, and a relative dielectric constant of 3.9. The gate electrode 4 is made of, for example, tungsten and has a thickness of, for example, 50 nm to 500 nm.

Here, the threshold voltage of the semiconductor memory device will be described. For example, when the thickness of the charge holding unit 1 is 10 nm and the dielectric constant of the vacuum is 8.9 × 10 ⁻¹⁴ F · cm ⁻¹ , the electric capacity per 1 cm ^{2 of the} charge holding unit 1 is approximately 6.2. It is calculated as ^{x10 −7} F · cm ⁻² . For example, when the thickness of the first insulating film 10 is 5 nm, the electric capacity per 1 cm ^{2 of} the first insulating film 10 is calculated to be approximately 6.9 × 10 ⁻⁷ F · cm ⁻² . Therefore, when rewriting from the written state to the erased state, the charged particles in the charge holding unit 1 move from the top to the bottom of the charge holding unit 1 by, for example, 1.3 × 10 ⁻⁶ C · cm ^−2. Compared with the threshold voltage when reading in the written state, the threshold voltage when reading in the erased state is decreased by about 2.0V. Using this threshold voltage difference, it is possible to distinguish between the written state and the erased state.

  In the semiconductor memory device of the present embodiment, as described above, charged particles do not pass through the first insulating film 10 during the write / erase operation. Therefore, there is no deterioration of the tunnel insulating film that occurs when the write / erase operation is performed a plurality of times in a flash memory or the like. Therefore, even if the write / erase operation is performed a plurality of times, the information recording characteristics are hardly deteriorated, and it is possible to withstand the rewriting more times than in the past. In addition, since the charge holding portion can store binary or higher information, a more highly integrated multilevel memory device can be provided.

  Next, a method for reading information from the semiconductor memory device of this embodiment will be described.

  Here, “reading” means detecting whether the semiconductor memory device is in a writing state or an erasing state.

  In order to read information stored as a distribution of charged particles localized in the charge holding unit 1, a voltage is applied between the electrodes to operate the transistor, and the information flows between the source electrode and the drain electrode. What is necessary is just to detect an electric current as a memory signal. Specifically, for example, + 3V is applied to the gate electrode 4, + 1V is applied to the drain electrode, and 0V is applied to the source electrode and the substrate electrode. At this time, if the semiconductor memory device is in the erased state, an inversion layer (channel layer) is formed on the surface of the P-type well region 5 under the charge holding portion 1, and current flows between the source region 2 and the drain region 3. Flowing. On the other hand, if the semiconductor memory device is in a written state, no inversion layer is formed on the surface of the P-type well region 5, and almost no current flows between the source region 2 and the drain region 3. As described above, when the transistor is operated, the amount of current flowing between the source region 2 and the drain region 3 varies depending on whether the semiconductor memory device is in a writing state or an erasing state. Therefore, if this current value is sent as a memory signal to a control circuit provided outside, and the magnitude of the memory signal is detected in the control circuit, it is detected whether the semiconductor memory device is in a write state or an erase state. It becomes possible.

  Next, a modification of the semiconductor memory device described above will be described with reference to FIG.

  FIG. 7 is a cross-sectional view showing a modification of the semiconductor memory device in this embodiment. In the semiconductor memory device of this modification, as shown in FIG. 7, the charge holding unit 16 is composed of a silicon oxide film 17 and a silicon nitride film 18, and the silicon oxide film 17 and the silicon nitride film 18 are alternately arranged. A total of ten laminated films are laminated. In this modification, the thickness of the silicon oxide film 17 is sufficiently thinner than the first insulating film 10 and the second insulating film 11, and the charged particles can easily pass through the silicon oxide film 17 by the tunnel effect. . Further, since the first insulating film 10 and the second insulating film 11 are sufficiently thick, the tunnel effect is hardly seen, and the charged particles held in the charge holding portion 16 do not move to the gate electrode 4 and the well region 5. . Therefore, the charge holding unit 16 holds the distribution state of the charged particles, whereby information can be written / erased / read.

  As described above, according to the semiconductor memory device of the present embodiment, in the information rewrite (write / erase) operation, it is not necessary to inject or extract charged particles into the charge holding portion. It is possible to prevent the level from increasing and the trap level in the insulating film from increasing. Therefore, the distinction between the written state and the erased state becomes clear, and information reading failure can be suppressed. In addition, since the charge holding portion is insulated, charged particles do not escape and information can be held for a long time.

  In addition, hot electron injection that requires a high voltage is not required, and a write operation at a low voltage is possible. Therefore, deterioration of the quality of the semiconductor memory device can be suppressed.

  In addition, the semiconductor memory device of this embodiment preferably includes an excitation device. Thereby, information can be rewritten while exciting charged particles. Therefore, the movement of the charged particles can be facilitated, and the voltage applied to the semiconductor memory device can be lowered.

  Furthermore, since the charge holding unit 1 is made of a silicon oxide film or a silicon nitride film, there are many trap levels and it is easy to hold charged particles. Therefore, information can be retained for a long time. In addition, the amount of information can be increased.

  In the above description, only two states are recorded: a state where many charged particles 6 having a positive charge are present on the semiconductor substrate side in the charge holding unit 1 and a state where many charged particles 6 are present on the gate electrode 4 side. Although described as a binary memory, it is not limited to this. That is, since the distribution state of the charged particles in the charge holding unit 1 can be continuously controlled by the magnitude of the gate voltage applied at the time of writing and erasing, a continuous memory signal corresponding to the distribution state of the charged particles is obtained. Can be obtained. Therefore, it can be used as a highly integrated analog memory. In addition, since the distribution state of the charged particles in the charge holding unit 1 can be discretely controlled and held, a discrete memory signal corresponding to the distribution state of the charged particles can be obtained. Therefore, it can be used as a multi-level memory.

  In this embodiment, the case where only one charge holding portion is formed in the semiconductor memory device has been described. However, a plurality of charge holding portions may be formed. In addition, a plurality of gate electrodes, insulating films, source regions, and drain regions may be formed corresponding to each charge holding portion. In this case, a plurality of charge holding units may be a memory cell array arranged in a matrix on a semiconductor substrate, for example. Thereby, a large amount of information can be stored.

  Further, a control circuit for controlling a voltage applied to the semiconductor memory device may be provided as necessary. Accordingly, for example, when the semiconductor memory device includes a plurality of charge holding units, it is possible to perform write, erase, and read operations on the plurality of charge holding units, respectively.

  In the semiconductor memory device provided by the present invention, it is preferable that the charge holding portion 1 is formed on the P-type well region 5 formed on the surface of the semiconductor substrate.

  Note that the semiconductor memory device of the present invention can be expressed as follows.

  [1] A first semiconductor memory device provided by the present invention is characterized in that information is stored by holding a distribution state of charged particles in a charge holding unit.

  [2] A second semiconductor memory device provided by the present invention includes a semiconductor substrate, a charge holding portion formed on the semiconductor substrate, an electrode (gate electrode) formed on the charge holding portion, A charge region having a channel region formed under the charge holding portion, a pair of diffusion layer regions formed on the left and right sides of the channel region, and an element isolation region, the position of which is fixed in the charge holding portion at room temperature It is characterized by containing particles.

  [3] A third semiconductor memory device provided by the present invention includes a semiconductor substrate, a charge holding portion formed on the semiconductor substrate, an electrode (gate electrode) formed on the charge holding portion, A charge region having a channel region formed under the charge holding portion, a pair of diffusion layer regions formed on the left and right sides of the channel region, and an element isolation region, the position of which is fixed in the charge holding portion at room temperature A cell array having a plurality of semiconductor nonvolatile memory cells containing particles, a device for activating charged particles in the charge holding unit and facilitating movement in the charge holding unit, and a circuit for controlling the current and voltage of the cell array It is characterized by comprising.

  [4] A fourth semiconductor memory device provided by the present invention is the semiconductor memory device according to any one of [1] to [3], wherein the charge holding unit includes a silicon nitride film or a silicon oxide film and a silicon nitride film. It is characterized by comprising a laminated film in which at least one layer is laminated.

  According to the configuration of [4] above, since many trap levels exist in the silicon nitride film, it is difficult to move charged particles in the charge holding portion at room temperature. Almost no change. In addition, when the charge holding unit is heated or when the charge holding unit is irradiated with electromagnetic waves, the movement of the charged particles in the charge holding unit is facilitated, so that the distribution state of the charged particles can be easily changed. is there.

  [5] A fifth semiconductor memory device provided by the present invention provides a heating circuit or an electromagnetic wave as a device for activating charged particles in the charge holding portion in the first to fourth semiconductor memory devices. It has a generation circuit.

  [6] In the semiconductor memory device write / erase method provided by the present invention, in the first to fifth semiconductor memory devices, a voltage is applied to the electrode formed on the charge holding portion in a state where heat or electromagnetic waves are applied. It is characterized in that information is rewritten by changing the distribution state of charged particles in the charge holding portion when applied.

  According to the configuration [6], since no charged particle injection into the charge holding unit is required during the write / erase operation, the interface is hardly deteriorated. Therefore, it is possible to withstand a large number of write / erase operations.

  According to the above configurations [1] to [6], the semiconductor memory device provided by the present invention stores information by holding the distribution state of the charged particles in the charge holding unit. The charged particles do not pass through the semiconductor substrate interface and the insulating film. Therefore, compared with a memory device that stores information by changing the amount of charged particles, there is less deterioration in the insulating film and at the semiconductor substrate interface. Therefore, the semiconductor memory device provided by the present invention can withstand the write / erase operation more times than before.

  The semiconductor memory device of the present invention is not particularly limited and can be applied to, for example, a semiconductor nonvolatile memory device.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

  In the semiconductor memory device according to the present invention, since the information storage characteristics are improved, the semiconductor memory device can be applied to a semiconductor device or a display device including the semiconductor memory device.

1 is a cross-sectional view of a semiconductor memory device in an embodiment of the present invention. It is sectional drawing which shows the distribution state of the hole in an electric charge holding part when the said semiconductor memory device is an erased state. It is sectional drawing which shows the distribution state of the hole in an electric charge holding part when the said semiconductor memory device is in a writing state. 4 is a graph showing respective gate voltage-drain current characteristics when the semiconductor memory device is in a write state and in an erase state. It is sectional drawing for demonstrating the erase method of the information to the said semiconductor memory device. It is sectional drawing for demonstrating the writing method of the information to the said semiconductor memory device. It is sectional drawing which shows the modification of the said semiconductor memory device. It is sectional drawing of the conventional semiconductor memory device.

Explanation of symbols

1 Charge holding part 2 Source region (diffusion layer region)
3 Drain region (diffusion layer region)
4 Gate electrode 5 P-type well region (channel region)
6 Charged Particle 7 Excitation Device 10 First Insulating Film 11 Second Insulating Film 16 Charge Holding Portion 17 Silicon Oxide Film 18 Silicon Nitride Film

Claims (5)

A channel region formed on a semiconductor substrate; a pair of diffusion layer regions formed so as to sandwich the channel region; a charge holding portion formed on the channel region via a first insulating film; and the charge A gate electrode formed on the holding portion via the second insulating film,
The charge holding unit holds the inside charged particles, Ri can der to store information by different distribution of the charged particles that its retention,
The charge holding portion is composed of a silicon oxide film and a silicon nitride film, a semiconductor memory device according to claim laminate film der Rukoto where the silicon oxide film and a silicon nitride film are alternately stacked. A channel region formed on a semiconductor substrate; a pair of diffusion layer regions formed so as to sandwich the channel region; a charge holding portion formed on the channel region via a first insulating film; and the charge A gate electrode formed on the holding portion via the second insulating film,
The charge holding portion is made of an insulator capable of holding a distribution state of charged particles inside at room temperature,
The amount of current flowing from one diffusion layer region to the other diffusion layer region when a voltage is applied to the gate electrode changes according to the distribution state of the charged particles held in the charge holding unit. And
The charge holding portion is composed of a silicon oxide film and a silicon nitride film, a semiconductor memory device according to claim laminate film der Rukoto where the silicon oxide film and a silicon nitride film are alternately stacked. The semiconductor memory device according to claim 1 or 2, wherein the further comprising a pumping device for exciting the charged particles in the charge holding portion. 4. The semiconductor memory device according to claim 3 , wherein the excitation device is a heat generating device or an electromagnetic wave generator. A method of operating a semiconductor memory device according to any one of claims 1-4,
Information is rewritten by changing the distribution state of the charged particles by applying a voltage to the gate electrode while the charged particles held in the charge holding portion are excited. How it works.

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