JP4933466B2 - Wireless communication system and receiving terminal - Google Patents

Description

  The present invention relates to a radio communication system and a receiving terminal that mainly perform communication using a network code.

In recent years, wireless mesh networks using network codes for the purpose of improving network throughput and multi-hop wireless communication have attracted attention. Network codes that are encoded at relay nodes on the network can improve throughput by multiplexing data by encoding at relay nodes compared to networks that do not perform encoding processing in multicast or unicast communications. It becomes possible to plan. Wireless mesh networks using network coding and multi-hop wireless communications are a combination of timely listening and network codes that effectively utilize the broadcast performance of wireless communications, and throughput in wireless mesh networks and multi-hop wireless communications. Improvement can be realized. Here, timely listening means receiving and storing a signal addressed to another node.
A node acting as a relay station encodes bit signals received from a plurality of transmitting station nodes with a linear code and relays them to a receiving station. The receiving station decodes using the bit signal received from the relay station node and the transmitting station node, or the bit signal stored in the own station, and obtains the lower data (Non-Patent Document 1 and Non-Patent Document 2). reference).
Below, a specific example is given and the radio | wireless network to which network coding is applied is demonstrated. Here, for the sake of simplicity, explanation will be made using exclusive OR for linear encoding.

  FIG. 16 is a schematic block diagram showing an internal configuration of a receiving terminal 91 used as a receiving node of a wireless network using a conventional network code. As shown in this figure, the receiving terminal 91 includes a radio unit 911, a symbol / bit conversion circuit 912, a soft decision circuit 913, a multiplication circuit 914, an error correction decoding circuit 915, a linear decoding circuit 916, an output switching circuit 917, a weighting factor. An extraction circuit 918, a signal storage circuit 919, an output switching circuit 920, an error correction code circuit 921, and a modulation circuit 922 are provided.

  The radio unit 911 extracts a desired signal from the received signal and outputs the extracted signal to the symbol / bit conversion circuit 912 and the weighting coefficient extraction circuit 918. The wireless unit 911 transmits the input signal. The symbol / bit conversion circuit 912 demodulates a signal obtained by modulating the input signal using QPSK, 16QAM, or the like. The soft decision circuit 913 performs soft decision on the input bit signal and outputs it as a signal including the reliability of the received bit signal. The multiplier circuit 914 multiplies two input signals. The error correction code circuit 915 performs error correction decoding on the input soft decision signal. The linear decryption circuit 916 uses the key signal to decrypt the input signal and obtain a bit signal. The output switching circuits 917 and 920 switch the output destination of the input signal depending on whether the input signal is a signal using a network code for decoding or the input signal is a decoded signal. The signal storage circuit 919 stores the input signal. The weighting coefficient extraction circuit 918 extracts a transmission path transmission coefficient or a coefficient based on received power using the received signal. The error correction code circuit 921 performs error correction coding on the input signal using a predetermined method. The modulation circuit 922 modulates the input signal using a method such as QPSK, for example.

  FIG. 17 is a schematic diagram illustrating a configuration example of the Alice & Bob topology of the wireless communication system 9 using a mesh network to which a network code is applied. The wireless communication system 9 is configured to include two receiving terminals 91 and one relay terminal. The operation | movement which exchanges the information which the receiving terminal 91-1 and the receiving terminal 91-2 arrange | positioned at both ends mutually have is demonstrated using this figure. The receiving terminal 91-1 stores the bit signal a in advance, and the receiving terminal 91-2 stores the bit signal b in advance. The receiving terminals 91-1,..., Receiving terminals 91-m (m = 1, 2, 3,..., N) have the same configuration, and the receiving terminals 91-1,. When any one or all of them are shown as a representative, they are referred to as receiving terminals 91.

First, in the receiving terminal 91-1 at time T1, the error correction code circuit 921 receives the bit signal a stored in the signal storage circuit 919 via the output switching circuit 920, performs error correction coding, and outputs it to the modulation circuit 922. To do. The modulation circuit 922 modulates the input signal and outputs the modulated modulation signal a to the radio unit 911. The wireless unit 911 transmits the input modulation signal a (step S91).
Next, in the receiving terminal 91-2 at time T2, similarly to the receiving terminal 91-1, the bit signal b stored in the own terminal is modulated and the modulated signal b is transmitted (step S92).
At time T3, the relay terminal 92 demodulates the modulated signal a received at time T1 and the modulated signal b received at time T2, and the exclusive logic of the bit signal a and bit signal b obtained by the demodulation is obtained. The sum is calculated, and the result obtained by the calculation is modulated and transmitted (step S93).
Note that the result of the exclusive OR of the bit signal a and the bit signal b is hereinafter referred to as a ^ b.

  In receiving terminal 91-1, radio section 911 detects modulated signal a ^ b, and outputs detected modulated signal a ^ b to symbol / bit conversion circuit 912. The symbol / bit conversion circuit 912 outputs a signal obtained by converting the input modulation signal a ^ b to the soft decision circuit 913. The soft decision circuit 913 performs soft decision on the input signal and outputs it to the multiplication circuit 914. The weighting factor extraction circuit 918 calculates a weighting factor from the received modulation signal a ^ b, and outputs the calculated weighting factor to the multiplication circuit 914. The multiplication circuit 914 multiplies the weight coefficient input from the weight coefficient extraction circuit 918 and the signal input from the soft decision circuit 913, and outputs the multiplication result to the error correction decoding circuit 915. The error correction decoding circuit 915 performs error correction decoding on the input signal and outputs the bit signal a ^ b obtained by the decoding to the linear decoding circuit 916. The linear decoding circuit 916 decodes the bit signal a ^ b input from the error correction decoding circuit 915 using the bit signal a input from the signal storage circuit 919 via the output switching circuit 920, and is obtained by decoding. The bit signal b is output as an output signal via the output switching circuit 917.

Similarly to the receiving terminal 91-1, the receiving terminal 91-2 also performs demodulation, error correction, and linear decoding on the received modulation signal a ^ b using the bit signal b stored in the own terminal. A bit signal a is obtained.
With the above operation, the bit signal a held by the receiving terminal 91-1 and the bit signal b held by the receiving terminal 91-2 are transmitted to each other receiving terminal.

  Next, FIG. 18 is a schematic diagram illustrating a configuration of the wireless communication system 9a in the X-topology. The wireless communication system 9a includes transmission terminals 93-1, 93-2, a relay terminal 92, and reception terminals 91-3, 91-4. The operation in the X-topology will be described using this figure. This is an operation for transmitting the bit signal a stored in the transmission terminal 93-1 and the bit signal b stored in the transmission terminal 93-2 to the reception terminals 91-3 and 91-4.

First, at time T1, the transmission terminal 93-1 modulates the bit signal a stored in the terminal itself and transmits the modulated signal a (step S94). The relay terminal 92 demodulates the received modulated signal a and stores the demodulated bit signal a.
The receiving terminal 91-3 listens to the modulated signal a transmitted to the relay terminal 92 in a timely manner. Radio section 911 detects modulated signal a and outputs detected modulated signal a to symbol / bit conversion circuit 912. The symbol / bit conversion circuit 912 converts the modulation signal a input from the radio unit 911 and outputs a signal obtained by the conversion to the soft decision circuit 913. The soft decision circuit 913 performs soft decision on the input signal and outputs it to the multiplication circuit 914. The weight coefficient extraction circuit 918 calculates a weight coefficient from the input modulation signal a, and outputs the calculated coefficient to the multiplication circuit 914. The multiplication circuit 914 multiplies the weight coefficient input from the weight coefficient extraction circuit 918 and the signal input from the soft decision circuit 913, and outputs the multiplication result to the error correction decoding circuit 915. The error correction decoding circuit 915 performs error correction decoding on the input signal, and outputs and stores the bit signal a in the signal storage circuit 919 via the output switching circuit.

Next, at time T2, the transmitting terminal 93-2 modulates the bit signal b stored in the terminal itself and transmits the modulated signal b (step S95). The relay terminal 92 demodulates the received modulated signal b and stores the demodulated bit signal b.
In the receiving terminal 91-4, similarly to the operation when the receiving terminal 91-3 receives the modulated signal a, the transmitting terminal 93-2 is similar to the operation when the receiving terminal 91-3 receives the modulated signal a. Listens to the modulated signal b transmitted to the relay terminal 92 in a timely manner. The receiving terminal 91-3 demodulates and stores the bit signal b from the modulated signal b by listening at appropriate times.

  At time T3, the relay terminal 92 performs an exclusive OR operation, that is, network coding, on the stored bit signal a and bit signal b to calculate the bit signal a ^ b. The relay terminal 92 modulates the calculated bit signal a ^ b and transmits the modulated signal a ^ b to the receiving terminal 91-3 and the receiving terminal 91-4 (step S96).

  Subsequently, in the reception terminal 91-3, the radio unit 911 detects the modulation signal a ^ b from the reception signal, and outputs the extracted modulation signal a ^ b to the symbol / bit conversion circuit 912 and the weight coefficient extraction circuit 918. . The symbol / bit conversion circuit 912 converts the input modulation signal a ^ b and outputs the converted signal to the soft decision circuit 913. The soft decision circuit 913 performs a soft decision on the signal input from the symbol / bit conversion circuit 913 and outputs the signal obtained by the decision to the multiplication circuit 914. The weighting coefficient extraction circuit 918 calculates a weighting coefficient from the input modulation signal a ^ b, and outputs the calculated weighting coefficient to the multiplication circuit 914. The multiplication circuit 914 multiplies the signal input from the soft decision circuit 913 by the coefficient signal output from the weight coefficient extraction circuit 918 and outputs the multiplication result to the error correction decoding circuit 915. The error correction decoding circuit 915 performs error correction decoding on the signal input from the multiplication circuit 914 to obtain a bit signal a ^ b. Further, the error correction decoding circuit 915 outputs the bit signal a ^ b obtained by decoding to the linear decoding circuit 916. The linear decoding circuit 916 decodes the bit signal a ^ b input from the error correction decoding circuit 915 using the bit signal a input from the signal storage circuit 919 via the output switching circuit 920, and converts the bit signal b into obtain. Also, the linear decoding circuit 916 outputs the bit signal b obtained by decoding as an output signal via the output switching circuit 917.

  In addition, the receiving terminal 91-4 demodulates the modulated signal a ^ b using the bit signal b stored in the signal storage circuit 919 of the receiving terminal 91-4 in the same manner as the receiving terminal 91-3. A bit signal a is obtained.

Through the above operation, in the wireless communication system 9a to which the network code is applied, the bit signal a stored in the transmission terminal 93-1 and the bit signal b stored in the transmission terminal 93-2 are converted into the reception terminals 91-3 and 91-. 4 is transmitted.
Sachin Katti, Hariharan Rahul, et al, "XORs in The Air: Practical Wireless Network Coding", Proc. ACM SIGCOMM 2006, Pisa Italy, Sep. 2006, p.243-254 R.Ahlswede, S.Li, and R.Yeung, "Network information flow", IEEE Trans. Inf. Theory, vol.46, July 2000, no.4, p.1204-1216

However, in the wireless communication system to which the network coding as described above is applied, the feature of wireless broadcasting is not effectively used, and the communication quality of the physical link between the terminals cannot be improved. As an example of not effectively using the broadcast performance, in the wireless communication system 9a shown in FIG. 18, even if the reception terminal 91-4 receives a signal transmitted by the transmission terminal 93-1 at time T1. It is not used because stable transmission cannot be performed. Further, in order to decode a linearly encoded signal, a key signal is indispensable. However, when the link quality through which the key signal passes is poor, the error rate characteristic of the entire received signal also deteriorates. There is.
In addition, the radio link of the radio communication system can generally improve the communication quality by performing cooperative transmission using a relay terminal, but the link quality through which the key signal passes is deteriorated and unstable. In the wireless communication system to which the conventional network coding is applied, the error rate characteristic of the entire wireless communication system deteriorates, so that there is a problem that it is not possible to receive the benefit of communication quality improvement by cooperative transmission.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a wireless communication system, a receiving terminal, and a relay terminal to which network coding is applied to improve communication quality by utilizing wireless broadcasting. There is.

In order to solve the above problems, the present invention includes a receiving terminal, the relay terminal and stores the key signal in advance, has a transmission terminal that transmits the key signal to the relay terminal, the network information signal by the key signal In a wireless communication system that performs communication by encoding, the relay terminal receives and detects a signal transmitted to the terminal, and outputs a detected signal and the first receiver A first signal storage circuit for storing a signal to be output; and network encoding in which any one of a plurality of signals stored in the first signal storage circuit is the key signal, for the plurality of signals, A first linear encoding circuit that outputs a network-encoded signal; and a first transmission unit that transmits a signal output from the first linear encoding circuit to the receiving terminal. , The communication addressed to your terminal The second receiver that receives and detects signals other than those addressed to the terminal itself, outputs the detected signals, and the signals output from the second receiver are network-encoded. In the case of the received signal, the signal output from the second receiving unit is used as the key signal , and the network decoding circuit that outputs a network decoded signal that is network-decoded, and the other terminal that is output from the second receiving unit A second likelihood signal storage circuit that stores the signal of likelihood as a likelihood signal, a likelihood signal stored by the second likelihood signal storage circuit, and a network decoded signal output by the network decoding circuit. maximum ratio combining to perform, non-network coding, which is the maximum ratio combining and adding circuit for outputting a signal, the likelihood signal the second likelihood signal storage circuit is not network coding stores Te An error correction decoding circuit that performs error correction decoding on the degree signal, the unnetwork encoded likelihood signal stored in the second likelihood signal storage circuit, and the second likelihood signal storage circuit A cross-correlation value calculation circuit that calculates a cross-correlation value with a network-encoded likelihood signal that is a network-encoded likelihood signal, and the network decoding circuit includes the second likelihood signal storage circuit Can be decoded without error by the error correction decoding circuit, network decoding is performed using the signal obtained by decoding the unnetwork encoded likelihood signal by the error correction decoding circuit as the key signal. If the uncorrected network code likelihood signal stored in the second likelihood signal storage circuit cannot be decoded without error by the error correction decoding circuit, the cross correlation value calculation is performed. Based on the cross-correlation value calculated by the circuit, an unnetwork encoded likelihood signal stored in the second likelihood signal storage circuit is selected, and the selected unnetwork encoded likelihood signal is used as the key signal. A wireless communication system characterized by performing network decoding .

  Further, the present invention is a wireless communication system having a first receiving terminal, a second receiving terminal, and a relay terminal, and performing communication by network-coding an information signal with a key signal, wherein the relay terminal is the receiving terminal A first receiver that receives and detects a signal transmitted from the first receiver and outputs the detected signal, and a first signal that is output from the first receiver and that is not addressed to the own terminal is stored as a likelihood signal. Performing a maximum ratio combining by adding the likelihood signal storage circuit, the likelihood signal stored in the first likelihood signal storage circuit, and the signal addressed to the terminal output by the first receiver, A first adder circuit that outputs a signal with the maximum ratio combined; a first signal storage circuit that stores a signal output from the first adder circuit; and a plurality of signals stored in the first signal storage circuit. Any one of the network encodings that becomes the key signal A first linear encoding circuit that performs a plurality of signals and outputs a network encoded signal, and transmits a network encoded signal output from the first linear encoding circuit to the receiving terminal A first transmission unit, wherein the first receiving terminal transmits a second signal storage circuit that stores the key signal in advance, and a second signal that transmits the key signal stored in the second signal storage circuit. A second receiving unit for receiving and detecting a signal addressed to the own terminal, receiving and detecting a signal other than the addressed to the own terminal, and outputting the detected signal; and the second receiving When the signal output from the unit is a network-encoded signal, a second network decoding circuit that outputs a network-decoded signal that is network-decoded using the key signal, and the other that is output from the second receiving unit Signals destined for the terminal are likelihood signals And adding the second likelihood signal storage circuit to be stored, the likelihood signal stored by the second likelihood signal storage circuit, and the network decoded signal output from the second network decoding circuit, A second adding circuit that performs maximum ratio combining and outputs a signal that has been maximum ratio combined, and the second receiving terminal receives and detects a signal addressed to the own terminal, and further, other than addressed to the own terminal. A third receiving unit that receives and detects the signal and outputs the detected signal; and a third signal storage circuit that stores, as the key signal, a signal addressed to the terminal output from the third receiving unit. A network-decoded signal output from the third receiving unit and network-decoded by using the signal stored in the third signal storage circuit as the key signal and the network-encoded signal addressed to its own terminal; Network decoding circuit, and A third likelihood signal storage circuit for storing a signal addressed to another terminal output from the third receiver as a likelihood signal, a likelihood signal stored by the third likelihood signal storage circuit, and the third A network decoding signal output from the network decoding circuit is added to perform a maximum ratio combining, and a third adding circuit for outputting the maximum ratio combined signal; and the key signal stored in the third signal storage circuit A wireless communication system, comprising: a third transmission unit that transmits to a relay terminal and transmits a signal output from the third addition circuit to the first reception terminal.

Further, the present invention includes a receiving terminal, the relay terminal and stores the key signal in advance, has a transmission terminal that transmits the key signal to the relay terminal performs communication with the network code information signal by the key signal A receiving terminal in the wireless communication system, which receives and detects a signal addressed to the own terminal, further receives and detects a signal other than the address addressed to the own terminal, and outputs a detected signal ; when signal output from the previous SL second reception unit of the network coded signal by using a signal in which the second receiving section is outputted as the key signal, a second outputting a network decoding signal network decoding A network decoding circuit, a second likelihood signal storage circuit for storing a signal addressed to another terminal output from the second reception unit as a likelihood signal, and the second likelihood signal storage circuit Likelihood signal and The network decoding circuit adds the network decoding signal outputted perform maximum ratio combining, a second adding circuit for outputting a maximum ratio combined signal, said network codes second likelihood signal storage circuit stores An error correction decoding circuit that performs error correction decoding on an unnetworked likelihood signal that is an unconverted likelihood signal, and the unnetworked likelihood signal stored in the second likelihood signal storage circuit And a cross-correlation value calculating circuit that calculates a cross-correlation value with a network-encoded likelihood signal that is a network-encoded likelihood signal stored in the second likelihood signal storage circuit , When the network decoding likelihood signal stored in the second likelihood signal storage circuit can be decoded without error by the error correction decoding circuit, the network decoding circuit Network decoding is performed using the signal obtained by decoding the work coding likelihood signal by the error correction decoding circuit as the key signal, and the unnetwork code likelihood signal stored in the second likelihood signal storage circuit is the error correction decoding. If the circuit cannot decode without error, an unnetwork-encoded likelihood signal stored in the second likelihood signal storage circuit is selected based on the cross-correlation value calculated by the cross-correlation value calculation circuit. A receiving terminal that performs network decoding using the unnetworked likelihood signal as the key signal .

  According to the present invention, the second wireless unit included in the receiving terminal receives an unnetwork encoded signal other than that addressed to the own terminal, and the received unnetwork encoded signal other than addressed to the own terminal and the relay terminal are encoded. The signal obtained by decoding the network encoded signal by the network decoding circuit is subjected to maximum ratio combining using the second adder circuit. Communication quality can be improved by the diversity effect by the maximum ratio combining performed by the second adder circuit.

  According to the present invention, when a signal is stored in advance in the second signal storage circuit included in the receiving terminal, the signal transmitted from the other receiving terminal to the relay terminal is received, and the second likelihood signal storage is performed. By storing in the circuit, the signal obtained by network decoding the network-encoded signal transmitted from the relay terminal, the signal stored in the second likelihood signal storage circuit, and the second adder circuit Perform maximum ratio synthesis. As a result, it is possible to improve communication quality due to the diversity effect.

  According to the present invention, when the signal is not stored in advance in the second signal storage circuit included in the receiving terminal, the second network decryption circuit uses the signal output from the second receiving unit as a key signal. It is possible to decode a network encoded signal.

  Further, according to the present invention, when an error is included in the signal received by the second receiving unit used as the key signal, the likelihood signal stored in the second likelihood signal storage circuit is network encoded. The cross-correlation value with the likelihood signal obtained is calculated, the likelihood signal stored in the second likelihood signal storage circuit is selected based on the calculated cross-correlation value, and the selected likelihood signal is selected as the key signal. It was set as the structure to do. As a result, even when an error is included in the received non-network encoded signal due to deterioration in communication quality, a signal suitable as a key signal for network decoding is selected from the received non-network encoded signal and network decoding is performed. It becomes possible.

  Further, according to the present invention, the second receiving terminal is arranged between the first receiving terminal that stores the signal to be transmitted and the relay terminal, and both wireless communication is performed using the second receiving terminal. By relaying, it is possible to improve communication quality due to the diversity effect even in a situation where the first receiving terminal and the relay terminal cannot communicate directly.

  Hereinafter, a wireless communication system, a receiving terminal, and a relay terminal according to embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a schematic block diagram showing the internal configuration of the receiving terminal 10 in the first embodiment. The receiving terminal 10 includes a radio unit 101, a symbol / bit conversion circuit 102, a soft decision circuit 103, output switching circuits 104, 107, 109, 117, a multiplication circuit 105, an addition circuit 106, an error correction decoding circuit 108, and a likelihood signal storage. A circuit 113, a modulation circuit 116, an error correction code circuit 118, a signal storage circuit 119, a weight coefficient extraction circuit 120, a network decoding circuit 121, and a cross correlation value calculation circuit 122 are provided. The network decoding circuit 121 includes a code / bit conversion circuit 110, an absolute value extraction circuit 111, a multiplication circuit 112, a linear decoding circuit 114, and a bit / code conversion circuit 115.

  Radio section 101 transmits an input signal, detects a desired symbol signal from the received signal, and outputs it. Here, the symbol signal is a signal modulated by QPSK (Quadrature Phase-Shift Keying), 16QAM (Quadrature Amplitude Modulation), or the like. The symbol / bit conversion circuit 102 converts an input received symbol signal into a bit series signal. The soft decision circuit 103 makes a soft decision on the input bit sequence signal and converts it into a soft decision signal. Here, the soft decision refers to a signal indicating one of two values “0” and “1” with respect to an input bit sequence signal, and a predetermined threshold value indicating how certain the indicated value is. This is a determination that determines a signal that is a set of signals that are expressed step by step. As an example, positive and negative are used to represent the binary values of “0” and “1”, and the probability is treated as a signal indicated by a numerical value. That is, the soft decision signal indicates 1 of the bit signal when the value indicated by the soft decision signal is positive, indicates 0 of the bit signal when the value indicated is negative, and the absolute value of the value indicated by the soft decision signal is It is a signal indicating the accuracy of the value of the bit signal indicated by a positive or negative sign. The output switching circuit 104 outputs the network-coded soft decision signal to the network decoding circuit 121 when decoding, and outputs the network-coded soft decision signal to the multiplication circuit 105 when not decoding. The multiplier circuit 105 multiplies the input signal. An adder circuit 106 adds two input signals. The output switching circuit 107 outputs to the likelihood signal storage circuit 113 when storing as a bit-by-bit likelihood signal (hereinafter referred to as bit-by-bit likelihood signal), and error correction decoding when not storing it as a bit-by-bit likelihood signal. Output to the circuit 108. The output switching circuit 109 outputs the input signal to the signal storage circuit 119 when storing it as a key signal, and outputs the input signal as an output signal when used in the processing of its own terminal. The output switching circuit 117 outputs the input signal to the modulation circuit 116 when transmitting the bit signal stored in the terminal itself, and when decoding the network-coded signal, the output switching circuit 117 sends the input signal to the network decoding circuit 121. Output. The likelihood signal storage circuit 113 stores the input bit-wise likelihood signal. The cross-correlation value calculation circuit 122 calculates a cross-correlation value between the network-encoded bit-by-bit likelihood signal stored in the likelihood signal storage circuit 113 and the network-encoded bit-by-bit likelihood signal, The calculated cross-correlation values are compared.

  The error correction decoding circuit 108 performs error correction decoding processing on the soft decision signal input as the likelihood signal and detects whether error correction has been performed. The modulation circuit 116 modulates an input signal by a predetermined method. The error correction code circuit 118 selects and reads the signal stored in the signal storage circuit 119 as a key signal, and performs error correction coding on the read bit signal using a predetermined method. Here, a convolutional code, a turbo code, or the like is used as the error correction code to be used. The signal storage circuit 119 stores the input bit signal. The weighting coefficient extraction circuit 120 calculates a coefficient from the input received signal based on information indicating the state of the transmission path. For example, it is calculated based on the received power.

The network decoding circuit 121 performs error correction coding on the soft decision signal input from the output switching circuit 104 or the bit-wise likelihood signal input from the likelihood signal storage circuit 113 and input via the output switching circuit 117. The network-encoded signal is decrypted using the obtained key signal. A signal input from the output switching circuit 104 to the network decoding circuit 121 is input to the code / bit conversion circuit 110 and the absolute value extraction circuit 111. A signal input from the output switching circuit 117 to the network decoding circuit 121 is input to the linear decoding circuit 114. The likelihood signal for each bit input from the likelihood signal storage circuit 113 to the network decoding circuit 121 is input to the code / bit conversion circuit 110 and the absolute value extraction circuit 111.
The sign / bit conversion circuit 110 includes a sign part of a soft decision signal input from the soft decision circuit 103 via the output switching circuit 104 and a soft decision signal input from the likelihood signal storage circuit 113 as a bit-wise likelihood signal. A bit signal is extracted from the signal and a bit signal indicated by the soft decision signal is output. The absolute value extraction circuit 111 calculates an absolute value for each bit indicated by the input soft decision signal, and outputs a signal indicating the probability for each bit included in the calculated soft decision signal. The multiplier circuit 112 multiplies two input signals. The linear decoding circuit 114 decodes the network-encoded signal using the input network-encoded signal and the input key signal. The bit / code conversion circuit 115 converts the input bit signal into a code of a soft decision signal and outputs the converted signal.

  FIG. 2 is a schematic block diagram showing the internal configuration of the relay terminal 20 in the present embodiment. The relay terminal 20 includes a radio unit 201, a symbol / bit conversion circuit 202, a soft decision circuit 203, a multiplication circuit 204, an error correction decoding circuit 205, an output switching circuit 206, a signal storage circuit 207, a linear encoding circuit 208, an error correction code. A circuit 209, a modulation circuit 210, and a weighting coefficient extraction circuit 211 are provided.

The wireless unit 201 transmits an input signal, detects a desired signal from the received signal, and outputs it. The symbol / bit conversion circuit 202 transmits an input signal, and detects and outputs a desired symbol signal from the received signal. The soft decision circuit 203 makes a soft decision on the input bit series signal and converts it into a soft decision signal. The multiplication circuit 204 multiplies two input signals. The error correction decoding circuit 205 performs error correction decoding on the input soft decision signal. The output switching circuit 206 outputs a signal to be network-encoded and transmitted to the signal storage circuit 207, and outputs a bit signal to be processed in the own terminal as an output signal in the own terminal. The signal storage circuit 207 stores the input bit signal. The linear encoding circuit 208 reads the bit signal stored in the signal storage circuit 207 and performs network encoding on the read bit signal by a predetermined method. The error correction code circuit 209 performs error correction coding on the input bit signal using a predetermined method. The modulation circuit 210 modulates an input signal by a predetermined method. The weighting coefficient extraction circuit 211 calculates a coefficient based on information indicating the state of the transmission path from the input reception signal. For example, it is calculated based on received power.
Note that the error correction code system used by the error correction code circuit 209 and the modulation system used by the modulation circuit 210 are the same system in the wireless communication system.

(Operation in Alice & Bob topology)
Next, FIG. 3 is a schematic diagram illustrating the wireless communication system 1 having the Alice & Bob topology configuration according to the first embodiment. The wireless communication system 1 is configured to include receiving terminals 10-1 and 10-2 and a relay terminal 20. The receiving terminal 10-1 and the receiving terminal 10-2 have the same configuration as the receiving terminal 10, and hereinafter, one or both of the receiving terminal 10-1 and the receiving terminal 10-2 will be representatively shown. In this case, it is referred to as receiving terminal 10.

The receiving terminal 10-1 has a bit signal a, and the receiving terminal 10-2 has a bit signal b. The operation of transmitting each bit signal in the wireless communication system 1 to which the network code is applied via the relay terminal 20 will be described using FIG. 3 and FIG.
First, FIG. 4 is a flowchart showing a process of transmitting / receiving a bit signal of the receiving terminal 10-1. In the network coding, exclusive OR is used, and the result of the exclusive OR of the bit signal a and the bit signal b is hereinafter referred to as a bit signal a ^ b using a hat symbol ^. That is, the linear decoding circuit 114 and the linear encoding circuit 208 perform decoding and encoding using exclusive OR.

(Operation of Receiving Terminal 10-1 in Alice & Bob Topology)
In receiving terminal 10-1, error correction code circuit 118 reads bit signal a stored in reception signal storage circuit 119 in advance, performs error correction coding, and outputs the result to modulation circuit 116 via output switching circuit 117. . The modulation circuit 116 modulates the input signal and outputs the modulated signal a to the wireless unit 101 (step S101).
Radio section 101 transmits modulated signal a to the relay device (step S102).

  Subsequently, in response to the reception terminal 10-2 detecting the modulation signal b transmitted to the relay terminal 20, the radio unit 101 detects the detected modulation signal b using the symbol / bit conversion circuit 102 and the weight coefficient extraction. Output to the circuit 120. That is, the receiving terminal 10-1 performs timely listening (step S103). Here, timely listening refers to receiving a signal addressed to another terminal and storing the transmitted signal.

  The symbol / bit conversion circuit 102 performs symbol-bit conversion on the input modulation signal b to convert it to a bit series signal b, and outputs the bit series signal b to the soft decision circuit 103. The soft decision circuit 103 performs a soft decision on the bit series signal b input from the symbol / bit conversion circuit 102 and converts the bit sequence signal b into a soft decision signal b. The soft decision signal b is multiplied by the multiplication circuit 105 via the output switching circuit 104. Output to. The weighting factor extraction circuit 120 calculates a weighting factor from the modulation signal b input from the wireless unit 101 and outputs the calculated weighting factor to the multiplication circuit 105. The multiplier circuit 105 multiplies the input soft decision signal b and the input weighting coefficient, and outputs a signal calculated by the multiplication to the adder circuit 106. The adder circuit 106 reads out a likelihood signal corresponding to the modulation signal b stored in the likelihood signal storage circuit 113, adds it to the signal input from the multiplier circuit 105, and adds a bit-wise likelihood signal (hereinafter, bit-wise likelihood). (Referred to as a degree signal) (step S104). In the initial state, since the likelihood signal storage circuit 113 does not store a bit-by-bit likelihood signal corresponding to the modulation signal b, the output of the adder circuit 106 is the same signal as the input signal.

  The adder circuit 106 causes the likelihood signal storage circuit 113 to store the calculated bit-wise likelihood signal as the bit-likelihood signal b corresponding to the modulation signal b via the output switching circuit 107 (step S105).

  Next, radio section 101 outputs detected modulation signal a ^ b to symbol / bit conversion circuit 102 and weighting coefficient extraction circuit 120 in response to detection of modulation signal a ^ b transmitted by relay terminal 20. (Step S106).

  The symbol / bit conversion circuit 102 performs symbol-bit conversion on the input modulation signal a b and outputs the bit sequence signal a b obtained by the conversion to the soft decision circuit 103. The soft decision circuit 103 performs a soft decision on the input bit sequence signal a ^ b and converts it into a soft decision signal a ^ b. The converted soft decision signal a ^ b is passed through the output switching circuit 104, The data is output to the sign / bit conversion circuit 110 and the absolute value extraction circuit 111. The code / bit conversion circuit 110 converts the code part of the input soft decision signal ab into a binary temporary bit signal ab of 0 and 1, and outputs it to the linear decoding circuit 114. The error correction code circuit 118 reads the bit signal a stored in the signal storage circuit 119, performs error correction coding on the read bit signal a, and outputs it to the linear decoding circuit 114 via the output switching circuit 117. The linear decoding circuit 114 decodes the temporary bit signal a ^ b input from the code / bit conversion circuit 110 using the error correction encoded bit signal a input from the output switching circuit 117 as a key signal, The temporary bit signal b is decoded (step S107).

  The linear decoding circuit 114 outputs the decoded temporary bit signal b to the bit / code conversion circuit 115. The bit / sign conversion circuit 115 converts the input temporary bit signal b into a sign in which 1 is positive and 0 is negative, and outputs a signal indicating the converted sign to the multiplication circuit 112. The absolute value extraction circuit 111 calculates an absolute value indicating the probability of the value of each bit of the input soft decision signal a ^ b, and outputs the calculated absolute value to the multiplication circuit 112. The multiplication circuit 112 multiplies the signal input from the bit / code conversion circuit 115 and the signal input from the absolute value extraction circuit 111, and outputs a signal indicating the result calculated by the multiplication to the multiplication circuit 105. The weighting coefficient extraction circuit 120 calculates a weighting coefficient from the modulation signal a ^ b input from the wireless unit 101 and outputs the calculated weighting coefficient to the multiplication circuit 105. The multiplication circuit 105 multiplies the signal input from the multiplication circuit 112 by the weighting coefficient input from the weighting coefficient extraction circuit 120, and outputs the bit-wise likelihood signal b calculated by the multiplication to the addition circuit 106 ( Step S108).

The adder circuit 106 reads the likelihood signal b stored when the modulated signal b is listened to in a timely manner in step S105, and adds it to the likelihood signal b input from the multiplier circuit 105 (step S109).
The adder circuit 106 outputs the bit-by-bit likelihood signal b that has been subjected to the maximum ratio synthesis by addition to the error correction decoding circuit 108 via the output switching circuit 107. The error correction decoding circuit 108 performs error correction decoding on the input bit-wise likelihood signal b, and obtains a bit signal b by decoding (step S110).

Next, the operation of the wireless communication system 1 will be described with reference to FIG.
First, the receiving terminal 10-1 modulates the bit signal a stored in its own terminal by the operations in steps S101 and S102, and transmits the modulated signal a to the relay terminal 20 (step S10).
At this time, in relay terminal 20, radio section 201 detects modulated signal a from the received signal, and outputs detected modulated signal a to symbol / bit conversion circuit 202 and weighting coefficient extraction circuit 211. The symbol / bit conversion circuit 202 performs symbol-bit conversion on the input modulation signal a, and outputs the bit series signal a obtained by the conversion to the soft decision circuit 203. The soft decision circuit 203 performs a soft decision on the input bit sequence signal a, converts it to the soft decision signal a, and outputs the soft decision signal a to the multiplication circuit 204. The weighting factor extraction circuit 211 calculates a weighting factor from the input modulation signal a, and outputs the calculated weighting factor to the multiplication circuit 204. The multiplication circuit 204 multiplies the soft decision signal a input from the soft decision circuit 203 by the weight coefficient input from the weight coefficient extraction circuit 211, and outputs a signal calculated by the multiplication to the error correction decoding circuit 205. The error correction decoding circuit 205 performs error correction decoding on the input signal, and outputs the decoded bit signal a to the signal storage circuit 207 via the output switching circuit 206 for storage.
Also, the receiving terminal 10-2 listens to the modulated signal a transmitted from the receiving terminal 10-1 toward the relay terminal 20 in a timely manner and stores it as a bit-wise likelihood signal a.

Next, at time T2, the receiving terminal 10-2 modulates the bit signal b stored in advance into the modulated signal b in the same manner as the operation performed by the receiving terminal 10-1 at time T1, and converts the modulated signal b to Transmit to the relay terminal 20. (Step S11).
At this time, the receiving terminal 10-1 performs the operations from step S103 to step S105, listens to the modulated signal b in a timely manner, and stores the bit-wise likelihood signal b.

  At time T2, in relay terminal 20, radio section 201 outputs detected modulation signal b to symbol / bit conversion circuit 202 and weighting coefficient extraction circuit 211 in response to detection of modulation signal b from the received signal. To do. The symbol / bit conversion circuit 202 performs symbol-bit conversion on the input modulation signal b, and outputs the bit series signal b obtained by the conversion to the soft decision circuit 203. The soft decision circuit 203 performs a soft decision on the input bit series signal b, converts it to the soft decision signal b, and outputs the soft decision signal b to the multiplication circuit 204. The weight coefficient extraction circuit 211 calculates a weight coefficient from the input modulation signal b and outputs the calculated weight coefficient to the multiplication circuit 204. The multiplication circuit 204 multiplies the soft decision signal b input from the soft decision circuit 203 by the weight coefficient input from the weight coefficient extraction circuit 211, and outputs a signal calculated by the multiplication to the error correction decoding circuit 205. The error correction decoding circuit 205 performs error correction decoding on the input signal, and outputs the decoded bit signal b to the signal storage circuit 207 via the output switching circuit 206 for storage.

  Subsequently, at time T3, in relay terminal 20, linear encoding circuit 208 reads bit signal a and bit signal b stored in signal storage circuit 207, performs network encoding, and obtains a bit signal obtained by network encoding. a ^ b is output to the error correction code circuit 209. The error correction encoding circuit 209 performs error correction encoding on the signal input from the linear encoding circuit 208 by a predetermined method, and outputs the error correction encoded signal to the modulation circuit 210. The modulation circuit 210 performs a predetermined modulation on the signal input from the error correction code circuit 209 to obtain a modulation signal a ^ b. Also, the modulation circuit 210 transmits the modulated signal a ^ b to the receiving terminal 10-1 and the receiving terminal 10-2 (step S12).

At time T3, the receiving terminal 10-1 performs the operations from step S106 to step S110. That is, the receiving terminal 10-1 receives the modulation signal a ^ b transmitted from the step relay terminal 20, and decodes the network code a ^ b. Further, the receiving terminal 10-1 combines the bit-likelihood signal b obtained by decoding and the bit-likelihood signal b stored in step S105 with a maximum ratio, and performs error correction decoding to obtain the bit signal b. Demodulate.
Similarly, in the receiving terminal 10-2, the modulated signal a ^ b is converted into a soft decision signal, and a bit-wise likelihood signal a is obtained by decoding using the bit signal b stored in the terminal itself. Maximum ratio combining and error correction decoding are performed on the bit-by-bit likelihood signal a, and the bit signal a is demodulated.

With the above operation, in the wireless communication system 1 having the Alice & Bob topology configuration, the relay terminal 20 applies the network code to the bit signals stored in the receiving terminals 10-1 and 10-2 located at both ends of the topology. To transmit.
Using the broadcast property of wireless communication, the receiving terminal 10-2 listens to the modulated signal a at time T1, and the receiving terminal 10-1 listens to the modulated signal b at time T2, and stores them as likelihood signals. To do. As a result, the maximum ratio combining can be performed with the signal obtained by linearly decoding the modulated signal a ^ b transmitted from the relay terminal 20 at time T3, and the communication quality at the receiving terminals 10-1 and 10-2 can be improved by the diversity effect. Become.

  Note that the transmission of the bit signal a from the reception terminal 10-1 to the relay terminal 20 and the transmission of the bit signal b from the reception terminal 10-2 to the relay terminal 20 are shown by dividing time. However, it may be performed simultaneously by transmitting using different frequency channels.

(Second Embodiment)
FIG. 5 is a schematic block diagram showing the internal configuration of the relay terminal 20a in the second embodiment. The relay terminal 20 according to the first embodiment is different in that it has a function of listening to a signal to be subjected to network coding in a timely manner, storing it as a likelihood signal, and performing maximum ratio combining. Therefore, the relay terminal 20a has the same configuration as that of the relay terminal 20 of the first embodiment except for the adder circuit 212, the output switching circuit 213, and the likelihood signal storage circuit 214. The adder circuit 212, the output switching circuit 213, and the likelihood signal storage circuit 214 will be described.

  The adder circuit 212 adds the two input likelihood signals and outputs the result. The output switching circuit 213 outputs the input signal to the likelihood signal storage circuit 214 when listening timely and storing it as a likelihood signal. When receiving the signal to be network encoded and relayed, the output switching circuit 213 gives an error to the input signal. The data is output to the correction decoding circuit 205. The likelihood signal storage circuit 214 stores an input likelihood signal.

FIG. 6 is a schematic diagram showing a new wireless communication system 1a having a chain topology configuration that is an extension of the Alice & Bob topology of the first embodiment of the second embodiment. The wireless communication system 1a has a configuration in which a receiving terminal 10-3, a receiving terminal 10-4, a relay terminal 20a, a receiving terminal 10-5, and a receiving terminal 10-6 are arranged in this order. It is assumed that the receiving terminal 10-3 stores the bit signal a and the receiving terminal 10-6 stores the bit signal b. Similarly to the first embodiment, network coding performed by the relay terminal 20a uses exclusive OR.
Hereinafter, the bit signal a and the bit signal b stored between the receiving terminal 10-3 and the receiving terminal 10-6 arranged at both ends are referred to as the receiving terminal 10-4, the relay terminal 20a, and the receiving terminal 10-5. The operations of the receiving terminal 10-3, the receiving terminal 10-4, and the relay terminal 20a when performing the transmission operation will be described with reference to flowcharts.

(Operation of the receiving terminal 10-3 in the chain topology of the second embodiment)
FIG. 7 is a flowchart illustrating the operation of the receiving terminal 10-3 according to the second embodiment. In the second embodiment, the transmission operation is started by the operation of the receiving terminal 10-3.

The error correction code circuit 118 reads the bit signal a stored in the reception signal storage circuit 119 in advance, converts it to an error correction code, and outputs it to the modulation circuit 116 via the output switching circuit 117. The modulation circuit 116 modulates the input signal and outputs the modulated signal a to the wireless unit 101 (step S201).
The wireless unit 101 transmits the input modulated signal a to the receiving terminal 10-4 (step S202).

The receiving terminal 10-3 waits until the relay terminal 20a transmits the modulated signal a ^ b to the receiving terminal 10-4 (step S203).
Radio section 101 extracts modulated signal a ^ b from the received signal in response to reception of modulated signal a ^ b transmitted from relay terminal 20a to receiving terminal 10-4, symbol / bit conversion circuit 102 and weight The detected modulation signal a ^ b is output to the coefficient extraction circuit 120. That is, timely listening is started (step S204).

  The symbol / bit conversion circuit 102 performs symbol-bit conversion on the input modulation signal a ^ b to convert it into a bit series signal a ^ b, and outputs the bit series signal a ^ b to the soft decision circuit 103. The soft decision circuit 103 performs a soft decision on the bit series signal a ^ b input from the symbol / bit conversion circuit 102 and converts it to a soft decision signal a ^ b. The soft decision signal a ^ b is output to the output switching circuit 104. To the sign / bit conversion circuit 110 and the absolute value extraction circuit 111. The code / bit conversion circuit 110 converts the code part of the input soft decision signal ab into a binary temporary bit signal ab of 0 and 1, and outputs it to the linear decoding circuit 114. The error correction code circuit 118 reads the bit signal a stored in advance by the signal storage circuit 119, performs error correction coding on the read bit signal a, and outputs it to the linear decoding circuit 114 via the output switching circuit 117. The linear decoding circuit 114 decodes the temporary bit signal a ^ b input from the code / bit conversion circuit 110 using the bit signal a input from the output switching circuit 117 as a key signal, and outputs the temporary bit signal b. Decoding is performed (step S205).

  The linear decoding circuit 114 outputs the decoded temporary bit signal b to the bit / code conversion circuit 115. The bit / sign conversion circuit 115 converts the input temporary bit signal b into a sign in which 1 is positive and 0 is negative, and outputs a signal indicating the converted sign to the multiplication circuit 112. The absolute value extraction circuit 111 calculates an absolute value indicating the probability of the value of each bit of the input soft decision signal a ^ b, and outputs the calculated absolute value to the multiplication circuit 112. The multiplication circuit 112 multiplies the signal input from the bit / code conversion circuit 115 and the signal input from the absolute value extraction circuit 111, and outputs a signal indicating the result calculated by the multiplication to the multiplication circuit 105. The weighting coefficient extraction circuit 120 calculates a weighting coefficient from the modulation signal a ^ b input from the wireless unit 101 and outputs the calculated weighting coefficient to the multiplication circuit 105. The multiplication circuit 105 multiplies the signal input from the multiplication circuit 112 by the weighting coefficient input from the weighting coefficient extraction circuit 120, and outputs the bit-wise likelihood signal b calculated by the multiplication to the addition circuit 106 ( Step S206).

  The adder circuit 106 reads out the bit-by-bit likelihood signal b stored in the likelihood signal storage circuit 113 and adds it to the signal input from the multiplier circuit 105. Further, the adder circuit 106 outputs the calculated signal to the likelihood signal storage circuit 113 via the output switching circuit 107, and stores it as a new bit-by-bit likelihood signal b (step S207). In the initial state, since the likelihood signal storage circuit 113 does not store the likelihood signal b, there is no signal read by the adder circuit 106, and the signal input from the multiplier circuit 105 is output as it is. Become.

  Next, radio section 101 detects modulated signal b in response to receiving modulated signal b transmitted from receiving terminal 10-4 to receiving terminal 10-3, and detects detected modulated signal b as a symbol. Output to the bit conversion circuit 102 and the weight coefficient extraction circuit 120 (step S208).

  The symbol / bit conversion circuit 102 performs symbol-bit conversion on the input modulation signal b to convert it to a bit series signal b, and outputs the bit series signal b to the soft decision circuit 103. The soft decision circuit 103 performs a soft decision on the bit series signal b input from the symbol / bit conversion circuit 102 and converts the bit sequence signal b into a soft decision signal b. The soft decision signal b is multiplied by the multiplication circuit 105 via the output switching circuit 104. Output to. The weighting factor extraction circuit 120 calculates a weighting factor from the modulation signal b input from the wireless unit 101 and outputs the calculated weighting factor to the multiplication circuit 105. The multiplication circuit 105 multiplies the input soft decision signal b and the input weighting factor, and outputs a signal calculated by the multiplication to the addition circuit 106 (step S209).

The adder circuit 106 reads out the likelihood signal corresponding to the modulation signal b stored in the likelihood signal storage circuit 113, adds it to the signal input from the multiplier circuit 105, and synthesizes the maximum ratio (step S210).
Further, the adder circuit 106 outputs the calculated signal to the error correction decoding circuit 108 via the output switching circuit 107. The error correction decoding circuit 108 performs error correction decoding on the input signal and decodes the bit signal b. Further, the error correction decoding circuit 108 outputs the decoded bit signal b as an output signal via the output switching circuit 109 (step S211).
The operation of the receiving terminal 10-6 is the same as the operation order of the receiving terminal 10-3, but the operations of step S201 and step S202 are performed on the bit signal b. Further, the operations from step S205 to step S207 are performed using the bit signal b stored in the terminal itself. In the operation after step S208, the modulated signal a is received, converted into a bit-by-bit likelihood signal, and error correction decoding is performed.

(Operation of the receiving terminal 10-4 in the chain topology of the second embodiment)
Next, FIG. 8 is a flowchart showing the operation of the receiving terminal 10-4 in the second embodiment.

  First, the radio unit 101 detects the modulation signal a in response to receiving the modulation signal a transmitted from the reception terminal 10-3 to the reception terminal 10-4, and converts the detected modulation signal a into symbol / bit conversion. The data is output to the circuit 102 and the weight coefficient extraction circuit 120 (step S221).

  The symbol / bit conversion circuit 102 performs symbol-bit conversion on the input modulation signal a to convert it to the bit sequence signal a, and outputs the bit sequence signal a to the soft decision circuit 103. The soft decision circuit 103 performs a soft decision on the bit series signal a input from the symbol / bit conversion circuit 102 and converts the bit sequence signal a into the soft decision signal a. The soft decision signal a is output to the multiplication circuit 105 via the output switching circuit 104. Output to. The weighting factor extraction circuit 120 calculates a weighting factor from the modulation signal a input from the wireless unit 101 and outputs the calculated weighting factor to the multiplication circuit 105. The multiplication circuit 105 multiplies the input soft decision signal a and the input weight coefficient, and outputs a signal calculated by the multiplication to the addition circuit 106. The adder circuit 106 reads out the likelihood signal corresponding to the modulation signal a stored in the likelihood signal storage circuit 113, adds the signal to the signal input from the multiplier circuit 105, and generates an error via the output switching circuit 107. The data is output to the correction decoding circuit 108. In the initial state, since the likelihood signal storage circuit 113 does not store a likelihood signal corresponding to the modulation signal a, the output of the adder circuit 106 is the same signal as the input signal. The error correction decoding circuit 108 performs error correction decoding on the likelihood signal input via the output switching circuit 107, and decodes the bit signal a (step S222).

In addition, the error correction decoding circuit 108 outputs the decoded bit signal a to the signal storage circuit 119 for storage (step S223).
In response to the reception terminal 10-6 having finished transmitting the modulated signal b, in the reception terminal 10-4, the error correction code circuit 118 reads the bit signal a stored in the reception signal storage circuit 119, and an error occurs. It is corrected and outputted to the modulation circuit 116 via the output switching circuit 117. The modulation circuit 116 modulates the input signal and outputs the modulated signal a to the radio unit 101 (step S224).
The radio unit 101 transmits the input modulated signal a toward the relay terminal 20a (step S225).

  The radio unit 101 outputs the modulation signal b to the symbol / bit conversion circuit 102 and the weight coefficient extraction circuit 120 in response to detecting the modulation signal b transmitted from the reception terminal 10-5 to the relay terminal 20a. That is, the receiving terminal 10-4 performs timely listening (step S226).

The symbol / bit conversion circuit 102 performs symbol-bit conversion on the input modulation signal b to convert it to a bit series signal b, and outputs the bit series signal b to the soft decision circuit 103. The soft decision circuit 103 performs a soft decision on the bit series signal b input from the symbol / bit conversion circuit 102 and converts the bit sequence signal b into a soft decision signal b. The soft decision signal b is multiplied by the multiplication circuit 105 via the output switching circuit 104. Output to. The weighting factor extraction circuit 120 calculates a weighting factor from the modulation signal b input from the wireless unit 101 and outputs the calculated weighting factor to the multiplication circuit 105. The multiplier circuit 105 multiplies the input soft decision signal b and the input weighting coefficient, and outputs a signal calculated by the multiplication to the adder circuit 106. The adder circuit 106 reads out a bit-by-bit likelihood signal corresponding to the modulation signal b stored in the likelihood signal storage circuit 113 and adds it to the signal input from the multiplier circuit 105 (step S227).
The adder circuit 106 causes the likelihood signal storage circuit 113 to store the calculated likelihood signal as the bit-wise likelihood signal b corresponding to the modulation signal b via the output switching circuit 107 (step S228).

  Next, the radio unit 101 detects the modulated signal a ^ b transmitted from the relay terminal 20a toward the terminal itself, and detects the detected modulated signal a ^ b using the symbol / bit conversion circuit 102 and the weighting coefficient. The data is output to the extraction circuit 120 (step S229).

  The symbol / bit conversion circuit 102 performs symbol-bit conversion on the input modulation signal a b and outputs the bit sequence signal a b obtained by the conversion to the soft decision circuit 103. The soft decision circuit 103 performs a soft decision on the input bit sequence signal a ^ b and converts it into a soft decision signal a ^ b. The converted soft decision signal a ^ b is passed through the output switching circuit 104, The data is output to the sign / bit conversion circuit 110 and the absolute value extraction circuit 111. The code / bit conversion circuit 110 converts the code part of the input soft decision signal ab into a binary temporary bit signal ab of 0 and 1, and outputs it to the linear decoding circuit 114. The error correction code circuit 118 reads the bit signal a stored in the signal storage circuit 119, performs error correction coding on the read bit signal a, and outputs it to the linear decoding circuit 114 via the output switching circuit 117. The linear decoding circuit 114 decodes the temporary bit signal a ^ b input from the code / bit conversion circuit 110 using the bit signal a input from the output switching circuit 117 as a key signal, and outputs the temporary bit signal b. Decoding is performed (step S230).

  The linear decoding circuit 114 outputs the decoded temporary bit signal b to the bit / code conversion circuit 115. The bit / sign conversion circuit 115 converts the input temporary bit signal b into a sign in which 1 is positive and 0 is negative, and outputs a signal indicating the converted sign to the multiplication circuit 112. The absolute value extraction circuit 111 calculates an absolute value indicating the probability of the value of each bit of the input soft decision signal a ^ b, and outputs the calculated absolute value to the multiplication circuit 112. The multiplication circuit 112 multiplies the signal input from the bit / code conversion circuit 115 and the signal input from the absolute value extraction circuit 111, and outputs a signal indicating the result calculated by the multiplication to the multiplication circuit 105. The weighting coefficient extraction circuit 120 calculates a weighting coefficient from the modulation signal a ^ b input from the wireless unit 101 and outputs the calculated weighting coefficient to the multiplication circuit 105. The multiplication circuit 105 multiplies the signal input from the multiplication circuit 112 by the weighting coefficient input from the weighting coefficient extraction circuit 120, and outputs a bit-wise likelihood signal b calculated by multiplication to the addition circuit 106. The adder circuit 106 reads out the bit-wise likelihood signal b stored in the likelihood signal storage circuit 113 obtained by timely listening in step S228 and adds it to the likelihood signal b input from the multiplier circuit 105 (step S231). .

  The adder circuit 106 outputs the likelihood signal b, which has been subjected to the maximum ratio synthesis by the addition, to the error correction decoding circuit 108 via the output switching circuit 107. The error correction decoding circuit 108 performs error correction decoding on the input bit-wise likelihood signal b, and obtains a bit signal b by decoding (step S232).

  The error correction decoding circuit 108 outputs the decoded bit signal b to the signal storage circuit 119 via the output switching circuit 109, and stores the bit signal b in the signal storage circuit 119 (step S234).

Subsequently, the error correction code circuit 118 reads the bit signal b stored in the reception signal storage circuit 119, converts it to an error correction code, and outputs it to the modulation circuit 116 via the output switching circuit 117. The modulation circuit 116 modulates the input signal and outputs the modulated signal b to the radio unit 101 (step S235).
The radio unit 101 transmits the input modulated signal b to the receiving terminal 10-3 (step S236).

  Thus, the operation of the signal receiving terminal 10-4 is completed between the receiving terminal 10-3 and the relay terminal 20a in the transmission in the chain topology. In the receiving terminal 10-5, the processing from step S221 to step S223 is performed on the received modulated signal b. Prior to steps S224 and 225, operations from step S226 to step S228 are performed on the modulation signal b. Further, after completion of steps S226 to S228, steps S224 to S225 are performed on the bit signal b stored in the signal storage circuit 119. The operations from step S231 to step S236 are performed using the bit signal b stored in the signal storage circuit 119 as a key signal.

(Operation of the relay terminal 20a in the chain topology of the second embodiment)
Next, FIG. 9 is a flowchart showing the operation of the relay terminal 20a in the second embodiment.

  First, in response to detecting the modulation signal a transmitted from the reception terminal 10-3 to the reception terminal 10-4 in the relay terminal 20a, the radio unit 201 performs symbol / bit conversion on the detected modulation signal a. The data is output to the circuit 202 and the weight coefficient extraction circuit 211. That is, the relay terminal 20a listens to the modulated signal a in a timely manner (step S241).

  The symbol / bit conversion circuit 202 performs symbol-bit conversion on the modulation signal a input from the radio unit 201 to convert it to the bit sequence signal a, and outputs the bit sequence signal a to the soft decision circuit 203. The soft decision circuit 203 performs a soft decision on the bit series signal a input from the symbol / bit conversion circuit 202, converts the bit sequence signal a into the soft decision signal a, and outputs the soft decision signal a to the multiplication circuit 204. The weight coefficient extraction circuit 211 calculates a weight coefficient from the modulation signal a input from the wireless unit 201 and outputs the calculated weight coefficient to the multiplication circuit 204. The multiplier circuit 204 multiplies the input soft decision signal a and the input weight coefficient, and outputs a signal calculated by the multiplication to the adder circuit 106 (step S242).

  The adder circuit 212 reads and adds the bit-by-bit likelihood signal a input from the multiplier circuit 204 and the bit-by-bit likelihood signal a stored in the likelihood signal storage circuit 214. Further, the adding circuit 212 outputs the calculated signal to the likelihood signal storage circuit 214 via the output switching circuit 213, and stores it as the bit-wise likelihood signal a (step S243). When the bit-wise likelihood signal a is not stored in the likelihood signal storage circuit 214, the adder circuit 212 outputs the likelihood signal a input from the multiplication circuit 204 as it is.

Next, in response to detecting the modulated signal b transmitted from the receiving terminal 10-6 to the receiving terminal 10-5, the radio unit 201 extracts the detected modulated signal b from the symbol / bit conversion circuit 202 and the weighting coefficient extractor. Output to the circuit 211. That is, the relay terminal 20a listens to the modulated signal b in a timely manner (step S244).
The symbol / bit conversion circuit 202 performs symbol-bit conversion on the modulation signal b input from the radio unit 201 to convert it to the bit sequence signal b, and outputs the bit sequence signal b to the soft decision circuit 203. The soft decision circuit 203 performs a soft decision on the bit series signal b input from the symbol / bit conversion circuit 202, converts the bit sequence signal b into the soft decision signal b, and outputs the soft decision signal b to the multiplication circuit 204. The weighting factor extraction circuit 211 calculates a weighting factor from the modulation signal b input from the wireless unit 201 and outputs the calculated weighting factor to the multiplication circuit 204. The multiplier circuit 204 multiplies the input soft decision signal b and the input weighting coefficient, and outputs the signal calculated by the multiplication to the adder circuit 212 (step S245).

  The adder circuit 212 reads and adds the likelihood signal b input from the multiplier circuit 204 and the bit-wise likelihood signal b stored in the likelihood signal storage circuit 214. Further, the adder circuit 212 outputs the calculated signal to the likelihood signal storage circuit 214 via the output switching circuit 213, and stores it as a bit-by-bit likelihood signal b (step S246).

  Next, in response to detecting the modulated signal a transmitted from the receiving terminal 10-4 to the relay terminal 20a, the radio unit 201 detects the detected modulated signal a as a symbol / bit conversion circuit 202 and a weight coefficient extraction circuit 211. (Step S247).

  The symbol / bit conversion circuit 202 performs symbol-bit conversion on the input modulation signal a to convert it to the bit sequence signal a, and outputs the bit sequence signal a to the soft decision circuit 203. The soft decision circuit 203 performs a soft decision on the bit series signal a input from the symbol / bit conversion circuit 202, converts the bit sequence signal a into the soft decision signal a, and outputs the soft decision signal a to the multiplication circuit 204. The weight coefficient extraction circuit 211 calculates a weight coefficient from the modulation signal a input from the wireless unit 201 and outputs the calculated weight coefficient to the multiplication circuit 204. The multiplication circuit 204 multiplies the input soft decision signal a and the input weighting coefficient, and outputs a signal calculated by the multiplication to the addition circuit 212. As a result, the modulation signal a is converted into a bit-by-bit likelihood signal (step S248).

The adder circuit 212 reads and adds the likelihood signal a input from the multiplier circuit 204 and the likelihood signal a stored in the likelihood signal storage circuit 214, and performs maximum ratio combining (step S249).
The adder circuit 212 outputs the calculated signal to the error correction decoding circuit 205 via the output switching circuit 213. The error correction decoding circuit 205 performs error correction decoding on the input signal, and error correction decodes the bit signal a (step S250).
Further, the error correction decoding circuit 205 outputs the decoded bit signal a to the signal storage circuit 207 via the output switching circuit 206, and stores the bit signal a in the signal storage circuit 207 (step S251).

  Next, in response to detecting the modulated signal b transmitted from the receiving terminal 10-5 to the relay terminal 20a, the radio unit 201 detects the detected modulated signal b as a symbol / bit conversion circuit 202 and a weighting factor extraction circuit 211. (Step S252).

  The symbol / bit conversion circuit 202 performs symbol-bit conversion on the input modulation signal b to convert it to a bit series signal b, and outputs the bit series signal b to the soft decision circuit 203. The soft decision circuit 203 performs a soft decision on the bit series signal b input from the symbol / bit conversion circuit 202, converts the bit sequence signal b into the soft decision signal b, and outputs the soft decision signal b to the multiplication circuit 204. The weighting factor extraction circuit 211 calculates a weighting factor from the modulation signal b input from the wireless unit 201 and outputs the calculated weighting factor to the multiplication circuit 204. The multiplication circuit 204 multiplies the input soft decision signal b and the input weight coefficient, and outputs a signal calculated by the multiplication to the addition circuit 212. Thereby, the modulation signal b is converted into a bit-by-bit likelihood signal (step S253).

The adder circuit 212 reads and adds the bit-by-bit likelihood signal b input from the multiplier circuit 204 and the bit-by-bit likelihood signal b stored in the likelihood signal storage circuit 214, and performs maximum ratio combining (step S254).
The adder circuit 212 outputs the calculated signal to the error correction decoding circuit 205 via the output switching circuit 213. The error correction decoding circuit 205 performs error correction decoding on the input signal, and error correction decodes the bit signal b (step S256).
Further, the error correction decoding circuit 205 outputs the decoded bit signal b to the signal storage circuit 207 via the output switching circuit 206, and stores the bit signal b in the signal storage circuit 207 (step S256).

Subsequently, the linear encoding circuit 208 reads the bit signal a and the bit signal b stored in the signal storage circuit 207 and performs network encoding on the read bit signal a and bit signal b, that is, exclusive OR. An arithmetic operation is performed to calculate the bit signal a ^ b (step S257).
The linear encoding circuit 208 outputs the calculated bit signal a ^ b to the error correction encoding circuit 209. The error correction code circuit 209 performs error correction coding on the input bit signal a ^ b and outputs the result to the modulation circuit 210. The modulation circuit 210 modulates the signal input from the error correction code circuit 209, and outputs the modulation signal a ^ b obtained by the modulation to the radio unit 201 (step S258).
The radio unit 201 transmits the input modulation signal a ^ b to the receiving terminal 10-4 and the receiving terminal 10-5 (step S259).
This completes the operation of the relay terminal 20a in transmission in the chain topology.

(Operation of the wireless communication system 1a in the chain topology of the second embodiment)
Next, the overall operation of the new wireless communication system 1a will be described with reference to FIG.
First, at time T1, the receiving terminal 10-3 modulates the bit signal a stored in the own terminal and transmits it to the receiving terminal 10-4 (step S21). The receiving terminal 10-4 receives the modulated signal a and stores the bit signal a obtained by demodulation as a key signal used for network decoding. At this time, the relay terminal 20a listens to the received modulated signal a in a timely manner and stores it as a likelihood signal a.
The operation of the receiving terminal 10-3 corresponds to the operations up to step S201 and step S202 in FIG. The operation of the receiving terminal 10-4 corresponds to the operation from step S221 to step S223 in FIG. The operation of the relay terminal 20a corresponds to the operations from step S241 to step S243 in FIG.

At time T2, the receiving terminal 10-6 modulates the bit signal b stored by itself and transmits it to the receiving terminal 10-5 (step S22). The receiving terminal 10-5 receives the modulated signal b, and stores the bit signal b obtained by demodulation as a key signal used for network decoding. At this time, the relay terminal 20a listens to the received modulated signal b in a timely manner and stores it as a bit-by-bit likelihood signal b.
The operation of the relay terminal 20a corresponds to the operations from step S244 to step S246 in FIG.

At time T3, the receiving terminal 10-4 modulates the stored bit signal a and transmits the modulated signal a to the relay terminal 20a (step S23). The relay terminal 20a performs maximum ratio combining on the received modulated signal a using the bit-wise likelihood signal a stored at time T1, and demodulates the bit signal a. At this time, the receiving terminal 10-5 listens to the received modulated signal a as appropriate, and stores it as a bit-by-bit likelihood signal a.
The operation of the receiving terminal 10-4 corresponds to the operations up to step S224 and step S225 in FIG. The operation of the relay terminal 20a corresponds to the operation from step S247 to step S251 in FIG.

At time T4, the receiving terminal 10-5 modulates the stored bit signal b and transmits the modulated signal b to the relay terminal 20a (step S24). The relay terminal 20a performs maximum ratio combining on the received modulated signal b using the bit-wise likelihood signal b stored at time T2, and demodulates the bit signal b. At this time, the receiving terminal 10-4 listens to the received modulated signal b in a timely manner and stores it as a bit-wise likelihood signal b.
The operation of the relay terminal 20a corresponds to the operation from step S252 to step S256 in FIG. The operation of the receiving terminal 10-4 corresponds to the operations from step S226 to step S228 in FIG.

At time T5, the relay terminal 20a performs network coding on the stored bit signal a and bit signal b, and transmits them to the receiving terminal 10-4 and the receiving terminal 10-5 (step S25). The receiving terminal 10-4 receives the modulated signal a ^ b, performs network decoding using the stored bit signal a, further performs maximum ratio combining using the stored bit-wise likelihood signal b, The signal b is demodulated and stored. The receiving terminal 10-5 receives the modulated signal a ^ b, performs network decoding using the stored bit signal b, further performs maximum ratio combining using the stored bit-wise likelihood signal a, Demodulate and store signal a.
At this time, the receiving terminal 10-3 listens to the modulated signal a ^ b in a timely manner, performs network decoding using the stored bit signal a, and stores the obtained bit-wise likelihood signal b. Similarly to the receiving terminal 10-3 and the like, the receiving terminal 10-6 listens to the modulated signal a ^ b in a timely manner, performs network decoding using the stored bit signal b, and stores the obtained bit-wise likelihood signal a. To do.
The operation of the relay terminal 20a corresponds to the operation from step S257 to step S259 in FIG. The operation of the receiving terminal 10-4 corresponds to the operations from step S229 to step S234 in FIG. The operation of the receiving terminal 10-3 corresponds to the operations from step S204 to step S207 in FIG.

At time T6, the receiving terminal 10-4 modulates the stored bit signal b, and transmits the modulated signal b to the receiving terminal 10-3 (step S26). The receiving terminal 10-3 receives the modulated signal b, performs maximum ratio combining with the stored bit-wise likelihood signal b, and demodulates the bit signal b by performing error correction decoding. At time T6, the receiving terminal 10-5 modulates the stored bit signal a, and transmits the modulated signal a to the receiving terminal 10-6 (step S27). The receiving terminal 10-6 receives the modulated signal a, performs maximum ratio combining with the stored bit-wise likelihood signal a, and demodulates the bit signal a by performing error correction decoding.
The operation of the receiving terminal 10-4 corresponds to the operation between step S235 and step S236 in FIG. The operation of the receiving terminal 10-3 corresponds to the operations from step S208 to step S211.

Through the above operation, the receiving terminal 10-3 transmits the bit signal a held by the receiving terminal 10-3 to the receiving terminal 10-6 via the receiving terminal 10-4, the relay terminal 20a, and the receiving terminal 10-5. In addition, the receiving terminal 10-6 transmits the bit signal b held by itself to the receiving terminal 10-3 via the receiving terminal 10-5, the relay terminal 20a, and the receiving terminal 10-4.
Even if each receiving terminal listens in a timely manner and the communication quality of the radio link between the terminals that directly transmit and receive signals deteriorates, the maximum ratio combining is applied using the likelihood signal stored in the terminal. Therefore, it is possible to prevent deterioration of communication quality.

(Third embodiment)
FIG. 10 is a diagram illustrating a radio communication system 1b having the X topology configuration of the third embodiment and the operation. The radio communication system 1b includes transmission terminals 30-1 and 30-2, a relay terminal 20, and reception terminals 10-7 and 10-8.
The transmission terminal 30-1 is a terminal that stores a bit signal a and has a function of performing error correction coding and modulation used in a wireless communication system and transmitting the bit signal a. The transmission terminal 30-2 is a terminal that stores the bit signal b and has a function of performing error correction coding and modulation used in the wireless communication system and transmitting the bit signal b. The receiving terminal 10-7 and the receiving terminal 10-8 have the same configuration as that of the receiving terminal 10 described above, and represent one or both of the receiving terminal 10-7 and the receiving terminal 10-8 below. Is referred to as a receiving terminal 10. The relay terminal 20 is the relay terminal 20 of FIG. 2 shown in the first embodiment.

  In the transmission in the X topology of the third embodiment, since the receiving terminals 10-7 and 10-8 do not store the key signal in advance, it is necessary to acquire the key signal by transmission. The relay terminal 20 receives the bit signal a and the bit signal b from the transmission terminals 30-1 and 30-2, performs network coding, and receives a modulated signal a ^ b that has been subjected to network coding and modulation as a reception terminal 10-7, Send to 10-8.

(Operation of the receiving terminal 10-7 in the X topology of the third embodiment)
FIG.11 and FIG.12 is a flowchart figure which shows operation | movement of the receiving terminal 10-7 in 3rd Embodiment.
First, the radio unit 101 of the receiving terminal 10-7 detects the modulated signal a addressed to the relay terminal 20 from the received signal, and detects the detected modulated signal a using the symbol / bit conversion circuit 102 and the weighting coefficient extracting circuit 120. Output to. That is, the receiving terminal 10-7 performs timely listening (step S301).

  The symbol / bit conversion circuit 102 performs symbol-bit conversion on the input modulation signal a to convert it to the bit sequence signal a, and outputs the bit sequence signal a to the soft decision circuit 103. The soft decision circuit 103 performs a soft decision on the bit series signal a input from the symbol / bit conversion circuit 102 and converts the bit sequence signal a into the soft decision signal a. The soft decision signal a is output to the multiplication circuit 105 via the output switching circuit 104. Output to. The weighting factor extraction circuit 120 calculates a weighting factor from the modulation signal a input from the wireless unit 101 and outputs the calculated weighting factor to the multiplication circuit 105. The multiplication circuit 105 multiplies the input soft decision signal a and the input weight coefficient, and outputs a signal calculated by the multiplication to the addition circuit 106. The adder circuit 106 reads out a likelihood signal corresponding to the modulation signal a stored in the likelihood signal storage circuit 113, adds it to the signal input from the multiplier circuit 105, and converts it into a bit-wise likelihood signal (step S302). . Since likelihood signal storage circuit 113 does not store a likelihood signal corresponding to modulated signal a, adder circuit 106 outputs the input signal without any change.

  The adder circuit 106 causes the likelihood signal storage circuit 113 to store the calculated bit likelihood signal as the bit likelihood signal a corresponding to the modulation signal a via the output switching circuit 107 (step S303).

  Next, in response to the detection of the modulated signal b transmitted from the transmission terminal 30-2 to the relay terminal 20, the wireless unit 101 detects the detected modulated signal b as a symbol / bit conversion circuit 102 and a weight coefficient extraction circuit 120. Output to. That is, the receiving terminal 10-7 performs timely listening (step S304).

  The symbol / bit conversion circuit 102 performs symbol-bit conversion on the input modulation signal b to convert it to a bit series signal b, and outputs the bit series signal b to the soft decision circuit 103. The soft decision circuit 103 performs a soft decision on the bit series signal b input from the symbol / bit conversion circuit 102 and converts the bit sequence signal b into a soft decision signal b. The soft decision signal b is multiplied by the multiplication circuit 105 via the output switching circuit 104. Output to. The weighting factor extraction circuit 120 calculates a weighting factor from the modulation signal b input from the wireless unit 101 and outputs the calculated weighting factor to the multiplication circuit 105. The multiplier circuit 105 multiplies the input soft decision signal b and the input weighting coefficient, and outputs a signal calculated by the multiplication to the adder circuit 106. The adder circuit 106 reads out the likelihood signal corresponding to the modulation signal b stored in the likelihood signal storage circuit 113, adds it to the signal input from the multiplier circuit 105, and converts it into a bit-wise likelihood signal (step S305). . Since the likelihood signal storage circuit 113 does not store a bit-by-bit likelihood signal corresponding to the modulation signal b, the adder circuit 106 outputs the input signal without any change.

  The adder circuit 106 causes the likelihood signal storage circuit 113 to store the calculated bit-wise likelihood signal as the bit-likelihood signal b corresponding to the modulation signal b via the output switching circuit 107 (step S306).

  Subsequently, the radio unit 101 detects the modulated signal a ^ b transmitted from the relay terminal 20 to the own terminal, and extracts the detected modulated signal a ^ b from the symbol / bit conversion circuit 102 and the weighting coefficient. The data is output to the circuit 120 (step S307).

  The symbol / bit conversion circuit 102 performs symbol-bit conversion on the input modulation signal a ^ b to convert it to a bit sequence signal a ^ b, and outputs the bit sequence signal a ^ b to the soft decision circuit 103. The soft decision circuit 103 performs a soft decision on the bit series signal a ^ b input from the symbol / bit conversion circuit 102 and converts it to a soft decision signal a ^ b. The soft decision signal a ^ b is output to the output switching circuit 104. To the multiplication circuit 105. The weighting coefficient extraction circuit 120 calculates a weighting coefficient from the modulation signal a ^ b input from the wireless unit 101 and outputs the calculated weighting coefficient to the multiplication circuit 105. The multiplication circuit 105 multiplies the input soft decision signal a ^ b and the input weighting coefficient, and outputs a signal calculated by the multiplication to the addition circuit 106. The adder circuit 106 reads out the likelihood signal corresponding to the modulation signal a ^ b stored in the likelihood signal storage circuit 113, adds it to the signal input from the multiplier circuit 105, and converts it into a bit-wise likelihood signal (step). S308). Since the likelihood signal storage circuit 113 does not store a likelihood signal corresponding to the modulation signal a ^ b, the adder circuit 106 outputs the input signal without any change.

  The adder circuit 106 causes the likelihood signal storage circuit 113 to store the calculated bit-wise likelihood signal as the bit-likelihood signal a ^ b corresponding to the modulation signal a ^ b via the output switching circuit 107 (step S309). ). With the operation so far, the likelihood signal storage circuit 113 of the receiving terminal 10-7 stores the bit-wise likelihood signals a, b, a ^ b.

  The likelihood signal storage circuit 113 outputs the stored bit-by-bit likelihood signal a to the error correction decoding circuit 108. The error correction decoding circuit 108 performs error correction decoding processing on the input bit-wise likelihood signal, and outputs and stores the bit signal a in the signal storage circuit 119 via the output switching circuit 109. Further, the error correction decoding circuit 108 feeds back to the likelihood signal storage circuit 113 whether or not the bit signal a has been correctly decoded (step S310).

  The likelihood signal storage circuit 113 outputs the stored bit-by-bit likelihood signal b to the error correction decoding circuit 108. The error correction decoding circuit 108 performs error correction decoding processing on the input bit-wise likelihood signal and outputs the bit signal b to the signal storage circuit 119 via the output switching circuit 109 for storage. Further, the error correction decoding circuit 108 feeds back to the likelihood signal storage circuit 113 whether or not the bit signal b has been correctly decoded (step S311).

Whether or not the bit signal b has been correctly decoded without error in the above-described step S311 is determined based on the decoding result of the error correction decoding circuit 108 (step S312).
When the bit signal b can be decoded without error (positive in step S312), whether or not the bit signal a is correctly decoded without error in the above-described step S310 is determined based on the decoding result of the error correction decoding circuit 108 (step S313). ). If the bit signal a can be correctly decoded (positive in step S313), the receiving terminal 10-7 completes the transmission process.

  When the bit signal a has an error and cannot be correctly decoded (error in step S313), the bit signal b stored in the signal storage circuit 119 and stored in the likelihood signal storage circuit 113 is stored as a key signal. The decoding of the network code of the bit-wise likelihood signal a ^ b to be started is started. First, the likelihood signal storage circuit 113 outputs a bit-by-bit likelihood signal a ^ b to be stored to the code / bit conversion circuit 110 and the absolute value extraction circuit 111. The code / bit conversion circuit 110 converts the code part of the bit-likelihood signal a ^ b input from the likelihood signal storage circuit 113 into a binary temporary bit signal ab of 0 and 1, and performs linear decoding Output to the circuit 114. The error correction code circuit 118 reads the correctly error-correction-decoded bit signal b stored in the signal storage circuit 119, performs error-correction coding on the read bit signal b, and outputs it to the linear decoding circuit 114 via the output switching circuit 117. To do. The linear decoding circuit 114 decodes the temporary bit signal a ^ b input from the code / bit conversion circuit 110 using the bit signal b error-corrected encoded from the output switching circuit 117 as a key signal, The signal a is decoded (step S321).

  The linear decoding circuit 114 outputs the decoded temporary bit signal a to the bit / code conversion circuit 115. The bit / sign conversion circuit 115 converts the input temporary bit signal a into a sign in which 1 is positive and 0 is negative, and outputs a signal indicating the converted sign to the multiplication circuit 112. The absolute value extraction circuit 111 calculates an absolute value indicating the probability of the value of each bit of the input soft decision signal a ^ b, and outputs the calculated absolute value to the multiplication circuit 112. The multiplication circuit 112 multiplies the signal input from the bit / code conversion circuit 115 and the signal input from the absolute value extraction circuit 111, and outputs a signal indicating the result calculated by the multiplication to the multiplication circuit 105. When the signal stored in the likelihood signal storage circuit 113 is network-decoded, the multiplication circuit 105 outputs the signal input from the multiplication circuit 112 to the addition circuit 106. The adder circuit 106 reads the bit-by-bit likelihood signal a stored in the likelihood signal storage circuit 113, adds the input signal and the read bit-by-bit likelihood signal a, and synthesizes the maximum ratio (step S322).

  Further, the adder circuit 106 outputs the bit-by-bit likelihood signal a that has been subjected to the maximum ratio synthesis by addition to the error correction decoding circuit 108 via the output switching circuit 107. The error correction decoding circuit 108 performs error correction decoding on the input bit-wise likelihood signal a, and the receiving terminal 10-7 completes the transmission process (step S323).

  If the bit signal b cannot be correctly decoded in the determination in step S312, the error correction decoding circuit 108 indicates whether or not the bit signal a has been correctly decoded without error in step S310. Determination is made (step S341).

  When the bit signal a is correctly decoded in the determination in step S341 (positive in step S341), the bit-wise likelihood signal a stored in the likelihood signal storage circuit 113 using the bit signal a stored in the signal storage circuit 119 as a key signal. Start decoding of the network code of ^ b. First, the likelihood signal storage circuit 113 outputs a bit-by-bit likelihood signal a ^ b to be stored to the code / bit conversion circuit 110 and the absolute value extraction circuit 111. The code / bit conversion circuit 110 converts the code part of the bit-likelihood signal a ^ b input from the likelihood signal storage circuit 113 into a binary temporary bit signal ab of 0 and 1, and performs linear decoding Output to the circuit 114. The error correction code circuit 118 reads the correctly error-corrected bit signal a stored in the signal storage circuit 119, performs error correction coding on the read bit signal a, and outputs it to the linear decoding circuit 114 via the output switching circuit 117. To do. The linear decoding circuit 114 decodes the temporary bit signal a ^ b input from the code / bit conversion circuit 110 using the bit signal a error-coded from the output switching circuit 117 as a key signal, and outputs a temporary bit. The signal b is decoded (step S342).

  The linear decoding circuit 114 outputs the decoded temporary bit signal b to the bit / code conversion circuit 115. The bit / sign conversion circuit 115 converts the input temporary bit signal b into a sign in which 1 is positive and 0 is negative, and outputs a signal indicating the converted sign to the multiplication circuit 112. The absolute value extraction circuit 111 calculates an absolute value indicating the probability of the value of each bit of the input soft decision signal a ^ b, and outputs the calculated absolute value to the multiplication circuit 112. The multiplication circuit 112 multiplies the signal input from the bit / code conversion circuit 115 and the signal input from the absolute value extraction circuit 111, and outputs a signal indicating the result calculated by the multiplication to the multiplication circuit 105. When the signal stored in the likelihood signal storage circuit 113 is network-decoded, the multiplication circuit 105 outputs the signal input from the multiplication circuit 112 to the addition circuit 106. The adder circuit 106 reads out the bit-wise likelihood signal b stored in the likelihood signal storage circuit 113, adds the input signal and the read bit-likelihood signal b, and synthesizes the maximum ratio (step S343).

  Further, the adder circuit 106 outputs the bit-by-bit likelihood signal b, which has been subjected to the maximum ratio synthesis by the addition, to the error correction decoding circuit 108 via the output switching circuit 107. The error correction decoding circuit 108 performs error correction decoding on the input bit-wise likelihood signal b, and the receiving terminal 10-7 completes the transmission process (step S344).

  When the bit signal a cannot be correctly decoded in the determination in step S341 (incorrect in step S341), the likelihood signal storage circuit 113 cross-correlates the bit-wise likelihood signals of a, b, and a ^ b to be stored. Output to the calculation circuit 122. The cross-correlation value calculation circuit 122 calculates a cross-correlation value between the input bit-wise likelihood signals a and b not subjected to network coding and the bit-likelihood signal of the network coded signal a ^ b. The cross-correlation value calculation circuit 122 also calculates the cross-correlation value between the calculated bit-wise likelihood signal a and the bit-likelihood signal a ^ b, the calculated bit-likelihood signal b, and the bit-wise likelihood signal a ^. The cross-correlation value with b is compared, and the comparison result is output to the likelihood signal storage circuit 113 (step S351).

If the cross-correlation value between the bit likelihood signal b and the bit likelihood signal a ^ b is large (a <b in step S351) in the cross correlation value comparison in step S351, the likelihood signal storage circuit 113 The decoding of the network code of the bit likelihood signal a ^ b stored in the likelihood signal storage circuit 113 is started using the bit likelihood signal b to be stored as a key signal.
First, the likelihood signal storage circuit 113 outputs the bit-by-bit likelihood signal b and the bit-by-bit likelihood signal a ^ b to the code / bit conversion circuit 110 and the absolute value extraction circuit 111. The sign / bit conversion circuit 110 receives a binary temporary bit signal a ^ of binary values 0 and 1 from the sign part of the bitwise likelihood signal b and the bitwise likelihood signal a ^ b input from the likelihood signal storage circuit 113. b, and the converted two temporary bit signals are output to the linear decoding circuit 114. The linear decoding circuit 114 uses the tentative bit signal b that is not network-encoded input from the code / bit conversion circuit 110 as a key signal, and uses the network-coded temporary bits input from the code / bit conversion circuit 110. The signal a ^ b is decoded, and the provisional bit signal a is decoded (step S352).

  The linear decoding circuit 114 outputs the decoded temporary bit signal a to the bit / code conversion circuit 115. The bit / sign conversion circuit 115 converts the input temporary bit signal a into a sign in which 1 is positive and 0 is negative, and outputs a signal indicating the converted sign to the multiplication circuit 112. The absolute value extraction circuit 111 calculates an absolute value indicating the probability of the value for each bit of the bit-wise likelihood signal b and the bit-wise likelihood signal a ^ b input from the likelihood signal storage circuit 113, and calculates Two absolute values are output to the multiplier circuit 112. The multiplication circuit 112 multiplies the signal input from the bit / code conversion circuit 115 and the two signals input from the absolute value extraction circuit 111, and outputs a signal indicating the result calculated by multiplication to the multiplication circuit 105. . When the signal stored in the likelihood signal storage circuit 113 is network-decoded, the multiplication circuit 105 outputs the signal input from the multiplication circuit 112 to the addition circuit 106 without changing the signal. The adder circuit 106 reads the bit-by-bit likelihood signal a stored in the likelihood signal storage circuit 113, adds the input signal and the read bit-by-bit likelihood signal a, and synthesizes the maximum ratio (step S353).

Further, the adder circuit 106 outputs the bit-by-bit likelihood signal a that has been subjected to the maximum ratio synthesis by addition to the error correction decoding circuit 108 via the output switching circuit 107. The error correction decoding circuit 108 performs error correction decoding on the input bit-wise likelihood signal a (step S354).
It is determined from the decoding result of the error correction decoding circuit 108 whether or not the bit signal a has been correctly decoded without error in the above-described step S354 (step S355).
If it is determined in step S355 that error correction decoding cannot be correctly performed on the bit signal a (error in step S355), the receiving terminal 10-7 completes the transmission process.

  If it is determined in step S355 that error correction decoding has been correctly performed on the bit signal a (positive in step S355), the processing from step S342 to step S344 described above is performed.

When the cross-correlation value in the step S351 is large, if the cross-correlation value between the bit-wise likelihood signal a and the bit-likelihood signal a ^ b is large (a> b in step S351), the likelihood signal storage circuit 113 The decoding of the network code of the bit-wise likelihood signal a ^ b stored in the likelihood signal storage circuit 113 is started using the bit-wise likelihood signal a to be stored as a key signal.
First, the likelihood signal storage circuit 113 outputs the bit-by-bit likelihood signal a and the bit-by-bit likelihood signal a ^ b to the code / bit conversion circuit 110 and the absolute value extraction circuit 111. The sign / bit conversion circuit 110 receives a binary temporary bit signal a ^ of binary values 0 and 1 from the sign portion of the bitwise likelihood signal a and the bitwise likelihood signal a ^ b input from the likelihood signal storage circuit 113. b, and the converted two temporary bit signals are output to the linear decoding circuit 114. The linear decoding circuit 114 uses the temporary bit signal a that has not been network-encoded input from the code / bit conversion circuit 110 as a key signal, and uses the network-encoded temporary bits input from the code / bit conversion circuit 110. The signal a ^ b is decoded and the temporary bit signal b is decoded (step S361).

  The linear decoding circuit 114 outputs the decoded temporary bit signal b to the bit / code conversion circuit 115. The bit / sign conversion circuit 115 converts the input temporary bit signal b into a sign in which 1 is positive and 0 is negative, and outputs a signal indicating the converted sign to the multiplication circuit 112. The absolute value extraction circuit 111 calculates an absolute value indicating the likelihood of the value of each bit of the bit-wise likelihood signal a and the bit-wise likelihood signal a ^ b input from the likelihood signal storage circuit 113, and calculates Two absolute values are output to the multiplier circuit 112. The multiplication circuit 112 multiplies the signal input from the bit / code conversion circuit 115 and the two signals input from the absolute value extraction circuit 111, and outputs a signal indicating the result calculated by multiplication to the multiplication circuit 105. . When the signal stored in the likelihood signal storage circuit 113 is network-decoded, the multiplication circuit 105 outputs the signal input from the multiplication circuit 112 to the addition circuit 106 without changing the signal. The adder circuit 106 reads out the bit-wise likelihood signal b stored in the likelihood signal storage circuit 113, adds the input signal and the read bit-likelihood signal b, and synthesizes the maximum ratio (step S362).

Further, the adder circuit 106 outputs the bit-by-bit likelihood signal b, which has been subjected to the maximum ratio synthesis by the addition, to the error correction decoding circuit 108 via the output switching circuit 107. The error correction decoding circuit 108 performs error correction decoding on the input bit-wise likelihood signal b (step S363).
In step S363 described above, it is determined whether or not the bit signal b has been correctly decoded without error (step S364).
If it is determined in step S364 that error correction decoding cannot be correctly performed on the bit signal b (error in step S364), the receiving terminal 10-7 completes the transmission process.

  If it is determined in step S364 that error correction decoding has been correctly performed on the bit signal b (positive in step S364), the processing from step S321 to step S323 described above is performed.

  Through the above processing, the receiving terminal 10-7 obtains the bit signal a and the bit signal b. If the bit signal a and the bit signal b cannot be obtained correctly, a retransmission request is made. The receiving terminal 10-8 performs the same operation as the receiving terminal 10-7, and obtains the bit signal a and the bit signal b.

  In addition, when the error correction decoding cannot be performed on the bit signal a without error (error in step S341), a cross-correlation value is calculated, and based on the calculated cross-correlation value, the likelihood for each bit that becomes a key signal Although signal selection is performed, all network-uncoded bit likelihood signals stored in the likelihood signal storage circuit 113 without selection are sequentially used as key signals, and brute force network decoding is performed. Maximum ratio synthesis may be performed. As a result, a diversity effect can be further obtained, and an improvement in communication quality can be expected.

(Operation of the wireless communication system 1b in the X topology of the third embodiment)
Next, transmission of the bit signal a and the bit signal b of the wireless communication system 1b to the receiving terminals 10-7 and 10-8 will be described with reference to FIG.
First, at time T1, the transmission terminal 30-1 modulates the bit signal a stored in the terminal itself, and transmits the modulated signal a obtained by the modulation to the relay terminal 20 (step S31).

In relay terminal 20, radio section 201 detects modulated signal a from the received signal, and outputs detected modulated signal a to symbol / bit conversion circuit 202 and weighting coefficient extraction circuit 211. The symbol / bit conversion circuit 202 performs symbol-bit conversion on the input modulation signal a, and outputs the bit series signal a obtained by the conversion to the soft decision circuit 203. The soft decision circuit 203 performs a soft decision on the input bit sequence signal a, converts it to the soft decision signal a, and outputs the soft decision signal a to the multiplication circuit 204. The weighting factor extraction circuit 211 calculates a weighting factor from the input modulation signal a, and outputs the calculated weighting factor to the multiplication circuit 204. The multiplication circuit 204 multiplies the soft decision signal a input from the soft decision circuit 203 by the weight coefficient input from the weight coefficient extraction circuit 211, and outputs a signal calculated by the multiplication to the error correction decoding circuit 205. The error correction decoding circuit 205 performs error correction decoding on the input signal, and outputs the decoded bit signal a to the signal storage circuit 207 via the output switching circuit 206 for storage.
The receiving terminals 10-7 and 10-8 perform the operations from step S301 to step S303, and listen to the modulated signal a in a timely manner.

Subsequently, at time T2, the transmission terminal 30-2 modulates the bit signal b stored in the terminal itself, and transmits the modulated signal a obtained by the modulation to the relay terminal 20 (step S32).
In relay terminal 20, radio section 201 detects modulated signal b from the received signal, and outputs detected modulated signal a to symbol / bit conversion circuit 202 and weighting coefficient extraction circuit 211. The symbol / bit conversion circuit 202 performs symbol-bit conversion on the input modulation signal b, and outputs the bit series signal b obtained by the conversion to the soft decision circuit 203. The soft decision circuit 203 performs a soft decision on the input bit series signal b, converts it to the soft decision signal b, and outputs the soft decision signal b to the multiplication circuit 204. The weight coefficient extraction circuit 211 calculates a weight coefficient from the input modulation signal b and outputs the calculated weight coefficient to the multiplication circuit 204. The multiplication circuit 204 multiplies the soft decision signal b input from the soft decision circuit 203 by the weight coefficient input from the weight coefficient extraction circuit 211, and outputs a signal calculated by the multiplication to the error correction decoding circuit 205. The error correction decoding circuit 205 performs error correction decoding on the input signal, and outputs the decoded bit signal b to the signal storage circuit 207 via the output switching circuit 206 for storage.
At this time, the receiving terminals 10-7 and 10-8 perform the operations from step S304 to step S306, and listen to the modulated signal b in a timely manner.

Subsequently, in the relay terminal 20 at time T3, the linear encoding circuit 208 reads the bit signal a and the bit signal b stored in the signal storage circuit 207, performs network encoding, and obtains a bit signal obtained by network encoding. a ^ b is output to the error correction code circuit 209. The error correction encoding circuit 209 performs error correction encoding on the signal input from the linear encoding circuit 208 by a predetermined method, and outputs the error correction encoded signal to the modulation circuit 210. The modulation circuit 210 performs a predetermined modulation on the signal input from the error correction code circuit 209 to obtain a modulation signal a ^ b. Also, the modulation circuit 210 transmits the modulated signal a ^ b to the receiving terminal 10-7 and the receiving terminal 10-8 (step S12).
At time T3, the receiving terminals 10-7 and 10-8 perform the operations after step S307, and obtain the bit signal a and the bit signal b, respectively.

  As described above, the receiving terminals 10-7 and 10-8 listen to the modulated signal transmitted from the transmitting terminals 30-1 and 30-2 to the relay terminal 20 in a timely manner, thereby demodulating the bit signal a demodulated at time T <b> 1. And it is possible to obtain the bit signal b demodulated at time T2. If there is an error in the bit signal demodulated at time T1 or time T2, the modulated signal a ^ b transmitted from the network code difference from the relay terminal 20 received at time T3 is network-decoded, and the obtained bit-by-bit likelihood is obtained. The degree signal and the bit-wise likelihood signal obtained at time T1 or time T2 are combined at the maximum ratio to improve the quality of the physical link. If there is an error in both of the bit signals obtained at time T1 and time T2, the bit signal having the stronger received power is used as the key signal in anticipation of higher reliability of the signal having the higher received power. The demodulation is performed again. The physical link refers to a process for handling a signal before demodulating it into a bit signal.

In a wireless communication system to which a conventional network code is applied, transmission from the transmission terminal 30-1 to the reception terminal 10-8 and transmission from the transmission terminal 30-2 to the reception terminal 10-7 cannot maintain a sufficient reception level. Since it was an encoded signal using a bit signal between the relay terminal 20 and the receiving terminals 10-7 and 10-8, it could not be combined in the physical layer. It is possible to improve the communication quality by performing maximum ratio combining before demodulation as a degree signal.
The receiving terminal multiplies the weighting factor based on the received power calculated by the weighting factor extraction circuit by the soft decision signal output from the soft decision circuit and the signal output from the network decoding circuit, thereby performing simple addition by the addition circuit. Allows maximum ratio synthesis.

(Simulation result in the X topology of the third embodiment)
13 to 15 show simulation results in the X topology of the third embodiment. The simulation was performed based on the IEEE 802.11a standard. FIG. 13 shows the simulation conditions. The signal band is 20 MHz, OFDM is used for the secondary modulation scheme, and 64QAM is applied for the subcarrier modulation scheme. The number of data subcarriers is 52, and the number of pilot subcarriers is 4. The packet length is 64 bytes, and the error correction code uses a convolutional code with a constraint length of 7 and a coding rate of 3/4. The error correction decoding method employs soft decision Viterbi decoding.
The propagation path environment between terminals as nodes is exponentially attenuated Rayleigh fading, delay dispersion is 100 ns, and free space propagation loss corresponding to each propagation path length is taken into consideration. Channel estimation is ideal estimation, and De-code & Forward is used as a relay method. It is assumed that there is no error in the relay terminal.

  FIG. 14A and FIG. 15B show the X topology configuration of the simulation. FIGS. 14B and 15B show error characteristics in transmission between the transmission terminal 30-1 and the reception terminal 10-7. It can be seen from FIG. 14 (b) that the characteristics are improved as an effect of the maximum ratio synthesis by performing timely listening.

  Note that the first receiving unit and the first transmitting unit described in the present invention correspond to the radio unit 201. The first signal storage circuit described in the present invention corresponds to the signal storage circuit 207. The first linear encoding circuit described in the present invention corresponds to the linear encoding circuit 208. Further, the second receiving unit and the second transmitting unit described in the present invention correspond to the radio unit 101. The second signal storage circuit described in the present invention corresponds to the signal storage circuit 119. The second network decoding circuit described in the present invention corresponds to the network decoding circuit 121. The second likelihood signal storage circuit described in the present invention corresponds to the likelihood signal storage circuit 113. The second adder circuit described in the present invention corresponds to the adder circuit 106.

  The first receiving terminal and the second receiving terminal described in the present invention correspond to the receiving terminal 10. Further, the third receiving unit and the third transmitting unit described in the present invention correspond to the radio unit 101. A third signal storage circuit described in the present invention corresponds to the signal storage circuit 119. The third network decoding circuit described in the present invention corresponds to the network decoding circuit 121. The third adder circuit described in the present invention corresponds to the adder circuit 106.

It is a schematic block diagram which shows the internal structure of the receiving terminal in this embodiment. It is a schematic block diagram which shows the internal structure of the relay terminal in 1st Embodiment and 3rd Embodiment. It is the schematic which shows the structure and operation | movement of the radio | wireless communications system in 1st Embodiment. It is a flowchart figure of operation | movement of the receiving terminal in 1st Embodiment. It is a schematic block diagram which shows the internal structure of the relay terminal in 2nd Embodiment. It is the schematic which shows the chain | topology structure of the radio | wireless communications system in 2nd Embodiment, and operation | movement of a radio | wireless communications system. It is a flowchart figure which shows operation | movement of the receiving terminal arrange | positioned at both ends in 2nd Embodiment. It is a flowchart figure which shows operation | movement of the receiving terminal arrange | positioned in the middle of the chain-topology structure in 2nd Embodiment. It is a flowchart figure which shows operation | movement of the relay terminal of the chain | topology structure in 2nd Embodiment. It is the schematic which shows X topology structure of the radio | wireless communications system in 3rd Embodiment, and the wild operation of a radio | wireless communications system. It is a flowchart figure which shows operation | movement of the receiving terminal of the radio | wireless communications system in 3rd Embodiment. It is a flowchart figure which shows operation | movement of the receiving terminal of the radio | wireless communications system in 3rd Embodiment. It is a figure which shows the simulation conditions in X topology of 3rd Embodiment. It is a figure which shows the structure and simulation result of X topology of 3rd Embodiment. It is a figure which shows the structure and simulation result of X topology of 3rd Embodiment. It is a schematic block diagram which shows the internal structure of the receiving terminal of the radio | wireless communications system to which the conventional network code is applied. It is a figure which shows the structure and operation | movement of the radio | wireless communications system to which the conventional network code | symbol is applied. It is a figure which shows the structure and operation | movement of the radio | wireless communications system to which the conventional network code | symbol is applied.

Explanation of symbols

10, 10-1, 10-2, 10-3, 10-4, 10-5, 10-6, 10-7, 10-8 ... receiving terminal 20, 20a ... relay terminal 30-1, 30-2 ... Transmission terminal 101: Radio unit 102: Symbol / bit conversion circuit 103 ... Soft decision circuit 105, 112 ... Multiplication circuit 106 ... Adder circuit 108 ... Error correction decoding circuit 110 ... Code / bit conversion circuit 111 ... Absolute value Extraction circuit 113 ... Likelihood signal storage circuit 114 ... Linear decoding circuit, 115 ... Bit / code conversion circuit, 116 ... Modulation circuit 118 ... Error correction code circuit, 119 ... Signal storage circuit, 120 ... Weight coefficient extraction circuit 104, 107 , 109, 117 ... output switching circuit 121 ... network decoding circuit, 122 ... cross-correlation value calculation circuit 201 ... wireless unit, 202 ... symbol / bit conversion circuit, 203 ... soft decision Constant circuit 204... Multiplier circuit 205 205 Error correction decoding circuit 207 Signal storage circuit 208 Linear encoder circuit 209 Error correction code circuit 210 Modulation circuit 211 Weight coefficient extraction circuit 212 Adder circuit 214 ... Likelihood signal storage circuit 206, 213 ... Output switching circuit

Claims (3)

The receiving terminal, the relay terminal and stores the key signal in advance, has a transmission terminal that transmits the key signal to the relay terminal, in a wireless communication system that performs communication by network coding an information signal by the key signal,
The relay terminal is
A first receiver that receives and detects a signal transmitted to the terminal, and outputs the detected signal;
A first signal storage circuit for storing a signal output from the first receiver;
A first linear encoding that performs network encoding on one of the plurality of signals stored in the first signal storage circuit as the key signal and outputs the network encoded signal. Circuit,
A first transmitter that transmits a signal output from the first linear encoding circuit to the receiving terminal;
With
The receiving terminal is
A second receiving unit for receiving and detecting a signal addressed to the own terminal, further receiving and detecting a signal other than the address addressed to the own terminal, and outputting the detected signal;
When the signal output from the second receiving unit is a network-encoded signal, a network decoding circuit that outputs a network-decoded network decoded signal using the signal output from the second receiving unit as the key signal When,
A second likelihood signal storage circuit for storing a signal addressed to another terminal output from the second reception unit as a likelihood signal;
An adder circuit that adds a likelihood signal stored in the second likelihood signal storage circuit and a network decoded signal output from the network decoding circuit to perform maximum ratio combining, and outputs a signal obtained by combining the maximum ratio;
An error correction decoding circuit that performs error correction decoding on an unnetwork-encoded likelihood signal that is a network-unencoded likelihood signal stored in the second likelihood signal storage circuit;
Network coding likelihood that is the network-encoded likelihood signal stored in the second likelihood signal storage circuit and the network-encoded likelihood signal stored in the second likelihood signal storage circuit A cross-correlation value calculating circuit for calculating a cross-correlation value with the signal;
Equipped with a,
The network decoding circuit includes:
When the uncorrected network code likelihood signal stored in the second likelihood signal storage circuit can be decoded without error by the error correction decoding circuit, a signal obtained by decoding the unnetwork encoded likelihood signal by the error correction decoding circuit Using the key signal as a key signal,
If the uncorrected network code likelihood signal stored in the second likelihood signal storage circuit cannot be decoded without error by the error correction decoding circuit, based on the cross correlation value calculated by the cross correlation value calculation circuit, Selecting an unnetwork encoded likelihood signal stored in the likelihood signal storage circuit of 2 and performing network decoding using the selected unnetwork encoded likelihood signal as the key signal;
A wireless communication system. In a wireless communication system having a first receiving terminal, a second receiving terminal, and a relay terminal, and performing communication by network-coding an information signal with a key signal,
The relay terminal is
A first receiving unit that receives and detects a signal transmitted from the receiving terminal and outputs the detected signal;
A first likelihood signal storage circuit that stores, as a likelihood signal, a signal that is output from the first receiving unit and that is not addressed to the own terminal;
The likelihood signal stored in the first likelihood signal storage circuit and the signal destined for the terminal output from the first receiving unit are added to perform maximum ratio combining, and the maximum ratio combining signal is output. A first adder circuit that
A first signal storage circuit for storing a signal output from the first addition circuit;
A first linear encoding that performs network encoding on one of the plurality of signals stored in the first signal storage circuit as the key signal and outputs the network encoded signal. Circuit,
A first transmitter that transmits a network-encoded signal output from the first linear encoder circuit to the receiving terminal;
With
The first receiving terminal is
A second signal storage circuit for storing the key signal in advance;
A second transmitter for transmitting the key signal stored in the second signal storage circuit;
A second receiving unit for receiving and detecting a signal addressed to the own terminal, further receiving and detecting a signal other than the address addressed to the own terminal, and outputting the detected signal;
A second network decoding circuit that outputs a network-decoded network decoded signal using the key signal when the signal output from the second receiving unit is a network-encoded signal;
A second likelihood signal storage circuit for storing a signal addressed to another terminal output from the second reception unit as a likelihood signal;
The likelihood signal stored in the second likelihood signal storage circuit and the network decoded signal output from the second network decoding circuit are added to perform maximum ratio combining, and the maximum ratio combined signal is output. A second adder circuit;
With
The second receiving terminal is
Receiving and detecting a signal addressed to the own terminal, further receiving and detecting a signal other than the address addressed to the own terminal, and outputting a detected signal;
A third signal storage circuit for storing, as the key signal, a signal addressed to the terminal output from the third receiving unit;
A network-decoded signal output from the third receiving unit is output as a network-decoded signal using the signal stored in the third signal storage circuit as the key signal and the network-encoded signal addressed to the own terminal. A network decoding circuit;
A third likelihood signal storage circuit for storing a signal addressed to another terminal output from the third receiver as a likelihood signal;
The likelihood signal stored in the third likelihood signal storage circuit and the network decoded signal output from the third network decoding circuit are added to perform maximum ratio combining, and a maximum ratio combined signal is output. A third adder circuit;
A third transmitter for transmitting the key signal stored in the third signal storage circuit to the relay terminal and transmitting the signal output from the third adder circuit to the first receiving terminal;
Comprising
A wireless communication system. The receiving terminal, the relay terminal and stores the key signal in advance, has a transmission terminal that transmits the key signal to the relay terminal, receiving in a wireless communication system that performs communication by network coding an information signal by the key signal terminal Because
A second receiving unit for receiving and detecting a signal addressed to the own terminal, further receiving and detecting a signal other than the address addressed to the own terminal, and outputting the detected signal ;
When signal output from the previous SL second reception unit of the network coded signal by using a signal in which the second receiving section is outputted as the key signal, a second outputting a network decoding signal network decoding Network decoding circuit of
A second likelihood signal storage circuit for storing a signal addressed to another terminal output from the second reception unit as a likelihood signal;
Wherein the likelihood signal second likelihood signal storage circuit stores, the network decoding circuit adds the network decoding signal outputted perform maximum ratio combining, a second adder for outputting a maximum ratio combined signal Circuit,
An error correction decoding circuit that performs error correction decoding on an unnetwork-encoded likelihood signal that is a network-unencoded likelihood signal stored in the second likelihood signal storage circuit;
Network coding likelihood that is the network-encoded likelihood signal stored in the second likelihood signal storage circuit and the network-encoded likelihood signal stored in the second likelihood signal storage circuit A cross-correlation value calculating circuit for calculating a cross-correlation value with the signal;
Equipped with a,
The network decoding circuit includes:
When the uncorrected network code likelihood signal stored in the second likelihood signal storage circuit can be decoded without error by the error correction decoding circuit, a signal obtained by decoding the unnetwork encoded likelihood signal by the error correction decoding circuit Using the key signal as a key signal,
If the uncorrected network code likelihood signal stored in the second likelihood signal storage circuit cannot be decoded without error by the error correction decoding circuit, based on the cross correlation value calculated by the cross correlation value calculation circuit, Selecting an unnetwork encoded likelihood signal stored in the likelihood signal storage circuit of 2 and performing network decoding using the selected unnetwork encoded likelihood signal as the key signal;
A receiving terminal.

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