JP4987259B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a fully depleted SOI transistor that suppresses threshold fluctuation caused by variations in the thickness of a semiconductor thin film on an SOI substrate.

5 to 7 are schematic cross-sectional views of a conventional method for manufacturing a semiconductor device having an SOI structure. As shown in FIG. 5A, a buried insulating film 202 is formed on a support substrate 201, and a semiconductor thin film (SOI layer) 203 is formed on the buried insulating film 202. After forming a field insulating film 204, for example, a thermal oxide film having a thickness of several thousand Å by the method, the insulating film in a region where a MOS transistor is to be formed is removed, and a channel forming portion 106 is formed. Thereafter, as shown in FIG. 5B, after the sacrificial oxide film 213 is grown on the SOI layer 103 by, for example, 15 nm, ion implantation for adjusting the threshold value is performed on the channel forming portion 206. Next, as shown in FIG. 6A, after the sacrificial oxide film 213 is etched with a hydrofluoric acid (HF) -based solution, a gate insulating film 205 is grown to, for example, several tens of nanometers, and is formed on the gate insulating film 205. A polycrystalline silicon gate 207 to be a gate electrode is formed by depositing polycrystalline silicon, introducing impurities by pre-deposition or ion implantation, and performing patterning. Subsequently, as shown in FIG. 6B, for example, As is added to the drain and source high-concentration regions 208 and 209 at both ends of the polycrystalline silicon gate 207, and preferably 1 × 10 ¹⁴ to 1 to reduce the sheet resistance. Ions are implanted at a concentration of × 10 ¹⁶ atoms / cm ² . In FIG. 7, subsequently, an interlayer insulating film 210 having a thickness of about 200 nm to 800 nm is deposited to form a contact hole 21 1 for connecting wirings to the source high concentration region 209 and the drain high concentration region 208 region. Next, when a wiring metal is formed by sputtering or the like and patterned, the metal 212 and the surface of the drain and source high concentration regions 208 and 209 are connected through the contact hole 211.

  In the above manufacturing method, by using the SOI structure, complete isolation between elements is facilitated, and soft errors and latch-up peculiar to CMOS transistors can be suppressed. Further, the SOI layer 203 is further reduced to about 100 nm, the channel impurity concentration is controlled to be relatively low, and the conditions are set so that the entire SOI layer 203 is almost depleted, whereby a fully depleted SOI transistor is obtained. In addition to reducing the diffusion layer capacitance, it is possible to have more excellent characteristics such as a steep rise in drain current in the subthreshold region.

Further, in the conventional SOI technology, in order to prevent the parasitic channel from being turned on in the vicinity of the buried insulating film 202 interface, the peak of the concentration of impurities introduced into the channel forming portion 206 in the vicinity of the SOI layer 203 / buried insulating film 202 interface (See, for example, JP-A-11-026769). Further, by increasing the thickness of the buried oxide film 202, the parasitic channel is turned on, and an increase in leakage current is suppressed.
JP-A-11-026769

  However, when the threshold value of the fully depleted SOI transistor is controlled by the concentration of the impurity introduced into the channel, the threshold value is determined by the total amount of the introduced impurity. As a result, the following problem occurs. That is, the conventional technique has a peak concentration of impurities introduced into the channel forming portion in the vicinity of the SOI layer / buried oxide film interface in order to prevent the parasitic channel from being turned on. Therefore, if the SOI layer thickness varies due to process variations, the ratio between the total amount of impurities introduced into the channel formation portion and the total amount of impurities introduced into the buried insulating film changes greatly, and this affects the threshold and leakage current. Had. This is particularly likely to occur with fully depleted SOI NMOS transistors. The present invention has been made paying attention to the above points, and the present invention relates to an impurity concentration for introducing a threshold value into a channel formation portion while preventing a parasitic channel in a fully depleted SOI transistor, particularly an NMOS transistor. It is an object of the present invention to provide a method for manufacturing a fully depleted SOI transistor in which the dependence of the threshold value on the SOI layer film thickness is suppressed even when the control is attempted.

In order to solve the above problems, the present invention uses the following means.
1. A semiconductor support substrate on the formed insulating film fully depleted SOI transistor formed on the SOI (S ilicon O n I nsulator ) substrate of a semiconductor thin film layer composed of a semiconductor thin film layer formed on the insulating film In the step of forming a channel in the method of manufacturing a semiconductor device having the method, the first conductivity type impurity implantation is performed a plurality of times by dividing the impurity concentration by changing the acceleration energy at the interface between the semiconductor thin film layer and the insulating film. This is a method for manufacturing a fully depleted SOI transistor.
2. A manufacturing method is performed in which the first conductivity type impurity is implanted through a sacrificial oxide film.
3. In the manufacturing method, the first conductivity type impurity is implanted through the gate insulating film.
4). In the manufacturing method, the first conductivity type impurity is implanted through the gate electrode of the transistor.

As described above, according to the present invention, in the channel formation step in the manufacturing method of a fully depleted SOI transistor, in particular, an NMOS transistor, ion implantation for threshold adjustment is performed on the interface between the SOI layer and the buried insulating film in the channel formation portion. By changing the acceleration energy and dividing the dose amount a plurality of times, the following effects can be obtained.
1. The threshold values are almost constant even if the SOI layer thickness varies.
2. It is possible to prevent parasitic channels.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, an outline of a method for manufacturing a fully depleted SOI NMOS transistor according to the present embodiment will be described with reference to FIG. As shown in FIG. 1A, for example, an SOI structure substrate having an SOI layer 103 having a thickness of 100 to 400 nm, a buried oxide film 102 having a thickness of 100 to 400 nm, and a support substrate 101 having a p-type resistivity of 20 to 30 Ω · cm. A field insulating film 104, for example, a thermal oxide film having a thickness of several thousand Å, for example, is formed on the SOI layer 103 by the LOCOS method, the SOI layer 103 is separated between elements, and then the insulating film in a region for forming a MOS transistor is removed Then, the channel forming portion 106 is formed.

Thereafter, as shown in FIG. 1B, after a sacrificial oxide film 113 is grown on the SOI layer 103, for example, by 15 nm, ion implantation for adjusting a threshold value is performed on the channel forming unit 106 by the SOI layer 103 / the buried insulating film 102. Acceleration is usually carried out at one interface, for example, with ion species: boron ion (B ⁺ ), acceleration energy: 30 keV, implantation angle: 7 °, dose amount: 1.8 × 10 ¹² atom / cm ^−2. The dose is divided by changing the energy, and the process is performed a plurality of times, for example, under the following conditions. However, the second and third doses are preferably adjusted to be smaller than the first dose for fine adjustment.
1st time: ion species: B ⁺ , acceleration energy: 30 keV, implantation angle: 7 °, dose amount: normal 10-20% decrease Second time: ion species: B ⁺ , acceleration energy: 1st time decrease of 3-10% , Implantation angle: 7 °, dose amount: normal 80 to 90% decrease Third time: ion species: B ⁺ , acceleration energy: first time increase of 3 to 10%, implantation angle: 7 °, dose amount: normal 80 -90% reduction As described above, by performing ion implantation in the vicinity of the interface between the SOI layer 103 and the buried insulating film 102 under the above-described conditions, the peak width of the impurity concentration introduced into the channel is widened as shown in FIG. Therefore, a change in the ratio between the total amount of impurities introduced into the channel formation portion 106 and the total amount of impurities introduced into the buried insulating film 103 due to variations in the SOI layer thickness 103 can be reduced. That is, the threshold value of the NMOS transistor is almost constant even if the SOI layer film thickness 203 varies.

  Further, since ion implantation for channel formation has a peak of the impurity concentration introduced into the channel formation portion in the vicinity of the SOI layer 103 / buried insulating film 102 interface, it is possible to prevent the parasitic channel from being turned on as before. . Here, the number of ion implantations is three as an example, but the number of implantations can be changed by adjusting the acceleration energy and the dose amount.

  Next, as shown in FIG. 2A, after the sacrificial oxide film 113 is etched with a hydrofluoric acid (HF) -based solution, a gate insulating film 105 is grown, for example, several tens of nanometers, followed by a polycrystalline silicon gate. PolySi to be 107 is deposited by, for example, 150 nm, an impurity (such as phosphorus) is introduced into the polycrystalline silicon gate 107, and then patterned.

Next, as shown in FIG. 2B, for example, As is used as an impurity in the diffusion layer that becomes the drain and source high-concentration regions 108 and 109 to reduce the sheet resistance, preferably 1 × 10 ¹⁴ to 1 ×. After ion implantation at a concentration of 10 ¹⁶ atoms / cm ² , a heat treatment for activating the impurities is performed under the following conditions, for example.

950 ° C., 10 seconds, N ₂ atmosphere, RTA treatment After that, by a normal manufacturing process of a semiconductor device, deposition of an interlayer insulating film 110 of about 200 nm to 800 nm, formation of a contact hole 111, and formation of a metal 112 by a sputtering method This is performed sequentially to form a fully depleted SOI NMOS transistor 1 as shown in FIG.

  By such a manufacturing method, the fully depleted SOI transistor 1 is formed, and the threshold value of each fully depleted SOI transistor 1 is made substantially constant even if the SOI layer thickness varies.

  In this embodiment, ion implantation is performed a plurality of times through the sacrificial oxide film 113 to suppress changes in the total amount of impurities. However, the gate insulating film 105 may be used without depositing the sacrificial oxide film. Thereafter, the polycrystalline silicon gate 107 may be deposited, and the process may be performed before and after the patterning of the polycrystalline silicon gate 107.

Sectional schematic cross-sectional view showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention. Sectional schematic cross-sectional view showing a first embodiment of a semiconductor device manufacturing method according to the present invention (continued) Sectional schematic cross-sectional view showing a first embodiment of a semiconductor device manufacturing method according to the present invention (continued) Comparison diagram of impurity concentration profiles in the present invention and conventional channel formation Schematic cross-sectional view in order of processes in a conventional semiconductor device manufacturing method Sectional schematic cross-sectional view of conventional semiconductor device manufacturing method (continued) Sectional schematic cross-sectional view of conventional semiconductor device manufacturing method (continued)

Explanation of symbols

101, 201 Support substrate 102, 202 Embedded insulating film 103, 203 SOI layer 104, 204 Field insulating film 105, 205 Gate insulating film 106, 206 Channel forming portion 107, 207 Polycrystalline silicon gate (gate electrode)
108, 208 Drain high concentration region 109, 209 Source high concentration region 110, 210 Interlayer insulating film 111, 211 Contact hole 112, 212 Metal 113, 213 Sacrificial oxide film

Claims (5)

The fully depleted SOI transistor formed on an SOI (Silicon On Insulator) substrate of the semiconductor thin film layer composed of a semiconductor support substrate on an insulating film formed from said semiconductor thin film layer formed on the insulating film In the step of forming a channel in the method for manufacturing a semiconductor device having ,
To widen the peak width of the impurities introduced to form a channel, the interface between the insulating film and the semiconductor thin film layer, changing the acceleration energy by dividing the amount of impurity of the first conductivity type, said first the injection of first conductivity type impurities have a step of performing a plurality of times,
In the step of implanting the first conductivity type impurity a plurality of times, the dose amount after the second time is smaller than the dose amount of the first time, and the implanted first conductivity type impurity is the semiconductor thin film layer and the semiconductor layer. A method for manufacturing a semiconductor device, characterized by having a concentration peak near an interface with an insulating film .   2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity of the first conductivity type is implanted through a sacrificial oxide film.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductivity type impurity is implanted through a gate insulating film.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductivity type impurity is implanted through a gate electrode of a transistor.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the channel is a channel of an N-type transistor, and the impurity of the first conductivity type is boron.

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