JP5018464B2 - Semiconductor integrated circuit device and method for testing semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a semiconductor integrated circuit device and a test method for a semiconductor integrated circuit device.
In recent years, with the miniaturization of the manufacturing process, the semiconductor integrated circuit device has been increased in scale and integration, while an increase in leakage current in the circuit cannot be ignored. Therefore, as a method for reducing such a leakage current, a method called power gating for stopping the power supply itself to the internal circuit has been proposed. However, in this power gating, it is necessary to test in advance whether the power cutoff circuit for stopping the power supply to the internal circuit is functioning normally.

  In recent years, with the miniaturization of the manufacturing process, the semiconductor integrated circuit device has been increased in scale and integration, and the power consumption is reduced by operating the circuit at a low voltage. However, on the other hand, as the manufacturing process is miniaturized and the operating voltage is lowered, the leakage current of the transistor increases, and the ratio of the power consumption due to the leakage current in the power consumption of the entire circuit cannot be ignored. I came.

Therefore, in recent years, as an effective method for reducing the leakage current inside the semiconductor integrated circuit device, a method called power gating for stopping the power supply itself to some or all of the internal circuits that are not operating has been proposed. (For example, refer to Patent Document 1). Specifically, as shown in FIG. 13, a power cutoff circuit 120 is inserted and connected between the power supply terminal of the internal circuit 110 and the power supply, and the power cutoff circuit 120 supplies and cuts off the power supply voltage to the internal circuit 110. It is a method to control. With such a method, supply of power supply voltage to circuits not used in the semiconductor integrated circuit device can be cut off for each internal circuit, so that power consumption due to leakage current can be greatly reduced.
JP 2004-201268 A

  By the way, when the power shutoff circuit 120 described above is not functioning normally, the power supply voltage cannot be supplied to or shut off from the internal circuit 110 at a desired timing. The internal circuit 110 cannot perform a predetermined function. Therefore, it is necessary to test in advance whether or not the power shutoff circuit 120 is functioning normally.

  As such a test method, as shown in FIG. 13, a node A (virtual power supply) between the internal circuit 110 and the power shutoff circuit 120 is connected to the power supply pad 130, and the above node is connected via the power supply pad 130. It is conceivable to measure the voltage A (virtual power supply voltage) VD1 from the outside. However, in the case of this circuit, it is necessary to route the power supply wiring WP having a wide wiring width from the virtual power supply to the power supply pad 130 arranged around the semiconductor integrated circuit. Therefore, there is a problem that the wiring area increases, resulting in a decrease in the area for arranging other wirings and a decrease in the degree of freedom of wiring.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor integrated circuit that can test whether the power shut-off circuit functions normally while suppressing an increase in wiring area. An object of the present invention is to provide a test method for a circuit device and a semiconductor integrated circuit device.

  In order to achieve the above object, the present invention described in claims 1 and 7 is connected between an internal circuit to which a power supply voltage is supplied and the internal circuit and a power supply for supplying the power supply voltage to the internal circuit. In a semiconductor integrated circuit device comprising a power cutoff circuit that controls supply / cutoff of the power supply voltage in accordance with a power cutoff control signal, the internal circuit and the power supply circuit at the time of an operation test for testing the operation of the power cutoff circuit Based on the virtual power supply voltage or virtual power supply current at the connection point with the power supply cutoff circuit, a determination signal indicating whether or not the power supply cutoff circuit is functioning normally is generated, and the generated determination signal is output to the output pad. Is provided with an operation determination circuit that outputs the signal.

  The invention according to claim 2 is that the power supply cutoff circuit functions normally based on a virtual power supply voltage or a virtual power supply current at a connection point between the internal circuits and the power supply cutoff circuits. A plurality of operation determination circuits for generating a determination signal indicating whether or not, and one of the plurality of determination signals input from each of the operation determination circuits is selected, and the selected determination signal is output to an output pad A selection circuit for outputting.

  According to these configurations, in the operation determination circuit, the power supply is cut off based on the virtual power supply voltage or the virtual power supply current at the connection point between the internal circuit and the power supply cutoff circuit, that is, the voltage (current) supplied to the internal circuit. A determination signal indicating whether the circuit is functioning normally is generated. Therefore, by detecting this determination signal via the output pad, it is possible to test whether the power cutoff circuit is functioning normally. In addition, the determination signal is output from the operation determination circuit (selection circuit) to the output pad. Thereby, the wiring from the operation determination circuit to the output pad can be a signal wiring having a wiring width narrower than that of the power supply wiring. Therefore, an increase in the wiring area can be suppressed as compared with the case where the wiring from the connection point between the internal circuit and the power cutoff circuit to the power supply pad is formed by the power supply wiring.

  Furthermore, according to the configuration of the second aspect, a plurality of determination signals output from the plurality of operation determination circuits are selected by the selection circuit and output to the output pad. As a result, the output pads provided for the operation test of the power shut-off circuit can be shared, so that even when a plurality of power shut-off circuits are provided, the increase in the number of output pads is suitably suppressed. Can do.

  According to a third aspect of the present invention, the operation determination circuit generates a first reference voltage when the power cut-off circuit is in a power supply operation for supplying the power supply voltage to the internal circuit, and the power cut-off circuit A reference voltage generation circuit for generating a second reference voltage during a power supply cutoff operation for cutting off the supply of the power supply voltage to the internal circuit, and the first reference voltage or the second reference voltage from the reference voltage generation circuit, And a comparison circuit that compares the virtual power supply voltage and generates the determination signal.

  According to this configuration, the reference voltage is compared with the virtual power supply voltage in the comparison circuit. Thereby, it can be determined whether the virtual power supply voltage is a desired voltage. At this time, if the power shutoff circuit is not functioning normally, a virtual power supply voltage of a desired voltage level cannot be obtained. Therefore, by detecting the determination result, that is, the determination signal generated by the comparison circuit It can be determined whether the power shut-off circuit is functioning normally. Further, in the above configuration, in the reference voltage generation circuit, the first reference voltage corresponding to the virtual power supply voltage when the power supply energization operation of the power supply cutoff circuit is functioning normally and the power supply cutoff operation of the power supply cutoff circuit are normal. A second reference voltage corresponding to the virtual power supply voltage when functioning is generated. Then, the virtual power supply voltage at that time and the first reference voltage are compared at the time of the test in the power supply energizing operation, and the virtual power supply voltage at that time and the second reference voltage are compared at the time of the test in the power-off operation. As a result, it is possible to reliably test whether the operations of both the power supply energization operation and the power supply interruption operation of the power supply cutoff circuit function normally.

  According to a fourth aspect of the present invention, the reference voltage generation circuit generates a divided voltage obtained by dividing a potential difference between a high potential power source and a low potential power source by using a variable resistor connected in series. A voltage dividing circuit that generates the second reference voltage, and the voltage dividing circuit changes the resistance value of the variable resistor in accordance with the power-off control signal, whereby the first reference voltage is used as the divided voltage. And generating the second reference voltage by switching.

  According to this configuration, both the first reference voltage and the second reference voltage used in the test for the power supply energization operation and the power supply cutoff operation of the power cutoff circuit are generated by a simple configuration of changing the resistance value of the variable resistor. can do. Further, the resistance values of these variable resistors are changed by a power cutoff control signal that controls the operation of the power cutoff circuit. Thus, since the power cutoff control signal that originally exists is shared as a control signal for switching generation of the first and second reference voltages, an increase in the number of control signals can be suitably suppressed. Note that the high potential power supply (voltage) and low potential power supply (voltage) supplied to the voltage dividing circuit are the same as the high potential power supply voltage and low potential power supply voltage supplied to the internal circuit, but are different. It may be.

  According to a fifth aspect of the present invention, the operation determination circuit includes a voltage shift circuit that converts the virtual power supply voltage into a comparison voltage corresponding to a sensitivity of the comparison circuit, and the comparison circuit includes the reference voltage generation circuit. The first reference voltage or the second reference voltage from the reference voltage is compared with the comparison voltage from the voltage shift circuit, and the determination signal is generated.

  According to this configuration, in the voltage shift circuit, the virtual power supply voltage is converted into a comparison voltage corresponding to the sensitivity of the comparison circuit. Thereby, the comparison operation of the comparison voltage and the reference voltage in the comparison circuit can be performed more reliably.

  According to a sixth aspect of the present invention, the power cutoff circuit controls supply / cutoff of the first power supply voltage to the internal circuit among the first power supply voltage and the second power supply voltage supplied to the internal circuit. The voltage shift circuit generates a divided voltage obtained by dividing a potential difference between the virtual power supply voltage and the second power supply voltage as a comparison voltage by a variable resistor connected in series. The operation determination circuit includes a control circuit that generates a test control signal in response to the start of the power shutdown operation of the power shutdown circuit, and the voltage divider circuit is configured to change the variable in response to the power shutdown control signal. The resistance is set to a resistance value for generating the comparison voltage, and the resistance value of the variable resistance is set lower than the resistance value of the resistance component in the internal circuit according to a test control signal from the control circuit. .

  According to this configuration, the resistance value of the variable resistor of the voltage dividing circuit in the voltage shift circuit is set according to the test control signal output from the control circuit based on the power cutoff control signal for causing the power cutoff circuit to perform the power cutoff operation. It is set lower than the resistance value of the resistance component in the internal circuit. Thereby, the discharge path by the low resistance from the virtual power source to the second power source at the connection point between the internal circuit and the power cutoff circuit can be formed. That is, by setting the variable resistance to a low resistance, the voltage dividing circuit can function as a discharge circuit at the start of the power shutoff operation. As a result, the charge charged in the capacitance component in the internal circuit can be quickly discharged via the voltage dividing circuit that functions as a discharge circuit. Therefore, after shifting to the power shut-off operation, an operation test can be performed promptly and the test time can be shortened.

  As described above, according to the present invention, a semiconductor integrated circuit device and a test method for a semiconductor integrated circuit device that can test whether the power cutoff circuit functions normally while suppressing an increase in the wiring area. Can be provided.

(First embodiment)
Hereinafter, an embodiment embodying the present invention will be described with reference to FIGS.
As shown in FIG. 1, the semiconductor integrated circuit device includes an internal circuit 10 to which a high potential power supply voltage VDD and a low potential power supply voltage VSS are supplied. The internal circuit 10 is configured by, for example, a logic circuit, a memory circuit, or a circuit in which a logic circuit and a memory circuit are combined, and is a circuit that exhibits a predetermined function. A power cutoff circuit 20 is inserted and connected between the high potential side power supply terminal of the internal circuit 10 and the high potential power supply VDD.

  The power shut-off circuit 20 is configured by, for example, a P channel MOS transistor. The power cutoff circuit 20 controls the supply / cutoff of the high potential power supply voltage VDD to the internal circuit 10 in accordance with a power cutoff control signal MS input from the outside. More specifically, the power cutoff circuit 20 supplies the high potential power supply voltage VDD to the internal circuit 10 in accordance with, for example, a logic low level (L level) power cutoff control signal MS (power supply energization operation). The power shutoff circuit 20 shuts off the supply of the high potential power supply voltage VDD to the internal circuit 10 in response to, for example, a logic high level (H level) power shutoff control signal MS (power shutoff operation).

  Here, when the power supply cutoff circuit 20 does not function normally, the high potential power supply voltage VDD cannot be supplied to or cut off from the internal circuit 10 at a desired timing. As described above, the internal circuit 10 cannot perform a predetermined function.

  Therefore, in the present embodiment, the operation determination circuit 30 is provided on the semiconductor chip in order to test whether the power supply energization operation and the power supply interruption operation of the power supply interruption circuit 20 function normally. In other words, the operation determination circuit 30 functions normally in the power supply test for determining whether the power supply interruption operation of the power supply cutoff circuit 20 is functioning normally and the power supply cutoff operation of the power supply cutoff circuit 20 in the test mode. It is a circuit for performing a power-off test for determining whether or not. The operation determination circuit 30 includes a voltage shift circuit 40, a reference voltage generation circuit 50, a voltage comparison circuit 60, and a test control circuit 70.

  The voltage shift circuit 40 is connected to a node A (virtual power supply) between the internal circuit 10 and the power cutoff circuit 20. The voltage shift circuit 40 is supplied with the power cutoff control signal MS from the outside and the test control signal TS and the test mode signal TM from the test control circuit 70. The voltage shift circuit 40 is activated in response to a test mode signal TM having a predetermined logic level (for example, H level) input in the test mode. Then, the activated voltage shift circuit 40 converts the voltage (virtual power supply voltage) VD1 of the node A into a comparison voltage Vn corresponding to the sensitivity of the voltage comparison circuit 60 based on the power cutoff control signal MS. The voltage shift circuit 40 also functions as a discharge circuit according to the test control signal TS.

  The reference voltage generation circuit 50 is supplied with a power cutoff control signal MS from the outside and a test mode signal TM from the test control circuit 70. The reference voltage generation circuit 50 is activated in response to an H level test mode signal TM input in the test mode. Then, the activated reference voltage generation circuit 50 generates a high potential reference voltage VRH and a low potential reference voltage VRL by switching according to the power cutoff control signal MS. More specifically, the reference voltage generation circuit 50 generates a high potential reference voltage VRH (first reference voltage) according to the L level power cutoff control signal MS, and decreases according to the H level power cutoff control signal MS. A potential reference voltage VRL (second reference voltage) is generated. Here, the high-potential reference voltage VRH is lower than the comparison voltage Vn generated by the voltage shift circuit 40 when the power shut-off circuit 20 is normally energized according to the L-level power shut-off control signal MS. The voltage is set. The low potential reference voltage VRL is a voltage higher than the comparison voltage Vn generated by the voltage shift circuit 40 when the power shutdown circuit 20 normally performs a power shutdown operation in response to the H level power shutdown control signal MS. Is set to a value.

  The voltage comparison circuit 60 compares the comparison voltage Vn from the voltage shift circuit 40 with the reference voltage VR (high potential reference voltage VRH or low potential reference voltage VRL) from the reference voltage generation circuit 50, and according to the comparison result. Thus, the determination signal JS of H level or L level is generated. The voltage comparison circuit 60 outputs the generated determination signal JS to the output pad 75 via the signal wiring WS and an input / output circuit (not shown).

  The test control circuit 70 outputs the test mode signal TM to the voltage shift circuit 40 and the reference voltage generation circuit 50. The test control circuit 70 generates the test control signal TS in response to an H level power cutoff control signal MS input from the outside, and outputs the test control signal TS to the voltage shift circuit 40.

Next, the internal configuration of each circuit 40, 50 constituting the operation determination circuit 30 will be described with reference to FIG.
As shown in FIG. 2, the voltage shift circuit 40 includes a first voltage dividing circuit 41 and a first switch SW1. The first voltage dividing circuit 41 includes a plurality (two in the present embodiment) of first and second variable resistors VR1 and VR2 connected in series between the node A and the low potential power supply VSS. A node B between the first variable resistor VR1 and the second variable resistor VR2 is connected to a non-inverting input terminal of the voltage comparison circuit 60. Accordingly, the first voltage dividing circuit 41 divides the potential difference between the virtual power supply voltage VD1 and the low potential power supply voltage VSS in accordance with the resistance value ratio between the first variable resistor VR1 and the second variable resistor VR2. (Divided voltage) is generated and output to the voltage comparison circuit 60.

  Here, the resistance values of the first and second variable resistors VR1 and VR2 are set based on the power cutoff control signal MS and the test control signal TS, respectively. These first and second variable resistors VR1 and VR2 are connected in parallel, for example, as shown in FIG. 3, and are connected in series to a plurality of resistors R1 to Rn having different resistance values. The switches S1 to Sn are configured. The first and second variable resistors VR1 and VR2 have a desired resistance value, that is, a virtual power supply voltage VD1 when a desired switch among the switches S1 to Sn is turned on based on the power cutoff control signal MS. Is set to a resistance value for converting to a comparison voltage Vn.

  On the other hand, these first and second variable resistors VR1 and VR2 operate because the voltage shift circuit 40 operates as a discharge circuit when a desired switch among the switches S1 to Sn is turned on based on the test control signal TS. Is set to the resistance value. Here, the reason why the first and second variable resistors VR1 and VR2 are set to such resistance values will be described below.

  First, when the internal circuit 10 is modeled, it is expressed by a resistance component Rm and a capacitance component Cm as shown in FIG. While the high-potential power supply voltage VDD is supplied to such an internal circuit 10, charges are charged in the capacitance component Cm of the internal circuit 10. For this reason, even when the internal circuit 10 is switched from the state in which the high potential power supply voltage VDD is supplied to the power cutoff state, the voltage of the node A (virtual power supply) is not charged until the charge charged in the capacitance component Cm is completely discharged. Voltage) VD1 cannot be measured accurately. Therefore, it cannot be accurately determined whether the power shutoff operation of the power shutoff circuit 20 is functioning normally. For this reason, in order to perform a power-off test for the power-off operation, it is necessary to completely discharge the electric charge charged in the capacitive component Cm. However, since this discharge usually takes a long time of several ms to several s, there is a problem that the test time is increased and, consequently, the cost is increased.

  Therefore, in the present embodiment, the first and second test control signals TS are generated when the power supply is switched off, and the voltage shift circuit 40 is operated as a discharge circuit based on the test control signal TS. The resistance values of the variable resistors VR1 and VR2 are set. That is, when switching to the power shut-off state, the resistance values of the first and second variable resistors VR1 and VR2 are set to be sufficiently lower than the resistance value of the resistance component Rm in the internal circuit 10, thereby reducing the resistance from the node A. A discharge path with a low resistance to the potential power supply VSS is formed. Thereby, the electric charge charged in the capacitance component Cm can be quickly discharged to the low potential power supply VSS via the first and second variable resistors VR1 and VR2.

  Further, as shown in FIG. 2, a first switch SW1 is inserted and connected between the second variable resistor VR2 and the low potential power supply VSS. The first switch SW1 is turned on / off by a test mode signal TM input from the test control circuit 70. The first switch SW1 that is turned on / off connects and disconnects the second variable resistor VR2 (first voltage dividing circuit 41) and the low potential power source VSS. That is, the first switch SW1 is turned on in response to the H-level test mode signal TM input in the test mode, and the first voltage dividing circuit 41 and the low potential power supply VSS are connected. Further, the first switch SW1 is turned off in response to the L-level test mode signal TM that is input at times other than the test mode, and the first voltage dividing circuit 41 and the low potential power supply VSS are disconnected. Therefore, it is possible to suppress the occurrence of leakage current in the voltage shift circuit 40 except during the test mode.

  The reference voltage generation circuit 50 includes a second voltage dividing circuit 51 and a second switch SW2. The second voltage dividing circuit 51 includes a plurality (two in the present embodiment) of third and fourth variable resistors VR3 and VR4 connected in series between the high potential power supply VDD and the low potential power supply VSS. . A node C between the third variable resistor VR3 and the fourth variable resistor VR4 is connected to the inverting input terminal of the voltage comparison circuit 60. Therefore, the second voltage dividing circuit 51 divides the potential difference between the high potential power supply voltage VDD and the low potential power supply voltage VSS according to the resistance value ratio between the third variable resistor VR3 and the fourth variable resistor VR4. A VR (divided voltage) is generated and output to the voltage comparison circuit 60.

  Here, the resistance values of the third and fourth variable resistors VR3 and VR4 are set based on the power cutoff control signal MS. More specifically, the third and fourth variable resistors VR3 and VR4 are set to resistance values for generating the high-potential reference voltage VRH as the reference voltage VR according to the L-level power cutoff control signal MS. Further, the third and fourth variable resistors VR3 and VR4 are set to resistance values for generating the low potential reference voltage VRL as the reference voltage VR in accordance with the H level power cutoff control signal MS. The third and fourth variable resistors VR3 and VR4 are configured in substantially the same manner as the first and second variable resistors VR1 and VR2. However, the difference is that the test control signal TS from the test control circuit 70 is not input.

  A second switch SW2 is inserted and connected between the fourth variable resistor VR4 and the low potential power supply VSS. Similar to the first switch SW1, the second switch SW2 is turned on / off by the test mode signal TM input from the test control circuit 70, and the fourth variable resistor VR4 (second voltage dividing circuit 51) and the low-potential power supply VSS. To and from.

  In the voltage comparison circuit 60, the comparison voltage Vn is input to the non-inverting input terminal, and the reference voltage VR is input to the inverting input terminal. The voltage comparison circuit 60 outputs an H level determination signal JS when the comparison voltage Vn is higher than the reference voltage VR, and outputs an L level determination signal JS when the comparison voltage Vn is lower than the reference voltage VR. Therefore, in the power supply energization test for the power supply energization operation of the power cut-off circuit 20, it is determined that the function is normal when the comparison voltage Vn is higher than the high potential reference voltage VRH and the H level determination signal JS is output. Is done. On the other hand, in the power-off test for the power-off operation of the power-off circuit 20, it is determined that the function is normal when the comparison voltage Vn is lower than the low potential reference voltage VRL and the L-level determination signal JS is output. Is done.

Next, a power supply energization test and a power cut-off test in the test mode of the operation determination circuit 30 configured as described above will be described with reference to FIGS.
First, a power supply energization test for determining whether the power supply energization operation of the power cut-off circuit 20 is functioning normally will be described with reference to FIG.

  First, an H-level test mode signal TM indicating the test mode is input to the first and second switches SW1 and SW2, and the switches SW1 and SW2 are turned on. That is, the voltage shift circuit 40 and the reference voltage generation circuit 50 are activated (step S1). Next, the L level power cutoff control signal MS is input to the power cutoff circuit 20 or the like (step S2).

  Subsequently, the resistance values of the first to fourth variable resistors VR1 to VR4 are set based on the L-level power cutoff control signal MS (step S3). Specifically, the first and second variable resistors VR1 and VR2 have resistance values for converting the virtual power supply voltage VD1 into the comparison voltage Vn, and the resistance values of the second variable resistor VR2 are shown in FIG. It is set to be sufficiently larger than the resistance value of the resistance component Rm of the internal circuit 10. The third and fourth variable resistors VR3 and VR4 are set to resistance values for generating the high potential reference voltage VRH as the reference voltage VR.

  When the resistance values of the first to fourth variable resistors VR <b> 1 to VR <b> 4 are set, the voltage comparison circuit 60 includes the comparison voltage Vn input from the voltage shift circuit 40 and the high potential reference input from the reference voltage generation circuit 50. The voltage VRH is compared, and a determination signal JS corresponding to the comparison result is generated. Then, the determination signal JS output from the voltage comparison circuit 60 is detected via the output pad 75, and whether the power supply energization operation of the power cut-off circuit 20 functions normally according to the logic level of the determination signal JS. It is determined whether or not (step S4). That is, when the power supply energization operation of the power supply cutoff circuit 20 is functioning normally, the comparison voltage Vn generated by the voltage shift circuit 40 becomes higher than the high potential reference voltage VRH. Accordingly, when the H level determination signal JS output from the voltage comparison circuit 60 is detected when the comparison voltage Vn is higher than the high potential reference voltage VRH, the power supply operation of the power supply cutoff circuit 20 functions normally. It is determined that On the other hand, when the L level determination signal JS is detected, it is determined that the power supply energization operation of the power cut-off circuit 20 is abnormal.

Next, a power shutdown test for determining whether the power shutdown operation of the power shutdown circuit 20 is functioning normally will be described with reference to FIG.
First, an H-level test mode signal TM indicating the test mode is input to the first and second switches SW1 and SW2, and the switches SW1 and SW2 are turned on. That is, the voltage shift circuit 40 and the reference voltage generation circuit 50 are activated (step S11). Next, the H level power cutoff control signal MS is input to the power cutoff circuit 20 or the like (step S12).

  Subsequently, immediately after the H-level power cutoff control signal MS is output, the test control signal TS is output from the test control circuit 70. Based on the test control signal TS, the resistance values of the first and second variable resistors VR1 and VR2 are sufficiently lower than the resistance value of the resistance component Rm of the internal circuit 10 shown in FIG. 4 (VR1 << Rm, VR2 < <Rm) is set (step S13). As a result, a discharge path with a low resistance is formed from the node A to the low potential power supply VSS. Therefore, when the high potential power supply VDD is normally shut off by the power shutoff circuit 20, it accumulates in the capacitance component of the internal circuit 10. The charged charges are quickly discharged to the low potential power supply VSS via the variable resistors VR1 and VR2.

  Next, the resistance values of the first to fourth variable resistors VR1 to VR4 are set based on the H-level power cutoff control signal MS (step S14). Specifically, the first and second variable resistors VR1 and VR2 have resistance values for converting the virtual power supply voltage VD1 into the comparison voltage Vn, and the resistance values of the second variable resistor VR2 are shown in FIG. It is set to be sufficiently larger than the resistance value of the resistance component Rm of the internal circuit 10. The third and fourth variable resistors VR3 and VR4 are set to resistance values for generating the low potential reference voltage VRL.

  When the resistance values of the first to fourth variable resistors VR <b> 1 to VR <b> 4 are set, the voltage comparison circuit 60 includes the comparison voltage Vn input from the voltage shift circuit 40 and the low potential reference input from the reference voltage generation circuit 50. The voltage VRL is compared, and a determination signal JS corresponding to the comparison result is generated. Then, the determination signal JS output from the voltage comparison circuit 60 is detected via the output pad 75, and whether the power cut-off operation of the power cut-off circuit 20 functions normally according to the logic level of the determination signal JS. It is determined whether or not (step S15). That is, when the power cutoff operation of the power cutoff circuit 20 is functioning normally, the comparison voltage Vn generated by the voltage shift circuit 40 is lower than the low potential reference voltage VRL. Therefore, when the L level determination signal JS output from the voltage comparison circuit 60 is detected when the comparison voltage Vn is lower than the low potential reference voltage VRL, the power shutdown operation of the power shutdown circuit 20 functions normally. It is determined that On the other hand, when the determination signal JS at the H level is detected, it is determined that the power cutoff operation of the power cutoff circuit 20 is abnormal.

According to this embodiment described above, the following effects can be obtained.
(1) An operation determination circuit 30 that generates a determination signal JS indicating whether the power shutoff circuit 20 is functioning normally is provided. Therefore, by detecting this determination signal JS via the output pad 75, it can be tested whether the power shutoff circuit 20 is functioning normally. Further, the determination signal JS is output from the operation determination circuit 30 to the output pad 75. Thereby, the wiring from the operation determination circuit 30 to the output pad 75 can be a signal wiring WS having a wiring width narrower than that of the power supply wiring WP. Therefore, an increase in the wiring area is suppressed as compared with the case where the wiring from the node A to the power supply pad 130 between the internal circuit 110 and the power supply cutoff circuit 120 is formed by the power supply wiring WP (see FIG. 13). Can do.

  Furthermore, since the output terminal of the operation determination circuit 30 (voltage comparison circuit 60) is connected to the output pad 75 via an input / output circuit (not shown), the node A (virtual power supply) and the power supply pad 130 are directly connected. Compared to the case (see FIG. 13), resistance to electrostatic discharge (ESD) can be improved.

  (2) In the power supply energization test, the comparison voltage Vn generated based on the virtual power supply voltage VD1 is compared with the high potential reference voltage VRH, and in the power interruption test, the comparison voltage Vn is compared with the low potential reference voltage VRL. Thus, the determination signal JS is generated. In this way, by comparing the reference voltage VR according to the operation state and the comparison voltage Vn, it is determined whether or not these operations are functioning normally for both the power supply operation and the power supply operation of the power supply circuit 20. Can be tested reliably.

  (3) The reference voltage generation circuit 50 generates the high-potential reference voltage VRH and the low-potential reference voltage VRL by switching according to the power-off control signal MS for switching and controlling the power-on / off operation of the power-off circuit 20. I tried to do it. Thus, since the power cutoff control signal MS that originally exists is shared as a control signal for switching the reference voltage VR, an increase in the number of control signals can be suppressed.

  (4) In the power-off test, the voltage shift circuit 40 is caused to function as a discharge circuit in accordance with the test control signal TS generated by the test control circuit 70 based on the H-level power-off control signal MS. . As a result, after the start of the power shutoff operation of the power shutoff circuit 20, the voltage shift circuit 40 (first and second variable resistors VR1 and VR2) that functions as a discharge circuit converts the charge charged in the capacitance component Cm in the internal circuit 10 into the voltage shift circuit 40. ) Can be quickly discharged. Therefore, after shifting to the power shut-off operation, the comparison operation in the voltage comparison circuit 60 can be performed quickly, and the test time can be shortened.

  (5) The voltage shift circuit 40 and the reference voltage generation circuit 50 are provided with first and second switches SW1 and SW2 that are turned off except during the test mode. Thereby, it is possible to suppress the occurrence of a leak current in the voltage shift circuit 40 and the reference voltage generation circuit 50 except during the test mode. Therefore, useless power consumption by the voltage shift circuit 40 and the reference voltage generation circuit 50 can be reduced.

(Second Embodiment)
A second embodiment embodying the present invention will be described below with reference to FIG. The same members as those shown in FIGS. 1 to 6 are denoted by the same reference numerals, and detailed description of these elements is omitted.

  As shown in FIG. 7, the semiconductor integrated circuit device includes a first internal circuit 10a to which a first high potential power supply voltage VDD1 and a low potential power supply voltage VSS are supplied, a second high potential power supply voltage VDD2, and a low potential power supply voltage VSS. Is supplied to the second internal circuit 10b.

  A power cutoff circuit 20a is inserted and connected between the high potential side power supply terminal of the first internal circuit 10a and the first high potential power supply voltage VDD1. A voltage shift circuit 40a is connected to a node A1 between the first internal circuit 10a and the power cutoff circuit 20a. The voltage (first virtual power supply voltage) VD1 at the node A1 is input to the voltage shift circuit 40a. The voltage comparison circuit 60a compares the comparison voltage Vn from the voltage shift circuit 40a with the reference voltage VR from the reference voltage generation circuit 50a, and generates a first determination signal JS1 according to the comparison result. The voltage comparison circuit 60a outputs the generated first determination signal JS1 to the selection circuit 80.

  On the other hand, a power cutoff circuit 20b is inserted and connected between the high potential side power supply terminal of the second internal circuit 10b and the second high potential power supply voltage VDD2. A voltage shift circuit 40b is connected to the node A2 between the second internal circuit 10b and the power cutoff circuit 20b. The voltage (second virtual power supply voltage) VD2 of the node A2 is input to the voltage shift circuit 40b. The voltage comparison circuit 60b compares the comparison voltage Vn from the voltage shift circuit 40b with the reference voltage VR from the reference voltage generation circuit 50b, and generates a second determination signal JS2 according to the comparison result. The voltage comparison circuit 60b outputs the generated second determination signal JS2 to the selection circuit 80.

  The test control circuit 70 outputs a test mode signal TM to the voltage shift circuits 40a and 40b and the reference voltage generation circuits 50a and 50b, and outputs a test control signal TS to the voltage shift circuits 40a and 40b. Further, the test control circuit 70 outputs a selection signal SS to the selection circuit 80.

  The selection circuit 80 selects one of the first determination signal JS1 and the second determination signal JS2 according to the selection signal SS from the test control circuit 70. The selection circuit 80 outputs the selected determination signal to the output pad 75 via the signal wiring WS and an input / output circuit (not shown). That is, the selection circuit 80 selects the first determination signal JS1 when performing a power supply energization test and a power supply shutoff test for the power supply shutoff circuit 20a, and selects the first determination signal JS1 when performing a power supply energization test and a power supply shutoff test for the power shutoff circuit 20b. 2 Select the determination signal JS2.

According to the embodiment described above, the following effects are obtained in addition to the effects (1) to (5) of the first embodiment.
(6) A selection circuit that selects one of the first and second determination signals JS1 and JS2 input from the plurality of voltage comparison circuits 60a and 60b and outputs the selected determination signal to the output pad 75. 80 was provided. As a result, the output pads provided for the operation test of the plurality of power shutoff circuits 20a and 20b can be shared, so that an increase in the number of output pads can be suitably suppressed.

  (7) An operation determination circuit is provided for each of the internal circuits 10a and 10b to which different power supply voltages (first high potential power supply voltage VDD1 or second high potential power supply voltage VDD2) are supplied. As a result, the voltage shift circuits 40a and 40b and the reference voltage generation circuits 50a and 50b in each operation determination circuit can be configured in accordance with the respective power supply voltages, so that the desired reference voltage VR is reliably generated. be able to.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to FIGS. The semiconductor integrated circuit device of this embodiment is different from the first embodiment in that a current detection circuit 90 is added. The same members as those shown in FIGS. 1 to 7 are denoted by the same reference numerals, and detailed description of these elements is omitted.

  As shown in FIG. 8, there is provided a current detection circuit 90 that is connected to a node A between the internal circuit 10 and the power cutoff circuit 20 and detects a virtual power supply current ID1 flowing through the node A (virtual power supply VD1). Yes. The current detection circuit 90 outputs a current detection signal DS corresponding to the detected current amount of the virtual power supply current ID1 to the output pad 76. An example of the internal configuration of such a current detection circuit 90 is shown in FIG.

  As shown in FIG. 9, the current detection circuit 90 includes a resistor Rd connected between the node A and the low potential power supply VSS. Both terminals of the resistor Rd are connected to the input terminal of the current amplifier 91. The current amplifier 91 detects the current ID1 flowing through the resistor Rd, that is, the virtual power supply current, and outputs a detection signal corresponding to the amount of current to the A / D converter 92. The A / D converter 92 converts the detection signal into a digital signal (current detection signal DS) and outputs the current detection signal DS to the output pad 76.

According to the embodiment described above, the following effects are obtained in addition to the effects (1) to (5) of the first embodiment.
(8) As shown in FIGS. 10A and 10B, a plurality (two in FIG. 10) of internal circuits 10a and 10b are connected to one power source (for example, the high potential power source VDD). In this case, the current flowing through the high potential power supply VDD is the sum of the currents flowing through the internal circuits 10a and 10b. Therefore, when the supply of the high-potential power supply voltage VDD to a specific internal circuit is cut off, even if the current flowing through the high-potential power supply VDD is measured, the current flowing through the node A of each internal circuit cannot be predicted. Have difficulty. Therefore, it is difficult to calculate the power consumption of each internal circuit calculated by multiplying the virtual power supply current and the high potential power supply voltage VDD.

  In contrast, in the present embodiment, the current detection circuit 90 that detects the virtual power supply current ID1 flowing in the virtual power supply (node A) is provided. Thus, even when the supply of the high potential power supply voltage VDD to a specific internal circuit is interrupted, the virtual power supply current of each internal circuit can be detected by the current detection circuit 90. Therefore, the power consumption of each internal circuit can be easily calculated using the current value detected by the current detection circuit 90.

In addition, the said embodiment can also be implemented in the following aspects which changed this suitably.
In each of the embodiments described above, the voltage of the node A (virtual power supply voltage) is detected, and the virtual power supply voltage is compared with the reference voltage VR to determine whether the power shutoff circuit 20 is functioning normally. did. For example, a current (virtual power supply current) flowing through the node A is detected, and the current is compared with a reference current to determine whether the power shutoff circuit 20 is functioning normally. Good.

  In each of the above embodiments, the power cutoff circuit 20 is inserted and connected between the high potential side power supply terminal of the internal circuit 10 and the high potential power supply VDD. For example, as illustrated in FIG. 11, the power cutoff circuit 20 may be inserted and connected between the low potential power supply terminal of the internal circuit 10 and the low potential power supply VSS. In this case, the power cut-off circuit 20 is configured by, for example, an N-channel MOS transistor. Alternatively, a power cutoff circuit may be inserted and connected both between the internal circuit 10 and the high potential power supply VDD and between the internal circuit 10 and the low potential power supply VSS.

  The test control signal TS output from the test control circuit 70 in each of the above embodiments may be omitted. That is, in this case, step S13 (see FIG. 6) in the test method for the power-off operation of the power-off circuit 20 is omitted.

  In each of the above embodiments, the power cutoff control signal MS for controlling the operation of the power cutoff circuit 20 is used as a signal for setting the resistance values of the voltage shift circuit 40 and the reference voltage generation circuit 50. However, the present invention is not limited thereto, and a dedicated control signal for controlling the voltage shift circuit 40 and the reference voltage generation circuit 50 may be input to the voltage shift circuit 40 and the reference voltage generation circuit 50.

In each of the above embodiments, the power cutoff control signal MS is input from the outside, but a circuit for outputting the power cutoff control signal MS may be provided on the semiconductor chip.
The test control circuit 70 in each of the above embodiments generates the test control signal TS in response to the input of the H level power shutoff control signal MS. The test control signal TS may be generated in response to the start of the power shutoff operation.

  In each of the above embodiments, the test control circuit 70 outputs the test control signal TS and the test mode signal TM. However, the test control signal TS and the test mode signal TM are input from the outside, respectively. Also good.

  The internal configuration of each of the variable resistors VR1 to VR4 in the above embodiments is not particularly limited to the configuration illustrated in FIG. For example, each of the variable resistors VR1 to VR4 may be configured by a P channel MOS transistor. In this case, the resistance value can be changed by changing the voltage applied to the control element (gate).

  The internal configuration of the voltage shift circuit 40 in each of the above embodiments is not particularly limited to the configuration shown in FIG. For example, the first switch SW1 of the voltage shift circuit 40 may be omitted. In this case, for example, other than in the test mode, the resistance values of the variable resistors VR1 and VR2 are set sufficiently higher than the resistance value of the resistance component Rm of the internal circuit 10, and leakage current flowing from the node A to the low potential power source VSS is generated. You may make it reduce. Alternatively, the first and second variable resistors VR1 and VR2 may be changed to fixed resistors.

  The internal configuration of the reference voltage generation circuit 50 in each of the above embodiments is not particularly limited to the configuration shown in FIG. For example, the second switch SW2 of the reference voltage generation circuit 50 may be omitted. The reference voltage generation circuit 50 is a circuit that switches and generates the high potential reference voltage VRH and the low potential reference voltage VRL in accordance with switching between supply / cutoff of the high potential power supply voltage VDD to the corresponding internal circuit 10. Preferably there is.

  In the above-described embodiments, the reference voltage generation circuit 50 generates the high potential reference voltage VRH and the low potential reference voltage VRL by using one second voltage dividing circuit 51. For example, the reference voltage generation circuit 50 may be configured by a circuit that generates the high potential reference voltage VRH and a circuit that generates the low potential reference voltage VRL.

  In each of the above embodiments, the high potential power supply voltage VDD and the low potential power supply voltage VSS are supplied to the reference voltage generation circuit 50. However, for example, a power supply voltage different from the high potential power supply voltage VDD and the low potential power supply voltage VSS is used. The reference voltage generation circuit 50 may be supplied.

  The voltage shift circuit 40 in each of the above embodiments may be omitted. In this case, the voltage value of the high potential reference voltage VRH or the low potential reference voltage VRL generated by the reference voltage generation circuit 50 can be set according to the virtual power supply voltage VD1 input to the voltage comparison circuit 60. preferable. For example, the high potential reference voltage VRH is set to a voltage value lower than the virtual power supply voltage VD1 when the power supply cutoff circuit 20 normally performs the power supply operation according to the L level power supply cutoff control signal MS. Further, the low potential reference voltage VRL is set to a voltage value higher than the virtual power supply voltage VD1 when the power shutdown circuit 20 normally performs the power shutdown operation in response to the H level power shutdown control signal MS.

  -There is no restriction | limiting in particular in the number of the internal circuits 10 (1st and 2nd internal circuit 10a, 10b) in the said 2nd Embodiment. The first and second internal circuits 10a and 10b are supplied with different high-potential power supply voltages VDD1 and VDD2, respectively, but may be supplied with the same high-potential power supply voltage.

  In the second embodiment, the selection circuit 80 selects one of the first and second determination signals JS1 and JS2 based on the selection signal SS input from the test control circuit 70. For example, any one of the power cutoff control signals MS1 and MS2 input to the power cutoff circuits 20a and 20b may be used as a selection signal. The selection signal SS may be input from the outside.

  In the second embodiment, the test control circuit 70 is shared by the plurality of internal circuits 10a and 10b. However, the test control circuit 70 may be provided for each internal circuit.

  In the second embodiment, the selection circuit 80 selects the determination signals JS1 and JS2 from the voltage comparison circuits 60a and 60b. For example, as shown in FIG. 12, the selection circuit 85 may select the virtual power supply voltage VD1 of the first internal circuit 10a and the virtual power supply voltage VD2 of the second internal circuit 10b. According to this configuration, one of the virtual power supply voltages VD 1 and VD 2 selected by the selection circuit 85 is input to the voltage shift circuit 40. Thus, one operation determination circuit 30 (voltage shift circuit 40, reference voltage generation circuit 50, voltage comparison circuit 60, test control circuit 70) for a plurality (two in FIG. 12) of power shutoff circuits 20a and 20b. It is possible to determine whether or not the power shutoff circuits 20a and 20b are functioning normally. Therefore, the circuit area can be greatly reduced.

  In the case of the configuration of FIG. 12, the voltage shift circuit 40 and the reference voltage generation circuit 50 correspond to the comparison voltage Vn and the reference corresponding to each power source according to the combination of the power cutoff control signals MS1, MS2 and the selection signal SS. A voltage VR is generated.

The internal configuration of the current detection circuit 90 in the third embodiment is not particularly limited to the configuration shown in FIG.
The current detection circuit 90 of the third embodiment may be applied to the semiconductor integrated circuit device of the second embodiment or the semiconductor integrated circuit device of FIG. In these cases, it is necessary to provide a selection circuit for the current detection circuit 90 corresponding to the selection circuits 80 and 85.

The various embodiments described above can be summarized as follows.
(Appendix 1)
Connected between an internal circuit to which a power supply voltage is supplied and the internal circuit and a power supply for supplying the power supply voltage, and controls supply / cutoff of the power supply voltage to the internal circuit according to a power supply cutoff control signal. In a semiconductor integrated circuit device comprising a power cutoff circuit,
Whether the power shutoff circuit is functioning normally based on the virtual power supply voltage or virtual power supply current at the connection point between the internal circuit and the power shutoff circuit during an operation test for testing the operation of the power shutoff circuit A semiconductor integrated circuit device comprising: an operation determination circuit that generates a determination signal indicating whether or not and outputs the generated determination signal to an output pad.
(Appendix 2)
A plurality of internal circuits each supplied with a corresponding power supply voltage, and connected between each internal circuit and a power supply that supplies the corresponding power supply voltage, and supply of the corresponding power supply voltage to each internal circuit In a semiconductor integrated circuit device comprising a plurality of power shut-off circuits for controlling shut-off according to a power shut-off control signal,
A plurality of internal circuits each having a power supply terminal, a single or a plurality of power supplies for supplying a power supply voltage corresponding to each of the power supply terminals of each internal circuit, and a connection between the power supply terminal of each internal circuit and the power supply A plurality of power shut-off circuits that control supply / shut-off of the power supply voltage to each internal circuit in accordance with a power shut-off control signal,
A plurality of determination signals indicating whether or not each of the power supply cutoff circuits is functioning normally based on a virtual power supply voltage or a virtual power supply current at a connection point between each of the internal circuits and each of the power supply cutoff circuits An operation determination circuit of
A semiconductor integrated circuit device comprising: a selection circuit that selects any one of a plurality of determination signals input from each of the operation determination circuits and outputs the selected determination signal to an output pad; .
(Appendix 3)
The operation determination circuit includes:
A power cutoff operation in which the power cutoff circuit generates a first reference voltage during a power supply energization operation for supplying the power supply voltage to the internal circuit, and the power cutoff circuit cuts off the supply of the power supply voltage to the internal circuit A reference voltage generating circuit for generating a second reference voltage at the time of
A comparison circuit that compares the first reference voltage or the second reference voltage from the reference voltage generation circuit with a virtual power supply voltage and generates the determination signal;
The semiconductor integrated circuit device according to appendix 1 or 2, characterized by comprising:
(Appendix 4)
4. The semiconductor integrated circuit device according to appendix 3, wherein the reference voltage generation circuit switches and generates the first reference voltage and the second reference voltage in accordance with the power cutoff control signal.
(Appendix 5)
The reference voltage generation circuit generates a divided voltage obtained by dividing a potential difference between a high potential power source and a low potential power source as a first reference voltage or a second reference voltage by a variable resistor connected in series. Pressure circuit,
The voltage dividing circuit generates the divided voltage by switching the first reference voltage and the second reference voltage by changing a resistance value of the variable resistor according to the power-off control signal. The semiconductor integrated circuit device according to appendix 3 or 4, characterized by the above.
(Appendix 6)
The operation determination circuit includes a voltage shift circuit that converts the virtual power supply voltage into a comparison voltage corresponding to the sensitivity of the comparison circuit,
The comparison circuit compares the first reference voltage or the second reference voltage from the reference voltage generation circuit with the comparison voltage from the voltage shift circuit, and generates the determination signal. The semiconductor integrated circuit device according to any one of appendices 3 to 5.
(Appendix 7)
The power cutoff circuit is a circuit that controls supply / cutoff of the first power supply voltage to the internal circuit among the first power supply voltage and the second power supply voltage supplied to the internal circuit,
The voltage shift circuit includes a voltage dividing circuit that generates, as the comparison voltage, a divided voltage obtained by dividing a potential difference between the virtual power supply voltage and the second power supply voltage by a variable resistor connected in series.
The operation determination circuit includes a control circuit that generates a test control signal in response to the start of the power-off operation of the power-off circuit.
The voltage dividing circuit sets the variable resistor to a resistance value for generating the comparison voltage according to the power-off control signal, and also sets a resistance of the variable resistor according to the test control signal from the control circuit. The semiconductor integrated circuit device according to appendix 6, wherein a value is set lower than a resistance value of a resistance component in the internal circuit.
(Appendix 8)
8. The semiconductor integrated circuit device according to appendix 6 or 7, wherein the voltage shift circuit and the reference voltage generation circuit are activated by a test mode signal indicating a test mode for performing the operation test.
(Appendix 9)
The semiconductor integrated circuit device according to any one of appendices 3 to 8, further comprising a current detection circuit that detects the virtual power supply current that flows to a connection point between the internal circuit and the power supply cutoff circuit.
(Appendix 10)
A plurality of internal circuits each having a power supply terminal, a single or a plurality of power supplies for supplying a power supply voltage corresponding to each of the power supply terminals of each internal circuit, and a connection between the power supply terminal of each internal circuit and the power supply A plurality of power shut-off circuits that control supply / shut-off of the power supply voltage to each internal circuit in accordance with a power shut-off control signal,
A virtual power supply voltage or a virtual power supply current at a connection point between each internal circuit and each power supply cutoff circuit is input, and any one of the plurality of virtual power supply voltages or any one of the plurality of virtual power supply currents is input. A selection circuit for selecting one virtual power supply current;
Based on the virtual power supply voltage or virtual power supply current selected by the selection circuit, a determination signal indicating whether or not the corresponding power cutoff circuit is functioning normally is generated, and the generated determination signal is output to the output pad. A semiconductor integrated circuit device comprising: an operation determination circuit for outputting.
(Appendix 11)
A power supply energizing operation for supplying the power supply voltage to the internal circuit and the power supply voltage to the internal circuit connected between the internal circuit to which the power supply voltage is supplied, the internal circuit and the power supply for supplying the power supply voltage A power cutoff circuit that switches and executes a power cutoff operation that cuts off the supply of power according to a power cutoff control signal, and the power supply based on a virtual power supply voltage at a connection point between the internal circuit and the power cutoff circuit A test method for a semiconductor integrated circuit device comprising: an operation determination circuit that generates a determination signal indicating whether or not a power supply energization operation and a power supply disconnection operation of a cutoff circuit are functioning normally and outputs them to an output pad ,
The operation determination circuit includes:
When testing the power supply energization operation of the power supply cut-off circuit, a first reference voltage is generated in response to the start of the power supply energization operation of the power supply cut-off circuit, and the first reference voltage is compared with the virtual power supply voltage. And generating the determination signal,
When testing the power shutdown operation of the power shutdown circuit, a second reference voltage is generated in response to the start of the power shutdown operation of the power shutdown circuit, and the second reference voltage is compared with the virtual power supply voltage. A test method for a semiconductor integrated circuit device, wherein the determination signal is generated.
(Appendix 12)
The operation determination circuit includes:
In the test of the power shutdown operation, a test control signal is generated according to the power shutdown control signal for causing the power shutdown circuit to perform the power shutdown operation, and a capacitance component of the internal circuit is charged according to the test control signal 12. The test method for a semiconductor integrated circuit device according to appendix 11, wherein a discharge path having a resistance lower than a resistance component of the internal circuit is formed to discharge the generated charge.

1 is a block diagram showing a semiconductor integrated circuit device according to a first embodiment. The circuit diagram which shows the internal structural example of a voltage shift circuit and a reference voltage generation circuit. The circuit diagram which shows the internal structural example of a variable resistance. Explanatory drawing which shows the modeled internal circuit. The flowchart which shows the test method about power supply energization operation | movement. The flowchart which shows the test method about power-off operation. The block diagram which shows the semiconductor integrated circuit device of 2nd Embodiment. The block diagram which shows the semiconductor integrated circuit device of 3rd Embodiment. The circuit diagram which shows the internal structural example of a current detection circuit. (A), (b) is a block diagram which shows a semiconductor integrated circuit device provided with a some internal circuit, respectively. The block diagram which shows the semiconductor integrated circuit device in another example. The block diagram which shows the semiconductor integrated circuit device in another example. Explanatory drawing for demonstrating the conventional test method.

Explanation of symbols

10, 10a, 10b Internal circuit 20, 20a, 20b Power cut-off circuit 30 Operation determination circuit 40, 40a, 40b Voltage shift circuit 41 Voltage divider circuit 50, 50a, 50b Reference voltage generation circuit 51 Voltage divider circuit 60, 60a, 60b Voltage Comparison circuit (comparison circuit)
70 Test control circuit (control circuit)
75 Output pad 80 Selection circuit 90 Current detection circuit VDD High potential power supply voltage (power supply voltage, first power supply voltage)
VSS Low potential power supply voltage (power supply voltage, second power supply voltage)
VD1, VD2 Virtual power supply voltage VR Reference voltage Vn Comparison voltage VR1-VR4 Variable resistance Rm Resistance component Cm Capacity component

Claims (7)

Connected between an internal circuit to which a power supply voltage is supplied and the internal circuit and a power supply for supplying the power supply voltage, and controls supply / cutoff of the power supply voltage to the internal circuit according to a power supply cutoff control signal. In a semiconductor integrated circuit device comprising a power cutoff circuit,
Whether the power shutoff circuit is functioning normally based on the virtual power supply voltage or virtual power supply current at the connection point between the internal circuit and the power shutoff circuit during an operation test for testing the operation of the power shutoff circuit A semiconductor integrated circuit device comprising: an operation determination circuit that generates a determination signal indicating whether or not and outputs the generated determination signal to an output pad. A plurality of internal circuits each supplied with a corresponding power supply voltage, and connected between each internal circuit and a power supply that supplies the corresponding power supply voltage, and supply of the corresponding power supply voltage to each internal circuit In a semiconductor integrated circuit device comprising a plurality of power shut-off circuits for controlling shut-off according to a power shut-off control signal,
A plurality of determination signals indicating whether or not each of the power supply cutoff circuits is functioning normally based on a virtual power supply voltage or a virtual power supply current at a connection point between each of the internal circuits and each of the power supply cutoff circuits An operation determination circuit of
A semiconductor integrated circuit device comprising: a selection circuit that selects any one of a plurality of determination signals input from each of the operation determination circuits and outputs the selected determination signal to an output pad; . The operation determination circuit includes:
A power cutoff operation in which the power cutoff circuit generates a first reference voltage during a power supply energization operation for supplying the power supply voltage to the internal circuit, and the power cutoff circuit cuts off the supply of the power supply voltage to the internal circuit A reference voltage generating circuit for generating a second reference voltage at the time of
A comparison circuit that compares the first reference voltage or the second reference voltage from the reference voltage generation circuit with a virtual power supply voltage and generates the determination signal;
The semiconductor integrated circuit device according to claim 1, comprising: The reference voltage generation circuit generates a divided voltage obtained by dividing a potential difference between a high potential power source and a low potential power source as a first reference voltage or a second reference voltage by a variable resistor connected in series. Pressure circuit,
The voltage dividing circuit generates the divided voltage by switching the first reference voltage and the second reference voltage by changing a resistance value of the variable resistor according to the power-off control signal. 4. The semiconductor integrated circuit device according to claim 3, wherein: The operation determination circuit includes a voltage shift circuit that converts the virtual power supply voltage into a comparison voltage corresponding to the sensitivity of the comparison circuit,
The comparison circuit compares the first reference voltage or the second reference voltage from the reference voltage generation circuit with the comparison voltage from the voltage shift circuit, and generates the determination signal. The semiconductor integrated circuit device according to claim 3 or 4. The power cutoff circuit is a circuit that controls supply / cutoff of the first power supply voltage to the internal circuit among the first power supply voltage and the second power supply voltage supplied to the internal circuit,
The voltage shift circuit includes a voltage dividing circuit that generates, as the comparison voltage, a divided voltage obtained by dividing a potential difference between the virtual power supply voltage and the second power supply voltage by a variable resistor connected in series.
The operation determination circuit includes a control circuit that generates a test control signal in response to the start of the power-off operation of the power-off circuit.
The voltage dividing circuit sets the variable resistor to a resistance value for generating the comparison voltage according to the power-off control signal, and also sets a resistance of the variable resistor according to the test control signal from the control circuit. 6. The semiconductor integrated circuit device according to claim 5, wherein a value is set lower than a resistance value of a resistance component in the internal circuit. A power supply energizing operation for supplying the power supply voltage to the internal circuit and the power supply voltage to the internal circuit connected between the internal circuit to which the power supply voltage is supplied, the internal circuit and the power supply for supplying the power supply voltage A power cutoff circuit that switches and executes a power cutoff operation that cuts off the supply of power according to a power cutoff control signal, and the power supply based on a virtual power supply voltage at a connection point between the internal circuit and the power cutoff circuit A test method for a semiconductor integrated circuit device comprising: an operation determination circuit that generates a determination signal indicating whether or not a power supply energization operation and a power supply disconnection operation of a cutoff circuit are functioning normally and outputs them to an output pad ,
The operation determination circuit includes:
When testing the power supply energization operation of the power supply cut-off circuit, a first reference voltage is generated in response to the start of the power supply energization operation of the power supply cut-off circuit, and the first reference voltage is compared with the virtual power supply voltage. And generating the determination signal,
When testing the power shutdown operation of the power shutdown circuit, a second reference voltage is generated in response to the start of the power shutdown operation of the power shutdown circuit, and the second reference voltage is compared with the virtual power supply voltage. A test method for a semiconductor integrated circuit device, wherein the determination signal is generated.

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