JP5051215B2 - Arithmetic system - Google Patents

Description

The present invention includes a plurality of memory banks for storing data relating to operation, the processor and, to a computation system with an address interconnection network that connects the processor and the memory bank to each other.

In an arithmetic system including an address interconnection network that couples a processor and an address generation device to a memory and a data interconnection network that couples a processor and an arithmetic unit to a memory, for example, the memory has a bank BNK0, an address adr8 assigned to addresses adr0-7. Bank BNK1 assigned to .about.15, bank BNK2 assigned to addresses adr16 to 23, and bank BNK3 assigned to addresses adr24 to 31.
In this case, when the address for accessing the memory from the processor is adr0, 8, 16, 24, 1, 9, 17, 25,..., 7, 15, 23, 31, this is described in Patent Document 1, for example. By using such a memory interleaving method, a desired access address can be generated.

JP 2000-163316 A

However, in this method, only address conversion is performed, and data corresponding to the address must be selected by another means.
Further, when the address when accessing the memory from the processor is, for example, adr0, 8, 16, 24, 1, 9, 17, 25,..., 7, 15, 23, 31, Since desired address translation is not performed, it is necessary to perform address calculation by the processor.
In this case, addresses such as 0, 8, 16, 24, 1, 9, 17, 25,..., 7, 15, 23, 31 cannot be generated only by using the simple address automatic generation function of the processor. .
Therefore, it is necessary to perform address calculation separately from the calculation using the processor, and there is a disadvantage that the number of processing cycles is extra for the generation of addresses than the number of cycles required for the calculation.

  In addition, the method disclosed in Patent Document 1 requires two stages of address translation devices, which increases the hardware scale and is not preferable from the viewpoint of cost reduction.

The present invention has been made in view of such circumstances, and its object is to reduce the number of extra processing cycles, improve memory access performance, reduce the hardware scale, and thus cost. to provide a computation system that can be reduced.

  In order to achieve the above object, an arithmetic system according to the first aspect of the present invention has a function of generating a plurality of memory banks to which a predetermined range of addresses in an address space is assigned, storing data related to the arithmetic operation, and consecutive addresses. And an address interconnection network that interconnects at least the processor and the plurality of memory banks, and the address interconnection network transmits the address generated by the processor to the address and at least the An address conversion device that converts the address into a predetermined regularity based on a parameter corresponding to the number of memory banks is provided, and the conversion address by the address conversion device is supplied to the memory bank including the conversion address.

  In the present invention, the plurality of memory banks are divided into at least a plurality of memory sets including one or a plurality of memory banks, and the address conversion device includes an address generated by the processor and a memory bank in the memory set. The address conversion is performed based on a parameter corresponding to the number of.

  According to the present invention, the address conversion device performs an address based on an address generated by the processor, a first parameter corresponding to the number of the memory banks, and a second parameter based on the number of addresses of the memory banks. Perform conversion.

  Preferably, a data interconnection network for selectively connecting at least data paths between the processor and the plurality of memory banks based on a bank selection signal is provided, and the address translation device includes the translation address and the memory bank. The bank selection signal is generated based on a third parameter based on the number of addresses and output to the data interconnection network.

  Preferably, the address translation device is set in at least a first register in which the first parameter is set, a second register in which at least the second parameter is set, and the first register. A first parameter, a second parameter set in the second register, and an address calculation circuit for calculating a translation address based on the address generated by the processor.

  Preferably, in the address translation device, at least a first register in which the first parameter is set, a second register in which at least the second parameter is set, and the third parameter are set. The conversion address is calculated based on the third register, the first parameter set in the first register, the second parameter set in the second register, and the address generated by the processor. Bank selection calculation for generating the bank selection signal on the basis of a third parameter based on the number of addresses calculated by the address calculation circuit and the conversion address by the address calculation circuit and the number of addresses in the memory bank, and outputting to the data interconnection network Circuit.

  In the present invention, the address calculation circuit sets x as the value of the first parameter set in the first register, y as the value of the second parameter set in the second register, and% is modulo. When the operation / represents integer division, the conversion address Adrn is calculated according to the following equation (6), and the bank selection calculation circuit sets the value of the third parameter 3 set in the third register to z When bank represents an integer division, the bank selection signal Sel is calculated according to the following equation (7).

[Equation 1]
Adrn = y * (Adr% x) + x * y * (Adr / (x * y)) + (Adr% (x * y)) / x

[Equation 2]
Sel = Adrn / z

  The address calculation circuit outputs the input address as it is when a parameter relating to the number of addresses set for the address space is set in the first register and the second register.

  Preferably, the address interconnection network selects either a translation address by the address translation device or an externally supplied address according to a control signal and supplies the selected address to the memory bank including the selected address. Having a selection device.

  The data interconnection network includes a selection device that selectively connects data paths between the external device and the plurality of memory banks according to a control signal.

  According to a second aspect of the present invention, there are provided a plurality of memory banks to which a predetermined range of addresses in an address space are assigned and storing data relating to operations, a processor having a function of generating consecutive addresses, and at least one address generation device At least one arithmetic unit, an address interconnection network for interconnecting the processor, the plurality of memory banks, and the address generation unit, and the processor, the plurality of memory banks, and the arithmetic unit are interconnected. A data interconnection network, wherein the address interconnection network converts the address generated by at least the processor into an address having a predetermined regularity based on the address and at least a parameter corresponding to the number of the memory banks. Convert, the number of the converted address and the address of the memory bank An address translation device that generates a bank selection signal based on the parameter based on the parameter and outputs the bank selection signal to the data interconnection network, and a translation address by the address translation device or the address generation device supplied from the address generation device according to a first control signal A first selection device that selects any one of the addresses and supplies the selected memory bank to the memory bank including the selected address, wherein the data interconnection network includes data between the processor and the plurality of memory banks. A second selection device that selectively connects paths based on a bank selection signal; and a third selection device that selectively connects data paths between the arithmetic unit and the plurality of memory banks according to a second control signal. And a selection device.

According to the present invention, for example, continuous addresses are generated in a processor and input to an address translation device of an address interconnection network.
In the address conversion device, the address generated by the processor is converted into an address having a predetermined regularity based on the address and at least a parameter corresponding to the number of memory banks.
The converted address is supplied to the memory bank including the converted address via the connection network of the address interconnection network.
For example, in the address conversion device, a first parameter corresponding to the number of memory banks is set in the first register, and a second parameter based on the number of addresses in the memory bank is set in the second register.
In the address calculation circuit, an address generated by the processor is a predetermined arithmetic expression using the address, the first parameter set in the first register, and the second parameter set in the second register. As required.
In the address translation device, a third parameter based on the number of addresses in the memory bank is set in the third register. Then, in the bank selection circuit, a bank selection signal is generated based on the conversion address by the address calculation circuit and the third parameter set in the third register, and is output to the data interconnection network.
In the data interconnection network, data paths between a processor and a plurality of memory banks are selectively connected based on a bank selection signal.

As described above, according to the present invention, the number of unnecessary processing cycles can be reduced, and the memory access performance can be improved.
Further, there is an advantage that the hardware scale can be reduced and the cost can be reduced.

1 is a configuration diagram showing a first embodiment of an arithmetic system according to the present invention. It is a figure which shows the specific structural example of the principal part of the address interconnection network which concerns on this 1st Embodiment. It is a block diagram which shows the specific structural example of the address converter which concerns on this embodiment. It is a figure which shows the example of an address conversion of the address calculation circuit based on a computing equation. It is a block diagram which shows the specific structural example of the data interconnection network which concerns on this 1st Embodiment. It is a block diagram which shows 2nd Embodiment of the arithmetic system which concerns on this invention. It is a figure which shows the specific structural example of the principal part of the address interconnection network which concerns on this 2nd Embodiment. It is a block diagram which shows the specific structural example of the data interconnection network which concerns on the 2nd embodiment.

First Embodiment FIG. 1 is a block diagram showing a first embodiment of an arithmetic system according to the present invention.

  As shown in FIG. 1, the computing system 10 includes a plurality (6 in the first embodiment) of memory banks (MBNK) 11-0 to 11-5 and a plurality (6 in the present embodiment) of address generation devices. (ADRG) 12-0 to 12-5, a plurality (6 in this embodiment) of arithmetic units (OP) 13-0 to 13-5, a processor (PRC) 14, and an address conversion unit (ACNV) 151 A connection network (ACNCT) 15 and a data interconnection network (DCNCT) 16 are included.

  The memory banks 11-0 to 11-5 store data related to operations. For example, in the first embodiment, assuming that the address space has 48 addresses adr0 to adr47, each is divided into 6 equal parts. For example, two memory banks constitute one memory set, and three memory sets are constituted as a whole.

The memory bank 11-0 is assigned eight addresses adr0 to adr7 as the memory address Adrc0.
The memory bank 11-1 is assigned eight addresses adr8 to adr15 as the memory address Adrc1.
The memory bank 11-2 is assigned eight addresses adr16 to adr23 as the memory address Adrc2.
The memory bank 11-3 is assigned eight addresses adr24 to adr31 as the memory address Adrc3.
The memory bank 11-4 is assigned eight addresses adr32 to adr39 as the memory address Adrc4.
The memory bank 11-5 is assigned eight addresses adr40 to adr47 as the memory address Adrc5.

The address generator 12-0 generates an address Adr0 corresponding to the memory address Adrc0 (adr0 to adr7) of the memory bank 11-0, for example, according to an instruction from a control system (not shown), and outputs it to the address interconnection network 15.
The address generation device 12-1 generates an address Adr1 corresponding to the memory address Adr1 (adr8 to adr15) of the memory bank 11-1 according to an instruction of a control system (not shown), for example, and outputs it to the address interconnection network 15.
The address generation device 12-2 generates an address Adr2 corresponding to the memory address Adr2 (adr16 to adr23) of the memory bank 11-2, for example, according to an instruction of a control system (not shown), and outputs it to the address interconnection network 15.
The address generation device 12-3 generates an address Adr3 corresponding to the memory address Adr3 (adr24 to adr31) of the memory bank 11-3, for example, according to an instruction from a control system (not shown), and outputs it to the address interconnection network 15.
The address generation device 12-4 generates an address Adr4 corresponding to the memory address Adr4 (adr32 to adr39) of the memory bank 11-4, for example, according to an instruction from a control system (not shown), and outputs it to the address interconnection network 15.
The address generation device 12-5 generates an address Adr5 corresponding to the memory address Adr5 (adr40 to adr47) of the memory bank 11-5, for example, according to an instruction of a control system (not shown), and outputs it to the address interconnection network 15.

  The arithmetic devices 13-0 to 13-5 perform, for example, an operation according to an instruction of a control system (not shown) on the data transferred via the data interconnection network 16, and the operation result is input to the data interconnection network 16. Output.

The processor 14 generates a continuous address, for example, an address Adr (0, 1, 2,..., 46, 47) corresponding to the address space, and outputs it to the address interconnection network 15.
The processor 14 inputs the data read from the desired memory banks 13-0 to 13-5 or the calculation results of the calculation devices 13-0 to 13-5 via the data interconnection network 16, and performs predetermined processing. In addition, predetermined data is transferred to the desired memory banks 13-0 to 13-5 or desired data is transferred to the arithmetic units 13-0 to 13-5 via the data interconnection network 16.

  The address interconnection network 15 includes an address conversion device 151 that converts an address adr by the processor 14 into an address having a predetermined regularity according to a predetermined arithmetic expression. The processor 14 and the address generation devices 12-0 to 12-5 are stored in the memory. The banks 11-0 to 11-5 are connected to each other.

  FIG. 2 is a diagram showing a specific configuration example of a main part of the address interconnection network according to the first embodiment.

  As shown in FIG. 2, the address interconnection network 15 includes an address translation device (ACNV) 151 and a first selection device (SEL) 152.

  The address translation device 151 uses the address Adr generated by the processor 14 in accordance with the address Adr and the number of memory banks (6 in the first embodiment) or the number of memory banks in the memory set (this first number). In one embodiment, the address is converted to an address Adrn having a predetermined regularity based on the first parameter X according to 2) and the second parameter Y according to the number of addresses in the memory bank, and the converted address and A bank selection signal Sel is generated based on the third parameter Z based on the number of addresses in the memory bank and output to the data interconnection network 16.

  Further, when address translation is not performed, the address translation device 151 is set to a parameter relating to the number of addresses set for the address space as the first parameter X and the second parameter Y, specifically, the address space. The minimum address number 1 is set as the first parameter X, the maximum address number 48 set in the address space is set as the second parameter Y, and the input address Adr is output as Adrn as it is.

  FIG. 3 is a block diagram showing a specific configuration example of the address translation apparatus according to the present embodiment.

As shown in FIG. 3, the address translation device 151 includes a first register (REG1) 1511 in which the first parameter X is set, a second register (REG2) 1512 in which the second parameter Y is set, , A third register (REG3) 1513 in which the third parameter Z is set, a first parameter X set in the first register 1511, a second parameter Y set in the second register 1512, And an address calculation circuit (ADRC) 1514 for calculating a conversion address based on the address Adr generated by the processor 14, a conversion address by the address calculation circuit 1514, and a third parameter Z set in the third register 1513. Bank selection signal Sel generated and output to the data interconnection network 16 And a circuit (BNKC) 1515.
Note that the first register 1511, the second register 1512, and the third register 1513 are configured so that the first parameter X, the second parameter Y, and the third parameter Z can be transmitted from the outside or through the processor 14. It can be set arbitrarily.

  The address calculation circuit 1514 sets the value of the first parameter X set in the first register 1511 to x, the value of the second parameter Y set in the second register as y, and% is a modulo operation. , / Represents integer division, the conversion address Adrn is calculated according to the following equation (8).

[Equation 3]
Adrn = y * (Adr% x) + x * y * (Adr / (x * y)) + (Adr% (x * y)) / x

  FIGS. 4A and 4B are diagrams showing an example of address conversion of the address calculation circuit 1514 based on the above equation, and FIG. 4A shows the continuous address Adr generated by the processor 14 before conversion. FIG. 4B shows the address Adrn after conversion by the address calculation circuit 1514.

As shown in FIG. 4A, the processor 14 sequentially generates 48 addresses Adr from 0 to 47 in order.
The continuous address Adr is converted into an address Adrn as shown in FIG. 4B by the address calculation circuit 1514 with a predetermined regularity.
This regularity is determined by the memory set MS0 constituted by the memory banks 11-0 and 11-1 constituting the memory sets MS0, MS1 and MS2, the memory set MS1 constituted by the memory banks 11-2 and 11-3, In each memory set of the memory set MS2 constituted by the memory banks 11-4 and 11-5, it is defined so that the addresses are alternately arranged from the smaller address of the memory banks.

  Specifically, in the memory set MS0, as shown in FIGS. 4A and 4B, the generated address Adr0 becomes the address Adrn0 after conversion, the generated address Adr1 becomes the address Adrn8 after conversion, and the generated address Adr2 Is converted to the address Adrn1, the generated address Adr3 is converted to the address Adrn9, the generated address Adr4 is converted to the address Adrn2, the generated address Adr5 is converted to the address Adrn10, and the generated address Adr6 is converted to the address Adrn3. The generated address Adr7 is converted to the address Adrn11, the generated address Adr8 is converted to the address Adrn4, the generated address Adr9 is converted to the address Adrn12, and the generated address Adr10 is changed. After that, the address Adrn5 is generated, the generated address Adr11 is converted to the address Adrn13, the generated address Adr12 is converted to the address Adrn6, the generated address Adr13 is converted to the address Adrn14, and the generated address Adr14 is converted to the address Adrn7. The generated address Adr15 becomes the address Adrn15 even after conversion.

  In the memory set MS1, as shown in FIGS. 4A and 4B, the generated address Adr16 becomes the address Adrn16 after conversion, the generated address Adr17 becomes the address Adrn24 after conversion, and the generated address Adr18 becomes the address after conversion. The generated address Adr19 is converted to the address Adrn25, the generated address Adr20 is converted to the address Adrn18, the generated address Adr21 is converted to the address Adrn26, the generated address Adr22 is converted to the address Adrn19, and the generated address Adr23 is generated. Is converted to address Adrn27, generated address Adr24 is converted to address Adrn20, and generated address Adr25 is converted to address Adrn28. The address Adr26 is converted to the address Adrn21, the generated address Adr27 is converted to the address Adrn29, the generated address Adr28 is converted to the address Adrn22, the generated address Adr29 is converted to the address Adrn30, and the generated address Adr30 is converted to the converted address Adr30. The address Adrn23 is generated, and the generated address Adr31 becomes the address Adrn31 after conversion.

  In the memory set MS2, as shown in FIGS. 4A and 4B, the generated address Adr32 becomes the address Adrn32 after conversion, the generated address Adr33 becomes the address Adrn40 after conversion, and the generated address Adr34 becomes the address after conversion. The generated address Adr35 is converted to the address Adrn41, the generated address Adr36 is converted to the address Adrn34, the generated address Adr37 is converted to the address Adrn42, the generated address Adr38 is converted to the address Adrn35, and the generated address Adr39 is generated. Becomes the address Adrn43 after conversion, the generation address Adr40 becomes the address Adrn36 after conversion, and the generation address Adr41 becomes the address Adrn44 after conversion. The address Adr42 is converted to an address Adrn37, the generated address Adr43 is converted to an address Adrn45, the generated address Adr44 is converted to an address Adrn38, the generated address Adr45 is converted to an address Adrn46, and the generated address Adr46 is converted to a converted address Adr46. The address Adrn39 is generated, and the generated address Adr47 becomes the address Adrn47 even after conversion.

  The bank selection calculation circuit 1515 calculates the bank selection signal Sel according to the following equation 9 when the value of the third parameter Z set in the third register 1513 is z and / represents an integer division.

[Equation 4]
Sel = Adrn / z

  The first selection device 152 selects either the translation address Adr by the address translation device 151 or the addresses Adr0 to Adr5 supplied from the address generation devices 12-0 to 12-5 in response to the first control signal ctrl1. The selected address is set to one of Adrc0 to Adrc5 and supplied to the memory banks 11-0 to 11-5 including the set address.

  The data interconnection network 16 is a data path to the processor 14 for the data Dat0 to Dat5 read from the desired memory banks 13-0 to 13-5 or the calculation result data Dat0 to Dat5 of the calculation devices 13-0 to 13-5. And the data path by the processor 14 to the desired memory banks 13-0 to 13-5, or the desired data to the arithmetic units 13-0 to 13-5 are selectively connected. To do.

  FIG. 5 is a block diagram showing a specific configuration example of the data interconnection network according to the first embodiment.

As shown in FIG. 5, the data interconnection network 16 includes a second selection device (SEL) 161 and a third selection device (SEL) 162.
The first selection device 161 includes the input / output data Dat of the processor 14 and the second selection device 162 (input / output data Dac0 to Dat5 of the plurality of memory banks 11-0 to 11-5, arithmetic devices 13-0 to 13- 5 and the input / output data Dat0 to Dat5) are selectively connected based on the bank selection signal Sel by the address translation device 151.
The second selection device 162 receives the input / output data Dat0 to Dat5 of the arithmetic devices 13-0 to 13-5 and the input / output data Datac0 to Datac5 of the memory banks 11-0 to 11-5 according to the second control signal ctrl. And / or a data path to the second selection device 161 (input / output data Dat of the processor 14) is selectively connected.

  Next, the operation of the above-described configuration will be described focusing on the operation of the above-described configuration of the address translation device, taking as an example the case where the processor 14 generates an address Adr.

First, address generation when no address translation is performed will be described.
In this case, the address conversion is performed by setting the first parameter X to the value x = 1, the second parameter Y to the value y = 48, and the third parameter Z to the value z = 8 by an external control system or by the processor 14. Supplied to the device 151.
As a result, 1 is set in the first register 1511, 48 is set in the second register 1512, and 8 is set in the third register 1513.
The first parameter X (value x = 1) set in the first register 1511 and the second parameter Y (value y = 48) set in the second register 1512 are supplied to the address calculation circuit 1514. . Further, the third parameter Z (value z = 8) set in the third register 1513 is supplied to the bank selection calculation circuit 1515.

  The address calculation circuit 1514 calculates the converted address according to the following equation.

[Equation 5]
Adrn = 48 * (Adr% 1) + (Adr% 48) / 1+ 48 * (Adr / 48) = Adr

In order to access the memory from the processor 14, an address Adr is generated, output to the address interconnection network 15, and input to the address conversion circuit 151.
At this time, for example, when the generated Adr is 0, Adrn = 0 when calculated using the above equation.
Then, the first selection device 152 is designated to select the translation address Adrn by the first control signal ctrl1. As a result, this value is selected by the first selection device 151, and the address Adrc0 = 0 of the memory bank 11-0 can be accessed.

  At the same time, the address conversion device 151 calculates the bank selection signal Sel in the bank selection calculation circuit 1515 according to the following equation and outputs it to the second selection device 161 of the data interconnection network 16.

[Equation 6]
Sel = Adrn / 8

At this time, the bank selection signal Sel becomes 0 because the address Adrn is 0. In the second selection device 161 of the data interconnection network 16, the data path to the memory bank 11-0 is selected according to the bank selection signal Sel.
At this time, the third selection device 162 is designated to select a data path with the memory bank by the second control signal ctrl2. As a result, the processor 14 can access data corresponding to Adrc0 = 0 in the memory bank 11-0.

In addition to the above example, when the address Adr generated and transferred by the processor 14 is 8, for example, the address calculation circuit 1514 of the address translation device 151 calculates Adrn = 8.
Then, the first selection device 152 is designated to select the translation address Adrn by the first control signal ctrl1. As a result, this value is selected by the first selection device 151, and the address Adrc1 = 8 of the memory bank 11-1 can be accessed.
The bank selection signal Sel = 1 calculated by the bank selection calculation circuit 1515 is set, and in the second selection device 161 of the data interconnection network 16, the data path to the memory bank 11-1 is selected according to the bank selection signal Sel. The
At this time, the third selection device 162 is designated to select a data path with the memory bank by the second control signal ctrl2. As a result, the processor 14 can access data corresponding to Adrc1 = 8 in the memory bank 11-1.

Next, access when address conversion is performed will be described.
Here, the processor 14 only generates the continuous addresses Adr0, 1, 2, 3,..., 47, and the addresses Adrc0, 8, 1, 9,..., 16, 24, 17, 25,. Address conversion for making 31, 32, ..., 39, 47 will be described.

In this case, the address conversion is performed by setting the first parameter X to the value x = 2, the second parameter Y to the value y = 8, and the third parameter Z to the value z = 8 by the external control system or by the processor 14. Supplied to the device 151.
As a result, 2 is set in the first register 1511, 8 is set in the second register 1512, and 8 is set in the third register 1513.
The first parameter X (value x = 1) set in the first register 1511 and the second parameter Y (value y = 8) set in the second register 1512 are supplied to the address calculation circuit 1514. . Further, the third parameter Z (value z = 8) set in the third register 1513 is supplied to the bank selection calculation circuit 1515.

  The address calculation circuit 1514 calculates the converted address according to the following equation.

[Equation 7]
Adrn = 8 * (Adr% 2) + (Adr% 16) / 2+ 16 * (Adr / 16)

As a result, the address calculation circuit 1514 performs conversion such as Adr = 0 when Adr = 0, Adr = 8 when Adr = 1, Adr = 16 when Adr = 16, Adr = 24 when Adr = 17, and the like. Is called.
That is, the processor 14 simply generates continuous addresses 0, 1, 2, 3,..., 47 as Adr, and addresses for accessing the memory are 0, 8, 1, 9,. ..., 31, 32, ..., 39, 47.
Then, the first selection device 152 is designated to select the translation address Adrn by the first control signal ctrl1. As a result, this value is selected by the first selection device 151, the address Adrc0 = 0 of the memory bank 11-0, the address Adrc1 = 8 of the memory bank 11-1, the address Adrc0 = 1 of the memory bank 11-0, the memory Similarly, the address Adrc1 = 9 in the bank 11-1, the address Adrc4 = 39 in the memory bank 11-4, and the address Adrc5 = 47 in the memory bank 11-5 can be accessed in the same manner.

  At the same time, the address conversion device 151 calculates the bank selection signal Sel in the bank selection calculation circuit 1515 according to the following equation and outputs it to the second selection device 161 of the data interconnection network 16.

[Equation 8]
Sel = Adrn / 8

At this time, for example, when the generation address Adr is 1, the conversion address Adrn is 8, and the bank selection signal Sel is 1.
Therefore, in the second selection device 161 of the data interconnection network 16, the data path to the memory bank 11-1 is selected according to the bank selection signal Sel.
At this time, the third selection device 162 is designated to select a data path with the memory bank by the second control signal ctrl2. As a result, the processor 14 can access data corresponding to Adrc1 = 8 in the memory bank 11-1.

When the address generation devices 12-0 to 12-5 generate addresses, Adr0 to Adr5 are generated by the address generation devices 12-0 to 12-5.
Then, the first selection device 152 is designated to select the addresses Adr0 to Adr5 by the first control signal ctrl1. As a result, this value is selected by the first selection device 151, and the desired address Adrc0 = 0 to Adrc5 = 47 of the desired memory bank 11-0 to 11-5 can be accessed.

  As described above, according to the first embodiment, the processor 14 and the address generators 12-0 to 12-5 are connected to the memory banks 11-0 to 11-5 selectively. 15. The address Adr generated by the processor 14 is changed to the address Adr, the first parameter X corresponding to the number of memory banks or the number of memory banks in the memory set, and the number of addresses of the memory banks. Is converted into an address Adrn having a predetermined regularity based on the second parameter Y according to the frequency, and a bank selection signal Sel is generated based on the third parameter Z based on the converted address and the number of addresses of the memory bank And an address converter 151 for outputting to the data interconnection network 16 is provided. Since so as to selectively set the data path between the processor 14 and the memory bank 11-0～11-5 based on sel, it is possible to obtain the following effects.

That is, according to the first embodiment, the memory access performance in the arithmetic system can be improved.
For example, when the addresses when accessing the memory banks 11-0 to 11-5 from the processor 14 are 0, 8, 16, 24, 1, 9, 17, 25, ..., 7, 15, 23, 31 By using the address translation device 151, a desired access address can be generated, and in addition to address translation, data corresponding to the address can be selected.
Further, the addresses when the processor 14 accesses the memory banks 11-0 to 11-5 are, for example, 0, 8, 1, 9, 2, 10,..., 7, 15, 16, 24, 17, 25,. , 23, and 31, the address translation device 151 can perform desired address translation, so that the processor 14 does not need to perform address translation. For this reason, it is possible to reduce an extra cycle in which the address calculation is performed separately from the calculation using the processor.
Furthermore, since only one address translation device is required, the hardware scale can be reduced and the cost can be reduced.

Second Embodiment FIG. 6 is a block diagram showing a second embodiment of the arithmetic system according to the present invention.

  The difference between the second embodiment and the first embodiment is that the number of elements in the memory bank 11, the number of elements in the address generator 12, and the number of elements in the arithmetic unit 13 are not six but are generally 1 × m. It is in the point which has the structure made into.

  In the second embodiment, the memory banks 11-0 to 11-1 × m−1 have n addresses, and m banks constitute a memory set MS, which is composed of l memory sets in total. The The address space is 0 to l × m × n−1.

As shown in FIG. 7, the address interconnection network 15A basically includes an address translation device 151 and a first selection device 152, as in FIG.
That is, the address interconnection network 15A uses the address Adr from the processor 14 and the addresses Adr0 to Adr (1 × m−1) from the address generators 12-0 to 12-1 × m−1 as input addresses. The bank selection signal Sel generated by the address conversion device 151 is output to the data interconnection network 16 with Adrc0 to Adrc (1 × m−1) selected by the selection device 151 as output addresses.
The address interconnection network 15 </ b> A converts the generated address Adr of the processor 14 by the address conversion device 151 and outputs the result to the first selection device 152.
Then, according to the first control signal ctrl1, the translation address Adrn or the addresses Adr0 to Adr (m * n-1) from the address generators 12-0 to 12-l × m-1 are selected, and each memory bank 11- Output addresses Adrc0 to Adrc (l × m−1) to 0 to 11−1 × m−1 are obtained.
The address translation device 151 has the same configuration and function as in FIG.

As shown in FIG. 8, the data interconnection network 16A basically includes a second selection device 161 and a third selection device 162 as in FIG.
That is, the first selection device 161 of the address interconnection network 15A includes the input / output data Dat of the processor 14 and the second selection device 162 (input / output data of a plurality of memory banks 11-0 to 11-1 × m−1). Based on the bank selection signal Sel by the address conversion device 151, the data path to the input / output data Dat0 to Data × m−1) of the data units Dac0 to Datcl × m−1 and the arithmetic devices 13-0 to 13−1 × m−1 Selectively connect.
The second selection device 162 receives the input / output data Dat0 to Data × m−1 of the arithmetic devices 13-0 to 13-1 × m−1 and the memory banks 11-0 to 11− according to the second control signal ctrl. The data path to the l × m−1 input / output data Dac0 to Datcl × m−1 and / or the second selection device 161 (input / output data Dat of the processor 14) is selectively connected.

  Next, the operation of the above-described configuration will be described focusing on the operation of the above-described configuration of the address translation device, taking as an example the case where the processor 14 generates an address Adr.

First, address generation when no address translation is performed will be described.
In this case, the first parameter X is set to the value x = 1, the second parameter Y is set to the value y = 1 * m * n, and the third parameter Z is set to the value z = n by the external control system or the processor 14. And supplied to the address translation device 151.
As a result, 1 is set in the first register 1511, (l * m * n) is set in the second register 1512, and n is set in the third register 1513.
The first parameter X (value x = 1) set in the first register 1511 and the second parameter Y (value y = 1 / * m * n) set in the second register 1512 are the address calculation circuit 1514. To be supplied. Further, the third parameter Z (value z = n) set in the third register 1513 is supplied to the bank selection calculation circuit 1515.

  In the address calculation circuit 1514, the address calculation is performed according to the following formula, but it is understood that the address conversion is not performed by this formula.

[Equation 9]
Adrn = l * m * n * (Adr% 1) + l * m * n * (Adr / (l * m * n)) + (Adr% (l * m * n)) / 1 = Adr

In order to access the memory from the processor 14, an address Adr is generated, output to the address interconnection network 15 A, and input to the address conversion circuit 151.
At this time, for example, when the generated Adr is 0, Adrn = 0 when calculated using the above equation.
Then, the first selection device 152 is designated to select the translation address Adrn by the first control signal ctrl1. As a result, this value is selected by the first selection device 151, and the address Adrc0 = 0 of the memory bank 11-0 can be accessed.

  At the same time, the address conversion device 151 calculates the bank selection signal Sel in the bank selection calculation circuit 1515 according to the following equation and outputs it to the second selection device 161 of the data interconnection network 16.

[Equation 10]
Sel = Adrn / n

At this time, the bank selection signal Sel becomes 0 because the address Adrn is 0. In the second selection device 161 of the data interconnection network 16, the data path to the memory bank 11-0 is selected according to the bank selection signal Sel.
At this time, the third selection device 162 is designated to select a data path with the memory bank by the second control signal ctrl2. As a result, the processor 14 can access data corresponding to Adrc0 = 0 in the memory bank 11-0.

Next, a case where address conversion is performed will be described.
Here, the processor 14 is
Consecutive addresses [0,1,… n-1, n,…, (m-1) * n, (m-1) * n + 1,… (m-1) * n + n-1,…,
(l-1) * m * n, 1 + (l-1) * m * n, ... n-1 + (l-1) * m * n, ... (m-1) * n + (l-1) * m * n, (m-1) * n + 1 + (l-1) * m * n, ... (m-1) * n + n-1 + (l-1) * m * n]
To generate the addresses to access the memory [0,… (m-1) * n, 1,… (m-1) * n + 1,… n-1,… (m-1) * n + n-1, ..., (l-1) * m * n, ... (m-1) * n + (l-1) * m * n, 1+ (l-1) * m * n, ... (m -1) * n + 1 + (l-1) * m * n, ... n-1 + (l-1) * m * n, ... (m-1) * n + n-1 + (l-1 ) * m * n]
The address conversion that can be performed will be described.

In this case, the address conversion is performed by setting the first parameter X to the value x = m, the second parameter Y to the value y = n, and the third parameter Z to the value z = n by the external control system or the processor 14. Supplied to the device 151.
Thus, m is set in the first register 1511, n is set in the second register 1512, and n is set in the third register 1513.
The first parameter X (value x = m) set in the first register 1511 and the second parameter Y (value y = n) set in the second register 1512 are supplied to the address calculation circuit 1514. . Further, the third parameter Z (value z = n) set in the third register 1513 is supplied to the bank selection calculation circuit 1515.

  The address calculation circuit 1514 performs address calculation according to the following equation.

[Equation 11]
Adrn = n * (Adr% m) + (Adr% (m * n)) / m + (m * n) * (Adr / (m * n))

As a result, for example, when Adr = 0, Adrn = 0, when Adr = 1, Adrn = nn, when Adr = m * n, Adrn = m * n, when Adr = m * n + 1, Adrn = n + m * n, Adr = (l-1) * m * n, Adrn = (l-1) * m * n, Adr = (l-1) * m * n + 1, Adrn = n + (l-1) Conversions such as * m * n are performed.
To summarize, continuous address
0,1,… n-1, n,…, (m-1) * n, (m-1) * n + 1,… (m-1) * n + n-1,…, (l-1 ) * m * n, 1 + (l-1) * m * n, ... n-1 + (l-1) * m * n, ... (m-1) * n + (l-1) * m * n , (m-1) * n + 1 + (l-1) * m * n, ... (m-1) * n + n-1 + (l-1) * m * n
Simply generate the address Adrn to access the memory.
0, ... (m-1) * n, 1, ... (m-1) * n + 1, ... n-1, ... (m-1) * n + n-1, ..., (l-1) * m * n,… (m-1) * n + (l-1) * m * n, 1+ (l-1) * m * n,… (m-1) * n + 1 + (l-1) * m * n, ... n-1 + (l-1) * m * n, ... (m-1) * n + n-1 + (l-1) * m * n
Can be converted to

  Then, the first selection device 152 is designated to select the translation address Adrn by the first control signal ctrl1. Thus, this value is selected by the first selection device 151, and the addresses Adrc0 to Adrc (l * m-1) of the corresponding memory can be generated.

  At the same time, the address conversion device 151 calculates the bank selection signal Sel in the bank selection calculation circuit 1515 according to the following equation and outputs it to the second selection device 161 of the data interconnection network 16.

[Equation 12]
Sel = Adrn / n

At this time, when Adr = 1, Adrn = n and the bank selection signal Sel becomes 1. In the second selection device 161 of the data interconnection network 16, the data path to the memory bank 11-1 is selected according to the bank selection signal Sel.
At this time, the third selection device 162 is designated to select a data path with the memory bank by the second control signal ctrl2. As a result, the processor 14 can access data corresponding to Adrc = n in the memory bank 11-1.

When the address generation devices 12-0 to 12-l × m−1 perform address generation, Adr0 to Adr5 are generated by the address generation devices 12-0 to 12-l × m−1.
Then, the first selection device 152 is designated to select the addresses Adr0 to Adrl × m-15 with the first control signal ctrl1. Thereby, this value is selected by the first selection device 151.
For example, when Adr0 = 0, Adrc0 = 0, and when Adr1 = 8, Adrc8 = 8.

  According to the second embodiment, the same effect as that of the first embodiment described above can be obtained.

  In the first and second embodiments, the case where the number of processors is 1 and the address generated by the processor 14 is converted has been described. However, when the address generated by the address generation device is converted, It is clear that the present invention can be applied to the case where the number is plural only by changing the configuration of the interconnection network.

  DESCRIPTION OF SYMBOLS 10,10A ... Arithmetic system, 11-0 to 11-5 ... Memory bank (MBNK), 12-0 to 12-5 ... Address generator (ADRG), 13-0 to 13-5 ... Arithmetic unit (OP), DESCRIPTION OF SYMBOLS 14 ... Processor (PRC), 15, 15A ... Address interconnection network (ACNCT), 151 ... Address translation device (ACNV), 152 ... First selection device (SEL), 16, 16A ... Data interconnection network (DCNCT) 161 ... second selection device (SEL), 162 ... third selection device (SEL).

Claims (7)

A plurality of memory banks that are assigned a predetermined range of addresses in the address space and store data related to operations;
A processor having a function of generating consecutive addresses;
An address interconnection network connecting at least the processor and the plurality of memory banks to each other;
The address interconnection network is
An address conversion device that converts an address generated by the processor into an address having a predetermined regularity according to the address and at least the number of the memory banks;
Supplying a translation address by the address translation device to the memory bank including the translation address;
The address translation device
Address conversion is possible based on the address generated by the processor, the number of memory banks, and the number of addresses in the memory bank, and the address conversion method is the number of memory banks and the address of the memory banks. Depending on the number setting,
An address calculation circuit for calculating a translation address based on the number of memory banks and the number of addresses of the memory bank, and an address generated by the processor;
The address calculation circuit is
One of the number of memory banks and the number of addresses in each memory bank is x, the other is y,% is a modulo operation, and / is an integer division, the conversion address Adrn is based on the original address Adr as follows: Has the function of calculating according to one equation [Equation 1 ]
Adrn = y * (Adr% x) + x * y * (Adr / (x * y)) + (Adr% (x * y)) / x
Arithmetic system. A data interconnection network for selectively connecting data paths between at least the processor and the plurality of memory banks based on a bank selection signal;
Address translation device
A bank selection calculation circuit that generates the bank selection signal based on a conversion address by the address calculation circuit and a parameter z based on the number of addresses of the memory bank, and outputs the bank selection signal to the data interconnection network;
The bank selection calculation circuit is
The arithmetic system according to claim 1, wherein the bank selection signal Sel is calculated according to the following equation ( 2 ).
[Equation 2 ]
Sel = Adrn / z It said data interconnection network, the operation system according to claim 1 or 2, wherein having a selection device for selectively connecting the data path between the external device and the plurality of memory banks in response to the control signal. The address calculation circuit
The arithmetic system according to any one of claims 1 to 3, wherein when a value related to the number of addresses set for the address space is set as the values of x and y, the input address is output as it is. The address interconnection network is
And in response to the control signal selects one of the address supplied from the conversion address or external by the address translator, of claims 1 to 4 having a selection device for supplying to said memory bank containing an address selected The computing system according to any one of the above. A plurality of memory banks that are assigned a predetermined range of addresses in the address space and store data related to operations;
A processor having a function of generating consecutive addresses;
At least one address generation device;
At least one computing device;
An address interconnection network interconnecting the processor, the plurality of memory banks, and the address generator;
A data interconnection network interconnecting the processor, the plurality of memory banks, and the arithmetic unit;
The address interconnection network is
At least an address generated by the processor is converted into an address having a predetermined regularity according to the address and at least the number of the memory banks, and a bank selection signal based on the converted address and the number of addresses of the memory bank An address translation device that generates and outputs to the data interconnection network;
A first selection for selecting either a translation address by the address translation device or an address supplied from the address generation device in response to a first control signal and supplying the selected address to the memory bank including the selected address And the device
The address translation device
It is possible to perform address conversion between the address generated by the processor, the number of the memory banks, and the number of addresses of the memory banks, and the address conversion method is the number of the memory banks and the number of addresses of the memory banks. It can be changed according to the setting,
The data interconnection network is
A second selection device for selectively connecting data paths between the processor and the plurality of memory banks based on a bank selection signal;
A third selection device that selectively connects data paths between the arithmetic device and the plurality of memory banks in response to a second control signal;
The address translation device
An address calculation circuit for calculating a translation address based on the number of memory banks and the number of addresses of the memory bank, and an address generated by the processor;
A bank selection calculation circuit that generates the bank selection signal based on the conversion address by the address calculation circuit and a parameter based on the number of addresses of the memory bank, and outputs the bank selection signal to the data interconnection network,
The address calculation circuit is
One of the number of memory banks and the number of addresses in each memory bank is x, the other is y,% is a modulo operation, and / is an integer division, the conversion address Adrn is based on the original address Adr as follows: Calculate according to equation 3 ,
The bank selection calculation circuit is
A parameter based on the number of addresses of the translated address and the memory bank by the address calculation circuit and is z, when a / represents integer division, to calculate the bank selection signal Sel according to the following Formula 4 [Formula 3]
Adrn = y * (Adr% x) + x * y * (Adr / (x * y)) + (Adr% (x * y)) / x
[Formula 4 ]
Sel = Adrn / z
Arithmetic system. The address calculation circuit
The arithmetic system according to claim 6 , wherein when a value related to the number of addresses set for the address space is set as the values of x and y, the input address is output as it is.

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