JP5052192B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a process for fabricating a silicon carbide semiconductor device in which a CNT can be formed selectively by short-time treatment under low temperature without using a fine particle catalyst. <P>SOLUTION: The process for fabricating a silicon carbide semiconductor device comprises (a) a step for making the surface of SiC 1 amorphous by introducing impurities, (b) a step for forming a CNT 5 on the surface of amorphous SiC 3 by heat treatment, and (c) a step for forming a CNT 5 further thereon by using the CNT 5 as a ground. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device.

  As a next-generation power device, a power device using silicon carbide (hereinafter referred to as SiC) is expected. A power device using SiC can significantly reduce loss compared to a power device using silicon (hereinafter referred to as Si). When the loss is reduced, the resistance of the wiring connecting the power device and the external circuit cannot be ignored. In the power device, particularly, the resistance between the electrode and the plug portion is the highest, and it is very important to reduce this resistance and to increase the allowable limit of the current density that can flow from the electrode to the plug portion.

  As such a countermeasure, there is a method of using carbon nanotubes (CNT) in the plug portion (see Non-Patent Document 1). Since CNT has the characteristics of 1000 times the current density resistance of copper and 10 times the thermal conductivity, it is possible to flow a larger current to the power device by using the CNT for the plug.

  As a method of selectively forming CNTs, a method of forming CNTs using a fine particle catalyst (see Patent Document 1), or a method of forming CNTs by performing a high-temperature / vacuum annealing process using a SiN mask (non-contained) Patent Document 2).

JP-A-2005-72171 “Electronic device applications of carbon nanotubes” FUJITU. 55,3, P262-266 (05.2004) Jpn. J. et al. Appl. Phys. 42 (2003) p. L1486-1488

  In Patent Document 1, it is difficult to form a fine particle catalyst, and it is necessary to introduce a new process that is not included in the manufacturing process of the conventional SiC power device, so that there is a problem that the number of processes increases and the process becomes complicated. . In Non-Patent Document 2, CNTs are formed without using a fine particle catalyst. However, since the processing temperature is 1700 ° C. for 30 minutes, which is a long time, the SiN mask can sufficiently withstand this processing. Therefore, it is difficult to miniaturize a region where CNTs are formed.

  The present invention has been made to solve these problems, and provides a method for manufacturing a silicon carbide semiconductor device capable of selectively forming CNTs without using a particulate catalyst by low-temperature, short-time treatment. For the purpose.

In order to solve the above problems, a method for manufacturing a silicon carbide semiconductor device according to the present invention is a method for manufacturing a silicon carbide semiconductor device, comprising: (a) introducing an impurity into a surface of a silicon carbide semiconductor by ion implantation to form an amorphous (B) forming a carbon nanotube on the surface of the silicon carbide semiconductor by heat-treating the amorphous silicon carbide semiconductor surface; and (c) using the carbon nanotube as a base, and forming C ₂ above it. characterized in that it comprises the step of of H ₂ Ru grown further carbon nanotubes are supplied.

According to the first aspect of the present invention, an impurity is introduced into the surface of the silicon carbide semiconductor by ion implantation to make it amorphous, and then the amorphous silicon carbide semiconductor surface is heat-treated to thereby form the surface of the silicon carbide semiconductor. forming a carbon nanotube, then using carbon nanotubes as a base, Runode grown further carbon nanotubes by supplying C ₂ H ₂ thereabove, a low temperature and short time process, used particulate catalyst CNTs can be selectively formed without any problems.

  Embodiments of the present invention will be described below with reference to the drawings.

<Embodiment 1>
1 to 9 are manufacturing process diagrams of the silicon carbide semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, for example, in SiC1, using a resist as an implantation mask 2, ions are implanted into a region where CNTs are to be formed to form amorphous SiC3. At this time, for example, when ion implantation is performed at room temperature, the nitrogen concentration should be 5 × 10 ¹⁹ cm ⁻³ or more if the implanted element is nitrogen, and the aluminum concentration should be 2 × 10 ¹⁹ cm ⁻³ or more if aluminum is used. That's fine.

As shown in FIG. 2, a region other than amorphous SiC 3 is covered with a graphite cap 4. In the case where a resist is used for the implantation mask 2 in FIG. 1, when the resist is heat-treated at, eg, 750 ° C. for 10 minutes, it becomes graphite. Although this graphite cap 4 is not necessarily required, when the process shown in FIG. 3 is performed, the region covered with the graphite cap 4 has a feature that the flatness of the surface of the SiC 1 is maintained without forming the CNT 5. is there. Further, when the surface of the amorphous SiC 3 is covered with the graphite cap 4, the CNT 5 is not formed because Si is not detached from the surface of the amorphous SiC 3 covered with the graphite cap 4 during the heat treatment. In the process of FIG. 3, for example, when activation annealing is performed at 1700 ° C. for 10 minutes in a vacuum (1 × 10 ⁻⁴ Torr or less), CNT5 is formed by removing Si from amorphous SiC3. Further, as shown in FIG. 4, CNTs are grown under conditions of 550 ° C. and 50 Torr while supplying C ₂ H ₂ by, for example, chemical vapor deposition (CVD).

In FIG. 5, the CNT 5 is protected by forming a mask, for example, a SiN mask 6 on the CNT 5, and the graphite cap 4 is removed by, for example, thermal oxidation (950 ° C., 15 minutes) as shown in FIG. 6 is removed. Then, as shown in FIG. 7, an SiO ₂ film is deposited on the entire wafer by a thermal CVD method using an interlayer insulating film 7, for example, TEOS (ethyl silicate), and in FIG. 8, the entire surface is etched or chemically mechanically polished. The SiO ₂ on the CNT ₅ is removed by (Chemical Mechanical Polishing: CMP) so that the CNT 5 comes out on the surface of the interlayer insulating film 7. Finally, as shown in FIG. 9, the CNT plug is formed by depositing the upper wiring metal 8 on the entire surface.

  In the above, the graphite cap 4 is used when forming the CNT 5 by the activation annealing as shown in FIG. 3, but the CNT 5 can be formed without using the graphite cap 4. 10 to 13 are diagrams showing a process of forming the CNT 5 without using the graphite cap 4 after the ion implantation. As shown in FIG. 10, the CNTs 5 are also growing in the non-amorphous region. The length of the CNT 5 formed in the non-amorphous region is, for example, about 0.1 μm in the activation annealing treatment at 1700 ° C. for 10 minutes. On the other hand, if the depth of the amorphized region is about 1 μm, the length of the CNT5 in the amorphized region is entirely formed by activation annealing at 1700 ° C. for 10 minutes. In FIG. 11, the entire surface of the wafer is removed by etching or CMP, and CNTs 5 remain only in the portions where plugs are to be formed. Then, as shown in FIG. 12, an interlayer insulating film 7 is formed to form a contact hole in the CNT plug portion. Finally, as shown in FIG. 13, CNT plugs are formed by growing CNTs 5 by CVD.

  By the above method, it is possible to form the CNT 5 that is the wiring plug by using the apparatus and materials used in the conventional manufacturing process of the SiC power device. Accordingly, the effective area of the chip is increased by reducing the area where the plug is wired, and the loss during energization is reduced, so that a large current can flow, leading to improvements in device performance and reliability. Further, since SiC1 is made amorphous by ion implantation, it is possible to form CNT5 by a process at a lower temperature and in a shorter time than conventional.

<Embodiment 2>
14 to 22 are manufacturing process diagrams of the silicon carbide semiconductor device according to the second embodiment of the present invention. As shown in FIG. 14, for example, in SiC1, using a resist as an implantation mask 2, ions are implanted into a region where CNT5 is to be formed, thereby forming amorphous SiC3. At this time, for example, when ion implantation is performed at room temperature, the nitrogen concentration is 5 × 10 ¹⁹ cm ⁻³ or more if the implanted element is nitrogen, and the aluminum concentration is 2 × 10 ¹⁹ cm ⁻³ or more if aluminum is aluminum. do it.

As shown in FIG. 15, a region other than amorphous SiC 3 is covered with a graphite cap 4. In the case where a resist is used for the implantation mask 2 in FIG. 14, if the resist is heat-treated at, eg, 750 ° C. for 10 minutes, it becomes graphite. Although this graphite cap 4 is not necessarily required, when the process shown in FIG. 16 is performed, the region covered with the graphite cap 4 is characterized in that the flatness of the surface of the SiC 1 is maintained without forming the CNT 5. is there. Further, when the surface of the amorphous SiC 3 is covered with the graphite cap 4, the CNT 5 is not formed because Si is not detached from the surface of the amorphous SiC 3 covered with the graphite cap 4 during the heat treatment. In the process of FIG. 16, for example, when activation annealing is performed at 1700 ° C. for 10 minutes in a vacuum (1 × 10 ⁻⁴ Torr or less), CNT5 is formed by removing Si from amorphous SiC3. The steps up to here are the same as in the first embodiment of the present invention.

As shown in FIG. 17, after protecting the CNT 5 by forming a mask, for example, a SiN mask 6 on the CNT 5, as shown in FIGS. 18 and 19, the graphite cap 4 and SiC1 in the region other than CNT5 is removed. In FIG. 19, SiC1 is removed by the length of the carbon nanotube, but this is not necessarily the case, and even if the etching amount of SiC1 is larger than the length of the carbon nanotube as long as the device characteristics to be manufactured are not affected. It may be small. In Figure 20, an interlayer insulating film is deposited 7 after removing the SiN mask 6, as shown in FIG. 21, CNT5 to remove SiO ₂ on CNT5 by performing blanket etching or CMP is the interlayer insulating film 7 Try to come out on the surface. As shown in FIG. 22, the CNT plug is formed by depositing the upper wiring metal 8 on the entire surface.

  By the above method, it is possible to form the CNT 5 that is the wiring plug by using the apparatus and materials used in the conventional manufacturing process of the SiC power device. Accordingly, the effective area of the chip is increased by reducing the area where the plug is wired, and the loss during energization is reduced, so that a large current can flow, leading to improvements in device performance and reliability. Further, since SiC1 is made amorphous by ion implantation, it is possible to form CNT5 by a process at a lower temperature and in a shorter time than conventional.

<Embodiment 3>
23 to 35 are manufacturing process diagrams of a MOSFET using CNT5 as a wiring plug in Embodiment 3 of the present invention. As shown in FIG. 23, an N source, a P well, and a JTE are formed by selectively implanting ions into a predetermined region of an SiC substrate in which an n ⁻ type epi layer is formed on an n type substrate. Although the P contact is not shown in FIG. 23, a P contact which is a high-concentration P-type SiC region is formed as shown in FIG. 46 to reduce the contact resistance between the CNT 5 and the P well in FIG. May be. As shown in FIG. 24, for example, ions are implanted into a region where CNTs are to be formed using a resist as a mask to make it amorphous. At this time, for example, when ion implantation is performed at room temperature, the nitrogen concentration should be 5 × 10 ¹⁹ cm ⁻³ or more if the implanted element is nitrogen, and the aluminum concentration should be 2 × 10 ¹⁹ cm ⁻³ or more if aluminum is used. That's fine.

As shown in FIG. 25, a region where the CNT 5 is formed is covered with a graphite cap 4. In the case where a resist is used for the implantation mask 2 in FIG. 24, the resist becomes graphite when heat-treated at 750 ° C. for 10 minutes, for example. Although this graphite cap 4 is not necessarily required, the region covered with the graphite cap 4 when the processing of FIG. 26 is performed is characterized in that the CNT 5 is not formed and the flatness of the surface of the SiC 1 is maintained. In FIG. 26, for example, when activation annealing is performed at 1700 ° C. for 10 minutes in a vacuum (1 × 10 ⁻⁴ Torr or less), Si is removed from amorphous SiC 3 to form CNT 5. Then, as shown in FIG. 27, CNT5 is grown under the condition of 50 Torr at 550 ° C. while supplying C ₂ H ₂ by, for example, the CVD method.

28, the CNT 5 is protected by forming a mask, eg, SiN, on the CNT 5, and the SiN mask 6 is removed by removing the graphite cap 4 by, for example, thermal oxidation (950 ° C., 15 minutes) as shown in FIG. To do. As shown in FIG. 30, after depositing a SiO ₂ film on the entire surface of the wafer by a thermal CVD method using as the CNT protective film 9 (field oxide film) for example TEOS, the SiO ₂ film in the region for forming a gate oxide film 10 Remove. In FIG. 31, a gate oxide film 10 is formed by thermal oxidation or the like, and in FIG. 32, a gate electrode 11, for example, poly-Si is formed by film formation and etching.

As shown in FIG. 33, an SiO ₂ film is deposited on the entire surface of the wafer by an interlayer insulating film 7, for example, a thermal CVD method using TEOS. In FIG. 34, SiO ₂ on CNT 5 is removed by whole surface etching or CMP. It comes out on the surface of the interlayer insulating film 7. Then, as shown in FIG. 35, the CNT plug is formed by depositing the upper wiring metal 8 on the entire surface. Here, in order to simplify the drawing, two CNTs 5 are shown in FIG. 35. However, in an actual MOSFET, a plurality of MOSFETs each having a unit cell between the left and right CNTs 5 are connected in parallel.

  Here, the region for forming CNTs is made amorphous by the method shown in FIG. 24. However, in the structure diagram after ion implantation shown in FIG. 46, for example, when the N source and the P contact 12 are formed by ion implantation. Alternatively, only the surface portion may be made amorphous by increasing the concentration of the surface portion. Thereby, the ion implantation process for amorphization shown in FIG. 24 can be omitted. In this method, the region for forming CNT5 and the region for amorphous SiC3 are different, but the device characteristics are not particularly affected.

  According to the method as described above, it is possible to form the CNTs 5 as wiring plugs by using the devices and materials used in the conventional SiC-MOSFET manufacturing process. As a result, a large current can flow in the SiC-MOSFET, leading to improvements in device performance and reliability.

<Embodiment 4>
36 to 45 are manufacturing process diagrams of a MOSFET using CNT5 as a wiring plug according to Embodiment 4 of the present invention. The manufacturing method of the MOSFET according to the fourth embodiment of the present invention is the same manufacturing method as that in the third embodiment up to FIGS. Here, the subsequent manufacturing steps will be described.

As shown in FIG. 36, after a mask, for example, a SiN mask 6 is formed on the CNT 5 to protect the CNT 5, the graphite cap 4 and SiC 1 around the CNT 5 are removed by thermal oxidation and etching or only etching in FIG. To do. In FIG. 37, the surrounding SiC surface is removed by the length of the carbon nanotube, but this is not necessarily the case, and the etching amount of SiC is larger than the length of the carbon nanotube as long as it does not affect the device characteristics to be produced. It can be large or small. After removing the SiN mask 6, as shown in FIG. 38, a SiO ₂ film is deposited on the entire surface of the wafer as a CNT protective film 9 (field oxide film) by, for example, a thermal CVD method using TEOS. The SiO ₂ film in the region where the gate oxide film 10 is to be formed is removed.

In FIG. 40, a gate oxide film 10 is formed by thermal oxidation or the like, and as shown in FIG. 41, a gate electrode 11, for example, poly-Si is formed by film formation and etching. As shown in FIG. 42, SiO ₂ is deposited on the entire surface of the wafer by thermal CVD using interlayer insulating film 7, for example, TEOS, and SiO ₂ on CNT ₅ is removed by selective etching in FIG. As shown in FIG. 44, CNT5 is grown under the condition of 50 Torr at 550 ° C. while supplying C ₂ H ₂ by CVD, for example, so that CNT5 comes out from the surface of the interlayer insulating film 7. Then, as shown in FIG. 45, the CNT plug is formed by depositing the upper wiring metal 8 on the entire surface. Here, in order to simplify the drawing, two CNTs 5 are shown in FIG. 45, but in an actual MOSFET, a plurality of MOSFETs each having a unit cell between the left and right CNTs 5 are connected in parallel.

  Here, the region for forming CNTs is made amorphous by the method shown in FIG. 24. However, in the structure diagram after ion implantation shown in FIG. 46, for example, when the N source and the P contact 12 are formed by ion implantation. Alternatively, only the surface may be made amorphous by increasing the concentration of the surface portion. Thereby, the ion implantation process for amorphization shown in FIG. 24 can be omitted. In this method, the region for forming the CNT 5 and the region for the amorphous SiC 3 are different, but the device characteristics are not particularly affected.

  According to the method as described above, it is possible to form the CNT 5 as a wiring plug by using an apparatus and a material used in a conventional SiC-MOSFET manufacturing process. As a result, a large current can flow in the SiC-MOSFET, leading to improvements in device performance and reliability.

It is a manufacturing process figure of the silicon carbide semiconductor device in Embodiment 1 of the present invention. It is a manufacturing process figure of the silicon carbide semiconductor device in Embodiment 1 of the present invention. It is a manufacturing process figure of the silicon carbide semiconductor device in Embodiment 1 of the present invention. It is a manufacturing process figure of the silicon carbide semiconductor device in Embodiment 1 of the present invention. It is a manufacturing process figure of the silicon carbide semiconductor device in Embodiment 1 of the present invention. It is a manufacturing process figure of the silicon carbide semiconductor device in Embodiment 1 of the present invention. It is a manufacturing process figure of the silicon carbide semiconductor device in Embodiment 1 of the present invention. It is a manufacturing process figure of the silicon carbide semiconductor device in Embodiment 1 of the present invention. It is a manufacturing process figure of the silicon carbide semiconductor device in Embodiment 1 of the present invention. It is a manufacturing process figure of the silicon carbide semiconductor device in Embodiment 1 of the present invention. It is a manufacturing process figure of the silicon carbide semiconductor device in Embodiment 1 of the present invention. It is a manufacturing process figure of the silicon carbide semiconductor device in Embodiment 1 of the present invention. It is a manufacturing process figure of the silicon carbide semiconductor device in Embodiment 1 of the present invention. It is a manufacturing process figure of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is a manufacturing process figure of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is a manufacturing process figure of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is a manufacturing process figure of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is a manufacturing process figure of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is a manufacturing process figure of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is a manufacturing process figure of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is a manufacturing process figure of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is a manufacturing process figure of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is a manufacturing process figure of MOSFET which used CNT for the wiring plug in Embodiment 3 of this invention. It is a manufacturing process figure of MOSFET which used CNT for the wiring plug in Embodiment 3 of this invention. It is a manufacturing process figure of MOSFET which used CNT for the wiring plug in Embodiment 3 of this invention. It is a manufacturing process figure of MOSFET which used CNT for the wiring plug in Embodiment 3 of this invention. It is a manufacturing process figure of MOSFET which used CNT for the wiring plug in Embodiment 3 of this invention. It is a manufacturing process figure of MOSFET which used CNT for the wiring plug in Embodiment 3 of this invention. It is a manufacturing process figure of MOSFET which used CNT for the wiring plug in Embodiment 3 of this invention. It is a manufacturing process figure of MOSFET which used CNT for the wiring plug in Embodiment 3 of this invention. It is a manufacturing process figure of MOSFET which used CNT for the wiring plug in Embodiment 3 of this invention. It is a manufacturing process figure of MOSFET which used CNT for the wiring plug in Embodiment 3 of this invention. It is a manufacturing process figure of MOSFET which used CNT for the wiring plug in Embodiment 3 of this invention. It is a manufacturing process figure of MOSFET which used CNT for the wiring plug in Embodiment 3 of this invention. It is a manufacturing process figure of MOSFET which used CNT for the wiring plug in Embodiment 3 of this invention. It is a manufacturing process figure of MOSFET which used CNT for the wiring plug in Embodiment 4 of this invention. It is a manufacturing process figure of MOSFET which used CNT for the wiring plug in Embodiment 4 of this invention. It is a manufacturing process figure of MOSFET which used CNT for the wiring plug in Embodiment 4 of this invention. It is a manufacturing process figure of MOSFET which used CNT for the wiring plug in Embodiment 4 of this invention. It is a manufacturing process figure of MOSFET which used CNT for the wiring plug in Embodiment 4 of this invention. It is a manufacturing process figure of MOSFET which used CNT for the wiring plug in Embodiment 4 of this invention. It is a manufacturing process figure of MOSFET which used CNT for the wiring plug in Embodiment 4 of this invention. It is a manufacturing process figure of MOSFET which used CNT for the wiring plug in Embodiment 4 of this invention. It is a manufacturing process figure of MOSFET which used CNT for the wiring plug in Embodiment 4 of this invention. It is a manufacturing process figure of MOSFET which used CNT for the wiring plug in Embodiment 4 of this invention. It is a manufacturing process figure of MOSFET which used CNT for the wiring plug in Embodiment 3 and Embodiment 4 of this invention.

Explanation of symbols

  1 SiC, 2 implantation mask, 3 amorphous SiC, 4 graphite cap, 5 CNT, 6 SiN mask, 7 interlayer insulating film, 8 upper wiring metal, 9 CNT protective film, 10 gate oxide film, 11 gate electrode, 12 P contact.

Claims (9)

A method for manufacturing a silicon carbide semiconductor device, comprising:
(A) introducing an impurity into the surface of the silicon carbide semiconductor by ion implantation to make it amorphous;
(B) forming a carbon nanotube on the surface of the silicon carbide semiconductor by heat-treating the amorphous silicon carbide semiconductor surface;
(C) the use of carbon nanotubes as a base, a step of Ru grown further carbon nanotubes by supplying C ₂ H ₂ thereabove,
A method for manufacturing a silicon carbide semiconductor device, comprising:   2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the step (b) is performed by covering a region where the carbon nanotubes are not formed with a graphite cap. 3. The step (b)
(D) a heat treatment step without a mask;
(E) removing carbon nanotubes formed outside the amorphous region;
The method for manufacturing a silicon carbide semiconductor device according to claim 1, comprising:   3. The method for manufacturing a silicon carbide semiconductor device according to claim 2, wherein the graphite cap is an implantation mask used to cover a region where the impurity is not introduced in the step (a). A method for manufacturing a silicon carbide semiconductor device, comprising:
(F) introducing an impurity into the region where the carbon nanotube is to be formed in the surface of the silicon carbide semiconductor by ion implantation to make it amorphous;
A step of forming the carbon nanotube in the region by heat treatment (g) of the area above amorphous,
(H) removing the surface of the silicon carbide semiconductor other than the region ;
(I) after the step (h), forming an insulating film so as to cover the surfaces of the carbon nanotubes and the silicon carbide semiconductor;
A method for manufacturing a silicon carbide semiconductor device, comprising:   6. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein in the step (g), the region where the carbon nanotube is not formed is covered with a graphite cap.   The method of manufacturing a silicon carbide semiconductor device according to claim 6, wherein the graphite cap is an implantation mask used to cover a region where the impurity is not introduced in the step (f). The carbon nanotube is a source wiring plug,
After step (c)
(J) The silicon carbide according to claim 1, further comprising a step of forming a gate oxide film and a gate electrode after covering the carbon nanotube with a protective film, and using the silicon carbide as a method for manufacturing a SiC-MOSFET. A method for manufacturing a semiconductor device. The carbon nanotube is a source wiring plug,
Between the step (b) and the step (c),
(K) The silicon carbide according to claim 1, further comprising a step of forming a gate oxide film and a gate electrode after covering the carbon nanotube with a protective film, and using the silicon carbide as a method for manufacturing a SiC-MOSFET. A method for manufacturing a semiconductor device.

Images