JP5070470B2 - Temporary phase clock generation method for encoder with failure detection function - Google Patents

Description

The present invention relates to a provisional phase clock generation method for an encoder with a failure detection function, and in particular, A phase,
By obtaining a temporary phase clock based on B-phase incremental signal, a novel improvement for obtaining a stable temporary phase clock even when the chattering incremental signal is generated.

In the case of an encoder with a built-in function of this type that has been used in the past, for example, the encoder disclosed in Patent Document 1 is not disclosed, but as a reference signal for performing fault detection A clock signal obtained from a clock generation circuit built in the signal processing circuit of the encoder is employed.
By using the clock signal, detection and correction of an erroneous signal of the encoder signal obtained from the signal processing circuit is performed.

JP-A-8-204572

  Conventional encoders with built-in failure detection functions use the clock signal from the built-in circuit as described above. To detect this clock abnormality, two clock signals are prepared. Therefore, there is a problem in both circuit configuration and cost.

  Further, in the above-described incremental encoder, when the shaft position is near the change point of the output logic, the encoder output may chatter due to electrical and mechanical factors. When abnormality of the system clock is detected based on the chattered incremental signal, a high-speed pulse exceeding the operable clock of the detection circuit may be input, and normal detection is difficult.

When the tentative phase clock generation method of fault detection function encoder according to the present invention, that generates a temporary phase clock using the A-phase incremental signal and the B-phase incremental signal rotation obtained by the detection by the detection unit of the rotating body, When the A-phase incremental signal is “1” and the B-phase incremental signal is “1”, the temporary phase clock is changed to “1”, the A-phase incremental signal is “0”, and the B-phase incremental signal is When the value is “0”, the temporary phase clock changes to “0”, and when the chattering signal is generated in the A-phase or B-phase incremental signal, the generation of the temporary phase clock is not affected. In addition, the A-phase and B-phase incremental signals are composed of four quadrant signals per cycle with phases different from each other by 90 °. When you generate a clock, the temporary phase clock as long as 2 quadrant apart condition is not established among the 4 quadrant is a method of using a logic inversion does not occur.

Since the provisional phase clock generation method for the encoder with a failure detection function according to the present invention is configured as described above, the following effects can be obtained.
That is, when you generate a temporary phase clock using the A-phase incremental signal and the B-phase incremental signal rotation obtained by the detection by the detection unit of the rotating body, the B-phase incremental by the A-phase incremental signal is "1" When the signal is “1”, the temporary phase clock changes to “1”, and when the A phase incremental signal is “0” and the B phase incremental signal is “0”, the temporary phase clock is “0”. When the chattering signal is generated in the A-phase or B-phase incremental signal, the generation of the temporary phase clock is not affected, and the A-phase and B-phase incremental signals are phase is composed of 4 quadrant signals per period differ with each other by 90 °, when you generate the temporary phase clock, Do 2 quadrant away condition of the 4 quadrant is satisfied Since the temporary phase clock only uses a logic inversion does not occur, even when the chattering occurs in the incremental signal, without being affected by chattering, and generate a stable temporary phase clock signals, the use of a redundant system Instead, a temporary phase clock can be obtained to detect a clock failure.

The present invention, A phase, by obtaining a temporary phase clock based on B-phase incremental signal, temporary fault detection function encoder as chattering incremental signal to obtain a temporary phase clock stabilized even when generated An object is to provide a phase clock generation method.

A preferred embodiment of a temporary phase clock generation method for an encoder with a failure detection function according to the present invention will be described below with reference to the drawings.
In FIG. 1, reference numeral 1 denotes a rotating body composed of a rotary code plate of an encoder, and a two-phase A-phase incremental signal 3 from the detection unit 2 optically obtained by the rotation of the rotating body 1 and The B-phase incremental signal 4 is configured to be generated as a temporary phase clock signal 6 via the signal processing unit 5.

FIG. 2 shows that, as the generation of the temporary phase clock 6, when the condition that the A phase incremental signal 3 is “1” and the B phase incremental signal 4 is “1” is satisfied, the temporary phase clock 6 is changed to “1”. When each of the incremental signals 3 and 4 is “0”, the temporary phase clock 6 is “0”.
In this case, when the chattering signal 7 is generated in the A-phase incremental signal 3 due to mechanical vibration or the like, the chattering signal 7 does not affect the temporary phase clock 6 and an abnormal frequency is not output.

Further, in the incremental encoder, since the phases of the A and B phase incremental signals 3 and 4 are shifted by 90 °, four quadrant signals can be obtained per cycle, but the temporary encoder for clock monitoring can be obtained from this incremental encoder. Oite when you generate a phase clock 6, 2 quadrant apart condition Crossed logic clock is not inverted unless established to the signal processing unit 5 (for example, first in quadrant "1", the third elephant Thus, even if the chattering signal 7 is generated, no chattering occurs in the monitoring temporary phase clock, and it can be used as a detection clock.

It is a block diagram which shows the temporary phase clock generation method by this invention. It is a wave form diagram of each signal of FIG.

DESCRIPTION OF SYMBOLS 1 Rotating body 2 Detection part 3 A phase incremental signal 4 B phase incremental signal 5 Signal processing part 6 Temporary phase clock 7 Chattering signal

Claims (2)

When you generate a temporary phase clock (6) using the A-phase incremental signal obtained by detecting by the detector rotation (2) of the rotating body (1) (3) and B-phase incremental signals (4),
When the A-phase incremental signal (3) is “1” and the B-phase incremental signal (4) is “1”, the temporary phase clock (6) changes to “1” and the A-phase incremental signal (3 ) Is “0” and the B-phase incremental signal (4) is “0”, the temporary phase clock (6) changes to “0” and changes to the A-phase or B-phase incremental signal (3,4). A temporary phase clock generation method for an encoder with a fault detection function, wherein generation of the temporary phase clock (6) is not affected when a chattering signal (7) is generated. The A-phase, B-phase incremental signals (3, 4), the phase is composed of 4 quadrant signals per period differ with each other by 90 °, when you generate the temporary phase clock, the 4 quadrant 2. The method of generating a temporary phase clock for an encoder with a fault detection function according to claim 1, wherein a logic that does not invert the temporary phase clock (6) is used unless conditions apart from two quadrants are satisfied.

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