JP4551780B2 - Encoder signal processing circuit - Google Patents

Description

  The present invention relates to an encoder signal processing circuit that generates a plurality of periodic signals whose phases are shifted in accordance with a change in position of an object to be measured, and that particularly improves malfunction due to chattering.

  Patent Document 1 discloses an optical encoder that generates a substantially sine wave analog signal having at least two phases shifted in accordance with a change in position of a measurement object. The two substantially phased sine wave analog signals A and B, which are out of phase, are input to a multiplication circuit to obtain two multiplication signals DA and DB of A phase and B phase having a predetermined phase difference as shown in FIG. Can do.

  The level (state) change of the A-phase and B-phase signals varies depending on the change direction as shown in FIG. That is, in a change in one direction, the levels of the two signals periodically change from 01 → 11 → 10 → 00 → 01, and the phase of the A phase changes 90 ° behind the phase of the B phase. In the change in the other direction, as shown in FIG. 6, 01 → 00 → 10 → 11 → 01 periodically changes, and the phase of the A phase changes 90 degrees ahead of the phase of the B phase. The movement direction can be detected by detecting this phase relationship, and the movement amount can be detected by counting the number of level (state) changes of the A-phase and B-phase signals.

  However, when chattering occurs in the A phase and B phase signals DA and DB as shown in FIG. 7 due to the influence of noise or the like, the movement amount is erroneously detected. Patent Document 2 discloses a signal processing circuit that does not erroneously detect a movement amount even when this chattering occurs. In other words, based on two input pulses with different phases, a sequential circuit appropriately performs logical processing to generate a count signal and an addition / subtraction determination signal, and generates a count value based on the two signals to detect a movement amount. ing. Patent Document 2 discloses the above-described sequential circuit as shown in FIG. 8, and FIG. 9 shows an output signal of the above-described logic circuit with respect to an input signal with chattering.

  In Patent Document 1, a count signal and an addition / subtraction determination signal are generated as follows. First, two input signals P1 and P2 are input to a sequential circuit, and two internal signals S1 and S2 are generated. In this sequential circuit, even if chattering occurs after one input signal P1 changes, chattering is not reflected in the internal signal S2 until the other input signal P2 changes. Next, the two internal signals S1 and S2 are input to the exclusive OR gate to generate the count signal C. Further, an addition / subtraction determination signal J is generated from the two input signals P1, P2 and the internal signals S1, S2.

  The internal signals S1 and S2 are basically signals obtained by removing chattering from the input signals P1 and P2. However, when the moving direction is switched, the first change of the input signals P1 and P2 cannot be reflected in the internal signals S1 and S2.

  FIG. 10 shows each signal immediately after the direction is switched at the timing indicated by the line segment X, and the change of the input signal P2 is not reflected in the internal signal S1. For this reason, the change of the input signal P2 is not reflected in the count signal C. Therefore, the movement amount is erroneously detected only by counting the count signal C. However, in Patent Document 2, in addition to the counting by the counting signal C, the erroneous detection is performed by correcting the count value by the addition / subtraction determination signal J. It is preventing.

  Patent Document 3 discloses another signal processing circuit that does not erroneously detect the amount of movement even when chattering occurs, and uses a processing circuit called a random logic circuit. The input signal to the random logic circuit is a signal obtained by latching two input signals having different phases and the output of the random logic circuit with a predetermined clock by a DFF (digital flip-flop circuit). The logic of the random logic circuit is the same as the sequential circuit of Patent Document 1, and even if chattering occurs after one input signal changes, chattering is not reflected until the other signal changes. Yes.

Japanese Patent Laid-Open No. 1-121723 Japanese Patent Publication No. 60-10454 JP-A-4-342310

  However, in Patent Documents 1 and 2, when the moving direction is switched, the first input signal change is not reflected in the count signal. For this reason, a special process of correcting the count value with the addition / subtraction determination signal is required. Similarly, in Patent Document 3, when the moving direction is switched, the first change of the input signal cannot be reflected in the output signal.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an encoder signal processing circuit that solves the above-described problems and faithfully outputs the amount of movement even when the encoder output signal has chattering or when the movement direction is changed. is there.

Technical characteristics of the encoder signal processing circuit according to the present invention for achieving the above object, after the signal processing as input two rectangular wave signals different phases generated with the change in position of the object to be measured In the signal processing circuit for output, an input terminal for initializing an output state when the two rectangular wave signals are input to the signal processing circuit, and an input terminal for inverting the output state by a pulse signal The memory circuit, a direction signal input means for inputting a direction signal indicating the phase shift direction of the two rectangular wave signals, the output signal of the storage circuit, the direction signal, and the direction signal. And a pulse generation circuit for generating a pulse signal for inverting the output state of the circuit.

  The encoder signal processing circuit according to the present invention can faithfully output changes other than chattering of the encoder output signal even when chattering generated in the encoder output signal is removed and the moving direction is changed.

The present invention will be described in detail based on the embodiment shown in FIGS.
FIG. 1 is a block circuit diagram showing the configuration of the embodiment. Output signals DA and DB that are rectangular wave signals of the encoder 1 are connected to the CPU 3 via a signal processing circuit 2 that generates a count signal. The direction signal DIR, the set signal SET, and the reset signal RST that are outputs of the CPU 3 are connected to the signal processing circuit 2. Further, the output of the CPU 3 is connected to the driver 4, and the output of the driver 4 is connected to the encoder 1 via the actuator 5.

The encoder 1 generates at least two substantially sine wave analog signals in accordance with a change in the position of the measurement object (object to be measured) , detects the polarity change, and generates two pulse signals DA and DB. The CPU 3 outputs an operation signal to DIR, SET, and RST as input terminals for initial setting of the output state in the signal processing circuit 2, and the CPU 3 counts the count signal C generated by the signal processing circuit 2. Detect position. The driver 4 drives the actuator 5 by an operation signal from the CPU 3, and the output signal of the encoder 1 changes by the operation of the actuator 5.

FIG. 2 is a specific configuration diagram of the signal processing circuit 2 as a pulse generation circuit . One output signal DA of the encoder 1 is input to the NOT gate 11 and an inverted signal of the signal DA is output. The other output signal DB of the encoder 1 is input to the NOT gate 12 and an inverted signal of the signal DB is output. To do. The AND gates 13 to 20 receive the output signals DA and DB and their inverted signals, and output signals DAO and DBO of a DFF (digital flip-flop circuit) as a memory circuit , which will be described later, and their inverted signals. The output signals of the AND gates 13 to 20 are input to the OR gates 22 to 25, the direction signal DIR output from the CPU 3 is input to the NOT gate 26, and the inverted signal thereof is output.

  The outputs of the OR gates 22 to 25 and the direction signal DIR output from the CPU 3 and its inverted signal are input to the AND gates 27 to 30, and the output signals of the AND gates 27 to 30 are input to the OR gates 31 and 32. The output signal of the OR gate 31 is input to the CK terminal of the DFF 33, and the output signal of the OR gate 32 is input to the CK terminal of the DFF 34. The AND gates 35 and 36 receive the output signals DA and DB of the encoder 1 and the set signal SET output from the CPU 3.

  The outputs of the AND gates 35 and 36 are input to the SB terminals of the DFFs 33 and 34. The NOT gates 37 and 38 receive the output signals DA and DB of the encoder 1. The AND gates 39 and 40 receive the outputs of the NOT gates 37 and 38 and the set signal SET output from the CPU 3. The AND gates 41 and 42 receive the output of the AND gates 39 and 40 and the reset signal RST output from the CPU 3, and the output is input to the RB terminals of the DFFs 33 and 34. Output signals from the QB terminals of the DFFs 33 and 34 are input to the D terminal, and output signals DAO and DBO from the Q terminal are output to the NOT gates 43 and 44, respectively.

  FIG. 3 is a waveform diagram of the signal processing circuit 2, and the CPU 3 sends the reset signal RST to H (high level) to the signal processing circuit 2 to release the reset of the signal processing circuit 2 and make it operable. As shown in a, the set signal SET is set to H, the output signals DA and DB of the encoder 1 are latched in the DFFs 33 and 34, and then the set signal SET is set to L (low level).

Next, the CPU 3 as the direction signal input means sets the direction signal DIR based on the direction in which the actuator 5 is driven. The direction in which the phase of the output signal DA of the encoder 1 changes by 90 ° with respect to the phase of the signal DB is DIR = H, and the direction in which the phase of the signal DA changes by 90 ° with respect to the phase of the signal DB is DIR = L. And

  In the waveform diagram shown in FIG. 3, DIR = H because the phase of the signal DA changes 90 ° behind the phase of the signal DB as shown in b. Thereafter, driving of the actuator 5 is started, and the output signals DA and DB of the encoder 1 change. In response to this change, the signal processing circuit 2 outputs signals DAO and DBO.

  When DIR = H, the signal DA changes from L to H in the state of DAO = L and DBO = L, and the signal DA changes from H to L in the state of DAO = H and DBO = H. Only when the output of the OR gate 31 changes from L to H, the state of the Q terminal and the QB terminal of the DFF 33 is changed.

  Similarly, only when the signal DB changes from L to H in the state of DAO = H and DBO = L, and only when the signal DB changes from H to L in the state of DAO = L and DBO = H. The output of 32 changes from L to H, and changes the state of the Q terminal and QB terminal of the DFF 34.

  When DIR = L, the signal DA changes from L → H in the state of DAO = L and DBO = H, and when the signal DA changes from H → L in the state of DAO = H and DBO = L. Only when it changes, the output of the OR gate 31 changes from L to H, and changes the state of the Q terminal and QB terminal of the DFF 33.

  Furthermore, the OR gate 32 only when the signal DB changes from L → H in the state of DAO = L and DBO = L, and only when the signal DB changes from H → L in the state of DAO = H and DBO = H. Changes from L to H, and changes the state of the Q terminal and QB terminal of the DFF 34.

  Therefore, even if chattering occurs in the output signals DA and DB of the encoder 1 as shown in FIG. 3c, appropriate signals from which chattering has been removed can be output as the output signals DAO and DBO.

  FIG. 4 shows a waveform diagram of the signal processing circuit 2 when the moving direction is switched. The signal processing circuit 2 faithfully follows the change in the output signals DA and DB of the first encoder 1 even when the moving direction is switched. Can be output.

  The present invention is not limited to the above-described embodiments, and various modifications and changes can be made within the scope of the claims.

It is a block circuit block diagram of an Example. It is a block diagram of a signal processing circuit. It is an output waveform diagram of the signal processing circuit. It is a wave form diagram of a signal processing circuit at the time of switching a moving direction. It is an output waveform diagram of a general encoder. It is an output waveform diagram of a general encoder. It is an output waveform diagram of an encoder in which chattering has occurred. It is a block diagram of the conventional signal processing circuit. It is an output waveform diagram of a conventional signal processing circuit. It is an output waveform diagram of the conventional signal processing circuit when the moving direction is switched.

Explanation of symbols

1 Encoder 2 Signal Processing Circuit 3 CPU
4 Driver 5 Actuator

Claims (2)

In the signal processing circuit for outputting after signal processing as input two rectangular wave signals different phases generated with the change in position of the object to be measured, receiving the two rectangular-wave signal to the signal processing circuit An input terminal for initial setting of the output state at the time of input, a memory circuit having an input terminal for inverting the output state by a pulse signal, and a direction signal indicating the phase shift direction of the two rectangular wave signals Direction signal input means, and a pulse generation circuit that generates a pulse signal that inverts the output state of the storage circuit from the two rectangular wave signals, the output signal of the storage circuit, and the direction signal. An encoder signal processing circuit.   2. The signal processing circuit for an encoder according to claim 1, wherein the memory circuit is a flip-flop circuit.

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