JP5083010B2 - Nonvolatile memory device and LSI device - Google Patents

Description

  The present invention relates to a non-volatile memory and an LSI (large-scale integrated circuit) device that can be applied to all semiconductor memories. For example, the present invention relates to a non-volatile memory device and an LSI device capable of extending the life while preventing unauthorized copying. .

  Non-volatile memories such as flash memories are characterized by a rewritable function, but have disadvantages such as a limited number of rewrites and weak points in terms of security. Here, as a security weak part, for example, data in a memory can be easily illegally copied.

  This type of illegal copying is due to the fact that in many conventional systems, there are many methods for providing security functions to the memory peripheral functions, and there is no method for providing security functions to the memory itself, so it is easy to copy data from the memory itself. I think that.

On the other hand, for example, techniques disclosed in Patent Documents 1 and 2 have been proposed from the viewpoint of preventing unauthorized copying of data in the memory. The technique described in Patent Document 1 stores encrypted data in a memory area, and outputs encrypted data in the memory area without performing decryption during an illegal read process. In the technique described in Patent Document 2, if a prohibited address is accessed when data is copied, erroneous data is output after a predetermined cycle.
JP 2002-268947 A Japanese Patent Application No. 7-243335

  However, although the techniques described in Patent Documents 1 and 2 are techniques for preventing unauthorized copying according to the study of the present inventor, it is considered that there is still room for improvement regarding the limitation on the number of rewrites. In a general memory structure, since the rewrite space uses the same space in the system, the memory life is shortened only in the space with high rewrite frequency.

  Therefore, in the nonvolatile memory, it is considered necessary to further extend the life while preventing the illegal copy as described above.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a nonvolatile memory device and an LSI device capable of extending the life while preventing unauthorized copying.

  A first aspect of the present invention is a non-volatile memory device including a readable / writable memory unit that holds data corresponding to a physical address, and an address storage unit for storing a physical head address; A security code storing means for storing a security code, a means for writing the security code in the security code storing means when a code setting command and a security code are input, and a security code in the security code storing means Based on the physical head address, means for writing the determined physical head address to the address storage means, means for receiving the input security code, logical address and read / write command, and the input security Code and security code storage means Means for comparing the security code, and means for calculating a physical address based on the input logical address and the physical head address in the address storage means if they match as a result of the comparison; and The means for sending the calculated physical address and the inputted read / write command to the memory unit, and if the result of the comparison is that they do not match, the inputted logical address or false address, and the read / write Means for sending a write command to the memory unit.

  According to a second aspect of the present invention, there is provided a non-volatile memory device having a readable / writable memory unit for holding data corresponding to a physical address, wherein each part of the physical head address is replaced. Address storage means for storing the replacement physical head address, wiring pattern storage means for storing wiring pattern information for each system code, and a switching unit capable of switching the wiring pattern based on the input switching signal. In order to store the security code and the wiring means for transmitting to the address storage means the replaced physical head address obtained by replacing each part of the physical head address sent on the wiring pattern by the switching unit. Security code storage means, and a code setting command and a security code, the security code is stored in the security code. When a system code is input and a means for writing to the code storage means, a switching signal corresponding to the wiring pattern information read from the wiring pattern storage means is input to the switching section based on the input system code. The physical head address is determined based on the security code in the security code storage means, and the determined physical head address is stored as the replacement physical head address via the wiring means to which the switching signal is input. Means for writing in the means; means for receiving the input security code, system code, logical address and read / write command; means for comparing the input security code with the security code in the security code storage means; As a result of this comparison, both agree The switching signal corresponding to the wiring pattern information read from the wiring pattern storage unit is input to the switching unit based on the input system code, and the switching unit receives the switching signal via the wiring unit to which the switching signal is input. First physical address reading means for reading out a replacement physical head address in the address storage means as a physical head address, a physical address read by the first physical address reading means, and the input logical address Based on the first physical address calculation means for calculating the physical address and, if the result of the comparison is that they do not match, the replacement from the address storage means via the wiring means without inputting the switching signal Read by the second physical address reading means for reading the physical head address and the second physical address reading means. A second physical address calculating means for calculating a physical address based on the replaced physical head address and the inputted logical address; and a physical address calculated by the first or second physical address calculating means; A non-volatile memory device comprising: means for sending the input read / write command to the memory unit.

  A third aspect of the present invention is a non-volatile memory device including a readable / writable memory unit that holds data corresponding to a physical address, and stores the physical address in association with the logical address. An address storage means, a security code storage means for storing a security code, a means for writing the security code in the security code storage means when a code setting instruction and a security code are input, and in the security code storage means A physical address is determined based on the security code, and a means for writing to the address storage means so as to associate the determined physical address with a logical address having a value different from the physical address, an input security code, a logical address, and Means for accepting read / write commands; The means for comparing the input security code with the security code in the security code storage means, and if the result of this comparison is that they match, the input logical address is sent to the address storage means to A means for reading a physical address from an address storage means; a means for sending the read physical address and the inputted read / write command to the memory unit; A non-volatile memory device comprising: a logical address or a false address; and a means for sending the read / write command to the memory unit.

  According to a fourth aspect of the present invention, there is provided a non-volatile memory device having a readable / writable memory unit for holding data corresponding to a physical address, wherein each part of a logical address is replaced. Address storage means for storing a physical address in association with a logical address, wiring pattern storage means for storing wiring pattern information for each system code, and switching capable of switching a wiring pattern based on an input switching signal A wiring means for transmitting to the address storage means a replacement logical address in which each part of the logical address sent on the wiring pattern is replaced by the switching section, and stores a security code Security code storage means, and a code setting instruction and a security code are input, the security code is Means for writing to the security code storage means; means for determining a physical address based on the security code in the security code storage means; and writing to the address storage means so as to associate the determined physical address with the replacement logical address; Means for receiving the input security code, system code, logical address and read / write command; means for comparing the input security code with the security code in the security code storage means; as a result of this comparison; If they match, based on the input system code, a switching signal corresponding to the wiring pattern information read from the wiring pattern storage means is input to the switching unit, and the input logical address is Wiring with switching signal input The first physical address reading means for sending out the physical address from the address storage means by sending it to the address storage means as a replacement logical address via the stage, and if the comparison results in a mismatch, input the switching signal The second physical address reading means for reading the input logical address from the wiring means to the address storage means and reading the physical address from the address storage means, and the first or second physical address reading. A non-volatile memory device comprising: a physical address read by the means and a means for sending the input read / write command to the memory unit.

  Note that the nonvolatile memory devices of the first to fourth aspects may be provided in an LSI device. The term "LSI device" here is used as a general term for semiconductor integrated circuits, and is limited to the usual definition of LSIs based on the degree of integration (semiconductor integrated circuits with 1000 or more and less than 100,000 elements mounted). For example, it is used as a general concept such as IC, SSI, MSI, LSI (normal definition), VLSI, ULSI or MPU.

(Function)
According to the first to fourth aspects, when the security codes match, the configuration is such that after reading the physical head address or physical address from the address storage means, the memory unit is accessed with the correct physical address obtained. Can be prevented.

  Further, according to the first to fourth aspects, since the input logical address and the physical address in the memory unit are different, the rewriting frequency of the entire memory unit can be made uniform, and the life can be extended.

  As described above, according to the present invention, it is possible to extend the life while preventing unauthorized copying.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a schematic diagram showing a configuration of an LSI device according to the first embodiment of the present invention, and FIG. 2 is a schematic diagram showing a configuration of a nonvolatile memory device included in the LSI device. In this LSI device, the CPU 1 is individually connected to the nonvolatile memory device 100 via the address bus 2, the data bus 3 and the control bus 4, and data is transferred to the nonvolatile memory device 100 via the buses 2 to 4. It has a read / write function and a normal program processing function.

  The nonvolatile memory device 100 includes a flash memory unit 10 and an address conversion unit 20.

  Here, the flash memory unit 10 is a readable / writable nonvolatile memory unit that holds data corresponding to a physical address, and is accessible from the address conversion unit 20. Although the retained data is arbitrary, for example, there are basic data (eg, control value, control program, etc.) for realizing the function of the LSI device in addition to a normal file or the like. This type of basic data affects the performance of LSI devices and is described by the system developer's unique technical knowledge (know-how). Therefore, only CPU1 can be used from the viewpoint of preventing counterfeiting and theft. It is desirable that unauthorized copying is not performed from the outside. Further, as the flash memory unit 10, a flash memory is used as an example of a nonvolatile memory. However, the present invention is not limited to this, and a nonvolatile memory other than the flash memory, such as a read-only ROM, may be used. .

  The address conversion unit 20 includes an address memory 21, a security code storage memory 22, a security code setting unit 23, a control unit 24, and a code comparison unit 25.

  Here, the address memory 21 is readable / writable from the control unit 24 and is a memory for storing a physical head address.

  The security code storage memory 22 can be read / written from the security code setting unit 23, can be read from the code comparison unit 25, and is a memory for storing a security code.

  The security code setting unit 23 has a function of writing the security code in the security code storage memory 22 when a code setting command and a security code are input from the CPU 1 via the buses 4 and 3.

  The control unit 24 determines the physical head address based on the security code in the security code storage memory 22, and writes the determined physical head address to the address memory 21, and the CPU 1 via the buses 3, 2, 4. As a result of comparison between the function for receiving the input security code, the logical address and the read / write command, the function for sending the input security code to the code comparison unit 25, and the comparison by the code comparison unit 25, both security codes match. In this case, based on the input logical address and the physical head address in the address memory 21, the function for calculating the physical address and the calculated physical address and the input read / write command are sent to the flash memory unit 10. As a result of comparison between the function to send and the code comparison unit 25, both security If Ikodo is a mismatch, it has the address of the logical address or false that is the input, and a function of sending out the read / write command to the flash memory section 10.

  The function for calculating the physical address based on the logical address and the physical head address is, for example, a function of adding the logical address and the physical head address to each other, or one of the logical address and the physical head address. Arbitrary arithmetic functions such as a function of subtracting can be used. The same applies to other embodiments that an arbitrary calculation function can be used as a function of calculating a physical address based on a logical address and a physical head address.

  The code comparison unit 25 compares the security code received from the control unit 24 (input from the CPU 1 via the data bus 3) with the security code in the security code storage memory 22, and the comparison result is sent to the control unit. 24.

  Next, the operation of the LSI device including the nonvolatile memory device configured as described above will be described in the order of initialization and read / write using the flowcharts of FIGS.

(At initialization)
The CPU 1 inputs a code setting command and a security code to the nonvolatile memory device 100 via the buses 4 and 3.

  In the nonvolatile memory device 100, the security code setting unit 23 writes the security code *** in the security code storage memory 22 based on the input code setting command and the security code ***. A security code is set (ST1). In addition, the security code setting unit 23 notifies the control unit 24 of the completion of writing the security code.

  The control unit 24 determines the physical head address *** based on the security code *** in the security code storage memory 22, and writes the determined physical head address *** in the address memory 21 (ST2). ).

  Thereby, the operation at the time of initialization is completed.

(When reading / writing)
The CPU 1 inputs the security code ***, the logical address XXX, and the read / write command to the nonvolatile memory device 100 via the buses 3, 2, and 4. In the case of a read command or a write command, the CPU 1 thereafter sends write data to the data bus 3 at a timing in accordance with step ST14 described later.

  In the nonvolatile memory device 100, when the control unit 24 receives the input security code ***, logical address xxx and read / write command (ST11), the inputted security code *** *** is sent to the code comparison unit 25.

  The code comparison unit 25 compares the security code *** with the security code *** in the security code storage memory 22 (ST12), and sends the comparison result to the control unit 24.

  As a result of the comparison by the code comparison unit 25, the control unit 24, based on the logical address XXX input from the CPU 1 and the physical head address *** in the address memory 21, if the two security codes match. , Calculate the correct physical address *** (= ****** + ○○○○) (ST13), and input the correct physical address *** and the input read / write command to the flash memory unit 10. Send out (ST14).

  In the flash memory unit 10, data ΔΔΔΔ corresponding to the correct physical address *** is read / written based on the read / write command.

  On the other hand, as a result of the comparison by the code comparison unit 25, if the two security codes do not match, the control unit 24 sends the logical address xxx or false address inputted from the CPU 1 and the read / write command to the flash memory. The data is sent to the unit 10 (ST15).

  In the flash memory unit 10, data corresponding to the logical address XXX or a false address (data not corresponding to the correct physical address ***) is read / written based on the read / write command.

  As described above, according to the present embodiment, when the security codes match, unauthorized copying is prevented by the configuration in which the flash memory unit 10 is accessed with the calculated correct physical address based on the physical head address in the address memory 21. be able to. If the security codes do not match, data is read from the flash memory unit 10 without accessing the address memory 21, so that data different from the originally intended data is read.

  Furthermore, according to the present embodiment, since the input logical address and the physical address in the memory unit are different, the rewriting frequency of the entire flash memory unit 10 can be made uniform, and the life can be extended.

  For example, in the prior art, as shown in FIG. 5, since the logical address input from the CPU and the physical address in the flash memory are the same, the frequency of rewriting the memory area near the physical head address is high. Life is shortened.

  On the other hand, in this embodiment, as shown in FIG. 6, the logical address input to the address conversion unit 20 and the physical address in the flash memory unit 10 are equivalent to the physical head address determined by the security code. Therefore, since the rewrite frequency is distributed and equalized throughout the flash memory unit 10, the life can be extended. In this case, in the flash memory unit 10, data is not arranged in the order of physical addresses, and data is arranged at random in appearance. Such equalization of the rewrite frequency can be further improved by setting a different security code for each data, for example.

(Second Embodiment)
FIG. 7 is a schematic diagram showing a configuration of an LSI device according to the second embodiment of the present invention. FIG. 8 is a schematic diagram showing a configuration of a nonvolatile memory device included in the LSI device. Substantially the same parts are denoted by the same reference numerals and detailed description thereof is omitted, and different parts are mainly described here. In the following embodiments, the same description is omitted.

  That is, the second embodiment is a modification of the first embodiment, and has a form in which the physical head address agitated according to the system code is held in the address memory 21a.

  Accordingly, the address conversion unit 20a includes an address memory 21a, a control unit 24a, a code corresponding wiring pattern memory 26, and a wiring unit 27 instead of the address memory 21 and the control unit 24, as compared with the address conversion unit 20 described above. It becomes the composition.

  Here, the address memory 21a is a memory that is readable / writable from the control unit 24a via the wiring unit 27 and stores a replacement physical head address obtained by replacing each part of the physical head address. .

  The code corresponding wiring pattern memory 26 is readable / writable from the control unit 24a, and stores the wiring pattern information of the wiring unit 27 for each system code.

  Here, the wiring pattern information is information for designating a wiring pattern in which the address line on the control unit 24a side and the address line on the address memory 21a side are different from each other. In the example shown in FIG. 8, a wiring pattern is designated in which the address line on the control unit 24a side is A0 and the address line on the address memory 21a side is A15. However, the wiring pattern information is not limited to this, and any wiring pattern can be specified as long as the address line on the control unit 24a side and the address line on the address memory 21a side are different from each other. Such wiring pattern information is the same in other embodiments.

  The wiring unit 27 includes an address line wiring pattern between the control unit 24a and the address memory 21a, and a switching unit that can switch the wiring pattern based on a switching signal input from the control unit 24a. This is for transmitting to the address memory 21a a replacement physical head address obtained by replacing each part of the physical head address sent from the section 24a onto the wiring pattern by the switching section. Here, for example, a multiplexer can be used as the switching unit.

  When a system code is input from the CPU 1 via the dedicated line 5, the control unit 24 a routes a switching signal corresponding to the wiring pattern information read from the code corresponding wiring pattern memory 26 based on the input system code. The physical head address is determined based on the security code in the security code storage memory 22 and is input to the switching unit of the unit 27 via the wiring unit 27 to which the switching signal is input. A function of writing to the address memory 21a as a replacement physical head address, a security code, a logical address and a read / write command inputted from the CPU 1 via the buses 3, 2, 4 and a special line 5 inputted from the CPU 1 A function that accepts system codes and the entered security codes If the security code matches the function sent to the unit 25 and the comparison by the code comparison unit 25, the switching corresponding to the wiring pattern information read from the code corresponding wiring pattern memory 26 is performed based on the input system code. A first physical address reading function that inputs a signal to the switching unit of the wiring unit 27 and reads the replacement physical head address in the address memory 21a as a physical head address via the wiring unit 27 to which the switching signal is input; Based on the physical address read by the first physical address reading function and the logical address input from the CPU 1, the result of the comparison by the first physical address calculating function for calculating the physical address and the code comparison unit 25, If they do not match, the address memory 21 is not connected via the wiring unit 27 without inputting a switching signal. Based on the second physical address reading function for reading the replacement physical head address from the second physical address, the replacement physical head address read by the second physical address reading function, and the logical address input from the CPU 1 A second physical address calculation function to be calculated; and a function to send the physical address calculated by the first or second physical address calculation function and the read / write command input from the CPU 1 to the flash memory unit 10. .

  Next, the operation of the LSI device including the nonvolatile memory device configured as described above will be described in the order of initialization and read / write using the flowcharts of FIGS.

(At initialization)
The CPU 1 inputs a code setting command and a security code to the nonvolatile memory device 100 via the buses 4 and 3.

  In the nonvolatile memory device 100, the security code setting unit 23 writes the security code *** in the security code storage memory 22 based on the input code setting command and the security code ***. A security code is set (ST21). Further, the security code setting unit 23 notifies the control unit 24a that the security code has been written.

  When the system code #### is input from the CPU 1 via the dedicated line 5, the control unit 24a reads the wiring pattern read from the code corresponding wiring pattern memory 26 based on the input system code ####. A switching signal corresponding to the information is input to the switching unit of the wiring unit 27 (ST22), and the physical head address *** is determined based on the security code *** in the security code storage memory 22, and the determination is made. The physical start address *** is written in the address memory 21a as the replacement physical start address □□□□ via the wiring unit 27 to which the switching signal is input (ST23).

  Thereby, the operation at the time of initialization is completed.

(When reading / writing)
The CPU 1 inputs the security code ***, the logical address XXX, and the read / write command to the nonvolatile memory device 100 via the buses 3, 2, and 4. In the case of a read command or a write command, the CPU 1 sends write data to the data bus 3 at a timing in accordance with step ST37 described later. Further, the CPU 1 inputs the system code #### into the nonvolatile memory device 100 via the dedicated line 5.

  In the nonvolatile memory device 100, when the control unit 24a receives the input security code ***, system code ####, logical address XXX, and read / write command (ST31), The input security code *** is sent to the code comparison unit 25.

  The code comparison unit 25 compares the security code *** with the security code *** in the security code storage memory 22 (ST32), and sends the comparison result to the control unit 24a.

  As a result of the comparison by the code comparison unit 25, the control unit 24a adds the wiring pattern information read from the code corresponding wiring pattern memory 26 based on the system code #### input from the CPU 1 when the two security codes match. A corresponding switching signal is input to the switching unit of the wiring unit 27, and the replacement physical start address □□□□ in the address memory 21a is input to the physical start address *** through the wiring unit 27 to which the switching signal is input. (ST33).

  Further, the control unit 24a corrects the physical address *** (= ***) based on the physical head address *** read out in step ST33 and the logical address OOXXX input from the CPU 1. * + ○○○○) is calculated (ST34).

  On the other hand, if the result of comparison in step ST32 is that they do not match, the control unit 24a reads the replacement physical head address □□□□ from the address memory 21a via the wiring unit 27 without inputting a switching signal ( ST35).

  Further, the control unit 24a, based on the replacement physical head address □□□□ read out in step ST35 and the logical address OOXX input from the CPU 1, is a bogus physical address XXXXXX (= □□□□ + ○○○○) is calculated (ST36).

  Thereafter, the control unit 24a sends the correct physical address *** calculated in step ST34 or the fake physical address XXX calculated in step ST36 and the input read / write command to the flash memory unit 10. (ST37).

  When the correct physical address *** is sent, the flash memory unit 10 reads / writes data △△△△ corresponding to the correct physical address *** based on the read / write command. .

  On the other hand, when a fake physical address XXX is sent, the flash memory unit 10 generates data corresponding to the fake physical address XXX (correct physical address *** based on the read / write command). (Data not corresponding to *) is read / written.

  As described above, according to the present embodiment, as in the first embodiment, it is possible to extend the life while preventing unauthorized copying.

  Further, if the CPU 1 does not input the correct system code in addition to the correct security code input, the control unit 24a cannot calculate the correct physical address, so that unauthorized copying can be prevented more reliably than in the first embodiment. Can do.

(Third embodiment)
FIG. 11 is a schematic diagram showing a configuration of a nonvolatile memory device according to the third embodiment of the present invention, and this nonvolatile memory device is provided in an LSI device as shown in FIG.

  The third embodiment is a modification of the first embodiment, and has a form in which a physical address corresponding to a logical address is held in the address memory 21b.

  Accordingly, the address conversion unit 20b includes an address memory 21b and a control unit 24b instead of the address memory 21 and the control unit 24, as compared with the address conversion unit 20 described above.

  Here, the address memory 21b is a memory that can be read / written from the control unit 24b and stores a physical address in association with a logical address.

  The control unit 24b determines a physical address based on the security code in the security code storage memory 22, and writes the address to the address memory 21b so as to associate the determined physical address with a logical address having a value different from the physical address. If the security code, the logical address and the read / write command input from the CPU 1 via the buses 3, 2, and 4 are matched with the security code as a result of the comparison by the code comparison unit 25, the input A function of sending the read logical address to the address memory 21b and reading the physical address from the address memory 21b, a function of sending the read physical address and the input read / write command to the flash memory unit 10, and a code As a result of comparison by the comparison unit 25, both security If Ikodo is a mismatch, it has the address of the logical address or false that is the input, and a function of sending out the read / write command to the flash memory section 10.

  Next, the operation of the LSI device including the nonvolatile memory device configured as described above will be described in the order of initialization and read / write using the flowcharts of FIGS.

(At initialization)
The CPU 1 inputs a code setting command and a security code to the nonvolatile memory device 100 via the buses 4 and 3.

  In the nonvolatile memory device 100, the security code setting unit 23 writes the security code *** in the security code storage memory 22 based on the input code setting command and the security code ***. A security code is set (ST41). In addition, the security code setting unit 23 notifies the control unit 24b that the security code has been written.

  The control unit 24b determines the physical address *** based on the security code *** in the security code storage memory 22, and writes the determined physical address *** in the address memory 21b (ST42).

  Thereby, the operation at the time of initialization is completed.

(When reading / writing)
The CPU 1 inputs the security code ***, the logical address XXX, and the read / write command to the nonvolatile memory device 100 via the buses 3, 2, and 4. In the case of a read command or a write command, the CPU 1 sends write data to the data bus 3 at a timing in accordance with step ST54 or ST55 described later.

  In the non-volatile memory device 100, when the control unit 24b receives the input security code ***, logical address XXX, and read / write command (ST51), the input security code * *** is sent to the code comparison unit 25.

  The code comparison unit 25 compares this security code *** with the security code *** in the security code storage memory 22 (ST52), and sends the comparison result to the control unit 24b.

  If the two security codes match as a result of the comparison by the code comparison unit 25, the control unit 24b sends the input logical address OOXX to the address memory 21b and the correct physical address ** from the address memory 21b. ** is read (ST53).

  Thereafter, the control unit 24b sends the correct physical address *** and the input read / write command to the flash memory unit 10 (ST54).

  In the flash memory unit 10, data ΔΔΔΔ corresponding to the correct physical address *** is read / written based on the read / write command.

  On the other hand, as a result of the comparison by the code comparison unit 25, if the two security codes do not match, the control unit 24b sends the logical address xxx or false address inputted from the CPU 1 and the read / write command to the flash memory. The data is sent to the unit 10 (ST55).

  In the flash memory unit 10, data corresponding to the logical address XXX or a false address (data not corresponding to the correct physical address ***) is read / written based on the read / write command.

  As described above, according to the present embodiment, as in the first embodiment, it is possible to extend the life while preventing unauthorized copying.

  In addition to this, the input logical address and the physical address in the flash memory unit 10 can be made different according to the association in the address memory 21b. The randomness of the data array can be improved and the writing frequency can be made uniform.

(Fourth embodiment)
FIG. 14 is a schematic diagram showing a configuration of a nonvolatile memory device according to the fourth embodiment of the present invention, and this nonvolatile memory device is provided in an LSI device as shown in FIG.

  The fourth embodiment is a combination example of the second and third embodiments. The logical address agitated according to the system code is held in the address memory 21c, and the physical address corresponding to the logical address is stored in the address memory 21c. It is a form to hold.

  Accordingly, the address conversion unit 20c includes an address memory 21c and a control unit 24c instead of the address memory 21a and the control unit 24a, and is connected to the address memory 21c, as compared with the address conversion unit 20a described above. The wiring part 27c is provided.

  Here, the address memory 21c is readable / writable from the control unit 24c via the wiring unit 27c, and stores a physical address in association with a replacement logical address obtained by replacing each part of the logical address. It is memory.

  The wiring unit 27c includes an address line wiring pattern between the control unit 24c and the address memory 21c, and a switching unit capable of switching the wiring pattern based on a switching signal input from the control unit 24c. This is for transmitting to the address memory 21c a replacement logical address obtained by replacing each part of the logical address sent from the unit 24c onto the wiring pattern by the switching unit. Here, for example, a multiplexer can be used as the switching unit.

  The control unit 24c determines a physical address based on the security code in the security code storage memory 22 and writes the address to the address memory 21c so as to associate the determined physical address with the replacement logical address. 2 and 4, a function for receiving a security code, a logical address and a read / write command input from the CPU 1 and a system code input from the CPU 1 via the dedicated line 5, and the input security code as a code comparison unit 25. If the security code matches as a result of the comparison by the code comparison unit 25 and the function transmitted to the network, a switching signal corresponding to the wiring pattern information read from the code corresponding wiring pattern memory 26 is generated based on the input system code. Input to the switching part of the wiring part 27c and CP A first physical address reading function that sends the logical address input from 1 to the address memory 21c as a replacement logical address via the wiring unit 27c to which the switching signal is input and reads the physical address from the address memory 21c; As a result of the comparison by the code comparison unit 25, if the two security codes do not match, the input logical address is sent from the wiring unit 27c to the address memory 21c without inputting the switching signal, and is physically transmitted from the address memory 21c. A second physical address reading function for reading an address; and a function for sending a physical address read by the first or second physical address reading function and an input read / write command to the flash memory unit 10. .

  Next, the operation of the LSI device including the nonvolatile memory device configured as described above will be described in the order of initialization and read / write using the flowcharts of FIGS.

(At initialization)
The CPU 1 inputs a code setting command and a security code to the nonvolatile memory device 100 via the buses 4 and 3.

  In the nonvolatile memory device 100, the security code setting unit 23 writes the security code *** in the security code storage memory 22 based on the input code setting command and the security code ***. Then, a security code is set (ST61). Further, the security code setting unit 23 notifies the control unit 24a that the security code has been written.

  When the system code #### is input from the CPU 1 via the dedicated line 5, the control unit 24a reads the wiring pattern read from the code corresponding wiring pattern memory 26 based on the input system code ####. A switching signal corresponding to the information is input to the switching unit of the wiring unit 27c (ST62), and the physical address *** is determined based on the security code *** in the security code storage memory 22, and the determination is made. The physical address *** is written to the address memory 21c in association with the replacement logical address □□□□ via the wiring unit 27c to which the switching signal is input (ST63).

  Thereby, the operation at the time of initialization is completed.

(When reading / writing)
The CPU 1 inputs the security code ***, the logical address XXX, and the read / write command to the nonvolatile memory device 100 via the buses 3, 2, and 4. In the case of a read command or a write command, the CPU 1 sends write data to the data bus 3 at a timing in accordance with step ST75 described later. Further, the CPU 1 inputs the system code #### into the nonvolatile memory device 100 via the dedicated line 5.

  In the non-volatile memory device 100, when the control unit 24c receives the input security code ***, system code ####, logical address XXX and read / write command (ST71), The input security code *** is sent to the code comparison unit 25.

  The code comparison unit 25 compares this security code *** with the security code *** in the security code storage memory 22 (ST72), and sends the comparison result to the control unit 24c.

  As a result of the comparison by the code comparison unit 25, the control unit 24 c adds the wiring pattern information read from the code corresponding wiring pattern memory 26 based on the system code #### input from the CPU 1 when the two security codes match. A corresponding switching signal is input to the switching unit of the wiring unit 27c, and the logical address OOXX input from the CPU 1 is set as a replacement logical address □□□□ through the wiring unit 27c to which the switching signal is input. The correct physical address *** is read out from the address memory 21c by sending it to the address memory 21c (ST73).

  On the other hand, if the result of comparison in step ST72 is that they do not match, the control unit 24a sends the input logical address OOXX from the wiring unit 27c to the address memory 21c without inputting a switching signal. A fake physical address xxx is read from the address memory 21c (ST74).

  Thereafter, the control unit 24a sends the correct physical address *** read out in step ST73 or the fake physical address XXX read out in step ST74 and the inputted read / write command to the flash memory unit 10. (ST75).

  When the correct physical address *** is sent, the flash memory unit 10 reads / writes data △△△△ corresponding to the correct physical address *** based on the read / write command. .

  On the other hand, when a fake physical address XXX is sent, the flash memory unit 10 generates data corresponding to the fake physical address XXX (correct physical address *** based on the read / write command). (Data not corresponding to *) is read / written.

  As described above, according to the present embodiment, as in the second and third embodiments, it is possible to extend the life while preventing unauthorized copying more reliably.

  For example, in addition to the correct security code input, if the CPU 1 does not input the correct system code, the control unit 24c cannot read out the correct physical address from the memory address 21c, which is more reliable than the third embodiment. Copying can be prevented.

  Note that the method described in the above embodiment includes a magnetic disk (floppy (registered trademark) disk, hard disk, etc.), an optical disk (CD-ROM, DVD, etc.), a magneto-optical disk (MO) as programs that can be executed by a computer. ), And can be distributed in a storage medium such as a semiconductor memory.

  Further, the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Moreover, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

1 is a schematic diagram showing a configuration of an LSI device according to a first embodiment of the present invention. It is a schematic diagram which shows the structure of the non-volatile memory device in the same embodiment. It is a flowchart for demonstrating the operation | movement at the time of initialization in the embodiment. 3 is a flowchart for explaining an operation at the time of reading / writing in the embodiment. It is a schematic diagram for demonstrating the relationship between the logical space and physical space in a prior art. It is a schematic diagram for demonstrating the relationship between the logical space and physical space in the embodiment. It is a schematic diagram which shows the structure of the LSI apparatus which concerns on the 2nd Embodiment of this invention. It is a schematic diagram which shows the structure of the non-volatile memory device in the same embodiment. It is a flowchart for demonstrating the operation | movement at the time of initialization in the embodiment. 3 is a flowchart for explaining an operation at the time of reading / writing in the embodiment. It is a schematic diagram which shows the structure of the non-volatile memory device which concerns on the 3rd Embodiment of this invention. It is a flowchart for demonstrating the operation | movement at the time of initialization in the embodiment. 3 is a flowchart for explaining an operation at the time of reading / writing in the embodiment. It is a schematic diagram which shows the structure of the non-volatile memory device which concerns on the 4th Embodiment of this invention. It is a flowchart for demonstrating the operation | movement at the time of initialization in the embodiment. 3 is a flowchart for explaining an operation at the time of reading / writing in the embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... CPU, 2 ... Address bus, 3 ... Data bus, 4 ... Control bus, 5 ... Dedicated line, 10 ... Flash memory part, 20, 20a, 20b, 20c ... Address conversion part, 21, 21a, 21b, 21c ... Address memory, 22... Security code storage memory, 23... Security code setting unit, 24, 24 a, 24 b, 24 c... Control unit, 25... Code comparison unit, 26. ... Non-volatile memory device.

Claims (5)

A non-volatile memory device including a readable / writable memory unit that holds data corresponding to a physical address,
Address storage means for storing a physical head address;
Security code storage means for storing the security code;
When a code setting instruction and a security code are input, means for writing the security code in the security code storage means;
Means for determining the physical head address based on a security code in the security code storage means, and writing the determined physical head address in the address storage means;
Means for receiving the input security code, logical address and read / write command;
Means for comparing the input security code with a security code in the security code storage means;
As a result of the comparison, if both match, a means for calculating a physical address based on the input logical address and the physical head address in the address storage means;
Means for sending the calculated physical address and the inputted read / write command to the memory unit;
If the result of the comparison is that they do not match, means for sending the input logical address or false address and the read / write command to the memory unit;
A non-volatile memory device comprising: A non-volatile memory device including a readable / writable memory unit that holds data corresponding to a physical address,
Address storage means for storing a replacement physical head address obtained by replacing each part of the physical head address;
Wiring pattern storage means for storing wiring pattern information for each system code;
A switching unit capable of switching a wiring pattern based on an input switching signal, and a replacement physical head address obtained by replacing each part of a physical head address sent on the wiring pattern by the switching unit; Wiring means for transmitting to the address storage means;
Security code storage means for storing the security code;
When a code setting instruction and a security code are input, means for writing the security code in the security code storage means;
When the system code is input, based on the input system code, a switching signal corresponding to the wiring pattern information read from the wiring pattern storage unit is input to the switching unit, and in the security code storage unit Means for determining a physical head address based on a security code, and writing the determined physical head address into the address storage means as the replacement physical head address via the wiring means to which the switching signal is input;
Means for receiving the input security code, system code, logical address and read / write command;
Means for comparing the input security code with a security code in the security code storage means;
As a result of the comparison, if both match, based on the input system code, a switching signal corresponding to the wiring pattern information read from the wiring pattern storage means is input to the switching unit, and the switching signal is First physical address reading means for reading out the replacement physical head address in the address storage means as a physical head address via the input wiring means;
First physical address calculating means for calculating a physical address based on the physical address read by the first physical address reading means and the input logical address;
If the result of the comparison is that they do not match, the second physical address reading means for reading the replacement physical head address from the address storage means via the wiring means without inputting the switching signal;
Second physical address calculating means for calculating a physical address based on the replacement physical head address read by the second physical address reading means and the input logical address;
Means for sending the physical address calculated by the first or second physical address calculation means and the inputted read / write command to the memory unit;
A non-volatile memory device comprising: A non-volatile memory device including a readable / writable memory unit that holds data corresponding to a physical address,
Address storage means for storing a physical address in association with a logical address;
Security code storage means for storing the security code;
When a code setting instruction and a security code are input, means for writing the security code in the security code storage means;
Means for determining a physical address based on a security code in the security code storage means, and writing the address to the address storage means so as to associate the determined physical address with a logical address having a value different from the physical address;
Means for receiving the input security code, logical address and read / write command;
Means for comparing the input security code with a security code in the security code storage means;
As a result of the comparison, if the two match, means for sending the input logical address to the address storage means and reading the physical address from the address storage means;
Means for sending the read physical address and the inputted read / write command to the memory unit;
If the result of the comparison is that they do not match, means for sending the input logical address or false address and the read / write command to the memory unit;
A non-volatile memory device comprising: A non-volatile memory device including a readable / writable memory unit that holds data corresponding to a physical address,
Address storage means for associating and storing a physical address with a replacement logical address in which each part of the logical address is replaced;
Wiring pattern storage means for storing wiring pattern information for each system code;
A switching unit that can switch a wiring pattern based on a switching signal that is input, and a logical address to be replaced in which each part of a logical address sent on the wiring pattern is replaced by the switching unit is stored in the address Wiring means for transmitting to the means;
Security code storage means for storing the security code;
When a code setting instruction and a security code are input, means for writing the security code in the security code storage means;
Means for determining a physical address based on a security code in the security code storage means, and writing the address to the address storage means so as to associate the determined physical address with a replacement logical address;
Means for receiving the input security code, system code, logical address and read / write command;
Means for comparing the input security code with a security code in the security code storage means;
As a result of this comparison, when both match, based on the input system code, a switching signal corresponding to the wiring pattern information read from the wiring pattern storage means is input to the switching unit and the input First physical address reading means for sending a logical address to the address storage means as a replacement logical address via the wiring means to which the switching signal is input, and reading the physical address from the address storage means;
As a result of the comparison, if they do not match, the second logical address is read out from the wiring means to the address storage means without inputting the switching signal, and the physical address is read out from the address storage means. Physical address reading means;
Means for sending the physical address read by the first or second physical address reading means and the inputted read / write command to the memory unit;
A non-volatile memory device comprising:   An LSI device comprising the nonvolatile memory device according to claim 1.

Images