JP5111205B2 - REFLECTIVE MASK, ITS INSPECTION METHOD, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - Google Patents

Description

  The present invention is suitable for, for example, EUV (Extreme Ultra Violet) lithography, and in particular, a reflective mask suitable for so-called off-telecentric exposure, a method in which exposure light is incident obliquely on the mask surface, and an inspection method thereof The present invention also relates to a method for manufacturing a semiconductor device.

  In the process of manufacturing a semiconductor device such as a semiconductor integrated circuit, a lithography technique is used as a method for transferring a fine pattern onto a substrate. This lithography technique mainly uses a projection exposure apparatus, and pattern transfer is performed by irradiating the resist on the substrate with exposure light transmitted through a photomask mounted on the projection exposure apparatus.

  In recent years, higher integration of devices and higher device operating speeds have been demanded, and in order to meet these demands, pattern miniaturization has been promoted. In order to respond to this demand for miniaturization, efforts have been made to improve the resolution of projected images by shortening the exposure wavelength, and recently, EUV (Extremely 13.5 nm wavelength shorter than conventional ultraviolet rays by one digit or more). An exposure method using Ultra Violet Light) is also being studied. Also, due to demands from lens aberration, angle of view, etc., as a state-of-the-art exposure method including the EUV exposure method, a scanner method that performs exposure by scanning an arc-shaped exposure region instead of the stepper method is the mainstream. It is used as.

  In EUV lithography, exposure is performed by an optical system called an off-telecentric optical system. Such off-telecentric exposure is a method in which exposure to a mask or wafer is performed with a light beam that is not perpendicular to the surface but slightly inclined with respect to the surface normal, and is employed in the configuration of an optical system off the central axis.

  FIG. 3 is a schematic block diagram showing an example of a typical EUV exposure apparatus. This EUV exposure apparatus includes an EUV light source 100 that supplies exposure light 101, a reflection optical system 102, a mask stage 103a for mounting a multilayer film reflection mask 103, an optical system box 104 that houses the optical system, and a reflection. The projection optical system 105 and the wafer stage 106 a for mounting the wafer 106 are included.

  The exposure light 101 supplied from the EUV light source 100 to the optical system box 104 is redirected by the reflection optical system 102 and irradiated to the multilayer reflective mask 103. In the multilayer reflective mask 103, an EUV reflective film made of a multilayer film such as Mo / Si is formed on a low thermal expansion material called synthetic quartz or LTEM, and an absorber pattern made of a material such as TaBN is formed thereon. Is formed.

  The EUV light irradiated to the multilayer reflective mask 103 is irradiated to the wafer 106 via a reflective projection optical system 105 composed of a plurality of multilayer mirrors. The pattern on the reflective mask 103 is imaged on the wafer 106 by this EUV exposure. An exposure optical system including the reflection optical system 102, the multilayer film reflection mask 103, and the reflection projection optical system 105 is surrounded by an optical system box 104, and the inside thereof is evacuated to a particularly high degree of vacuum compared to the surroundings. ing. This protects the optical system from contamination. An opening through which exposure light to the wafer 106 passes is provided on the wafer side of the optical system box 104.

  The configuration of the optical system employs an optical system with a central axis removed in order to prevent vignetting caused by the reflecting mirror, and this is to obtain the widest possible exposure field when all are configured by the reflecting optical system. It is a device. Therefore, the exposure light 101 is incident obliquely so that the incident angle α with respect to the surface normal of the mask 103 is about 5 ° to 6 °. Further, the exposure light 112 emitted from the reflection projection optical system 105 is incident on the surface normal of the wafer 106 at an incident angle slightly inclined to form an image.

  Scan exposure is used as the EUV exposure method. The exposure light 101 supplied from the EUV light source 100 is reflected by the reflection optical system 102 and enters the reflection mask 103 obliquely. The exposure light reflected from the reflective mask 103 is spatially modulated in accordance with the shape of the absorber pattern, and subsequently imaged on the wafer 106 via the reflective projection optical system 105. In this state, the exposure pattern of the exposure mask 103 can be projected onto the wafer 106 by performing synchronous scanning of the mask stage 103a and the wafer stage 106a.

  As shown in FIG. 4, in the scan exposure, the resist applied on the entire surface of the wafer 106 is exposed by continuously scanning the chip shot area 10 corresponding to the mask exposure area along the scan direction 12. The chip shot area 10 corresponds to a shot size in stepper exposure, and one chip shot area 10 may correspond to a single chip area or may include a plurality of chip areas.

  In the case of the scan exposure, the chip shot area 10 is not exposed in one shot as in the stepper exposure, but continuously forms an elongated arc-shaped exposure area 21 symmetrical with respect to the scan direction 12 as shown in FIG. The reflective mask 103 is irradiated while being relatively moved. On the other hand, exposure is performed on the wafer 106 while continuously moving the arc-shaped exposure area imaged via the reflective projection optical system 105 continuously.

  At this time, in the off-telecentric optical system having the off-center projection optical system configuration as described above, the exposure light is obliquely incident on the mask surface. There is a problem that changes.

  As shown in FIG. 5, attention is paid to, for example, three separated positions 22 a, 22 b and 22 c on the same axis perpendicular to the scanning direction 12 within the arc area 21. The position 22b is at the center of symmetry of the exposure area 21, and the positions 22a and 22c are separated from the position 22b by a predetermined distance from side to side. When the same absorber pattern is disposed at these positions 22a to 22c and scanning exposure is performed, the pattern transferred to the wafer undergoes shape deformation as indicated by reference numerals 23a to 23c. With the shape 23b corresponding to the absorber pattern at the position 22 as a reference, the deformation increases as the shapes 23a and 23c increase from the center. When such deformation occurs, various problems occur. An example is shown in FIG.

  FIG. 6 shows a circuit pattern on a wafer formed by lithography. Reference numeral 201 is a gate and gate wiring generally called poly, reference numeral 202 is a diffusion layer (active layer), and reference numeral 203 is a contact (conduction layer). Indicates. FIG. 6A shows a case where the gate and gate wiring 201 have a desired pattern shape, and FIG. 6B shows a modified gate and gate wiring 201 ′.

  As a part of the pattern is obliquely cut off, the gate wiring 201 ′ and a part of the contact 203 are stepped off in the region 210, thereby causing problems such as increased contact resistance, poor contact, or process damage to the lower part of the gate. appear. Further, in the region 211, the end portion of the gate wiring 201 ′ is cut and contracted, so that an overhang with the diffusion layer 202 is reduced and the transistor characteristics are deteriorated.

  FIG. 7A is a graph showing the relationship between the distance from the center of the exposure area and the deformation amount, where the vertical axis is the position shift amount (nm) and the horizontal axis is the azimuth angle θ (°). FIG. 7B is an explanatory diagram showing the definition of the azimuth angle θ. 7B, the surface of the mask 103 is the XY plane, the normal direction is the Z direction, and the exposure light 101 is incident obliquely with respect to the mask surface at an incident angle α, and the Y axis is the symmetric center line. An arcuate exposure area 21 is formed. At this time, the angle formed by the straight line passing through the origin O and the position in the exposure area and the X axis can be defined as the azimuth angle θ.

  In the graph of FIG. 7A, the azimuth angle θ = 90 ° corresponds to the center position of the exposure area 21. At this time, the X position shift is 0 nm and the Y position shift is about −4 nm. On the other hand, at the position where the azimuth angle θ = 60 °, the X position shift is about 2.7 nm and the Y position shift is about -3 nm. At the position where the azimuth angle θ is 120 °, the X position shift is about −2.6 nm and the Y position shift is about −3 nm. Thus, it can be seen that the position shift amount in the Y direction does not vary much due to the oblique incidence of the exposure light, but the position shift amount in the X direction changes greatly linearly.

  In order to solve this deformation problem, a method has been proposed in which a mask pattern is deformed and corrected for each pattern arrangement position (Non-Patent Document 1). In this method, as shown in FIG. 8, even if the mask pattern is the same, the corner shape is slightly corrected according to the positions 22a, 22b, and 22c on the mask, for example, mask patterns 24a, 24b, and 24c. As shown in FIG. By such shape correction, the transfer pattern on the wafer can be obtained with the same transfer pattern as shown by reference numerals 25a, 25b, and 25c in FIG. 9, and shape deformation caused by oblique incidence can be prevented. can do.

A. M. Goethals et al., "EUV lithography program at IMEC", Proc. Of SPIE, Vol. 6517, (2007), pp. 651707-1-12

  In such a conventional method, even if the mask pattern is the same, the mask pattern shape is locally different because correction for preventing shape deformation is performed according to the position in the exposure area. This makes it difficult to perform so-called die-to-die inspection, which compares the same patterns on the layout and inspects the mask pattern for defects. Therefore, a so-called die-to-data inspection that compares the actual pattern on the layout with the design data is necessary as an alternative to the die-to-die inspection.

  In die-to-data inspection, the data volume is enormous, and the processing time for data transfer and data comparison processing increases by orders of magnitude compared to die-to-die inspection. Therefore, the mask inspection time, TAT (turn around time), mask inspection system cost This is difficult to implement. Further, in the die-to-die inspection, error factors such as the aberration of the optical system and the influence of the resist are reflected in both the comparison patterns, so that high-sensitivity inspection based on the difference can be performed. On the other hand, since the die-to-data inspection is a comparison between the pattern image simulated using the layout pattern data and the pattern image obtained by imaging, it is difficult to separate the various error factors and to increase the inspection sensitivity. There's a problem.

  Due to these problems, the die-to-data inspection is not suitable in terms of mask inspection TAT and inspection sensitivity, and the yield is likely to decrease. If shape correction according to the azimuth angle of the exposure light is not performed, the shape of the transfer pattern is deformed and the position is shifted, and the problem of yield reduction occurs. In particular, the problem of mask inspection TAT is an important problem in a logic device, SoC (System On Chip), which has a small variety and a short product cycle.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a reflective mask capable of performing mask inspection by pattern comparison on a layout and a method for inspecting the same in a system in which exposure light is obliquely incident on a mask to perform scan exposure.

  Another object of the present invention is to provide a method of manufacturing a semiconductor device using such a reflective mask.

According to one embodiment of the present invention, a mask on which a desired pattern is formed is irradiated with exposure light obliquely incident on the mask surface in a predetermined exposure area, and the light reflected on the mask surface is irradiated on the wafer. In a reflective mask for transferring a desired pattern onto a wafer by performing projection exposure and scanning exposure ,
In order to correct the transfer shape caused by the oblique incident light, the shape of the pattern on the mask is corrected according to the distance from the mask center line based on the mask center line along the same direction as the scan direction of the scan exposure. Is given,
Further, a plurality of chips comprising mask pattern groups are arranged on the mask, the chips are arranged with two or more different kinds of chips together with two or more kinds of similar chips, and the same kind of chips are arranged as described above. They are arranged in the same direction along the scanning direction.

  According to another embodiment of the present invention, the reflective mask inspection method includes a step of performing a mask inspection by comparing chip regions including the same mask pattern arranged along the scanning direction. Including.

  According to this embodiment, a plurality of chip regions including the same mask pattern are present along the scanning direction, so that it is possible to perform mask inspection by pattern comparison on the layout, so-called die-to-die inspection. . Therefore, the mask inspection TAT and the inspection sensitivity can be improved, and the product yield can be improved.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof may be simplified or omitted.

Embodiment 1 FIG.
FIG. 1 is a plan view showing an example of a chip layout of a reflective mask according to the present invention. In the mask exposure area 10 of the reflective mask, a plurality of (six in the example of FIG. 1) rectangular chip regions 11a to 11f including the same layout pattern are arranged. Among them, the two chip regions 11 a and 11 b are arranged so that the longitudinal direction of the rectangle is parallel to the scanning direction 12 and aligned along the scanning direction 12. On the other hand, the four chip regions 11c to 11f are arranged so that the longitudinal direction of the rectangle is perpendicular to the scanning direction 12 and is aligned along the scanning direction 12, respectively. By arranging the chip regions in this way, mask patterns to be subjected to mask defect inspection are arranged along the scanning direction 12.

  Here, as described with reference to FIG. 8, when shape correction is performed according to the distance (azimuth angle θ) from the center line of the exposure area 21 for the purpose of reducing an error caused by oblique incidence of exposure light, 2 Since the chip regions 11a and 11b have the same distance (azimuth angle θ) from the center line of the exposure area 21, the mask patterns after shape correction are the same. On the other hand, since the distance (azimuth angle θ) from the center line of the exposure area 21 is also the same for the four chip regions 11c to 11f, the mask patterns after shape correction are the same.

  Therefore, when performing the so-called die-to-die inspection, in which the same pattern is compared with each other on the layout and the so-called die-to-die inspection is performed, the two chip regions 11a and 11b have the same mask pattern after shape correction. Pattern comparison can be performed between the two. Since the four chip regions 11c to 11f have the same mask pattern after shape correction, any two chip regions can be selected and pattern comparison can be performed.

  FIG. 2 is a plan view showing another example of the chip layout of the reflective mask according to the present invention. A plurality of (six in the example of FIG. 2) rectangular chip regions 11a to 11f including the same layout pattern are arranged in the mask exposure area 10 of the reflective mask. The six chip regions 11 a to 11 f are arranged in a matrix so that the longitudinal direction of the rectangle is parallel to the scan direction 12 and aligned along the scan direction 12. The same mask pattern is formed in the same locations 13a to 13f in the chip regions 11a to 11f in terms of layout design.

  Here, as described with reference to FIG. 8, when shape correction is performed according to the distance (azimuth angle θ) from the center line of the exposure area 21 for the purpose of reducing an error caused by oblique incidence of exposure light, The mask patterns at 13a to 13f are different. However, since the mask patterns at the locations 13a and 13d have the same distance (azimuth angle θ) from the center line of the exposure area 21, the mask patterns after shape correction are the same. Similarly, since the mask patterns at the locations 13b and 13e have the same distance (azimuth angle θ) from the center line of the exposure area 21, the mask patterns after shape correction are the same. Since the mask patterns at the places 13c and 13f have the same distance (azimuth angle θ) from the center line of the exposure area 21, the mask patterns after shape correction are the same.

  Therefore, in the case of performing so-called die-to-die inspection, in which the same pattern is compared with each other on the layout and so-called die-to-die inspection is performed, conventionally, the comparison between the places 13a-13b or the place 13b- where the pattern interval is narrow and the comparison inspection is easy. 13c was compared. However, when shape correction according to the distance (azimuth angle θ) from the center line of the exposure area 21 is performed, the mask pattern is different, so that die-to-die inspection is difficult or impossible.

  In the present invention, since chip regions including the same mask pattern are arranged along the scanning direction 12, even after shape correction, the comparison of the places 13a-13d, the comparison of the places 13b-13e, or A comparison of locations 13c-13f can be performed.

  When designing the arrangement of a plurality of chip areas including the same layout pattern, whether the chip arrangement of FIG. 1 or the chip arrangement of FIG. 2 is adopted takes into consideration the size of the chip and the size of the mask exposure area. The determination may be made based on the arrangement efficiency. That is, the number of chips stored in the mask exposure area or the size of the mask exposure area for accommodating the same number of chips may be determined.

  The reflective mask thus obtained is placed on the mask stage 103a of the EUV exposure apparatus in FIG. Subsequently, the exposure light 101 obliquely incident on the mask surface is irradiated on the symmetrical elongated arc-shaped exposure area 21, and the light reflected on the mask surface is projected onto the semiconductor wafer to perform scan exposure. By repeatedly applying such EUV lithography, a semiconductor device such as an integrated circuit can be manufactured.

  As described above, in this embodiment, a plurality of chip regions including the same mask pattern exist along the scan direction, so that it is possible to perform mask inspection by pattern comparison on the layout, so-called die-to-die inspection. Become. Therefore, the mask inspection TAT and the inspection sensitivity can be improved, and the product yield can be improved.

Embodiment 2. FIG.
FIG. 10 is a plan view showing a chip layout example of a conventional reflective mask in which a plurality of types of chip regions are mixedly mounted. FIG. 11 is a plan view showing a chip layout example of a reflective mask according to the present invention in which a plurality of types of chip regions are mixedly mounted.

  First, in FIG. 10, a plurality of (three in the example of FIG. 10) rectangular first chip regions 31a to 31c including the same layout pattern are arranged in the mask exposure area 10 of the reflective mask. Further, a plurality of (seven in the example of FIG. 10) rectangular second chip regions 32a to 32g including the same mask pattern different from the first chip regions 31a to 31c are arranged.

  The three first chip regions 31 a to 31 c are arranged so that the longitudinal direction of the rectangle is parallel to the scanning direction 12 and aligned along a line orthogonal to the scanning direction 12. Of the seven second chip regions 32a to 32g, five second chip regions 32a to 32e are lines in which the longitudinal direction of the rectangle is parallel to the scan direction 12 and orthogonal to the scan direction 12 respectively. Are arranged in line. The remaining two second chip regions 32 f and 32 g are arranged so that the longitudinal direction of the rectangle is perpendicular to the scanning direction 12 and aligned along a line orthogonal to the scanning direction 12. By disposing the chip region in this way, it is possible to dispose the chip in the mask exposure area 10 with a relatively high density.

  However, as described with reference to FIG. 8, when the shape correction is performed according to the distance (azimuth angle θ) from the center line of the exposure area 21 for the purpose of reducing the error due to the oblique incidence of the exposure light, the same type Since no chip area including the same mask pattern exists in the scan direction 12 among the chip areas, die-to-die inspection is difficult or impossible. As an alternative, when a die-to-data inspection is performed, the mask inspection time is orders of magnitude longer than that of the die-to-die inspection, and the inspection sensitivity is lowered, which may miss a fatal defect.

  On the other hand, in FIG. 11, a plurality of (three in the example of FIG. 11) rectangular first chip regions 31A to 31C including the same layout pattern are arranged in the mask exposure area 10 of the reflective mask. ing. Furthermore, a plurality of (six in the example of FIG. 11) rectangular second chip regions 32A to 31F including the same mask pattern different from the first chip regions 31A to 31C are arranged.

  The three first chip regions 31 </ b> A to 31 </ b> C are arranged so that the longitudinal direction of the rectangle is perpendicular to the scanning direction 12 and aligned along the scanning direction 12. Of the six second chip regions 32A to 32F, the two second chip regions 32A and 32B are arranged along the scan direction 12 with the longitudinal direction of the rectangle parallel to the scan direction 12. Are arranged as follows. The remaining four second chip regions 32 </ b> C to 32 </ b> F are arranged in a matrix shape with the longitudinal direction of the rectangle perpendicular to the scanning direction 12.

  Here, as described with reference to FIG. 8, when shape correction is performed according to the distance (azimuth angle θ) from the center line of the exposure area 21 for the purpose of reducing an error caused by oblique incidence of exposure light, 3 Since the first chip regions 31A to 31C have the same distance (azimuth angle θ) from the center line of the exposure area 21, the mask patterns after shape correction are the same. Since the two second chip regions 32A and 32B have the same distance (azimuth angle θ) from the center line of the exposure area 21, the mask patterns after shape correction are the same. Further, since the two chip regions 32C and 32D among the four second chip regions 32C to 32F have the same distance (azimuth angle θ) from the center line of the exposure area 21, the mask pattern after the shape correction is performed. Are identical to each other. Since the remaining two chip regions 32E and 32F have the same distance (azimuth angle θ) from the center line of the exposure area 21, the mask patterns after shape correction are the same.

  Therefore, when performing a so-called die-to-die inspection in which the same pattern is compared on the layout to perform a defect inspection of the mask pattern, the three first chip regions 31A to 31C have the same mask pattern after shape correction. Therefore, a pattern comparison can be performed between the two. Further, since the mask patterns after the shape correction are the same in the two second chip regions 32A and 32B, the pattern comparison can be performed between them. Since the two chip regions 32C and 32D have the same mask pattern after shape correction, pattern comparison can be performed between them. Since the two chip regions 32E and 32F have the same mask pattern after shape correction, pattern comparison can be performed between them.

  When the layout of FIG. 10 and the layout of FIG. 11 are compared, the number of second chip regions that can be arranged in the mask exposure area 10 is reduced by one. As a countermeasure, by reducing the mask exposure area 10 to the mask exposure area 41, the number of exposure shots can be increased, and the number of chips that can be obtained from one wafer can be maintained at the same level as in the past.

  A device in which a plurality of types of chip regions are mounted in this manner is typically a SoC (logic). Since SoC needs to be developed and supplied with high-mix low-volume production, short product life, and short TAT according to demand, mask defect inspection TAT is extremely important and is a priority over chip packing density in exposure shots. There are often.

  The reflective mask thus obtained is placed on the mask stage 103a of the EUV exposure apparatus in FIG. Subsequently, the exposure light 101 obliquely incident on the mask surface is irradiated on the symmetrical elongated arc-shaped exposure area 21, and the light reflected on the mask surface is projected onto the semiconductor wafer to perform scan exposure. By repeatedly applying such EUV lithography, a semiconductor device such as an integrated circuit can be manufactured.

  As described above, in this embodiment, even in a device in which a plurality of types of chip areas are mixedly mounted, a plurality of chip areas including the same mask pattern exist along the scan direction, so that pattern comparison on the layout is possible. It is possible to perform mask inspection by so-called die-to-die inspection. Therefore, the mask inspection TAT and the inspection sensitivity can be improved, and the product yield can be improved.

  The present invention is extremely useful industrially in that a semiconductor device including a fine and highly accurate pattern can be manufactured with high production efficiency.

It is a top view which shows an example of the chip | tip layout of the reflection type mask which concerns on this invention. It is a top view which shows the other example of the chip | tip layout of the reflection type mask which concerns on this invention. It is a schematic block diagram which shows an example of a typical EUV exposure apparatus. It is a top view which shows the mode of the scanning exposure with a wafer. It is a top view which shows the mode of the scanning exposure with a reflective mask. It is a top view which shows the circuit pattern example on the wafer formed of the lithography process. FIG. 7A is a graph showing the relationship between the distance from the center of the exposure area and the amount of deformation, and FIG. 7B is an explanatory diagram showing the definition of the azimuth angle θ. It is a top view explaining an example of shape correction of a mask pattern. It is a top view which shows the example of the transfer pattern in the wafer by shape correction. It is a top view which shows the chip layout example of the conventional reflection type mask which mixedly mounted multiple types of chip area | regions. It is a top view which shows the chip | tip layout example of the reflection type mask which concerns on this invention which mixedly mounted multiple types of chip | tip area | region.

Explanation of symbols

10 chip shot areas, 11a to 11f chip areas,
13a-13f location, 21 exposure area, 22a-22c position,
23a-23c transfer pattern, 24a-24c mask pattern,
25a-25c transfer pattern,
31a to 31c, 31A to 31C first chip region,
32a to 32g, 32A to 32F second chip area, 41 mask exposure area,
100 EUV light source, 101 exposure light, 102 reflective optical system,
103 reflective mask, 104 optical box, 105 reflective projection optical system,
106 wafers, 112 exposure light,
201 diffusion layer, 202 gate wiring, 203 contact.

Claims (4)

To mask the desired pattern is formed, the exposure light obliquely incident on the mask surface is irradiated with a predetermined exposure area, by performing scanning exposure by projecting the light reflected by the mask surface on the wafer A reflective mask for transferring a desired pattern onto a wafer ,
In order to correct the transfer shape caused by the oblique incident light, the shape of the pattern on the mask is corrected according to the distance from the mask center line based on the mask center line along the same direction as the scan direction of the scan exposure. Is given,
Further, a plurality of chips comprising mask pattern groups are arranged on the mask, the chips are arranged with two or more different kinds of chips together with two or more kinds of similar chips, and the same kind of chips are arranged as described above. A reflective mask characterized by being arranged in the same direction along the scanning direction . Exposure light reflective mask according to claim 1, comprising the EUV light. A method of inspecting a reflective mask according to any one of claims 1-2,
A reflection mask inspection method comprising a step of performing a mask inspection by comparing chip regions including the same mask pattern arranged along a scanning direction. By placing a reflective mask according to a reflection type exposure apparatus in any one of claims 1-2, manufacture of a semiconductor device which comprises a step of performing scanning exposure by projecting a mask pattern on a semiconductor substrate Method.