JP5846785B2 - Projection exposure method, projection exposure apparatus, and mask pattern transfer method - Google Patents

Description

  The present invention relates to a lithography technique for forming a circuit pattern of a semiconductor device, and more particularly to a projection exposure method and projection in an exposure process using so-called extreme ultraviolet light (EUV (Extreme Ultra-Violet) light) having a wavelength of about 10 to 15 nm. The present invention relates to a technique effective when applied to an exposure apparatus.

  A semiconductor device (semiconductor integrated circuit device) irradiates a mask, which is an original on which a circuit pattern is drawn, with exposure light, and the circuit pattern is applied to the main surface of a semiconductor substrate (referred to as a wafer) via a reduction optical system. It is mass-produced by repeatedly using the photolithography process to transfer.

  In recent years, in response to demands for miniaturization of semiconductor devices, methods for increasing the resolution by shortening the exposure wavelength of photolithography have been studied. So far, ArF lithography using fluorinated Argosi (ArF) excimer laser light with a wavelength of 193 nm has been mainly developed, but in order to improve the resolving power of the optical system limited by the diffraction limit of light, excimer laser light is used. Instead, development of lithography using EUV light having a shorter wavelength (for example, 13.5 nm) is being advanced.

  In this wavelength region, a transmission mask cannot be used because of the light absorption of the substance. Therefore, a multilayer film reflective substrate using reflection by a multilayer film such as molybdenum (Mo) and silicon (Si) is a mask for EUV lithography (referred to as EUVL). Used as blanks (referred to as mask blanks). Multilayer reflection is a kind of reflection utilizing interference. The EUVL mask has an absorber pattern, that is, a buffer, as a low reflection region on the surface of a mask blank in which a multilayer film such as molybdenum (Mo) and silicon (Si) is deposited on a quartz glass or a low thermal expansion glass substrate. A pattern in which a film and an EUV light absorbing film are laminated is formed (for example, Non-Patent Document 1).

  Similarly, since an optical element for EUV light cannot use a transmission refraction type optical element, a multilayer film reflecting mirror is used. For example, as described in Japanese Patent Application Laid-Open No. 2001-244168 (Patent Document 1), the projection optical system of the EUV exposure apparatus uses a reflection type projection optical system. The light from the light source is made uniform through a reflection type illumination optical system and irradiated to the EUVL mask. The light irradiated on the EUVL mask is reflected by the EUVL mask, reaches the wafer through a reflective projection optical system, and the absorber pattern of the EUVL mask is projected onto the main surface of the wafer.

  In EUVL, even if a height abnormality of only a few nanometers occurs on the surface of the mask blank, a large phase change is caused in the EUV reflected light due to the height abnormality, and the absorber pattern is transferred onto the main surface of the wafer. In this case, defects such as a dimensional change or poor resolution are caused. A defect that gives such a phase change is called a phase defect. Therefore, it is necessary to detect the phase defect at the stage of the mask blank before depositing the absorber pattern.

  As a general mask blank inspection method, there are a method of irradiating a mask blank with a laser beam and detecting foreign matter from light that is diffusely reflected, or a method of detecting a bright field image (microscope image). On the other hand, there is an in-wavelength (at wavelength) inspection method in which a defect is detected using detection light having the same wavelength as EUV light used for exposure. As an example of this method, a method using a dark field inspection image is disclosed in, for example, Japanese Patent Application Laid-Open No. 2003-114200 (Patent Document 2). Furthermore, an inspection method for distinguishing unevenness on the surface of a phase defect is disclosed in, for example, Japanese Patent Application Laid-Open No. 2007-219130 (Patent Document 3).

JP 2001-244168 A JP 2003-114200 A JP 2007-219130 A

Isao Tabuchi, Yoichi Takehana, Morihisa Homoto, “Introductory Photomask Technology”, Industrial Research Committee, published in December 2006, p. 266-268

  In the conventional EUVL, after detecting a phase defect on the surface of the mask blank, the defect transferability is examined, and if it is determined that the defect transferability is small, the mask blank is handled as a non-defective product. Even if a critical defect is determined at the mask blank inspection stage, the phase defect is not fatal as a result of evaluating the transfer pattern on the main surface of the wafer after forming the absorber pattern on the surface of the mask blank. In some cases, the EUVL mask is non-defective.

  In fact, even if the phase defect is fatal in the mask blank inspection stage, if the layout completely covers the phase defect when forming the absorber pattern, the defect of the EUVL mask is substantially Don't be. Therefore, it is not essential to confirm that there are no phase defects at the mask blank inspection stage. Further, even if the phase defect is exposed after the absorber pattern is formed at the mask blank inspection stage, the phase defect is allowed if it is determined that the dimensional error of the transfer pattern is within the allowable value. If the degree of phase defect transfer is small, the phase defect remains acceptable. These are extremely useful for reducing the defective rate of the mask blank.

  However, even a phase defect that is allowed to remain may be transferred as a defect if the exposure conditions are different at the stage of transferring the absorber pattern onto the main surface of the wafer. For example, if the focus is sufficient, the phase defect does not substantially reduce the quality of the transfer pattern, but may be transferred as a defect in some defocus states even within the depth of focus. . Even if an EUVL mask is manufactured under the assumption of certain exposure conditions and there is no phase defect that substantially affects the transfer, if the EUVL mask is used under different exposure conditions, the phase defect will affect the transfer. May give. In response to such various exposure conditions, if it is required to be substantially defect-free under all exposure conditions, it becomes extremely difficult to manufacture an EUVL mask, and a reduction in the mask blank manufacturing yield is inevitable. . In the conventional exposure method or phase defect inspection method, the avoidance of such a decrease in the manufacturing yield of the mask blank has not been considered.

  An object of the present invention is to perform projection exposure of an absorber pattern that can reduce the influence of the phase defect on the transferred image of the absorber pattern even if a minute phase defect remains in the EUVL mask having a multilayer film and the absorber pattern. It is to provide a method.

  Another object of the present invention is to provide a projection exposure apparatus that can reduce the influence of a phase defect remaining in an EUVL mask on a transfer image of an absorber pattern.

  Another object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device that uses an EUVL mask and a projection exposure apparatus to reduce the cost of the EUVL mask.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, an embodiment of a representative one will be briefly described as follows.

  In this embodiment, projection exposure is performed by using an EUVL mask having a multilayer film and an absorber pattern formed on the multilayer film, and transferring the absorber pattern onto the main surface of the wafer via a projection optical system. A method of acquiring defect information related to an EUVL mask, a step of irradiating EUV light to an EUVL mask, and moving the EUVL mask and wafer to a predetermined exposure position in synchronization with each other. And transferring the absorber pattern onto the main surface of the wafer. When the EUVL mask and the wafer are moved synchronously to a predetermined exposure position, the transfer conditions are changed according to the defect information about the EUVL mask. To do.

  In this embodiment, the absorber pattern is transferred onto the main surface of the wafer via the projection optical system using the EUVL mask having the multilayer film and the absorber pattern formed on the multilayer film. A projection exposure apparatus that holds and moves an EUVL mask, an illumination optical system that irradiates the EUVL mask with EUV light, a wafer stage that holds and moves the wafer, and an EUVL mask Driving means for synchronously moving the wafer and the wafer, a storage unit for storing defect information relating to the EUVL mask, an exposure condition calculating means for calculating the exposure conditions corresponding to the defect information, and the EUVL mask and the wafer are synchronously moved. And an exposure condition changing means for changing the exposure condition to match the result obtained by the exposure condition calculating means.

  In this embodiment, the absorber pattern is transferred onto the main surface of the wafer via the projection optical system using the EUVL mask having the multilayer film and the absorber pattern formed on the multilayer film. A mask pattern transfer method, a step of forming a multilayer film on a substrate, a step of inspecting whether a phase defect exists in the multilayer film, and a phase defect when a phase defect is detected. A step of determining whether or not the material can remain, a step of forming an absorber pattern on the multilayer film to manufacture an EUVL mask, and a step of inspecting whether or not there is a defect in the absorber pattern If it is determined that the shape of the absorber pattern needs to be corrected, a step of correcting the shape of the absorber pattern, a step of recording defect information of phase defects remaining in the EUVL mask, and EUVL Mask for dew projection A step of placing the wafer on the mask stage of the apparatus, a step of placing the wafer on the wafer stage of the projection exposure apparatus, a step of inputting defect information to the projection exposure apparatus, and an optimum focus in the projection exposure apparatus according to the defect information An EUVL mask comprising: a step of aligning a position; a step of irradiating an EUVL mask with EUV light; and a step of transferring a pattern on the main surface of the wafer by synchronously moving the EUVL mask and the wafer. When the wafer and the wafer are moved synchronously, the pattern transfer conditions are changed according to the defect information relating to the EUVL mask.

  Among the inventions disclosed in the present application, effects obtained by one embodiment of a representative one will be briefly described as follows.

  To provide a projection exposure method for an absorber pattern capable of reducing the influence of the phase defect on the transfer image of the absorber pattern even if a minute phase defect remains in the EUVL mask having the multilayer film and the absorber pattern. it can.

  Further, it is possible to provide a projection exposure apparatus that can reduce the influence of the phase defect remaining in the EUVL mask on the transferred image of the absorber pattern.

  Further, it is possible to provide a method for manufacturing a semiconductor integrated circuit device in which the cost of the EUVL mask is kept low by using the EUVL mask and the projection exposure apparatus.

(A) is a principal part top view of the surface in which the absorber pattern of the EUVL mask by Embodiment 1 of this invention was formed, (b) is a part along the AA line of the same figure (a). It is principal part sectional drawing which expands and shows. (A) is principal part sectional drawing of the mask blank which has the phase defect by Embodiment 1 of this invention, (b) is an absorber pattern and a buffer layer in the mask blank which has the phase defect by Embodiment 1 of this invention. It is principal part sectional drawing of the formed mask for EUVL. (A) is a principal part top view which expands and shows the absorber pattern of the mask for EUVL by Embodiment 1 of this invention, (b) is principal part sectional drawing along the BB line of the same figure (a). (C) shows the result of calculating the transfer image obtained by projecting the absorber pattern of FIG. (A) onto the main surface of the wafer by the 1/4 reduction projection exposure apparatus for three types of defocusing. It is a principal part top view. (A) indicates the change in line width in the vicinity of the bump phase defect of the transferred L & S pattern obtained by projecting the L & S pattern of the EUVL mask according to the first embodiment of the present invention, and summarizes the defocus position dependency thereof. FIG. 6B is a graph showing a change in line width in the vicinity of the pit phase defect of the transferred L & S pattern obtained by projecting the L & S pattern of the EUVL mask according to the first embodiment of the present invention, and its defocus position. It is the graph which summarized the dependence. It is a block diagram of the projection exposure apparatus which carries out reduction transfer of the absorber pattern on the EUVL mask by Embodiment 1 of this invention on the main surface of a wafer. It is a figure explaining the scanning area | region at the time of carrying out scanning exposure of the mask for EUVL by Embodiment 1 of this invention. (A) is a principal plan view showing a part of the EUVL mask having phase defects according to the first embodiment of the present invention in an enlarged manner, (b) is an overlapping arc region that can be collectively transferred to FIG. It is a principal part top view which expands and shows some EUVL masks which have the phase defect. It is a graph which shows the change of the Z direction position control amount (focus position setting value) of a mask stage while the position of a circular arc area moves with the movement of the mask stage in the scanning exposure by Embodiment 1 of this invention. It is a flowchart figure explaining the flow of the projection exposure method by Embodiment 1 of this invention. It is a flowchart figure explaining the flow which acquires the information of the phase defect by Embodiment 1 of this invention. (A) is a principal part top view which expands and shows a part of EUVL mask which has a phase defect by Embodiment 2 of this invention, (b) has overlapped the circular arc area | region which can be batch-transferred to the figure (a). It is a principal part top view which expands and shows some EUVL masks which have the phase defect. While the position of the arc region is moved together with the movement of the mask stage in the scanning exposure according to the second embodiment of the present invention, the change in the Z-direction position control amount (focus position setting value) of the mask stage and the amount of inclination (inclination) It is a graph which shows the change of quantity setting value. It is process drawing which shows an example of the basic flow of manufacture of the semiconductor device by Embodiment 3 of this invention. It is principal part sectional drawing of the semiconductor device explaining the manufacturing process of the semiconductor device by Embodiment 3 of this invention. FIG. 15 is an essential part cross-sectional view of the same portion as that of FIG. 14 of the semiconductor device during a manufacturing step following that of FIG. 14; FIG. 16 is an essential part cross-sectional view of the same portion as that of FIG. 14 of the semiconductor device during a manufacturing step following that of FIG. 15; FIG. 17 is an essential part cross-sectional view of the same portion as that of FIG. 14 of the semiconductor device during a manufacturing step following that of FIG. 16; FIG. 18 is an essential part cross-sectional view of the same portion as that of FIG. 14 of the semiconductor device during a manufacturing step following that of FIG. 17; FIG. 19 is an essential part cross-sectional view of the same portion as that of FIG. 14 of the semiconductor device during a manufacturing step following that of FIG. 18;

  In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Further, in the drawings used in the following embodiments, hatching may be added to make the drawings easy to see even if they are plan views. In the following embodiments, the term “wafer” is mainly a Si (Silicon) single crystal wafer. However, not only that, but also an SOI (Silicon On Insulator) wafer and an integrated circuit are formed thereon. Insulating film substrate or the like. The shape includes not only a circle or a substantially circle but also a square, a rectangle and the like.

  In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
In describing the projection exposure method according to the first embodiment, first, the structure of the EUVL mask and the phase defect generated in the EUVL mask will be described with reference to FIGS. 1 and 2, respectively. FIG. 1A is a plan view of an essential part of the surface on which the absorber pattern of the EUVL mask is formed, and FIG. 1B is an enlarged view along a line AA in FIG. It is principal part sectional drawing. 2A is a cross-sectional view of a main part of a mask blank having a phase defect, and FIG. 2B is a cross-sectional view of a main part of an EUVL mask in which an absorber pattern and a buffer layer are formed on the mask blank having a phase defect. FIG.

  As shown in FIG. 1A, the central portion of the EUVL mask M has a device pattern area MDE having a circuit pattern of the semiconductor integrated circuit device, and the EUVL mask M is aligned at the peripheral portion. Alignment mark areas MA1, MA2, MA3, MA4 including a mark or a wafer alignment mark are arranged.

  As shown in FIG. 1B, the mask blank of the EUVL mask M includes a substrate MS made of quartz glass or low thermal expansion glass, molybdenum (Mo) and silicon (Si) formed on the main surface of the substrate MS. ) Are alternately stacked (for example, each layer is about 40 layers), the capping layer CAP formed on the multilayer film ML, and the back surface (surface opposite to the main surface) of the substrate MS. The EUVL mask M is composed of a metal film CF for electrostatic chucking. The thickness of the substrate MS is, for example, about 7 to 8 mm, and the thickness of the multilayer film ML is, for example, about 300 nm. Furthermore, the absorber pattern ABS is formed on the capping layer CAP via the buffer layer BUF. The thickness of the absorber pattern ABS is, for example, about 50 to 70 nm.

  In EUVL, even if a height abnormality of only a few nanometers occurs on the surface of the mask blank, a large phase change is caused in the EUV reflected light due to the height abnormality, and the absorber pattern is transferred onto the main surface of the wafer. Cause defects. 2A is a cross-sectional view of the main part of the mask blank shown in FIG. 2A, when the multilayer film ML is deposited on the substrate MS, the multilayer film ML with the minute depressions or protrusions existing on the main surface of the substrate MS. As a result, the pit phase defect PD1 having a concave surface or the bump phase defect PD2 having a concave surface is shown.

  When the buffer layer BUF and the absorber pattern ABS are formed while leaving these defects, for example, as shown in FIG. 2B, the pit phase defect PD1 or the bump phase defect PD2 remains between the adjacent absorber patterns ABS. There is a case. When these pit phase defect PD1 or bump phase defect PD2 exists, the pattern (transfer image, transfer pattern, projection image, pattern projection image) transferred onto the main surface of the wafer is disturbed, and the transfer pattern on the main surface of the wafer is changed. Defects occur.

  In the conventional transmission mask blank for optical lithography, even if the surface has irregularities of about several nm, this can be ignored. However, the EUVL mask has a large qualitative difference in defect transfer as compared with the conventional transmission mask, and it is necessary to avoid the generation of a mask blank defect (pit phase defect PD1 or bump phase defect PD2) that gives a phase difference. Don't be.

  An example of the influence of the pit phase defect PD1 or the bump phase defect PD2 on the transferred image of the absorber pattern will be described with reference to FIGS.

  FIG. 3A is an enlarged plan view of an essential part showing an absorber pattern of an EUVL mask. Line and space (L & S and L & S) in which a plurality of line-like absorber patterns ABS are arranged at regular intervals. Pattern) and the bump phase defect PD2 remaining between the adjacent absorber patterns ABS. The line width of the plurality of line-shaped absorber patterns ABS is 128 nm, and the pitch is 256 nm.

  FIG. 3B is a cross-sectional view of the main part along the line BB in FIG. 3A, and the bump phase defect PD2 has a convex shape over the entire layer of the multilayer film ML. .

  FIG. 3C shows the result of calculating a transfer image obtained by projecting the absorber pattern ABS onto the main surface of the wafer by the 1/4 reduction projection exposure apparatus for three types of defocus. It is a principal part top view. With negative defocusing, a transfer pattern 11 having an increased line width in the vicinity of the bump phase defect PD2 was obtained. Even when the defocus was 0, a transfer pattern 12 having an increased line width in the vicinity of the bump phase defect PD2 was obtained. Furthermore, a transfer pattern 13 in which a change in line width was recognized even in positive defocus was obtained.

  FIG. 4 (a) shows the change in line width near the bump phase defect PD2 of the transferred L & S pattern obtained by projecting the L & S pattern of the EUVL mask in%, and shows the result of summarizing the defocus position dependency. . When the bump phase defect PD2 does not exist, the change in the line width hardly changes as shown by the curve 14, but when the bump phase defect PD2 is present, focus dependency is recognized as shown by the curve 15.

  FIG. 4B shows the change in line width in the vicinity of the pit phase defect PD1 of the transferred L & S pattern obtained by projecting the L & S pattern of the EUVL mask, and shows the result of summarizing the defocus position dependency. . Similarly to the bump phase defect PD2, the focus dependency is recognized as shown by the curve 16 when the pit phase defect PD1 is included.

  From these facts, when the pit phase defect PD1 or the bump phase defect PD2 exists between the adjacent absorber patterns ABS, the line width of the transferred L & S pattern changes, and the change shows defocus dependency. It can be seen that the dependency shows a reverse tendency between the pit phase defect PD1 and the bump phase defect PD2, and that there is a defocus level with a small line width error in the pit phase defect PD1 and the bump phase defect PD2. Therefore, when a small phase defect remains, the error in the line width can be reduced by adjusting the focus level, so that it can be handled as a substantially defect-free EUVL mask. The amount of movement of the focus level is preferably suppressed within the allowable focal depth determined by the optical parameters of the projection exposure apparatus. When the allowable focal depth is exceeded, it is processed as a mask for EUVL with a defect.

  The concept of the configuration of the projection exposure apparatus that realizes the projection exposure method according to the first embodiment using the above phenomenon will be described with reference to FIG. FIG. 5 shows a block diagram of a projection exposure apparatus that reduces and transfers the absorber pattern on the EUVL mask M onto the main surface of the wafer.

  The projection exposure apparatus includes an optical system unit including the light source 20, the illumination optical system 21, and the reduction projection optical system 22 as main components, a mechanism unit for moving and positioning the EUVL mask M and the wafer W, and the projection exposure apparatus as a whole. A main controller 34 is provided for controlling automatically. Further, a recording unit 32 for storing all parameters necessary for exposure and a monitor unit 33 for displaying the exposure state are also provided. EUV light having a central wavelength of 13.5 nm emitted from the light source 20 illuminates the pattern surface of the EUVL mask M through an illumination optical system 21 composed of a multilayer mirror. The EUV light reflected from the pattern surface passes through the reduction projection optical system 22 composed of a multilayer mirror and transfers the absorber pattern onto the main surface of the wafer W. Note that the illumination optical system 21 and the reduction projection optical system 22 shown in the figure show a concept composed of a number of multilayer film reflecting mirrors, and do not show the actual configuration itself.

  Here, the mask stage MST for electrostatically fixing the EUVL mask M can be moved within the predetermined stroke range in the direction indicated by the arrow 24 by the mask stage driving means 23. The position of the mask stage MST in the moving plane is always detected with high resolution by the mask position measuring laser length measuring device 26 through a reference mirror 25 fixed to a part thereof.

  On the other hand, wafer stage WST that electrostatically attracts wafer W can be moved in the XY two-dimensional plane represented by arrow 28 by wafer stage driving means 27, and wafer W can be moved in the Z-axis direction indicated by arrow 29 and with respect to the XY plane. It is configured to be able to finely move in the tilt direction. The position of wafer stage WST can be accurately detected by measuring the position of reference mirror 30 fixed thereto with laser length measuring device 31. Further, although not shown, a focus position detecting means for measuring the position of the main surface of the wafer W in the Z-axis direction is provided, and the reduction projection optical system 22 reduces the main surface of the wafer W by fine movement in the Z-axis direction. It has a focusing function that accurately matches the image plane. The main controller 34 controls the mask stage driving unit 23 and the wafer stage driving unit 27 to control the synchronous scanning of the EUVL mask M and the wafer W and the stepping of the wafer W so that the exposure operation is performed accurately. And control.

  In the projection optical system used here, the region where the pattern of the EUVL mask M can be accurately transferred at once is limited to the arc region 35 shown in FIG. FIG. 6 shows a view of the pattern surface of the EUVL mask M, but the actual pattern surface of the EUVL mask M is disposed downward toward the reduction projection optical system 22. Here, when the EUVL mask M is moved in the above-described synchronous scanning in the direction indicated by the arrow 36 in the plane perpendicular to the optical axis of the reduction projection optical system 22, the arc region 35 moves the pattern surface of the EUVL mask M to the arrow. It moves to the direction shown in 37 (the direction opposite to the arrow 36). By performing exposure while scanning the EUVL mask M in synchronization with the movement of the wafer W, the entire desired pattern formed on the EUVL mask M can be transferred onto the main surface of the wafer W.

  Next, the projection exposure method according to the first embodiment will be described with reference to FIGS. FIG. 7A is an enlarged plan view of a main part showing a part of an EUVL mask M to which the present invention is applied. After forming an absorber pattern (not shown), two bump phase defects 41 are formed. , 42 and one pit phase defect 43, a total of three phase defects remain. FIG. 7B is an enlarged plan view showing a part of the EUVL mask M in which arc regions that can be collectively transferred are superimposed on FIG. The projection exposure apparatus shown in FIG. 5 is used for this projection exposure.

  When scanning and exposing the EUVL mask M, the mask stage MST and the wafer stage WST are synchronously scanned via the mask stage driving unit 23 and the wafer stage driving unit 27 based on an instruction from the main controller 34.

  Here, as shown in FIG. 7B, when the EUVL mask M is scanned in the direction indicated by the arrow 44, the arc region that can be collectively transferred is in the direction indicated by the arrow 45 (the direction opposite to the arrow 44). The pattern surface of the mask M is moved. At this time, the position of the wafer W (not shown) in the Z-axis direction is positioned at a defocus amount of zero. Here, when the arc region reaches the position 46 including the bump phase defect 41 and the position 47 including the bump phase defect 42, the main surface of the wafer W is associated with defect information in advance by controlling the wafer stage WST. Control to defocus to position. Further, when the arc region reaches a position 48 including the pit phase defect 43, the wafer stage WST is controlled so that the main surface of the wafer W is defocused to a position previously associated with the defect information.

  FIG. 8 shows the Z-direction position control of the mask stage MST while scanning exposure is started and the position of the arc region (for example, the arc region 35 shown in FIG. 6 described above) moves from X0 to X7 along with the movement of the mask stage MST. It is a graph which shows the change 49 of quantity (focus position setting value).

  Basically, as long as there is no phase defect, the defocus amount of the wafer W is controlled to be 0, and the Z direction position (focus position) of the wafer stage WST is kept at f2. The range where the X coordinate is X1 <X <X2 is an area where the arc region corresponds to the position 46 shown in FIG. Therefore, the Z-direction position (focus position) of wafer stage WST is controlled to f3 to give a predetermined defocus amount. When the X coordinate exceeds X2, the position in Z direction (focus position) of wafer stage WST is returned to f2. Thereafter, similarly, since the above-described bump phase defect 42 is included in the arc region in the range where the X coordinate is X3 <X <X4, the Z direction position (focus position) of the wafer stage WST is set to f4, and the X coordinate is set to X5 <X. In the range of <X6, since the pit phase defect 43 described above is included in the arc region, the Z direction position (focus position) of wafer stage WST is controlled to f1. When the X coordinate is other than the above, the Z direction position (focus position) of wafer stage WST is controlled to f2, and the defocus amount of wafer W is set to zero.

  Here, the predetermined defocus amount is the size of the phase defect and the transfer pattern as described with reference to the curve 15 shown in FIG. 4A or the curve 16 shown in FIG. 4B. This is a defocus level obtained by combining with the above dimensions, which reduces the error in line width. Needless to say, the range of the defocus amount is within the allowable depth of focus in consideration of the dimension of the transfer pattern sufficiently separated from the phase defect.

  Incidentally, the curve 15 shown in FIG. 4A or the curve 16 shown in FIG. 4B changes depending on the size of the phase defect and the size of the transfer pattern. A predetermined defocus amount can be controlled by using a calculation means for calculating an optimum focus position by recording a curve in advance or inputting a phase defect size and a transfer pattern dimension.

  In the first embodiment, the projection exposure apparatus is provided with a storage unit for storing defect information, and further provided with exposure condition calculation means and exposure condition change means. The exposure condition calculation means is means for calculating an exposure condition (for example, a local focus position of the wafer) corresponding to the defect information. The exposure condition changing means is means for changing a preset exposure condition to an exposure condition that matches the result obtained by the exposure condition calculation means. For example, a local focus position of the wafer, illumination of EUV light. It is means for changing one condition or two or more conditions among the condition, the speed of the synchronous movement, and the numerical aperture of the projection optical system. The storage unit can be provided in the recording unit 32 of the projection exposure apparatus shown in FIG. 5, and the exposure condition calculation means and the exposure condition change means are provided in the main controller 34 of the projection exposure apparatus shown in FIG. be able to.

  Next, the flow of the projection exposure method according to the first embodiment will be described with reference to the flowchart shown in FIG.

<Step S101>
First, the EUVL mask in which the phase defect remains is placed on the mask stage of the projection exposure apparatus shown in FIG.

<Step S102>
As input information related to the EUVL mask, information on phase defects of the EUVL mask, that is, position coordinates of the phase defects, size of the phase defects, and distinction of the pattern surface unevenness are input.

<Step S103>
A wafer to which the absorber pattern is transferred is placed on the wafer stage of the projection exposure apparatus.

<Step S104>
The wafer is moved to an exposure position where the pattern can be transferred, and scanning exposure is started by synchronous scanning of the mask stage MST and the wafer stage WST.

<Step S105>
When the position of the EUVL mask reaches the position of the phase defect input in advance during the scanning exposure, it is determined whether or not the focus position of the wafer should be moved.

<Step S106 or S107>
When the focus position needs to be moved (step S106), the focus position is moved according to the phase defect information to perform scanning exposure, and when the focus position does not need to be moved (step S107), the focus position is moved. Continue scanning exposure.

<Step S108>
It is determined whether or not scanning exposure on the entire surface of the wafer has been completed. If there is still an unexposed portion, the process returns to step S104 to perform the next scanning exposure.

<Step S109>
When the scanning exposure on the entire wafer surface is completed, the wafer is collected and it is determined whether the scanning exposure for all the prepared wafers is completed. If there are still wafers, the process returns to step S103 to place the next wafer on the wafer stage and start scanning exposure. When all the wafers have been exposed, a series of scanning exposure processing is completed.

  In the first embodiment, information on phase defects relating to the EUVL mask and optimum exposure conditions corresponding to the phase defects are input to the projection exposure apparatus. Therefore, it is necessary to recognize the position of the phase defect remaining in the EUVL mask in advance. Next, a flow for obtaining information on the phase defect will be described with reference to a flowchart shown in FIG.

<Step S201>
First, in manufacturing the EUVL mask, a quartz glass or a low thermal expansion glass substrate is prepared.

<Step S202>
A mask blank is manufactured by forming a multilayer film and a capping layer in which molybdenum (Mo) and silicon (Si) are alternately stacked on a quartz glass or low thermal expansion glass substrate.

<Step S203>
Inspect the phase defect of the mask blank. As this inspection method, in addition to the inspection method using DUV (Deep Ultra-Violet) light, for example, there is an inspection method using EUV light described in Patent Documents 2 and 3 described above. In these inspections, the magnitude of the phase defect or the position of the phase defect associated with the magnitude of the defect detection signal can be recognized, and it is also possible to determine the distinction between the irregularities on the surface of the phase defect. However, in the mask blank stage where only the multilayer film is formed, it is generally difficult to accurately identify the defect position. A fiducial mark is separately formed on the mask blank, and the relative position to the mark is determined. It is possible to recognize it as coordinates.

<Step S204>
The presence or absence of a fatal phase defect in the mask blank is determined.

<Step S205 or S213>
If it is determined in step S204 that a phase defect having a size that is obviously irreparable has been detected, the mask blank is processed as a defective product (step S213). On the other hand, when it is determined that the defect-free or residual phase defect has an allowable size, a buffer layer and an absorber pattern are further formed to manufacture an EUVL mask (step S205).

<Step S206>
The EUVL mask is inspected with a pattern inspection apparatus to detect the size of the defect or the position of the defect in the absorber pattern.

<Step S207>
The presence or absence of defects in the absorber pattern in the EUVL mask is determined.

<Step S208 or S213>
If it is determined in step S207 that an irreparable size defect has been detected in the absorber pattern, the EUVL mask is processed as a defective product (step S213). In other cases, it is determined whether or not the absorber pattern needs to be corrected (step S208).

<Step S209>
If it is determined in step S208 that the absorber pattern needs to be corrected, the absorber pattern is appropriately corrected so as to suppress the influence of the phase defect within an allowable range.

<Step S210>
If necessary, the final absorber pattern is checked, such as checking the correction result of the absorber pattern. Specifically, there is a method of recognizing the defect of the absorber pattern finally remaining from the intensity distribution of the bright field projection image using EUV light as inspection light.

<Step S211>
When phase defects remain in the mask blank inspection stage and phase defects that are not completely covered by the absorber pattern exist in the EUVL mask, for example, the specific absorption in which the phase defect is constituted by the absorber pattern If it is expressed by relative position coordinates when the body pattern is the origin, the position becomes clear. The optimum focus position corresponding to the phase defect is calculated by using the information of the phase defect remaining, such as the position coordinates of the phase defect and the surface irregularities of the phase defect thus obtained.

<Step S212>
The optimum focus position corresponding to the position coordinates of the phase defect is recorded.

  In the description of step S102 in FIG. 9 (projection exposure method flow) described above, in reading the phase defect information of the EUVL mask, the position coordinates of the phase defect, the size of the phase defect, and the pattern surface unevenness are distinguished. In this case, the projection exposure apparatus is provided with means (exposure condition calculation means) for calculating an optimum focus position corresponding to the phase defect. If the process proceeds to step S212 in FIG. 10 (flow for obtaining phase defect information) in the EUVL mask manufacturing process, the phase defect in step S102 in FIG. 9 (flow of projection exposure method) will be described. Reading of information becomes phase defect position information and optimum focus position information corresponding thereto.

  In the first embodiment, an example in which the exposure condition to be changed is the optimum focus position is shown. Furthermore, it was also stated that the range in which the focus position can be changed is within the allowable depth of focus. Although it is inevitable that the allowable focus error range (process window) will be reduced if the focus position is changed, the EUV light illumination condition for exposure illumination or the numerical aperture of the reduction projection optical system is changed according to the absorber pattern. It is possible to change and optimize the exposure conditions.

  As described above, when the projection exposure method for the EUVL mask according to the first embodiment is adopted, even if a fine phase defect remains in the EUVL mask having the multilayer film and the absorber pattern, the phase defect becomes the absorber pattern. The effect on the transferred image can be reduced. Thereby, the manufacturing yield of the EUVL mask can be improved, and the cost of the EUVL mask can be finally reduced.

(Embodiment 2)
In the second embodiment, a projection exposure method in the case where two or more phase defects having different sizes exist in an arc region that can be collectively exposed when scanning and exposing the absorber pattern of the EUVL mask is shown in FIGS. 12 will be described. The projection exposure apparatus to be used is basically the same as that described in the first embodiment, and its configuration is as shown in FIG.

  FIG. 11A is an enlarged plan view of a main part showing a part of the EUVL mask M to which the present invention is applied. Bump phases having different sizes are formed after an absorber pattern (not shown) is formed. In this example, a total of five phase defects, that is, defects 51, 52, 53 and pit phase defects 54, 55 remain. The method for recognizing the position of the remaining bump phase defects 51, 52, 53 and the pit phase defects 54, 55 or the pattern surface unevenness is the same as that described in the first embodiment.

  When scanning and exposing the EUVL mask M, the mask stage MST and the wafer stage WST are synchronously scanned via the mask stage driving unit 23 and the wafer stage driving unit 27 based on an instruction from the main controller 34. .

  Here, as shown in FIG. 11B, when the EUVL mask M is scanned in the direction indicated by the arrow 56, the arc region that can be collectively transferred is the EUVL for the direction indicated by the arrow 57 (the direction opposite to the arrow 56). The pattern surface of the mask M is moved. At this time, the position of the wafer W (not shown) in the Z-axis direction is positioned at a defocus amount of zero. Here, when the arc region reaches the position 58 including the two bump phase defects 51 and 52 having different sizes, the position of the wafer stage WST in the Z direction and the amount of inclination with respect to the XY plane are controlled. The optimum focal plane is controlled so that the influence of the individual phase defects (bump phase defects 51 and 52) on the transfer is reduced. Since both are bump phase defects 51 and 52, the amount of movement in the Z-axis direction, that is, the direction of focus movement, has the same sign, and gives an amount of inclination corresponding to the difference in the size of the phase defect. Of course, when the wafer stage WST is controlled to incline the XY plane of the wafer, it is necessary to suppress the regions at both ends of the arc region at the position 58 within the allowable depth of focus.

  Even when the arc region reaches the position 59 including the bump phase defect 53 and the pit phase defect 54, the two phase defects (bump phase defects) are controlled by controlling the Z-direction position of the wafer stage WST and the amount of inclination with respect to the XY plane. 53 and the pit phase defect 54) are controlled so that the influence on the transfer is reduced. Since the amount of movement in the Z-axis direction with respect to the two phase defects, that is, the direction of focal movement, has a different sign, the average amount of movement of wafer stage WST in the Z direction is small, and the amount of tilt with respect to the XY plane is mainly controlled.

  Furthermore, when the arc region reaches the position 60 including the pit phase defect 55, the same wafer stage WST control as that described in the first embodiment may be performed.

  FIG. 12 shows an average of the Z direction of the mask stage MST while scanning exposure is started and the position of the arc region (for example, the arc region 35 shown in FIG. 6 described above) moves from X10 to X17 along with the movement of the mask stage MST. It is a graph which shows the change 61 of the position control amount (focus position setting value), and the change 62 of the inclination amount (inclination amount setting value) with respect to XY plane.

  As in the first embodiment, the defocus amount and the tilt amount of the wafer W are controlled to be zero as long as there is basically no phase defect. That is, the Z-direction average position (focus position) of wafer stage WST is set to f2.

  In FIG. 12, the range where the X coordinate of the arc region is X11 <X <X12 corresponds to the region 58 shown in FIG. 11B and includes two bump phase defects 51 and 52 having different sizes. It is an area. Therefore, the Z stage average position of wafer stage WST is controlled to f5, and a small amount of tilt θ1 is given. When the X coordinate exceeds X12, the average position in the Z direction of wafer stage WST is returned to f2, and the tilt amount is also returned to zero.

  Thereafter, similarly, in the range of X13 <X <X14, it corresponds to the region 59 shown in FIG. 11B, and includes the bump phase defect 53 and the pit phase defect 54. Therefore, the average position in the Z direction of the wafer stage WST is The inclination amount is controlled to θ2 at a minute value f6. In the range of X15 <X <X16, it corresponds to the region 60 shown in FIG. 11B and includes only one pit phase defect 55. Therefore, the Z-direction average position of the wafer stage WST is controlled to f7 and tilted. Return the amount to zero. When the X coordinate is other than the above, the Z direction average position of the wafer stage WST is controlled to f2, the tilt amount is controlled to 0, and the defocus amount of the wafer W is set to 0.

  In the case where three or more phase defects are included in the arc region to be scanned, the Z position average position amount and the surface inclination amount of wafer stage WST are minimized so that the influence of phase defects on pattern transfer is minimized. Will be controlled. As a result of the control, it is desirable that all desired absorber patterns to be transferred in the arc region fall within the allowable depth of focus. If this condition is not satisfied, the EUVL mask M is basically a defective product. In order to avoid this, for example, in the EUVL mask M shown in FIG. 1 described above, a device pattern MDE is arranged around the device pattern MDE so that an absorber pattern larger than the inner region is arranged. It is conceivable to increase the value of the substantial depth of focus at both ends.

  In the second embodiment, in addition to the fine movement amount of the wafer stage WST in the Z-axis direction and the tilt amount of the XY plane, the EUV light for exposure illumination is changed according to the absorber pattern as in the first embodiment described above. It is possible to optimize the exposure condition by changing the illumination condition or the numerical aperture of the reduction projection optical system.

  As described above, when the projection exposure method for the EUVL mask according to the second embodiment is adopted, a fine phase defect remains in the EUVL mask having the multilayer film and the absorber pattern, and an arc that can be exposed and scanned at one time is scanned. Even when phase defects of different sizes or types exist in the region, the influence of the phase defects on the transfer image of the absorber pattern can be reduced. Thereby, the manufacturing yield of the EUVL mask can be improved, and the cost of the EUVL mask can be finally reduced.

(Embodiment 3)
In the third embodiment, a manufacturing method of a semiconductor device adopting the above-described projection exposure apparatus and the method of scanning and exposing the absorber pattern of the EUVL mask will be described with reference to FIGS. FIG. 13 is a process diagram showing an example of a basic flow of manufacturing a semiconductor device such as an IC (Integrated Circuit), an LSI (Large Scale Integrated Circuit), a liquid crystal panel, or a CCD (Charge Coupled Device) chip, and FIGS. It is principal part sectional drawing of a semiconductor device.

  First, a semiconductor device manufacturing process will be briefly described with reference to FIG.

<Step S301>
Design circuit patterns to realize semiconductor device functions.

<Step S302>
Make a mask with the designed circuit pattern. This mask has a different structure depending on the lithography process. That is, when the mask is used for normal optical lithography, a light transmission type transmission mask is manufactured, and when the mask is used for EUV lithography, a reflection type EUVL mask is manufactured.

<Step S303>
A wafer is manufactured using a material such as silicon.

<Step S304>
The mask manufactured in step S302 and the wafer manufactured in step S303 are prepared, and a circuit pattern is formed on the main surface of the wafer by lithography. Here, various lithography processes, film forming processes, etching processes, and the like are included.

<Step S305>
The semiconductor device is assembled using the wafer processed in step S304. This step S305 includes a package process such as a dicing process for cutting out a semiconductor chip from the wafer, a bonding process for connecting wiring with the outside, and a semiconductor chip encapsulation, as necessary.

<Step S306>
Finally, inspections such as an operation confirmation test and a durability test are performed on the assembled semiconductor device. After passing through the above steps, those that pass the inspection are shipped as finished products.

  Next, a semiconductor device manufacturing method in the wafer processing in step S304 will be briefly described with reference to FIGS. Here, a case where a twin well type CMIS (Complimentary Metal Insulator Semiconductor) circuit is manufactured is exemplified, but the present invention can be applied to other various types of circuits. 14 to 19, a region indicated by pMIS is a p-channel field effect transistor (pMIS transistor) formation region, and a region indicated by nMIS is an n-channel field effect transistor (nMIS transistor) formation region.

  First, as shown in FIG. 14, a substrate 101 made of single crystal silicon (Si) (at this stage, a semiconductor thin plate having a substantially circular shape called a semiconductor wafer) is prepared. Next, after an oxide film 102 is formed on the main surface of the substrate 101, a resist pattern 103 for an ion implantation mask is formed on the oxide film 102 by using normal photolithography. Thereafter, phosphorus (P) or arsenic (As) is ion-implanted to form an n-type well 104n in the pMIS region.

  Next, as shown in FIG. 15, ashing is performed to remove the resist pattern 103, and then the oxide film 102 is removed. Subsequently, after an oxide film 105 is formed on the substrate 101, a resist pattern 106 for an ion implantation mask is formed on the oxide film 105 by using normal photolithography. Thereafter, boron (B) is ion-implanted to form a p-type well 104p in the nMIS region.

  Next, as shown in FIG. 16, ashing is performed to remove the resist pattern 106, and then the oxide film 105 is removed. Subsequently, an isolation field insulating film 107 made of, for example, silicon oxide is formed on the main surface of the substrate 101 in the shape of trench isolation. The shape of the groove-type isolation requires a strict value on the nanometer level as well as the minimum dimension on the wafer. Therefore, EUVL can be used as lithography for forming this groove type isolation.

  In the active region surrounded by the field insulating film 107, an nMIS transistor Qn and a pMIS transistor Qp are formed. The gate insulating film 108 of each of the nMIS transistor Qn and the pMIS transistor Qp is made of, for example, silicon oxide and is formed by a thermal oxidation method or the like. Each of the gate electrodes 109 of the nMIS transistor Qn and the pMIS transistor Qp is required to have a strict value of, for example, a minimum dimension as small as 30 to 20 nm on the wafer and a dimensional accuracy of 3 to 2 nm. Therefore, after depositing a conductive film made of low-resistance polycrystalline silicon (Si) using, for example, a CVD (Chemical Vapor Deposition) method, a resist pattern is formed using EUVL, and a gate electrode 109 is formed by etching treatment. To do. Lithography in this process is generally referred to as gate layer lithography, and requires extremely fine pattern transfer with high dimensional accuracy.

  The semiconductor region 110 of the nMIS transistor Qn is self-aligned with the gate electrode 109 by introducing, for example, phosphorus (P) or arsenic (As) into the substrate 101 using the gate electrode 109 as a mask, by ion implantation or the like. It is formed. Further, the semiconductor region 111 of the pMIS transistor Qp is formed in a self-aligned manner with respect to the gate electrode 109 by introducing, for example, boron (B) into the substrate 101 by using the gate electrode 109 as a mask, by ion implantation or the like. .

  Here, the gate electrode 109 is not limited to being formed of a single layer film of low-resistance polycrystalline silicon, and can be variously changed. For example, the gate electrode 109 may have a so-called polycide structure in which a silicide layer such as tungsten silicide (WSi) or cobalt silicide (CoSi) is provided on a low-resistance polycrystalline silicon film. Alternatively, the gate electrode 109 is formed by interposing a barrier conductor film such as titanium nitride (TiN) or tungsten nitride (WN) on a low-resistance polycrystalline silicon film, and further forming a metal film such as tungsten (W). A so-called polymetal structure may be provided.

  Next, as shown in FIG. 17, an interlayer insulating film 112 made of silicon oxide is formed on the substrate 101 by using, for example, a CVD method, and then a polycrystalline silicon film for wiring is formed on the interlayer insulating film 112 by CVD. Deposit by the method. Subsequently, the polycrystalline silicon film is patterned by lithography and etching, and then impurities are introduced into a predetermined region of the patterned polycrystalline silicon film, thereby forming a wiring 113L and a resistor 113R made of the polycrystalline silicon film.

  Next, as shown in FIG. 18, a silicon oxide film 114 is deposited on the substrate 101 by using, for example, a CVD method or the like. Then, a resist pattern is formed on the interlayer insulating film 112 and the silicon oxide film 114 using EUVL, and a connection hole 115 is formed by etching to expose a part of the semiconductor regions 110 and 111 and the wiring 113L. . Since fine holes are difficult to resolve due to the effects of light diffraction, EUVL having high resolution is applied to the lithography for the connection holes.

  Next, as shown in FIG. 19, a metal film made of titanium (Ti), titanium nitride (TiN), and tungsten (W) is sequentially deposited on the substrate 101 by using, for example, a sputtering method or a CVD method. A resist pattern is formed on the metal film using EUVL, and the first wiring layer 116 is formed by an etching process. The first wiring layer 116 includes a fine dense pattern and an isolated pattern, and has a complicated layout shape because the wiring is routed around neighboring wirings or connected between the wirings. Therefore, the first wiring layer lithography is also required to have high resolution and dimensional accuracy.

  Thereafter, by forming the second wiring layer (not shown) and the like in the same manner as the first wiring layer 116, the final product is manufactured, and the wafer processing step is completed.

  In the above-described series of wafer processing steps, sufficiently high resolution is required for the gate layer lithography, the connection hole lithography, and the first wiring layer lithography. Therefore, it is desirable to apply EUVL.

  The EUVL mask for the gate layer and the first wiring layer is inspected for the presence of phase defects, and pattern transfer can be performed using the exposure apparatus and projection exposure method described in the first and second embodiments. preferable. In addition, since there is a substantial limit in terms of resolution in normal optical lithography in forming the connection hole, the exposure apparatus and the projection exposure method described in the first and second embodiments are used using the EUVL mask. It is desirable. Since the area of the connection hole is small and the pattern density is often 10% or less, the ratio of occurrence of defects near the connection hole is small, and the remaining phase defects are extremely small. Accordingly, the yield of the mask that can be used by the exposure method of the present invention is increased.

  As described above, when the semiconductor device manufacturing method according to the third embodiment is employed, the exposure apparatus and the projection exposure described in the first and second embodiments described above can be used even with the EUVL mask in which minute phase defects remain. By using this method, pattern transfer substantially equivalent to circuit pattern transfer using a defect-free mask can be performed. For this reason, the yield of the manufactured EUVL mask can be improved, and as a result, the manufacturing cost of the semiconductor device can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to the manufacture of a semiconductor device that requires fine processing.

11, 12, 13 Transfer patterns 14, 15, 16 Curve 20 Light source 21 Illumination optical system 22 Reduction projection optical system 23 Mask stage driving means 24 Arrow 25 Reference mirror 26 Mask position measuring laser side lengthening device 27 Wafer stage driving means 28, 29 Arrow 30 Reference mirror 31 Laser side length 32 Recording unit 33 Monitor unit 34 Main controller 35 Arc region 36, 37 Arrow 41, 42 Bump phase defect 43 Pit phase defect 44, 45 Arrows 46, 47, 48 Position of arc region 49 Z-direction position change 51, 52, 53 Bump phase defect 54, 55 Pit phase defect 56, 57 Arrow 58, 59, 60 Arc region position 61 Z-direction average position control amount change 62 Tilt amount with respect to XY plane Change 101 substrate 102 oxide film 103 resist pattern 104n n-type well 104p p-type well 1 05 oxide film 106 resist pattern 107 field insulating film 108 gate insulating film 109 gate electrode 110, 111 semiconductor region 112 interlayer insulating film 113L wiring 113R resistance 114 silicon oxide film 115 connection hole 116 first wiring layer ABS absorber pattern BUF buffer layer CAP Capping layer CF Metal film M EUVL mask MA1, MA2, MA3, MA4 Alignment mark area MDE Device pattern area ML Multilayer film MS Substrate MST Mask stage PD1 Pit phase defect PD2 Bump phase defect Qn n-channel field effect transistor Qp p-channel type Field Effect Transistor W Wafer WST Wafer Stage

Claims (4)

Projection exposure method for transferring an absorber pattern onto a main surface of a wafer via a projection optical system using a EUV lithography mask having a multilayer film that reflects EUV light and an absorber pattern that absorbs the EUV light Because
(A) obtaining defect information of phase defects remaining in the EUV lithography mask;
(B) irradiating the EUV light on the EUV lithography mask;
(C) synchronously moving the EUV lithography mask and the wafer to a predetermined exposure position, and transferring the absorber pattern onto the main surface of the wafer at the predetermined exposure position;
Have
The defect information of the phase defect is information for distinguishing the position coordinates of the phase defect and the unevenness of the pattern surface of the EUV lithography mask,
In the step (c), when the EUV lithography mask and the wafer are moved synchronously, a local focus position of the wafer is changed according to the defect information regarding the EUV lithography mask. Projection exposure method. Projection exposure apparatus for transferring an absorber pattern onto a main surface of a wafer via a projection optical system using a EUV lithography mask having a multilayer film that reflects EUV light and an absorber pattern that absorbs the EUV light Because
A mask stage that holds and moves the EUV lithography mask;
An illumination optical system for irradiating the EUV light on the EUV lithography mask;
A wafer stage that holds and moves the wafer;
Driving means for synchronously moving the EUV lithography mask and the wafer;
A storage unit for storing defect information of phase defects remaining in the EUV lithography mask;
Exposure condition calculation means for calculating a local focus position of the wafer corresponding to the defect information;
An exposure condition changing means for changing to the local focus position of the wafer obtained in the exposure condition calculating means when the EUV lithography mask and the wafer are moved synchronously;
I have a,
The projection exposure apparatus according to claim 1, wherein the defect information of the phase defect is information on a position coordinate of the phase defect and information on the unevenness of a pattern surface of the mask for EUV lithography . Using a mask for EUV lithography having a multilayer film that reflects EUV light and an absorber pattern that absorbs the EUV light, a mask pattern for transferring the absorber pattern onto the main surface of the wafer via a projection optical system A transfer method,
(A) forming the multilayer film on a substrate;
(B) inspecting whether or not a phase defect exists in the multilayer film;
(C) if the phase defect is detected, determining whether the phase defect may remain;
(D) after forming an absorber layer on the multilayer film, processing the absorber layer into a desired shape to form the absorber pattern, and manufacturing a mask for EUV lithography;
(E) inspecting whether there is a defect in the absorber pattern;
(F) When it is determined that the shape of the absorber pattern needs to be corrected, the step of correcting the shape of the absorber pattern;
(G) recording defect information of the phase defect remaining in the EUV lithography mask;
(H) placing the EUV lithography mask on a mask stage of a projection exposure apparatus;
(I) placing the wafer on a wafer stage of the projection exposure apparatus;
(J) inputting the defect information into the projection exposure apparatus;
(K) determining an optimum focus position in the projection exposure apparatus according to the defect information;
(L) irradiating the EUV light on the EUV lithography mask;
(M) performing a pattern transfer on the main surface of the wafer by moving the EUV lithography mask and the wafer synchronously;
Have
In the step (m), when the EUV lithography mask and the wafer are moved synchronously, a local focus position of the wafer is changed according to the defect information related to the EUV lithography mask. To transfer the mask pattern. The method of transferring a mask pattern according to claim 3 .
The method of transferring a mask pattern, wherein the defect information of the phase defect is information on a position coordinate of the phase defect and information on distinguishing unevenness of a pattern surface of the mask for EUV lithography.

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