JP5115318B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

  A general semiconductor device has a semiconductor substrate, that is, a semiconductor chip, and an insulating substrate on which the semiconductor chip is mounted. The semiconductor chip is bonded to the insulating substrate with solder. In a semiconductor device including such a solder joint, when the heat generation amount of the semiconductor chip exceeds the melting point of the solder, the solder melts and the operation of the semiconductor device stops. For this reason, the operating temperature of the semiconductor device needs to be at least below the melting point of the solder. Examples of the solder include Sn—Ag—Cu, which is a general lead-free solder, and the melting point of the solder is about 220 ° C.

  The higher the power handled by a circuit including a semiconductor device is, or the higher the required reliability (stability over time, heat resistance, moisture resistance, etc.) is, the safer insulation is required. The heat resistance mentioned here includes the heat resistance when the current handled by the semiconductor device is large and the heat generated in the semiconductor substrate is large. Recently, there has been a demand for a semiconductor device that generates a large amount of heat and requires high reliability.

In order to meet such a demand, a technique for directly joining a semiconductor chip to an insulating substrate without using solder has been proposed (see Patent Document 1). In the semiconductor device described in Patent Document 1, the electrode surface of the semiconductor chip and the surface of the circuit pattern on the insulating substrate are formed from the same material. Then, the electrode surface and the circuit pattern surface are faced to each other, and ultrasonic vibration is applied while applying pressure, thereby directly bonding without solder.
JP 2004-14599 A

  The solder plays a role of buffering a difference in thermal expansion coefficient between the wiring metal on the semiconductor chip side and the wiring metal on the circuit pattern side. Since the semiconductor device described in Patent Document 1 does not have solder that plays the above role, if a large temperature difference is repeatedly applied, the stress may concentrate on the interface due to thermal stress, and cracks may occur. In addition, the flatness of each surface must be managed, and manufacturing is complicated, and there is a concern that costs increase.

  In view of the problems as described above, an object of the present invention is to provide a highly reliable semiconductor device that can reduce thermal stress or thermal strain generated during manufacturing or operation and can operate stably over a long period of time.

In order to achieve the above object, a semiconductor device according to the present invention includes a semiconductor substrate, an insulating ceramic plate on which the semiconductor substrate is mounted, and a stress buffering portion that relieves thermal stress. The stress buffer portion is provided between (a) the semiconductor substrate and the insulating ceramic plate , or (b) between the semiconductor substrate and the insulating ceramic plate, and the semiconductor substrate is mounted on both sides of the insulating ceramic plate. It is provided in direct contact with the surface opposite to the side. The stress buffer portion is formed of a structure including at least Al and a second phase, and the second phase is Al ₄ X (X = at least one of alkaline earth metal elements).

  According to the present invention, it is possible to obtain a semiconductor device that can relieve thermal stress or thermal strain generated during manufacturing or operation and can operate stably over a long period of time.

  First Embodiment FIG. 1 is a cross-sectional view showing a package structure of a semiconductor device 11 according to a first embodiment of the present invention, and FIG. 2A is a semiconductor device 11 according to the first embodiment. FIG. 2B is a cross-sectional view taken along line 2B-2B of FIG.

Referring to FIG. 1 and FIG. 2, the semiconductor device 11 generally includes a semiconductor substrate 20, that is, a semiconductor chip 20, an insulating ceramic plate 30 on which the semiconductor chip 20 is mounted, and a stress buffering portion 40 that relieves thermal stress. ,have. In the illustrated example, the stress buffering portion 40 is provided between the semiconductor substrate 20 and the insulating ceramic plate 30. The stress buffer portion 40 is formed of a structure including at least Al and a second phase, and the second phase is Al ₄ X (X = at least one kind of alkaline earth metal element). Examples of alkaline earth metal elements include Ca, Sr, Ba and the like.

  A wiring metal layer 50 is provided on one surface of both surfaces of the insulating ceramic plate 30, and a back metal layer 60 is provided on the other surface to constitute a composite substrate. The semiconductor chip 20 is provided on the wiring metal layer 50 via the stress buffering portion 40. Under the back metal layer 60, a heat sink 71 as a cooling body is bonded. A heat sink 71 is attached to a case 72 made of resin. In the figure, reference numeral 73 denotes a terminal whose one end is electrically connected to the semiconductor device 11 and the other end is drawn out of the case 72, and reference numeral 74 denotes a bonded wire.

The stress buffering portion 40 has an Al-based two-phase structure, and when Al ₄ X (X = at least one of alkaline earth metal elements) is present as the second phase, the elastic modulus is lowered, so that the stress is effectively reduced. Can be buffered.

The elastic modulus of pure Al is about 70 GPa. In the two-phase structure of the present invention, for example, when X = Ca is used, although it varies depending on the volume fraction of the second phase and the type of X of Al ₄ X. , Can be lowered to the 30 GPa range.

FIG. 3 shows changes in elastic modulus, linear expansion coefficient, thermal conductivity, and conductivity when the volume fraction of Al ₄ Ca in Al is changed when Ca is used as X.

  As shown in the figure, it can be seen that the linear expansion coefficient also decreases with respect to pure Al. If the linear expansion coefficient is lowered, the difference in linear expansion coefficient from the semiconductor chip 20 and the insulating ceramic plate 30 is reduced, so that the generated thermal stress can be further reduced.

The thermal conductivity is important for effectively radiating the heat generated in the semiconductor device 11, and is preferably as high as possible. As shown in FIG. 3, it decreases as the amount of Al ₄ Ca increases. However, the heat conductivity of the solder can secure a sufficiently high value as compared with, for example, about 50 W / m · K for eutectic solder. This is presumed to be because high heat conduction is maintained in the Al phase because the amount of dissolved Ca in the Al phase of the two phases is small.

The conductivity is important in order to suppress the heat generation of the semiconductor device 11 and increase the efficiency. The higher the conductivity, the lower the electrical resistance. As shown in FIG. 3, it decreases as the amount of Al ₄ Ca increases. However, a sufficiently high value can be secured for the conductivity of the solder compared to, for example, about 11% IACS for eutectic solder. This is presumed to be because a high conductivity is maintained in the Al phase because the amount of dissolved Ca in the Al phase of the two phases is small.

FIG. 4 shows, as an example of a structural photograph of the stress buffering portion 40, an optical micrograph when Al ₄ Ca in Al is contained at about 45% (Al-9 at.% Ca).

In the figure, the darkly represented portion is Al ₄ Ca, and the thinly represented portion is Al, which is a fine two-phase structure as shown. For this reason, even if fatigue accumulates due to repeated stress and cracks occur, the elongation is delayed and the long-term reliability is excellent.

Although only the case of X = Ca is shown in the figure, the same tendency can be obtained even if Sr or Ba is used as X, and the effect can be exhibited. When Ca, Sr, and Ba are added to Al, they become Al ₄ Ca, Al ₄ Sr, and Al ₄ Ba, respectively, at 20 atomic weight% in the equilibrium state. These intermetallic compounds are all assumed to have the same crystal structure of the Al ₄ Ba type (D1 ₃ ) and have a lower elastic modulus than pure Al. Moreover, since Ca, Sr, and Ba all have a small amount of solid solution in Al, the thermal conductivity and conductivity of the Al phase are not greatly deteriorated.

Table 1 below shows the components and measurement results of an alloy containing Al ₄ Ca in Al shown in FIG. For comparison, Table 1 also shows data of pure Al (A1070) and A4032 alloy as a general Al alloy.

  As shown in Table 1, No. constituting the stress buffering portion 40 of the present invention. 1-No. It can be confirmed that the alloy No. 3 can reduce the elastic modulus and the linear expansion coefficient at the same time, and is suitable as the stress buffer portion 40.

  Aluminum alloys having the compositions shown in Table 1 were produced as follows.

  Using pure metals of Al and Ca having a purity of 99.9% or more, alloy powders having the composition shown in Table 1 (average particle diameter: about 50 μm) were prepared by an atomizing method.

  After this alloy powder was filled in a container (diameter 50 mm), it was deaerated at 300 to 400 ° C. and extruded at 400 ° C. into a rod shape having a diameter of 10 mm.

(Comparative Example 1)
Commercially available pure Al (A1070) having a diameter of 10 mm manufactured by a general method was annealed at 400 ° C. for 1 hour.

(Comparative Example 2)
An A4032 alloy having a diameter of 10 mm manufactured by a general method was subjected to T6 treatment.

<Evaluation method>
The following evaluation was performed about the aluminum alloy of each said example.

1. Young's modulus For each example of Examples 1 to 3 and Comparative Examples 1 and 2, the Young's modulus in the longitudinal direction of the bar was measured at room temperature by a tensile test in accordance with JIS Z 2280: 1993 (Method for testing high-temperature Young's modulus of metal materials). did. The results are shown in Table 1.

2. X-ray diffraction About Examples 1-3, the constituent phase at room temperature was investigated using X-ray diffraction. For the X-ray measurement, a sample was crushed into a powder and then heat treated for strain removal at 300 ° C. for 10 minutes. A Cu tube was used. The peak of the X-ray diffraction pattern was analyzed to determine the constituent phase. The results are shown in Table 1, and it was found that both had a two-phase structure of Al (first phase or Al matrix) and Al ₄ Ca (second phase).

3. Structure observation and volume fraction of second phase Further, the aluminum alloys of Examples 1 to 3 were observed with an optical microscope having a cross section perpendicular to the longitudinal direction of the bar. Although it was a two-phase structure, it was confirmed by EPMA analysis that the dark portion in the figure was the second phase composed of Al ₄ Ca and the thin portion was Al.

Based on the observation result, binarization processing was performed by image analysis, and the area fraction of the second phase made of Al ₄ Ca was obtained. Further, the area fraction of the longitudinal parallel cross section was similarly obtained from the optical micrograph, and the average volume ratio with the area fraction of the vertical cross section was obtained as the volume fraction. Table 1 shows the results of the volume fraction of the second phase composed of Al ₄ Ca in each example. In any of Examples 1 to 3, no significant difference in structure depending on the observation direction was observed.

4). Tensile test About each example of Examples 1-3 and Comparative Examples 1 and 2, the tensile strength and elongation were measured by the tensile test at room temperature according to JIS Z2241: 1998 (metal material tensile test method). The results are shown in Table 1.

5. Thermal expansion coefficient (average linear expansion coefficient)
About Examples 1-3 and Comparative Examples 1-2, the average linear expansion coefficient was calculated | required by TMA (Thermal Mechanical Analysis; thermomechanical analyzer) measurement. The shape of the test piece was 5 mmφ × 20 mm in diameter, and the average linear expansion coefficient was determined in the range of −50 ° C. to 300 ° C. at a temperature increase / decrease rate of 5 ° C./min. The results are shown in Table 1.

6). Thermal conductivity About each example of Examples 1-3 and Comparative Examples 1-2, the thermal conductivity at room temperature was measured by the laser flash method. The results are shown in Table 1.

7). Electrical conductivity About each example of Examples 1-3 and the comparative example 1, the sample was cut out to 2 mm x 2 mm x 100 mm, and was measured by the 4 terminal method.

8). Density For each of Examples 1-3 and Comparative Examples 1-2, the density was calculated by measuring the dimensions and weight at room temperature. The results are shown in Table 1.

  The alloy composition other than Al of “A4032” shown in the “Others” column of the component of Comparative Example 2 in Table 1 is Si: 11.8%, Fe: 0.49%, Cu: 0.43%, Mg: 1.13%, Cr: 0.05%, Zn 0.1%, Ni: 0.47%. Each component “%” of these alloy compositions is “wt.%”.

  In order to confirm the effect of the stress buffer 40, the stress generated at the chip angle 81a by FEM analysis was relatively compared using a model as shown in FIG.

  The analysis model is the semiconductor chip 81, the intermediate layer 82, the wiring metal layer 83, the insulating ceramic plate 84, and the back surface metal layer 85, and is a 1/4 model from the symmetry. Each thickness and physical property value are shown in Table 2 below.

  Of these, it is assumed that the intermediate layer 82, the wiring metal layer 83, and the back metal layer 85, which are metal regions, are made of the same metal material, and all are stress buffer portions 40, and the elastic modulus and linear expansion coefficient are changed. The equivalent stress generated in the vicinity of the chip angle 81a when the temperature difference was applied at 280 ° C. was obtained. Note that the plastic deformation of the material, creep, and temperature change of each physical property value are ignored. FIG. 6 shows a map of the stress generated on the chip with respect to the elastic modulus (E) and the coefficient of linear expansion (CTE) of the stress buffering part / wiring metal layer based on the result. The elastic modulus and linear expansion coefficient (described in FIG. 3 and Table 1) of the Al—Ca alloy constituting the stress buffer portion 40 of the present invention are shown in FIG. As a comparison, data of pure Al (A1070) and Al—Si based A4032 material which is a kind of Al alloy are also plotted.

As shown in the figure, it was confirmed that the alloy containing Al ₄ Ca in Al as an example of the present invention can greatly reduce the stress generated in the semiconductor chip 20. On the other hand, although pure Al and other Al alloys are shown in the figure, a sufficiently low elastic modulus cannot be obtained unless Al ₄ X (X = at least one of alkaline earth metal elements) is present as the second phase. The thermal stress cannot be reduced.

The second phase of the stress buffer portion 40 preferably has a volume fraction of 5% or more. If it is 5% or less, the effect of preventing the extension of cracks is poor, and the effect of lowering the elastic modulus is also small, so that sufficient reliability may not be ensured.

  FIG. 7 is a diagram conceptually showing the multiphase structure constituting the stress buffering portion 40.

  As shown in the figure, the second phase 42 of the stress buffer 40 is preferably dispersed in the Al matrix 41. More preferably, it is uniformly dispersed in the Al matrix 41. When the Al matrix 41 has a network structure, it is possible to minimize the loss of heat conduction and conductivity due to the presence of the second phase 42 and to ensure sufficient ductility. Because it can.

The stress buffer 40 is made of 3-12 at. % Is more preferable. Since Ca has a lower density than Ba, the weight can be reduced and the cost can be reduced. Further, Ca has a large effect of reducing the elastic modulus with respect to Sr, and can be reduced in cost. When the Ca content is less than 3%, the presence of the Al ₄ Ca phase is small, so that the effect of preventing the extension of cracks is poor, and the effect of lowering the elastic modulus is small, so that sufficient reliability may not be ensured. On the other hand, the Ca content is 12 at. If it is contained in excess of%, the thermal conductivity and conductivity may be deteriorated and the performance of the apparatus may be impaired.

  The stress buffering part 40 of the present invention is mainly composed of Al, but Al is the remaining part, and its content is not limited. For example, when the atomic weight ratio is considered, the most abundant element may be Al. In particular, the entire Al alloy is 100 at. %, The Al content is 70 at. % Or more is preferable for achieving high conductivity and low elasticity. Other than the above, for example, it is excluded to mix Mg, Si, Mn, Cu, Fe, P, Ti, Ba, Sr, Cr, Zn and the like within a range not departing from the spirit of the aluminum alloy of the present invention. is not.

  Although the manufacturing method of the stress buffer part 40 is not specifically limited, For example, the board | plate of an Al-Ca alloy can be manufactured by melt | dissolution, rolling, etc. In addition, as a method for joining the stress buffering portion 40 when assembling the semiconductor device 11, direct joining such as ultrasonic joining, superplastic joining, diffusion joining, etc. may be used, or joining using various brazing materials and solder indirectly. good. The thin film may be formed directly on the insulating ceramic plate by sputtering or the like.

  Referring again to FIG. 2, the stress buffer 40 is in contact with the wiring metal layer 50. The electrical conductivity of the wiring metal layer 50 is preferably larger than the electrical conductivity of the stress buffer portion 40. As described above, in the two-phase structure of the stress buffer portion 40, conductivity and heat conduction are somewhat negative factors. Therefore, only the portion where stress buffering is necessary is used as the stress buffering portion 40, and the other wiring metal layer 50 is made of a material having high thermal conductivity and high conductivity such as Cu or Al. With such a configuration, a highly efficient semiconductor device 11 can be obtained.

  At this time, the wiring metal layer 50 is preferably formed from Al or an Al alloy. If the wiring metal is Al or an Al alloy, a brittle intermetallic compound is not formed at the interface between the stress buffering portion 40 and the wiring metal, so that the semiconductor device 11 having excellent long-term reliability can be obtained.

According to the semiconductor device 11 of the first embodiment, the stress buffer portion 40 is a structure in which Al ₄ X (X = at least one of alkaline earth metal elements) is dispersed in Al, and has an elastic modulus and a linear expansion coefficient. Is small and can prevent cracks from extending. Thereby, it is possible to effectively relieve, absorb, and buffer the thermal stress or thermal strain generated during the manufacturing or operation of the semiconductor device 11, and there is no risk of deformation, modification, or destruction of each member, and stable over a long period of time. Excellent long-term reliability that can be operated. Furthermore, since the members are not directly joined to each other, it is not necessary to manage the flatness of the surface of each member more than necessary, and the manufacturing is not complicated and the cost is not increased. In addition, since the semiconductor device 11 can be operated even at a temperature exceeding the melting point of the solder, it is possible to provide the semiconductor device 11 that can operate at a high temperature that has not been conventionally available.

  Further, by dispersing the second phase 42 of the stress buffer portion 40 in the Al matrix 41, the Al matrix 41 takes a network structure, and the presence of the second phase 42 impairs heat conduction and conductivity. In addition to being able to minimize the occurrence of this, it is possible to ensure sufficient ductility.

  The stress buffer portion 40 is made of 3-12 at. %, The weight can be reduced and the cost can be reduced as compared with the case of X = Ba. Further, Ca has a large effect of reducing the elastic modulus with respect to Sr, and can be reduced in cost. Ca amount is 3 to 12 at. %, The effect of preventing the extension of cracks is sufficiently obtained, and sufficient reliability can be secured. The Ca content is 12 at. %, The thermal conductivity and conductivity are not deteriorated, and sufficient performance of the apparatus can be secured.

  Further, by making the electrical conductivity of the wiring metal layer 50 larger than the electrical conductivity of the stress buffering portion 40, even if the stress buffering portion 40 is provided, the decrease in the electrical conductivity is suppressed and the highly efficient semiconductor device 11 can be obtained. it can.

  Further, by forming the wiring metal layer 50 from Al or an Al alloy, the wiring metal layer 50 is made of a material having high thermal conductivity and high conductivity, and the semiconductor device 11 with higher efficiency can be obtained. In addition, since a brittle intermetallic compound is not formed at the interface between the stress buffering portion 40 and the wiring metal, the semiconductor device 11 having excellent long-term reliability can be obtained.

Although the semiconductor device 11 in which the stress buffering portion 40 is provided between the semiconductor substrate 20 and the insulating ceramic plate 30 is shown, the present invention is not limited to this case. The stress buffering part 40 exhibits the effect of the buffer function by a low Young's modulus and a low linear expansion coefficient, and the life improvement by the crack progress suppression by a multiphase structure. For this purpose, the stress buffering section 40 is either (a) between the semiconductor chip 20 and the insulating ceramic plate 30 or (b) between the semiconductor chip 20 and the insulating ceramic plate 30 and on both sides of the insulating ceramic plate 30. Of these, it is sufficient if it is provided in direct contact with the surface opposite to the side on which the semiconductor chip 20 is mounted. Furthermore, in addition to the form in which the stress buffering portion 40 is directly fixed to the semiconductor chip 20 and the insulating ceramic plate 30, a form in which the stress buffering part 40 is fixed indirectly through another intermediate layer may be employed. Here, the other intermediate layer is provided for the purpose of reducing the contact resistance of the semiconductor chip, for example, when a thin layer made of Ni or the like in contact with the semiconductor chip, or when a wiring metal layer is bonded to an insulating ceramic plate A layer made of the brazing material used can be exemplified.

Further, it is sufficient that the stress buffer portion 40 is formed of a structure including at least Al and the second phase. The alloy structure includes at least a first phase composed of Al and a second phase composed of Al ₄ X (X = at least one of alkaline earth metal elements), and further includes an Al phase and Al ₄ X (X = alkali). It may contain other phases (phases of the third phase or more) other than the phase (at least one kind of earth metal element). That is, it may be a two-phase structure composed only of the Al phase and Al ₄ X (X = at least one of the alkaline earth metal elements) phase, or the Al phase and Al ₄ X (X = alkaline earth metal element). It may be a three-phase structure or a multi-phase structure composed of one or more phases and another phase (one or more phases).

(Second Embodiment)
FIG. 8 is a cross-sectional view showing a semiconductor device 12 according to the second embodiment.

  The second embodiment is different from the first embodiment in which the stress buffer 40 and the wiring metal layer 50 are provided in that the stress buffer 40 also serves as a wiring metal layer.

  In the second embodiment, in addition to the operational effects of the first embodiment, all the wiring metal portions are the stress buffer portions 40, so the interface of different materials is reduced, and the risk of destruction at the interface is reduced. The semiconductor device 12 can be suppressed and can be further improved in reliability.

(Third embodiment)
FIG. 9A is a plan view showing the semiconductor device 13 according to the third embodiment, and FIG. 9B is a cross-sectional view taken along line 9B-9B in FIG. 9A.

  The third embodiment is a first embodiment in which the stress buffering portion 40 is disposed at a position where it abuts against the corner portion 21 of the semiconductor chip 20 and is disposed so as to abut against the entire back surface of the semiconductor chip 20. Is different.

  The stress buffering portion 40 of the present invention is desirably disposed at least at a position where it abuts on the corner portion 21 of the semiconductor chip 20. Thermal stresses or thermal strains generated during the manufacturing or operation of the semiconductor device 11 are concentrated near the corners 21 of the semiconductor chip 20. Further, the semiconductor is brittle and the vicinity of the corner portion 21 is easily damaged. For this reason, in order to ensure device reliability, it is preferable to dispose the stress buffering portion 40 at a position in contact with the corner portion 21 of the semiconductor chip 20. Al or Cu can be selected as the wiring metal.

  In the third embodiment, in addition to the effects of the first embodiment, the stress buffering portion 40 is disposed at a position where it abuts against the corner portion 21 of the semiconductor chip 20, so that the corner portion 21 of the semiconductor chip 20 is destroyed. Risks can be suppressed, and the semiconductor device 13 with even higher reliability can be provided. Furthermore, since the stress buffering portion 40 is disposed only at a position where it abuts against the corner portion 21 of the semiconductor chip 20, it is possible to achieve both high conductivity and high heat conduction by selecting Al or Cu as the wiring metal. Thus, the semiconductor device 13 having high heat dissipation can be obtained.

(Fourth embodiment)
FIG. 10 is a cross-sectional view showing a semiconductor device 14 according to the fourth embodiment.

  In the fourth embodiment, stress buffering is provided at three locations between the semiconductor chip 20 and the wiring metal layer 50, between the wiring metal layer 50 and the insulating ceramic plate 30, and between the insulating ceramic plate 30 and the back surface metal layer 60. This is different from the first embodiment in which the stress buffering portion 40 is provided only between the semiconductor chip 20 and the wiring metal layer 50 in that the portions 40a, 40b, and 40c are provided.

  Al is used as the wiring metal constituting the wiring metal layer 50. For this reason, a brittle intermetallic compound is not generated between the stress buffer portion 40a and the upper surface of the wiring metal layer 50 and at the interface between the lower surface of the wiring metal layer 50 and the stress buffer portion 40b. Therefore, the semiconductor device 14 with higher reliability can be obtained.

  Furthermore, by placing the stress buffering portions 40b and 40c at positions where the stress buffering portions 40b and 40c come into contact with the insulating ceramic plate 30, it is possible to achieve further effects. That is, since thermal stress is generated due to a difference in linear expansion coefficient, thermal stress is generated at the interface between the semiconductor chip 20 or the insulating ceramic plate 30 having a low linear expansion coefficient with respect to the metal and the metal layers 50 and 60. concentrate. Therefore, by disposing the stress buffer portions 40b and 40c between the insulating ceramic plate 30 which is a stress concentration portion other than the semiconductor chip 20 and the metal layers 50 and 60, the insulating ceramic plate 30 is broken or peeled off at the interface. Can be prevented, and a further reliability improvement effect can be exhibited.

  In the fourth embodiment, in addition to the effects of the first embodiment, since Al is used as the wiring metal constituting the wiring metal layer 50, the stress buffer 40a and the upper surface of the wiring metal layer 50 are It is possible to suppress the risk of breakage at the interface between the wiring metal layer 50 and the lower surface of the wiring metal layer 50 and the stress buffer portion 40b, and it is possible to provide the semiconductor device 14 with even higher reliability. Furthermore, since the stress buffering portions 40b and 40c are arranged at positions where they abut against the insulating ceramic plate 30, it is possible to prevent the edge ceramic plate 30 from being broken or peeled off at the interface. Can improve the performance.

(Fifth embodiment)
FIG. 11 is a cross-sectional view showing a semiconductor device 15 according to the fifth embodiment.

  The fifth embodiment is different from the fourth embodiment in that the area of the stress buffer portion 40 on the semiconductor chip 20 side is increased.

In the fifth embodiment, similarly to the brazing sheet, Al ₄ X (X = alkaline earth) is previously formed in Al constituting the stress buffer portions 40 and 40 on both surfaces of Al serving as the wiring metal. It is preferable to produce a stress buffering sheet in which a plate material having a structure in which at least one kind of metal-like element is dispersed is pressure-bonded with a clad or the like. By using this stress buffering sheet in the mounting process of the semiconductor device 15, the manufacturing cost of the semiconductor device 15 can be reduced.

  In the fifth embodiment, in addition to the effects of the fourth embodiment, the manufacturing cost of the semiconductor device 15 can be reduced by using a stress buffer sheet manufactured in advance in the mounting process of the semiconductor device 15.

(Sixth embodiment)
FIG. 12A is a cross-sectional view showing the semiconductor device 16 according to the sixth embodiment, and FIG. 12B is a diagram conceptually showing a multiphase structure constituting the stress buffering portion 40.

The sixth embodiment is different from the first embodiment in that the volume fraction of the second phase 42 in the stress buffer 40 is gradually reduced as it approaches the interface between the stress buffer 40 and the wiring metal layer 50. is doing.

  As described in the first embodiment, the conductivity of the wiring metal layer 50 with which the stress buffering portion 40 abuts is preferably larger than the conductivity of the stress buffering portion 40, and the wiring metal layer 50 is made of Al or Al. It is preferable to form from an alloy.

Furthermore, in the sixth embodiment, the structure control is performed so that the volume fraction of the second phase 42 in the stress buffer 40 gradually decreases as the interface between the stress buffer 40 and the wiring metal layer 50 is approached. It is. Specifically, Al is used as the wiring metal, but the amount of Al ₄ X (X = at least one of alkaline earth metal elements) in the vicinity of the interface between the wiring metal layer 50 and the stress buffer 40 is less than the wiring metal layer. The organization is controlled so as to gradually decrease toward 50. Thereby, stress concentration at the interface between the wiring metal layer 50 and the stress buffering portion 40 can be prevented. In addition, since the semiconductor device 16 has high conductivity and high heat dissipation and can effectively buffer thermal stress, the semiconductor device 16 having excellent reliability can be provided. The texture-controlled stress buffer 40 can be manufactured by sintering, for example.

  In the sixth embodiment, in addition to the functions and effects of the first embodiment, the following functions and effects are achieved. That is, since the structure control is performed so that the volume fraction of the second phase 42 in the stress buffer 40 gradually decreases as the interface between the stress buffer 40 and the wiring metal layer 50 is approached, the wiring metal layer 50 and the stress buffer The semiconductor device 16 can be made more excellent in long-term reliability by suppressing the stress concentration at the interface with 40.

(Seventh embodiment)
FIG. 13A is a cross-sectional view showing the semiconductor device 17 according to the seventh embodiment, and FIG. 13B conceptually shows a wiring metal layer 50 formed from a multiphase structure constituting the stress buffer portion 40. FIG.

  The seventh embodiment is different from the first embodiment in that the wiring metal layer 50 is also formed of a multiphase structure constituting the stress buffer portion 40, and is different from the sixth embodiment in that the structure is controlled. It is common.

The wiring metal layer 50 is formed of a multiphase structure constituting the stress buffering portion 40, but Al ₄ X (near the interface with the stress buffering portion 40 on the semiconductor chip 20 side and the interface with the insulating ceramic plate 30 ( The structure is controlled such that the amount of X = at least one of the alkaline earth metal elements gradually increases toward each interface. In addition, the structure of the wiring metal layer 50 is controlled so that the amount of Al ₄ X (X = at least one of alkaline earth metal elements) in the substantially central region gradually decreases toward the central region. Thereby, stress concentration on the interface with the semiconductor chip 20 side and the interface with the insulating ceramic plate 30 can be prevented. In the substantially central region of the wiring metal layer 50, high conductivity and high heat dissipation can be ensured. Since the semiconductor device 17 has high conductivity and high heat dissipation and can effectively buffer thermal stress, the semiconductor device 17 having excellent reliability can be provided. The texture-controlled stress buffer 40 can be manufactured by sintering, for example.

  In the seventh embodiment, in addition to the functions and effects of the first embodiment, the following functions and effects are achieved. That is, since the wiring metal layer 50 is formed from the multiphase structure constituting the stress buffering portion 40 and the structure is controlled, the stress concentration at the interface with the semiconductor chip 20 side and the interface with the insulating ceramic plate 30 can be suppressed. The semiconductor device 17 having excellent long-term reliability can be obtained.

It is sectional drawing which shows the package structure of the semiconductor device which concerns on the 1st Embodiment of this invention. 2A is a plan view showing the semiconductor device according to the first embodiment, and FIG. 2B is a cross-sectional view taken along line 2B-2B in FIG. 2A. Modulus when changing the volume fraction of Al 4 _Ca in Al, coefficient of linear expansion, thermal conductivity is a diagram illustrating a change in conductivity. As an example of a structure photograph of the stress buffer portion, it is an optical micrograph of a case where Al ₄ Ca in Al is contained at about 47% (Al-9 at.% Ca). It is a perspective view showing a FEM analysis model. It is a graph which shows the chip | tip generating stress when changing the elasticity modulus and linear expansion coefficient of a stress buffer part. It is a figure which shows notionally the double phase structure | tissue which comprises a stress buffer part. It is sectional drawing which shows the semiconductor device which concerns on 2nd Embodiment. FIG. 9A is a plan view showing a semiconductor device according to the third embodiment, and FIG. 9B is a cross-sectional view taken along line 9B-9B in FIG. 9A. It is sectional drawing which shows the semiconductor device which concerns on 4th Embodiment. It is sectional drawing which shows the semiconductor device which concerns on 5th Embodiment. FIG. 12A is a cross-sectional view showing a semiconductor device according to the sixth embodiment, and FIG. 12B is a diagram conceptually showing a multiphase structure constituting the stress buffering portion. FIG. 13A is a sectional view showing a semiconductor device according to the seventh embodiment, and FIG. 13B is a diagram conceptually showing a wiring metal layer formed from a multiphase structure constituting a stress buffering portion. is there.

Explanation of symbols

11-17 Semiconductor device,
20 Semiconductor substrate (semiconductor chip),
21 corners,
30 Insulating ceramic plate,
40, 40a-40c Stress buffering part,
41 Al matrix,
42 Phase 2,
50 wiring metal layer,
60 Back metal layer.

Claims (8)

A semiconductor substrate;
An insulating ceramic plate on which the semiconductor substrate is mounted;
(A) provided between the semiconductor substrate and the insulating ceramic plate ; or (b) the semiconductor substrate is mounted between the semiconductor substrate and the insulating ceramic plate and among both surfaces of the insulating ceramic plate. A stress buffering part that is provided in direct contact with the surface opposite to the side facing and relaxes thermal stress,
The semiconductor device, wherein the stress buffer portion is formed of a structure including at least Al and a second phase, and the second phase is Al ₄ X (X = at least one of alkaline earth metal elements).   The semiconductor device according to claim 1, wherein the second phase is dispersed in an Al matrix.   The stress buffer portion contains Ca at 3 to 12 at. 3. The semiconductor device according to claim 1, wherein the semiconductor device is made of an aluminum alloy containing 1%.   4. The semiconductor device according to claim 1, wherein the stress buffering portion is disposed at a position in contact with a corner portion of the semiconductor substrate.   The semiconductor device according to claim 1, wherein the stress buffering portion is disposed at a position in contact with the insulating ceramic plate. Further comprising a wiring metal layer provided so as to be in direct contact with or not in direct contact with the surface on which the semiconductor substrate is mounted among both surfaces of the insulating ceramic plate,
The stress buffer portion provided between the semiconductor substrate and the insulating ceramic plate is in contact with the wiring metal layer, and the conductivity of the wiring metal layer is larger than the conductivity of the stress buffer portion. The semiconductor device according to any one of the above.   The semiconductor device according to claim 6, wherein the wiring metal layer is made of Al or an Al alloy.   8. The semiconductor device according to claim 6, wherein the volume fraction of the second phase gradually decreases as it approaches the interface between the stress buffer portion and the wiring metal layer.