JP5192930B2 - Joining method - Google Patents

Description

  The present invention relates to a bonding method for bonding at least two semiconductor substrates on which semiconductor elements are formed.

  Conventionally, as shown in FIG. 6B, there has been proposed a semiconductor device in which two semiconductor substrates 1 and 2 each having a semiconductor element formed on one surface side are bonded by room temperature bonding (Patent Document 1). reference).

  Here, in the semiconductor device having the configuration shown in FIG. 6B, the first insulating layers 12a ′ and 22a ′ formed on the one surface of each of the semiconductor substrates 1 and 2, and the first insulating layer 12a. On the first through-hole wirings 15a and 25a penetrating in the thickness direction of each of ', 22a' and electrically connected to the wiring layers 13 and 23 of the semiconductor element, and on the first insulating layers 12a 'and 22a' The formed ground layers 19 and 29 that absorb radiation noise generated from the semiconductor element, and the second through wiring 15b that penetrates the ground layers 19 and 29 in the thickness direction and continues to the first through wiring 15a and 25a. , 25b, and second insulating layers 12b ′, 22b ′ that insulate the second through wirings 15b, 25b and the ground layers 19, 29 from each other.

In this method of manufacturing a semiconductor device, as shown in FIG. 6A, the first through-hole 12c is formed on the one surface of each of the semiconductor substrates 1 and 2 using photolithography technology, film formation technology, and lift-off technology. After performing the first insulating layer forming step for forming the first insulating layers 12a 'and 22a' through which ', 22c' is penetrated, the first insulating layers 12a 'and 22a' are penetrated in the thickness direction. In addition, first through wirings 15a and 25a that are electrically connected to the wiring layers 13 and 23 formed on the one surface side of the semiconductor substrates 1 and 2 are formed by a photolithography technique, a film forming technique, and a lift-off technique. 1 is formed, and then a ground layer is formed to form the ground layers 19 and 29 in which the second through holes 19c and 29c are penetrated by a photolithography technique, a film forming technique, and a lift-off technique. After performing the process, after performing a second through wiring forming process of forming second through wirings 15b and 25b that penetrate the ground layers 19 and 29 in the thickness direction and continue to the first through wirings 15a and 25a. A second insulating layer forming step of forming the second insulating layers 12b ′ and 22b ′ by embedding an insulating material between the second through wires 15b and 25b and the insides of the second through holes 19c and 29c. After that, after performing a flattening step of flattening the surface side of the second insulating layers 12b ′ and 22b ′ by polishing, the second through wirings 15b and 25b are overlapped to overlap each other. , 2 is applied with a compressive load at room temperature to join the semiconductor substrates 1 and 2 to each other, and a joining method for obtaining a semiconductor device having the configuration shown in FIG. 6B is employed. Here, in the planarization step, the second through wires 15b and 25b, the second insulating layers 12b ′ and 22b ′, and the ground layers 19 and 29 are polished simultaneously.
Japanese Patent No. 3532788

  However, in the bonding method described in Patent Document 1, in the planarization step, the polishing rate of the second through wirings 15b and 25b formed of metal as compared with the second insulating layers 12b ′ and 22b ′ made of an insulating material. In some cases, the second through wirings 15b and 25b are formed in a depressed shape as compared with the surrounding second insulating layers 12b ′ and 22b ′. Then, when the semiconductor substrates 1 and 2 are bonded to each other, a gap is generated in a bonding portion between the second through wirings 15b and 25b, and a conduction failure is likely to occur between the second through wirings 15b and 25b. There was a risk that the yield would decrease. In the planarization step, if the polishing rate is slowed down in order to ensure the flatness of the bonding surface of the second through wirings 15b, 25b, the throughput may decrease and the manufacturing cost may increase.

  This invention is made | formed in view of the said reason, The objective is to provide the joining method which can improve the yield of the joining process of semiconductor substrates.

The invention according to claim 1, in order to achieve the object, a joining method for joining at least two semiconductor substrates together which a semiconductor element is formed, the for each semi conductor substrate you joined together, wherein a planarization step of planarizing by CMP the surface of the semi-conductor substrate is formed on the side to be opposed to the insulating layer of the bonding partner in the semi conductor substrate, the thickness of the insulating layer in either before or after the flat tanker step after performing the through wiring forming step of forming a through wiring which is electrically connected to the semiconductor element through the direction, the through-wiring end face and of the insulating layer exposed on the table surface of the insulating layer after performing the bonding pad forming step of forming a bonding pad electrically connected to the penetrations wire to said surface, each of said for the junction formed on the surface of the insulating layer in a semi-conductor substrate Characterized in that the head together perform a bonding step of room-temperature bonding.

According to the present invention, the flattening step of flattening the surface of the semi-conductor substrate insulating layer formed on the side to be opposed to the joining partner by CMP in each semiconductor substrate, either before or after the flat tanker step wherein after performing the through wiring forming step of forming an electrically connected to the through wiring in the semiconductor device penetrating in the thickness direction of the insulating layer, the penetration wiring exposed on the table surface of the insulating layer in the electrically form a connected junction pad are in the through wiring on the surface of the end surface and the insulating layer, by room-temperature bonding pads to each other for the bonding, the yield of the bonding step of bonding the semi-conductor substrate to each other Can be improved.

According to a second aspect of the present invention, in the first aspect of the invention, the bonding pad forming step is performed on the adhesion improving metal film and the adhesion improving metal film for improving the adhesion to the insulating layer. setting the thickness of且one said a u film formed of a laminated film of a laminated Au film and forming the bonding pad is 500nm or less.

According to this invention, the bonding pad is constituted by a laminated film of an adhesion improving metal film for improving adhesion to the insulating layer and an Au film laminated on the adhesion improving metal film. and setting the thickness of且one said a u film since the 500nm or less, it is possible to improve the yield of the bonding process.

According to the present invention, the flattening step of flattening the surface of the semi-conductor substrate insulating layer formed on the side to be opposed to the joining partner by CMP in each semiconductor substrate, a flat tanker step after performing the through wiring forming step of forming a through wiring which is the penetrating in the thickness direction of the insulating layer electrically connected to the semiconductor device in either before or after, the exposed in table face side of the insulating layer electrically connected to form a junction pad in the through wiring on the end surface and the surface of the insulating layer of the through wiring, by room-temperature bonding pads to each other for the bonding, bonding for bonding the semi-conductor substrate to each other There is an effect that the yield of the process can be improved.

(Embodiment 1)
Hereinafter, the joining method of this embodiment is demonstrated based on Fig.1 (a)-(f).

  First, one surface side (semiconductor substrate) in which a semiconductor element (not shown) such as an IC and a wiring layer 1a electrically connected to the semiconductor element are formed in a semiconductor substrate (for example, a silicon substrate, an SOI substrate, etc.) 1 1, an insulating layer forming step is performed in which an insulating layer 12 made of a silicon oxide film is formed on the semiconductor substrate 2 to be bonded (the side facing the semiconductor substrate 2 (see FIGS. 1E and 1F)) (FIG. 1A). reference). Here, in the insulating layer forming step, it is necessary to form the insulating layer 12 at a temperature lower than the heat resistant temperature of the semiconductor element formed on the semiconductor substrate 1, and the insulating layer 12 is formed by a CVD method such as plasma CVD or thermal CVD. Is deposited. In addition, the film-forming method of the insulating layer 12 is not restricted to CVD method, For example, you may employ | adopt other methods, such as a SOG (Spin On Glass) coating method.

  By the way, the insulating layer 12 formed by the CVD method or the SOG coating method on the one surface side of the semiconductor substrate 1 on which the semiconductor element and the wiring layer 1a electrically connected to the semiconductor element are formed has surface flatness. Is relatively low. In the present embodiment, after the insulating layer forming step, by performing a first flattening step of flattening the surface of the insulating layer 12 formed on the one surface side of the semiconductor substrate 1 by CMP (Chemical Mechanical Polishing). The structure shown in FIG. In this first planarization step, CMP, which is relatively advantageous in terms of flatness after polishing, cleanliness, and cost, is employed as a polishing method. In addition, the surface of the insulating layer 12 formed on the one surface side of the semiconductor substrate 1 on which the semiconductor element is formed needs to have high flatness in consideration of a bonding process described later. Here, in the first planarization step, the RMS roughness is desirably 1.5 nm or less with respect to the planarity of the surface of the insulating layer 12, and a smaller value is preferable.

  After the above-described first planarization step, a through-hole forming step for forming a through-hole 12c that penetrates the insulating layer 12 in the thickness direction is performed using a photolithography technique and an etching technique. The through hole 12c is preferably perpendicular to the one surface of the semiconductor substrate 1 from the viewpoint of miniaturization, and is etched substantially perpendicularly. The shape of the through hole 12c is not limited to this, and other shapes may be adopted according to the specifications, cost, etc. of the semiconductor element.

  After the above-described through-hole forming step, through-holes 15 are formed inside the through-holes 12c by electrolytic plating so as to penetrate the insulating layer 12 in the thickness direction and to be electrically connected to the semiconductor element and the wiring layer 1a. A wiring formation process is performed. In addition, although Cu is employ | adopted as a material of the penetration wiring 15, it is not limited to Cu, For example, W, Al, or an alloy which has these as a main component is desirable from a viewpoint of resistance value. Further, polysilicon having good step coverage may be used as the material of the through wiring 15. Further, in the present embodiment, the electrolytic plating method is adopted in the through wiring forming step, but the present invention is not limited to this, and for example, depending on the material of the through wiring 15, for example, an electroless plating method or a CVD method. An optimal method may be selected from the above.

  After the above-described through-wiring forming step, a structure shown in FIG. 1C is obtained by performing a second flattening step in which the surface side of the insulating layer 12 is flattened by CMP. Here, in the second planarization step, CMP is adopted as a polishing method because it is relatively advantageous from the viewpoint of flatness after polishing, cleanliness, and cost. At this time, in the second planarization step, the surface roughness of the insulating layer 12 is important from the viewpoint of improving the yield in the bonding step described later, and the RMS roughness is 1.5 nm or less with respect to the flatness of the surface of the insulating layer 12. And smaller values are preferred.

  In the present embodiment, the first planarization step and the second planarization step are performed before and after the through-hole forming step and the through-wiring forming step, but only the first planarization step is performed and the second planarization step is performed. The planarization step may be omitted. Moreover, you may abbreviate | omit the 1st planarization process and perform only a 2nd planarization process among a 1st planarization process and a 2nd planarization process. However, when the first planarization step is omitted, in the second planarization step, it is desirable to perform planarization so that the RMS roughness is 1.5 nm or less with respect to the planarity of the surface of the insulating layer 12. Smaller values are preferred.

  After the above-described second planarization step, a bonding pad forming step is performed in which a bonding pad 14 that is electrically connected to the through wiring 15 is formed on the surface of the insulating layer 12 (see FIG. 1D). ). The bonding pad 14 can be formed using a material different from the material forming the through wiring 15. The through wiring 15 is formed of Cu, which is a low resistance material, and the bonding pad 14 is an insulating layer. From a laminated film of a Ti film (not shown), which is an adhesion improving metal film for improving adhesion to the adhesive film 12, and an Au film (not shown) laminated on the adhesion improving metal film It is configured. That is, the surface side of the bonding pad 14 is made of an Au film, and a natural oxide film is hardly formed on the surface of the bonding pad 14. Here, the set film thickness of the Au film is set to 500 nm or less.

  On the other hand, in the above-described semiconductor substrate (for example, a silicon substrate, an SOI substrate, etc.) 2, a semiconductor substrate 2 in which a semiconductor element (not shown) such as an IC and a wiring layer 2a electrically connected to the semiconductor element are formed. An insulating layer forming step of forming an insulating layer 22 on one surface side of the semiconductor substrate 2 (a surface side facing the semiconductor substrate 1 to be bonded (see FIG. 1E)), on the one surface side of the semiconductor substrate 2 A first planarization step of planarizing the surface of the formed insulating layer 22 by CMP, a through hole forming step of forming a through hole 22c penetrating in the thickness direction in the insulating layer 22, and the semiconductor element inside the through hole 22c A through-wiring forming step for forming the through-wiring 25 electrically connected to the second wiring, a second planarization step for flattening the surface side of the insulating layer 22 by CMP, and an electric current to the through-wiring 25 on the surface of the insulating layer 22. By performing the bonding pad forming step of forming a bonding pad 24 which is connected successively to obtain a structure shown in FIG. 1 (e).

  Then, after the bonding pad forming process described above is completed for each of the semiconductor substrates 1 and 2, a bonding process is performed in which the bonding pads 14 and 24 of the semiconductor substrates 1 and 2 are bonded at room temperature (FIG. 1 ( f)). In the normal temperature bonding, before bonding, the bonding pads 14 and 24 which are the bonding surfaces of the semiconductor substrates 1 and 2 are opposed to each other as shown in FIG. The surface of 24 is irradiated with argon plasma, ion beam or atomic beam in vacuum to clean and activate each bonding surface, and then the surfaces of bonding pads 14 and 24 are brought into contact with each other at room temperature. The structure shown in FIG. 1F is obtained by applying an appropriate load and bonding the bonding pads 14 and 24 at room temperature. Note that the method of cleaning and activating the surfaces of the bonding pads 14 and 24 is not limited to the above-described method, and may be appropriately selected in consideration of the specifications of the semiconductor element, productivity, and the like.

  Thus, the first planarization step of planarizing the surfaces of the insulating layers 12 and 22 formed on the semiconductor substrate 1 and 2 on the side facing the semiconductor substrate 2 and 1 to be bonded with each other by the CMP, After the planarization step, after performing the through wiring forming step of forming the through wiring 15 that penetrates in the thickness direction of the insulating layers 12 and 22 and is electrically connected to the semiconductor element, the surface of the insulating layers 12 and 22 is formed. A second flattening step is performed by flattening by CMP, and thereafter, bonding pads 14 and 24 are formed on the surfaces of the insulating layers 12 and 22, and the bonding pads 14 and 24 are bonded to each other at room temperature. The yield can be improved. Moreover, since the surface side of the bonding pads 14 and 24 is made of an Au film, it is difficult to form a natural oxide film on the surfaces of the bonding pads 14 and 24, and the occurrence of poor conduction can be suppressed. The yield of the joining process can be improved.

  As described above, the bonding pads 14 and 24 are bonded to each other at room temperature, so that even if the end surfaces of the through wirings 15 and 25 exposed on the surface side of the insulating layers 12 and 22 have low flatness, Since the influence on the yield is small, there is no need to slow down the polishing rate in order to improve the flatness of the end faces of the through wirings 15 and 25 in the second flattening step, thereby suppressing a reduction in throughput and reducing the manufacturing cost. The rise can be prevented. Further, as described above, if any one of the first planarization step and the second planarization step is omitted, the throughput can be improved and the manufacturing cost can be reduced.

  Further, if the through wirings 15 and 25 are made of Au, Au atoms from the through wirings 15 and 25 to the semiconductor element side formed on the semiconductor substrates 1 and 2 may diffuse, leading to significant deterioration of the semiconductor element. However, in this embodiment, Cu is used as the material of the through wirings 15 and 25, and Au is used only for the bonding pads 14 and 24. Therefore, the semiconductor element is formed by diffusion of Au atoms to the semiconductor element side. Can be prevented.

  Here, the result of examining the set film thickness of the Au film will be described.

  A first silicon wafer for bonding test in which an insulating layer, a Ti film, and an Au film are laminated on the entire surface of one surface side of the first silicon wafer that is the basis of the semiconductor substrate 1, and a second that is the basis of the semiconductor substrate 2 The second silicon wafer for bonding test in which the insulating layer, the Ti film, and the Au film are laminated on the entire surface of the one surface side of the silicon wafer has the same Au film thickness (Au film thickness) and various Au film thicknesses. After preparing a bonding step by room temperature bonding method, the ratio of the bonding area between the first bonding test silicon wafer and the second bonding test silicon wafer to the wafer area by ultrasonic microscopy is determined. Rated as a rate. As a result, it has been found that the junction area ratio decreases as the thickness of the Au film increases, and that if the thickness of the Au film is 500 nm or less, a value greater than 90% can be obtained as the junction area ratio. By the way, in order to improve the overall yield in manufacturing the semiconductor device, it is necessary to improve the yield for each process, and it is desirable to set the yield for each process to a value of 90% or more. Therefore, it can be seen that the set film thickness of the Au film of each bonding pad 14, 24 may be set to 500 nm or less in order to set the yield of the bonding process to 90% or more. Note that the lower limit value of the film thickness of the Au film is set to 10 nm or more because if the Au film becomes too thin, the film continuity of the Au film is lowered and the resistance is increased and conduction failure is likely to occur. Is desirable.

  Therefore, by setting the set film thickness of the Au film constituting the bonding pads 14 and 24 to 500 nm or less, a value larger than 90% can be obtained as the above-mentioned bonding area ratio in the bonding pads 14 and 24. The yield of the joining process can be improved.

  In this embodiment, the surface side of the bonding pads 14 and 24 is formed of an Au film. However, the present invention is not limited to this. For example, an Al film, a Cu film, a Pt film, or the like is used. Also good. Further, the bonding pads 14 and 24 may be formed of different materials.

(Embodiment 2)
Hereinafter, the joining method of this embodiment is demonstrated based on Fig.2 (a)-(g).

  In the semiconductor substrate bonding method of the present embodiment, as described in the first embodiment, the semiconductor substrate 1 is bonded to one surface side of the semiconductor element 1 and the wiring layer 1a (semiconductor substrate 1). In the step of forming an insulating layer 12 on the surface facing the semiconductor substrate 2 to be bonded (refer to FIGS. 2F and 2G), the insulating layer 12 is formed on the one surface side of the semiconductor substrate 1. A first flattening step of flattening the surface of the layer 12 by CMP, a through hole forming step of forming a through hole 12c penetrating in the thickness direction in the insulating layer 12, and electrically connecting the semiconductor element to the inside of the through hole 12c. A through wiring forming step for forming the through wiring 15 to be connected, a second planarization step for flattening the surface side of the insulating layer 12 by CMP, and electrically connected to the through wiring 15 on the surface of the insulating layer 12. Bonding pad 4 to obtain the structure shown in FIG. 2 (f) by sequentially performing the bonding pad forming step of forming a.

  On the other hand, the semiconductor substrate 2 is formed by forming an insulating layer 2b between the one surface on which the semiconductor element is formed and the wiring layer 2a. After the first insulating layer forming step of forming the insulating layer 22 made of a silicon oxide film on the one surface side where the semiconductor element and the wiring layer 2a are formed, the photolithography technique and the etching technique are used to make the semiconductor substrate 2 A through hole forming step is performed in which the through hole 2c penetrating in the thickness direction is formed by etching (see FIG. 2A). Here, the through hole 2c is preferably perpendicular to the one surface of the semiconductor substrate 2 from the viewpoint of miniaturization, and is etched substantially perpendicularly. The shape of the through hole 2c may be other shapes depending on the specifications and cost of the semiconductor element. Further, in order to shorten the time required for the through hole forming step and reduce the length of the through hole 2c, the semiconductor substrate 2 may be polished and thinned in advance.

  After performing the above-described through hole forming step, a second insulating layer forming step is performed in which insulating layers 2d and 2e made of a silicon oxide film are formed on the other surface of the semiconductor substrate 2 and the inner peripheral surface of the through hole 2c (FIG. 2 (b)). The insulating layers 2d and 2e are formed by a CVD method such as plasma CVD or thermal CVD, as in the first insulating layer forming step.

  After performing the second insulating layer forming step described above, a third flattening step is performed in which the surface of the insulating layer 2e formed on the other surface side of the semiconductor substrate 2 is flattened by CMP (FIG. 2C). )reference). In addition, the surface of the insulating layer 2e is required to have high flatness in consideration of a bonding process described later. Here, in the third planarization step, the RMS roughness is desirably 1.5 nm or less with respect to the planarity of the surface of the insulating layer 2e, and a smaller value is preferable.

  After performing the above-mentioned 3rd planarization process, the penetration wiring formation process which forms penetration wiring 25 electrically connected to wiring layer 2a inside penetration hole 2c by electrolytic plating is performed. As for the material and forming method for forming the through wiring 25, other materials and other forming methods may be adopted as described in the through wiring forming process of the first embodiment.

  After performing the above-described through wiring formation process, a structure shown in FIG. 2D is obtained by performing a fourth planarization process in which the surface side of the insulating layer 2e is planarized by CMP.

  In the present embodiment, the third flattening step and the fourth flattening step are performed on the semiconductor substrate 2 before and after the through wiring forming step, but only the third flattening step is performed and the fourth flattening step is performed. The forming step may be omitted. In addition, only the fourth planarization step may be performed in the third planarization step and the fourth planarization step, and the third planarization step may be omitted. However, when the third planarization step is omitted, in the fourth planarization step, it is desirable to perform planarization so that the RMS roughness is 1.5 nm or less with respect to the planarity of the surface of the insulating layer 2e. Smaller values are preferred.

  After performing the above-described fourth planarization step, a bonding pad forming step is performed in which a bonding pad 24 electrically connected to the through wiring 25 is formed on the surface of the insulating layer 2e (FIG. 2E). )reference). Here, the bonding pad 24 can be formed using a material different from the material of the through wiring 25, the through wiring 25 is formed of Cu, which is a low resistance material, and the bonding pads 14 and 24 are insulated. Laminated film of Ti film (not shown), which is an adhesion improving metal film for improving adhesion to layer 2e, and Au film (not shown) laminated on the adhesion improving metal film It is composed of Therefore, an Au film is formed on the surface side of the bonding pad 24, and a natural oxide film is hardly formed on the surface of the bonding pad 24. Here, the set film thickness of the Au film is set to 500 nm or less.

  After performing the above-described bonding pad forming step, the bonding pad 14 formed on the insulating layer 12 of the semiconductor substrate 1 and the bonding pad 24 formed on the insulating layer 2e of the semiconductor substrate 2 are bonded at room temperature. A joining step is performed (see FIGS. 2F and 2G). In the normal temperature bonding, the surfaces of the bonding pads 14 and 24 that are the bonding surfaces are cleaned and activated before bonding, and then the surfaces of the bonding pads 14 and 24 are brought into contact with each other to form the semiconductor substrate 1. , 2 are joined together.

  Thus, a first planarization step for planarizing the surfaces of the insulating layers 12 and 2e formed on the side facing the semiconductor substrates 2 and 1 to be bonded to each of the semiconductor substrates 1 and 2 by CMP, After the third planarization step, the first planarization step, and the third planarization step, through wirings 15 and 25 penetrating in the thickness direction of the insulating layers 12 and 2e and electrically connected to the semiconductor element After performing the through-wiring forming step for forming the insulating layer 12, the second planarizing step and the fourth planarizing step for planarizing the surfaces of the insulating layers 12, 2e by CMP, and then the insulating layers 12, 2e Since the bonding pads 14 and 24 of the semiconductor substrates 1 and 2 are bonded to each other after the bonding pads 14 and 24 are formed on the surface, the yield of the bonding process can be improved. Moreover, since the surface side of the bonding pads 14 and 24 is made of an Au film, it is difficult to form a natural oxide film on the surfaces of the bonding pads 14 and 24, and the occurrence of poor conduction can be suppressed. The yield of the joining process can be improved.

  Further, in the bonding method of this embodiment, as described above, the bonding pads 14 and 24 are bonded to each other so that the end faces of the through wirings 15 and 25 exposed on the surface side of the insulating layers 12 and 2e have flatness. Even if it is low, since the influence on the yield of the bonding process is small, the polishing rate is reduced in order to improve the flatness of the end faces of the through wirings 15 and 25 in the second flattening process and the fourth flattening process. This is unnecessary, and it is possible to suppress a decrease in throughput and prevent an increase in manufacturing cost. Further, if any one of the third planarization step and the fourth planarization step is omitted, the throughput can be improved and the manufacturing cost can be reduced.

(Embodiment 3)
Hereinafter, the joining method of this embodiment is demonstrated based on Fig.3 (a)-(c), Fig.4 (a), (b). In this embodiment, the semiconductor substrate 2 is bonded to the one surface side of the semiconductor substrate 1 described in the first embodiment, and further, the semiconductor substrate 3 is bonded to the semiconductor substrate 2 on the side opposite to the semiconductor substrate 1.

  In the bonding method of the present embodiment, as described in the first embodiment, the semiconductor substrate 1 is bonded to the one surface side where the semiconductor element and the wiring layer 1a are formed (the bonding partner in the semiconductor substrate 1). An insulating layer forming step of forming an insulating layer 12 on the surface facing the semiconductor substrate 2 (see FIG. 3A), the surface of the insulating layer 12 formed on the one surface side of the semiconductor substrate 1 by CMP A first flattening step for flattening, a through hole forming step for forming a through hole 12c penetrating in the thickness direction in the insulating layer 12, and a through wiring 15 electrically connected to the semiconductor element inside the through hole 12c. A through-wiring forming step to be formed; a second flattening step of flattening the surface side of the insulating layer 12 by CMP; and a bonding pad 14 electrically connected to the through-wiring 15 is formed on the surface of the insulating layer 12 For joining Sequentially performed a head-forming step. Here, the bonding pad 14 of the semiconductor substrate 1 includes a Ti film that is an adhesion improving metal film for improving the adhesion to the insulating layer 14 and an Au film laminated on the adhesion improving metal film. The set film thickness of the Au film is 500 nm or less.

  On the other hand, the semiconductor substrate 2 is formed by forming an insulating layer 2b between one surface on which the semiconductor element is formed and the wiring layer 2a. The semiconductor element is formed on the semiconductor substrate 2. After the first insulating layer forming step of forming the insulating layer 22 on the one surface side, a through hole forming step of forming a through hole 2c penetrating from the surface of the insulating layer 22 to the other surface of the semiconductor substrate 2 is performed. After that, a second insulating layer forming step for forming insulating layers 2d and 2e on the other surface of the semiconductor substrate 2 and the inner peripheral surface of the through hole 2c is performed, and then the semiconductor element is electrically connected to the inside of the through hole 2c. A through-wiring forming process for forming the through-wiring 25 to be connected is performed. And after performing the 3rd planarization process which planarizes the surface side of the insulating layer 2e by CMP, it is the 1st bonding pad 24a electrically connected to the penetration wiring 25 on the said surface of the insulating layer 2e. A first bonding pad forming step for forming the substrate is performed. Thus, the structure as shown in FIG. 3A is obtained for the semiconductor substrate 2. In the second insulating layer forming step, insulating layers 2d and 2e made of a silicon oxide film are formed on the other surface of the semiconductor substrate 2 and the inner peripheral surface of the through hole 2c, but are formed inside the through hole 2c. The insulating layer 2d is formed by, for example, a thermal oxidation method. In addition, the first bonding pad 24a is composed of a Ti film, which is an adhesion improving metal film for improving adhesion to the insulating layer 2e, and an Au film laminated on the adhesion improving metal film. It is composed of a laminated film, and the set film thickness of the Au film is 500 nm or less.

  Then, after the bonding pad formation process is performed on the semiconductor substrate 1 and after the first bonding pad formation process is performed on the semiconductor substrate 2, the semiconductor substrate 1 is formed on the insulating layer 12. 3B is performed by performing a first bonding step in which the bonding pad 14 thus formed and the first bonding pad 24a formed on the insulating layer 2e of the semiconductor substrate 2 are bonded at room temperature. obtain.

  After the first bonding step, a structure shown in FIG. 3C is obtained by performing a fourth flattening step in which the surface side of the insulating layer 22 is flattened by CMP. Thereafter, a second bonding pad forming step for forming a second bonding pad 24 b electrically connected to the through wiring 25 on the surface of the insulating layer 22 is performed. Here, the second bonding pad 24b includes a Ti film, which is an adhesion improving metal film for improving adhesion with the insulating layer 22, and an Au film laminated on the adhesion improving metal film. The set film thickness of the Au film is 500 nm or less.

  The semiconductor substrate 3 is formed by forming an insulating layer 3b between one surface on which a semiconductor element such as an IC is formed and a wiring layer 3a electrically connected to the semiconductor element. 3, a penetration that penetrates from the surface of the insulating layer 32 to the other surface of the semiconductor substrate 3 after the third insulating layer forming step of forming the insulating layer 32 on the one surface side where the semiconductor element is formed. After performing the through hole forming step of forming the hole 3c by etching, a fourth insulating layer forming step of forming insulating layers 3d and 3e on the other surface of the semiconductor substrate 3 and the inner peripheral surface of the through hole 3c is performed. Thereafter, a through-wiring forming process for forming a through-wiring 35 that penetrates in the thickness direction of each of the insulating layer 32 and the insulating layer 3e and is electrically connected to the semiconductor element is performed, and then the surface side of the insulating layer 3e is formed by CMP. flat A third bonding pad forming step for forming a third bonding pad 34a electrically connected to the through wiring 35 on the surface of the insulating layer 3e after performing the fifth flattening step. Do. Thereafter, after performing a sixth flattening step of flattening the surface side of the insulating layer 32 by CMP, a fourth bonding pad 34b electrically connected to the through wiring 25 on the surface of the insulating layer 32. The structure shown in FIG. 4A is obtained by performing the fourth bonding pad forming step for forming the. Here, the third bonding pad 34a and the fourth bonding pad 34b are formed of the Ti film, which is an adhesion improving metal film for improving the adhesion between the insulating layer 3e and the insulating layer 32, and the adhesion. It is constituted by a laminated film with an Au film laminated on the metal film for improvement, and the set film thickness of the Au film is 500 nm or less.

  Then, after the second bonding pad forming process is performed on the semiconductor substrate 2 and after the fourth bonding pad forming process is performed on the semiconductor substrate 3, the second of the semiconductor substrate 2 is performed. 4B is formed by bonding the two semiconductor substrates 2 and 3 by performing a second bonding step in which the bonding pads 24b of the semiconductor substrate 3 and the third bonding pads 34a of the semiconductor substrate 3 are bonded at room temperature. The structure shown in FIG.

  In the bonding method of this embodiment, the thickness of the semiconductor substrates 2 and 3 is determined after the fifth insulating layer forming step of forming the insulating layers 22 and 32 on the one surface side with respect to the semiconductor substrates 2 and 3. A through hole forming step of forming first through holes 2c, 3c penetrating in the direction by etching, and then the other surface side of the semiconductor substrates 2, 3 on which the insulating layers 22, 32 are formed on the one surface side And after performing the insulating layer formation process which forms insulating layer 2d, 2e, 3d, 3e in the internal peripheral surface of the 1st through-hole 2c, the surface side of the insulating layers 22 and 32 is planarized by CMP. After performing the flattening process, the insulating layer 2e, 3e is penetrated in the thickness direction, and the through wiring forming process for forming the first through wiring 25a, 35a electrically connected to the semiconductor element is performed. 2nd penetration which penetrates 22 and 23 in thickness direction After performing the through-hole forming step of forming 22c and 32c by etching, and after performing the eighth flattening step of flattening the surfaces of the insulating layers 22 and 32 by CMP, in the thickness direction of the insulating layers 22 and 32 A second through-wiring forming process is performed to form second through-wirings 25b and 35b that penetrate and are electrically connected to the semiconductor element, and then a first bonding pad is formed on each of the semiconductor substrates 2 and 3 First bonding pad forming step and third bonding pad forming step for forming 24a and third bonding pad 34a, and second bonding pad 24b and fourth bonding pad 34b for forming second bonding pad 34b. After the bonding pad forming step 2 and the fourth bonding pad forming step 2 are performed, the bonding pad 14 of the semiconductor substrate 1 and the first bonding pad 24a of the semiconductor substrate 2 are bonded. While performing a 1st joining process, the 2nd joining process of joining the 2nd bonding pad 24b of the semiconductor substrate 2 and the 1st joining pad 34a of the semiconductor substrate 3 is performed, and the structure shown in FIG. 5 is obtained. It may be a thing.

  Here, in the structure shown in FIG. 4B, through wirings 25 and 35 penetrating from the surface side of the insulating layers 22 and 32 to the surface side of the insulating layers 2e and 3e are formed on both surface sides of the semiconductor substrates 2 and 3. 5 is connected to the bonding pads 24a and 24b and the bonding pads 34a and 34b, the structure shown in FIG. 5 has the bonding pads 24a and 24b and the bonding pads 34a and 34b to each other. The difference is that the structure is connected via the wiring layers 2a and 3a.

  Thus, after performing the first planarization step of planarizing the surface of the insulating layer 12 formed on the surface of the semiconductor substrate 1 facing the semiconductor substrate 2 to be bonded and the through-wiring forming step, the insulation is performed. The insulating layer 2e formed after the second planarization step for planarizing the surface of the layer 12 and on the surface side of the semiconductor substrate 2 facing the semiconductor substrate 1 to be bonded is formed in the thickness direction. After performing the penetrating wiring forming step, the third planarizing step for planarizing the surface of the insulating layer 2e is performed, and then the bonding pads 14 and 24a are formed on the surfaces of the insulating layers 12 and 2e. Since the bonding pads 14 and 24a are bonded to each other, the yield of the first bonding process can be improved. In addition, a fourth planarization step and a fifth planarization step of planarizing the surfaces of the insulating layers 22 and 3e formed on the surface of the semiconductor substrates 2 and 3 facing the semiconductor substrates 3 and 2 to be bonded are provided. A through-wiring forming process for forming through-wirings 25 and 35 that penetrate through the insulating layers 22 and 3e in the thickness direction and are electrically connected to the semiconductor element before the fourth and fifth flattening processes. Since the bonding pads 24b and 34a are formed on the surfaces of the insulating layers 22 and 3e and then the bonding pads 24b and 34a are bonded to each other, the yield of the second bonding process is increased. Can be improved.

  Further, as described above, by bonding the bonding pad 14 of the semiconductor substrate 1 and the bonding pad 24a of the semiconductor substrate 2, and the bonding pad 24b of the semiconductor substrate 2 and the bonding pad 34a of the semiconductor substrate 3, respectively. Even if the flatness of the end faces of the through wirings 15, 25, 35 exposed on the surfaces of the insulating layers 12, 2e, 22, 3e, 32 is low, the influence on the yield of the bonding process is small, so that the second planarization is performed. There is no need to slow down the polishing rate in order to improve the flatness of the end faces of the through-wirings 15, 25, and 35 in the process through the seventh flattening process, thereby suppressing a decrease in throughput and preventing an increase in manufacturing cost. Can do.

  In the second bonding step, for example, a bonding method using room temperature bonding that does not require heating is employed unlike eutectic bonding, diffusion bonding, anodic bonding, and the like. , 2 and 3 have almost no residual stress or strain. Therefore, even if the first bonding step or the second bonding step is performed a plurality of times on the semiconductor substrates 1, 2, 3, the semiconductor element is deteriorated due to heat, and the stress or strain generated in the semiconductor substrates 1, 2, 3 Degradation of the semiconductor substrate 1, 2, 3 due to the Thus, it is possible to realize a structure in which three or more semiconductor substrates (not shown) having the same structure as the semiconductor substrates 2 and 3 are bonded to the semiconductor substrate 1 and integrated.

  Here, the order of the flattening step, the through hole forming step, the through wiring forming step, and the bonding pad forming step is not limited to the order of the present embodiment, and the constituent materials in the semiconductor substrates 1, 2, and 3 You may select suitably according to the specification of a semiconductor element, etc.

FIG. 3 is a main process cross-sectional view for explaining the joining method of the first embodiment. FIG. 10 is a main process sectional view for explaining the joining method of the second embodiment. FIG. 10 is a main process cross-sectional view for explaining a joining method according to a third embodiment. It is principal process sectional drawing for demonstrating the joining method same as the above. It is sectional drawing for demonstrating the other joining method same as the above. It is principal process sectional drawing for demonstrating the joining method of a prior art example.

Explanation of symbols

1, 2, 3 Semiconductor substrate 12, 22, 2e, 32, 3e Insulating layers 14, 24, 24a, 24b, 34a, 34b Bonding pads 15, 25, 25a, 25b, 35, 35a, 35b Through wiring

Claims (2)

A bonding method for bonding at least two semiconductor substrates together which a semiconductor element is formed, a surface which faces the the respective semiconductors substrates, the semi-conductor substrate of the bonded mating in the semi-conductor substrate joined together a planarization step of planarizing by CMP the surface of the formed on the side insulating layers, the penetrating in the thickness direction of the insulating layer through which is electrically connected to the semiconductor device in either before or after the flat tanker step after performing a through wiring formation process of forming the wiring, junction electrically connected to the through wiring end face and the penetrations wire to the surface of the insulating layer exposed on the table surface of the insulating layer after performing the bonding pad forming step of forming a use pad, to carry out each of the bonding step of the junction pads between which is formed on the surface of the insulating layer in a semi-conductor substrate to the room temperature bonding Bonding method and butterflies. The bonding pad forming step, one且is constituted by a laminated film of an Au film stacked on the insulating layer for improving adhesion metal film for improving the adhesion between the said improving adhesion metal film joining method of claim 1, wherein the set thickness of the a u film and forming the bonding pad is 500nm or less.

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