JP5204040B2 - Transmission circuit and parameter adjustment method - Google Patents

Description

  The present invention relates to a transmission circuit and a parameter adjustment method, and more particularly to a technology for transmitting and receiving signals between LSIs via signal lines, and more particularly to a technology for adjusting parameters related to transmission and reception accuracy.

  In a circuit using a plurality of LSIs, communication between LSIs is performed via signal lines. The LSI on the transmission side outputs a high / low voltage from the signal line in a predetermined cycle according to the information to be transmitted. The LSI on the receiving side recognizes the received signal during a period when the voltage change of the signal line is stable. That is, during that period, when the voltage of the received signal is higher than a preset threshold voltage, it is recognized as high, and when it is low, it is recognized as low.

  On the other hand, as a technique for signal transmission between LSIs in recent years, simultaneous bidirectional signal transmission (hereinafter, referred to as “SBTL”) can be cited. FIG. 8 is an explanatory diagram showing an outline of simultaneous bidirectional signal transmission. The two LSIs shown in the upper part of the figure transmit and receive signals via one SBTL signal line. Each LSI is provided with a functional circuit, that is, a normal logic circuit that realizes a function unique to the LSI, and an SBTL transmission / reception unit for realizing SBTL. The SBTL transmission / reception unit further includes a transmission unit and a reception unit.

  In the lower part of the figure, the principle of SBTL is shown schematically. In the LSI shown on the left side, the illustrated high (H) / low (L) transmission signal and reception signal are simultaneously transmitted and received. The signal on the SBTL signal line is a signal obtained by combining the transmission signal and the reception signal (hereinafter, this combined signal may be referred to as an SBTL signal), and is high (H), middle (M), and low (L). The three values are taken. For example, in the sections a and b where one of the transmission signal and the reception signal is high (H) and the other is low (L), the middle (M) is obtained. In the section c in which both are low (L), it becomes low (L). In the section d in which both are high (H), it becomes high (H). Identification of ternary high (H) and middle (M) and identification of middle (M) and low (L) in the SBTL signal is performed based on threshold voltages Thm and Tml, respectively. In other words, this threshold voltage is, in other words, a voltage serving as a reference when quantizing the SBTL signal. Here, quantization means that the signal is binarized, ternarized, or multi-valued. The LSI can extract the reception signal by subtracting the transmission signal from the SBTL signal.

  In order to increase the transmission amount of such an SBTL signal per unit time, it is necessary to transmit at a high frequency or use a plurality of signal lines in a bundle. In such SBTL, in order to improve the recognition accuracy of a signal, it is important to correctly adjust the recognition timing of the signal and the threshold voltage used for the recognition.

  FIG. 9 is an explanatory diagram showing the relationship between the signal waveform of the transmission signal and the reception signal and the signal waveform of the SBTL signal. Consider a case where a transmission signal and a reception signal are transmitted in a certain cycle CYL. It is assumed that the cycle of the reception signal is shifted by the time Dc from the cycle of the transmission signal. At this time, since the SBTL signal is a signal obtained by synthesizing the transmission signal and the reception signal, the voltage becomes unstable in the interval Pu in which one of the voltages changes, and the signal cannot be correctly recognized. Therefore, it is necessary to perform the above adjustment in order to recognize the signal in the period Ps in which the voltage change formed between the voltage change point of the transmission signal and the voltage change point of the reception signal is stable. Hereinafter, such a period Ps is referred to as a window period.

In order to increase the signal transmission reliability by widening the window period in which the voltage change is stable, it is necessary to narrow the section Pu. Hereinafter, such a period Pu is referred to as a phase difference.
As described above, for example, techniques described in Patent Document 1 and Patent Document 2 described below are known as techniques for adjusting the signal recognition timing and the threshold voltage used for the recognition.

In the technology of Patent Document 1, one LSI can transmit a known adjustment pattern to the other LSI, and can receive a known adjustment pattern transmitted from the other LSI and recognize the adjustment pattern correctly. As described above, the threshold voltage is adjusted by changing the resistance setting value of the variable resistor. In addition, in one LSI, the recognition timing is adjusted by changing the delay (delay amount) in the variable delay layer on the receiving side stepwise so that the adjustment patterns can be recognized in the window period.
In the technique of Patent Document 2, the delay in the variable delay layer on the transmission side is changed stepwise so that the window period can be maximized using these adjustment patterns, and the survey results are accumulated comprehensively. Therefore, the phase difference is adjusted to be minimum.

JP 2005-20494 A JP 2006-340037 A

  In recent years, with an increase in processing speed in LSIs, an improvement in signal transmission speed between LSIs is desired. Such an improvement in signal transmission speed means shortening of the signal cycle CYL in FIG. 9, and the signal window period Ps inevitably tends to be narrowed.

On the other hand, if there are manufacturing variations in LSIs, signal line delay variations between LSIs, clock driver clock signal variations applied to LSIs, clock signal line delay variations, etc. In some cases, the unstable period Pu of the voltage becomes wide. In such a case, the window period Ps becomes narrower as the period Pu becomes wider.
As described above, when the window period Ps in the signal is narrowed, the period in which the signal can be correctly recognized is narrowed, so that there is a problem that the recognition accuracy for the signal may be lowered.

  On the other hand, in the technique described in Patent Document 1 described above, the recognition timing is adjusted so that the adjustment pattern can be recognized in the window period, and the threshold voltage is adjusted so that the adjustment pattern can be correctly recognized. It is possible to perform optimum recognition for a given window period, but it has not been possible to cope with the narrowing of the window period itself as described above.

Further, in the technique described in Patent Document 2, the window period itself is narrowed as described above, but Pu can be narrowed and the window period itself can be widened by adjusting the transmission timing. Accumulating survey results and finding the phase difference requires a lot of computing resources and time, and it may be difficult to adjust to the appropriate transmission timing with limited computing resources and time .
In particular, when a plurality of signal lines are used in a bundle, the problems of calculation resources and calculation time become more remarkable by exhaustively investigating each signal line.

  Accordingly, in view of the above points, an object of the present invention is to provide a transmission circuit and a parameter that can adjust a window period in a signal appropriately with less calculation resources and calculation time, and can improve recognition accuracy for the signal. It is to provide an adjustment method.

In order to achieve at least a part of the above object, the transmission circuit of the present invention is a transmission circuit that performs simultaneous bidirectional signal transmission of a signal via a plurality of signal lines, for example,
A transmission timing setting unit for setting the transmission timing of a signal to be transmitted;
A setting unit for setting a recognition timing for recognizing the received signal;
A start instruction unit for instructing a start instruction for starting the adjustment of the setting in the transmission circuit and another transmission circuit connected to the signal line;
After the start instruction, an adjustment signal transmitter that transmits an adjustment signal to the other transmission circuit;
Transmission timing setting adjustment for adjusting the setting of the transmission timing based on a signal recognition result when the adjustment signal transmitted to the other transmission circuit and the adjustment signal received from the other transmission circuit are combined. And
A setting adjustment unit that adjusts the setting in the setting unit based on a signal recognition result when the adjustment signal transmitted to the other transmission circuit and the adjustment signal received from the other transmission circuit are combined. When,
With
The setting adjustment unit, based on the recognition result, so that a window period formed between the voltage change point of the transmitted adjustment signal and the voltage change point of the received adjustment signal is maximized. The transmission timing setting is adjusted.

  Thus, in the transmission circuit of the present invention, at the time of adjustment, each adjustment signal transmitted to the other transmission circuit and the adjustment signal received from the other transmission circuit are combined based on the recognition result of each signal. The transmission timing setting unit sets the transmission timing of the signal to be transmitted and adjusts the setting of the transmission timing so that the phase difference is calculated from the variation of the signal line window and the phase difference is corrected.

Therefore, according to the transmission circuit of the present invention, even when the window period is narrow due to manufacturing variations in LSI, etc., by adjusting the setting of the transmission timing based on the signal recognition result, The time lag from the voltage change point of the received signal can be reduced to widen the window period, and the recognition accuracy for the signal can be improved.
In the transmission circuit of the present invention, the setting unit may further include a setting unit that sets a threshold voltage that is a reference for quantizing the received signal.

  With this configuration, it is possible to consider setting of a threshold voltage that is a reference for quantization of the received signal in the recognition result at the time of adjustment. For this reason, a more appropriate window period can be set, and the recognition accuracy for the signal can be further improved.

In an embodiment to be described later, the variable delay layers 20 (0) to (15) on the transmission side are the transmission timing setting unit described above, the adjustment activation control unit 14 is the transmission instruction adjustment control unit 16 (0) to (15) and transmission units 18 (0) to (15) are added to the adjustment signal transmission unit described above, the transmission side adjustment control units 16 (0) to (15), the optimum set value determination unit 28, and The buffers 30 correspond to transmission timing setting adjustment units, respectively. Furthermore, the variable delay layer 24 (0) to (15) or the variable resistor 34 on the reception side includes the reception side adjustment control unit 26, the threshold voltage adjustment control unit 27, the optimum set value determination unit 28, and the buffer 30 in the setting unit described above. Corresponds to the above-described setting adjustment unit.
Note that the present invention is not limited to the above-described aspects of the device invention such as the transmission circuit, and can also be realized as a method invention such as a transmission circuit adjustment method.

According to the first solution of the present invention,
A transmission circuit that performs simultaneous bidirectional signal transmission of signals in parallel via a plurality of signal lines,
A plurality of transmission / reception unit circuits corresponding to each of the plurality of signal lines;
A set value determining unit for setting and changing a threshold voltage, a transmission delay value, and a reception delay value to predetermined values;
The transmission / reception unit circuit includes a transmission unit for transmitting a predetermined transmission signal;
A first delay unit that gives a delay corresponding to a set transmission delay value to the transmission signal from the transmission unit and outputs the delay to the signal line;
A receiver for extracting a reception signal from a received simultaneous bidirectional signal based on a set threshold voltage and the transmission signal;
A receiver for recognizing the received signal;
A second delay unit that gives a delay corresponding to a set reception delay value to the reception signal extracted by the receiver and outputs the delay to the reception unit;
The set value determining unit
For each of the plurality of transmission / reception unit circuits, a reception delay value that can sequentially change a reception delay value for each of a plurality of predetermined threshold voltages and recognize a predetermined adjustment pattern transmitted from another transmission circuit. Means for determining a fixed window width, and setting a threshold voltage at which the window width is maximum or equal to or greater than a predetermined threshold;
The window width corresponding to the threshold voltage set by the means for setting the threshold voltage is aggregated for each of the plurality of transmission / reception unit circuits, and the value indicating the variation in the window width is greater than or equal to a predetermined value And a means for setting a transmission delay value in accordance with a value indicating the variation or in accordance with a predetermined value.

According to the second solution of the present invention,
A plurality of transmission / reception unit circuits for performing simultaneous bidirectional signal transmission of signals in parallel, and a set value determining unit for setting and changing a threshold voltage, a transmission delay value, and a reception delay value to predetermined values, A transmission / reception unit circuit for transmitting a predetermined transmission signal; and a first delay device for giving a delay corresponding to a set transmission delay value to the transmission signal from the transmission unit and outputting the delay to a signal line Based on the set threshold voltage and the transmission signal, the receiver extracts the received signal from the received simultaneous bidirectional signal, the receiver for recognizing the received signal, and the received signal extracted by the receiver. A parameter for adjusting parameters including a threshold voltage and a transmission delay value in a transmission circuit having a second delay device that gives a delay according to the received delay value and outputs the delay to the receiving unit. A chromatography data adjustment method,
For each of the plurality of transmission / reception unit circuits, a reception delay value that can sequentially change a reception delay value for each of a plurality of predetermined threshold voltages and recognize a predetermined adjustment pattern transmitted from another transmission circuit. Determining a fixed window width, and setting a threshold voltage at which the window width is a maximum or equal to or greater than a predetermined threshold;
When the window width corresponding to the threshold voltage set in the step of setting the threshold voltage is aggregated for each of the plurality of transmission / reception unit circuits, and the value indicating the variation in the window width is equal to or greater than a predetermined value And a step of setting a transmission delay value according to a value indicating the variation or according to a predetermined value.

  ADVANTAGE OF THE INVENTION According to this invention, the transmission circuit and parameter adjustment method which can adjust the window period in a signal so that it may extend appropriately with less calculation resources and calculation time, and can improve the recognition precision with respect to a signal can be provided.

It is a block diagram which shows the structure of the transmission circuit as one embodiment of this invention. It is explanatory drawing which shows a mode that two transmission circuits shown in FIG. 1 are connected via the signal wire | line. 3 is a flowchart showing a processing procedure of parameter adjustment processing in the transmission circuit of FIG. 1. It is a flowchart which shows a part of parameter adjustment process of FIG. 3A in detail. It is explanatory drawing which shows the adjustment method of a receiving side delay. It is explanatory drawing which shows the adjustment method of a threshold voltage. It is explanatory drawing which shows the adjustment method of a transmission side delay. It is explanatory drawing which shows the adjustment method of a transmission side delay. It is explanatory drawing which shows the outline | summary of simultaneous bidirectional signal transmission. It is explanatory drawing which shows the relationship between the signal waveform of a transmission signal and a received signal, and the signal waveform of a SBTL signal. It is explanatory drawing which shows the modification which added the parallel clock to the transmission circuit shown in FIG. It is explanatory drawing which shows the modification which added CPU, CPU bus, and memory to the transmission circuit shown in FIG.

Hereinafter, embodiments of the present invention will be described in the following order.
A. Transmission circuit configuration:
B. Parameter adjustment processing:
C. Effects of the embodiment:
D. Variations:

A. Transmission circuit configuration:
FIG. 1 is a block diagram showing the configuration of the transmission circuit of the present embodiment.
The transmission circuit 100 includes a functional circuit 10 and an SBTL transmission / reception circuit 12, and includes a variable resistor 34 outside. The transmission circuit 100 is connected to other transmission circuits having the same configuration via the SBTL signal lines 36 (0) to (15) and the adjustment control signal line 38.

The functional circuit 10 corresponds to various circuits depending on the part to which the transmission circuit 100 is applied. For example, when the transmission circuit 100 is applied to a router, a transfer engine or a crossbar switch in the router is applicable. In addition, a clock signal from the outside is input to the functional circuit 10 via the PLL circuit 32, and the functional circuit 10 operates based on this clock signal.
In this embodiment, the transmission circuit 100 is configured as a single LSI, but the functional circuit 10 and the SBTL transmission / reception circuit 12 may be configured as separate LSIs. The SBTL signal line is configured as a 16-bit parallel signal, but may be configured by changing the bit width as necessary.

  In the SBTL transmission / reception circuit 12, the illustrated functional blocks are configured by hardware, and in the transmission / reception unit circuit 13 (0), the illustrated functional blocks are also configured by hardware. Some of these functional blocks may be configured by software, that is, configured by the CPU executing a predetermined program. The transmission / reception unit circuits 13 (1) to (15) also have the same configuration as the transmission / reception unit circuit 13 (0), although the illustration of the transmission side adjustment control unit 16 and the reception side adjustment control unit 26 is omitted in the figure. ing.

  The transmission unit 18 (0) transmits the transmission signal received from the functional circuit 10 to the SBTL signal line 36 (0) via the variable delay layer (first delay device) 20 (0) and the transmission side amplifier. The variable delay layer 20 (0) is a circuit that delays the timing of transmitting the signal from the transmission unit 18 (0) to the SBTL signal line 36 (0) in a stepwise manner. By changing the delay of the variable delay layer 20 (0) and adjusting the transmission timing of the signal to be transmitted, the window period of the signal can be adjusted as will be described later.

  The receiving unit 22 (0) receives the signal from the SBTL signal line 36 (0) via the receiving side amplifier (receiver) and the variable delayer (second delayer) 24 (0). The variable amplifier 34 described above is connected to the receiving side amplifier in order to adjust the threshold voltages Thm and Tml. The receiving side amplifier identifies three values of high / middle / low in the SBTL signal based on the threshold voltages Thm and Tml. Then, the reception signal is extracted by subtracting the transmission signal from the SBTL signal. The variable delay layer 24 (0) is a circuit that delays the timing of outputting the extracted reception signal to the reception unit 22 (0) in a stepwise manner. By adjusting the delay of the variable delay layer 24, the recognition timing at which the reception unit 22 (0) recognizes the reception signal can be adjusted.

In this embodiment, since a plurality of transmission / reception signals are transmitted / received at the same time, a repetitive configuration such as transmission / reception unit circuits 13 (0) to (15) is employed.
The SBTL transmission / reception circuit 12 is provided with a circuit for adjusting the above-described various parameters, that is, a transmission side delay, a reception side delay, and a threshold voltage. The adjustment activation control unit 14 activates these adjustment processes based on an adjustment activation signal input from the outside, and controls the entire process. The adjustment activation control unit 14 exchanges an adjustment control signal with the adjustment activation control unit in the other transmission circuit via the adjustment control signal line 38, and advances the adjustment process while synchronizing with each other. Although the adjustment control signal line 38 is shown as an SBTL signal, the adjustment signal line 38 operates at a transmission speed with a sufficient margin at a low speed. In addition, the adjustment signal line may take the form of a signal line that uses a plurality of bidirectional signals or a plurality of unidirectional signals in a time division manner instead of the SBTL signal.

  When receiving the adjustment start instruction from the adjustment activation control unit 14, the transmission side adjustment control unit 16 (0) issues a transmission suppression instruction to the transmission unit 18 (0) and sends a prepared adjustment pattern. . Thereby, the transmission unit 18 (0) temporarily stops transmission of the transmission signal from the functional circuit 10, and instead, the adjustment pattern received from the transmission side adjustment control unit 16 (0) is transmitted to the SBTL signal line 36 (0). Send to. Similarly, in the other transmission circuit, since the adjustment pattern is transmitted to the SBTL signal line 36 (0) in response to the adjustment start instruction, the adjustment pattern is synchronized with the SBTL signal line 36 from both transmission circuits. Will be output. This adjustment pattern is used for adjusting a threshold voltage, a transmission side delay, and a reception side delay, which will be described later.

  On the other hand, when receiving the adjustment start instruction from the adjustment activation control unit 14 (0), the reception side adjustment control unit 26 (0) also issues a reception suppression instruction to the reception unit 22 (0). Thereby, the reception unit 22 (0) temporarily stops transmission of the reception signal to the functional circuit 10.

  The transmission-side adjustment control unit 16 (0) adjusts the transmission-side delay by giving a delay setting value to the variable delay layer 20 (0) on the transmission side and changing the delay setting value stepwise. The reception side adjustment control unit 26 (0) also adjusts the reception side delay by giving a delay setting value to the variable delay layer 24 (0) on the reception side and changing the delay setting value stepwise. Further, the threshold voltage adjustment control unit 27 adjusts the threshold voltage by giving a resistance setting value to the variable resistor 34 and changing the resistance setting value stepwise. In the present embodiment, the transmission side adjustment control unit 16 and the reception side adjustment control unit 26 exist for each transmission / reception unit circuit 13, and one threshold voltage adjustment control unit 27 exists in the SBTL transmission / reception circuit 12. However, each transmission / reception unit circuit may have a variable resistor and a threshold voltage adjustment control unit.

At this time, the transmission side adjustment control unit 16 (0) gives the delay setting value given to the variable delay layer 20 (0), and the reception side adjustment control unit 26 (0) gives the delay given to the variable delay layer 24 (0). The set value and the resistance set value given to 34 are respectively notified to the optimum set value determining unit 28.
As described above, when adjustment is started, an adjustment pattern flows through the SBTL signal line 36 (0). This is received by the reception unit 22 (0) as a reception signal via the reception side amplifier and the variable delay layer 24 (0), and it is determined whether or not this adjustment pattern is correctly recognized, that is, whether or not it can be read. The result is sent to the optimum set value determination unit 28 via the reception side adjustment control unit 26 (0).

  The optimum setting value determination unit 28 associates the notified setting value with the determination result for the notified setting value and stores it in the determination result table in the buffer 30. Thereafter, the optimum setting value determination unit 28 determines an optimum combination of setting values from the determination result table, notifies the setting values to the transmission side adjustment control unit 16 and the reception side adjustment control unit 26, and In the buffer 30, it is rewritten as a new preset value. The transmission side adjustment control unit 16 gives the notified optimum delay setting value to the variable delay layer 20, and the reception side adjustment control unit 26 sets the optimum delay setting value to the variable delay layer 24 and the optimum resistance setting value to the variable resistance. 34, respectively. The setting of the optimum setting value will be described later.

  FIG. 2 is an explanatory diagram showing a state in which two transmission circuits shown in FIG. 1 are connected via a signal line. The transmission circuits 100 </ b> A and 100 </ b> B are the above-described transmission circuit 100 and have the same configuration, and are connected via the SBTL signal lines 36 (0) to (15) and the adjustment control signal line 38. In the figure, only components related to circuit connection are shown, and the threshold voltage adjustment control unit 27 and the like are omitted. In addition, a clock signal output from the clock generation circuit 400 via the clock driver 300 is branched to these transmission circuits 100A and 100B and input via the clock drivers 200A and 200B. The signals are input to the functional circuits 10A and 10B via the PLL circuits 32A and 32B, respectively.

  As described above, in this embodiment, the clock signal output from the same clock generation circuit 400 is used as a reference for operation in the transmission circuits 100A and 100B. Accordingly, the transmission circuit 100A and the transmission circuit 100B have the same source oscillation so that the voltage change points of the transmission signals are simultaneously temporally in the transmission circuits 100A and 100B (that is, the phases of the transmission signals are matched). ing). In this embodiment, the delay (wiring delay) of the SBTL signal line 36 connecting the transmission circuits 100A and 100B is set to be a multiple of the operating frequency in the transmission circuits 100A and 100B. By doing so, the window period of the signal is maximized under ideal conditions.

  With the above configuration, the transmission circuit 100 according to the present embodiment adjusts the transmission side delay, the reception side delay, and the threshold voltage, and can realize the SBTL appropriately and accurately with less calculation resources and calculation time. Hereinafter, the adjustment process of these parameters will be specifically described.

B. Parameter adjustment processing:
FIG. 3A is a flowchart showing a processing procedure of parameter adjustment processing in the transmission circuit of FIG. A process executed in cooperation with each functional block of the transmission circuit 100 is shown. First, when an adjustment activation signal is input from the outside (step S100), the adjustment activation control unit 14 activates an adjustment process and transmits an adjustment start instruction to the other transmission circuit by the adjustment control signal (step S102). As a result, both transmission circuits connected to the SBTL signal lines 36 (0) to (15) start to operate synchronously.

  Next, the adjustment activation control unit 14 instructs the transmission side adjustment control units 16 (0) to (15) and the reception side adjustment control units 26 (0) to (15) to start adjustment, and performs these transmission side adjustments. The control units 16 (0) to (15) and the reception side adjustment control units 26 (0) to (15) transmit and receive to the transmission units 18 (0) to (15) and the reception units 22 (0) to (15). Inhibition is instructed, and transmission / reception of signals between the transmission units 18 (0) to (15) and the reception units 22 (0) to (15) and the functional circuit 10 is stopped (step S104). Furthermore, the adjustment activation control unit 14 selects one of the three types of adjustment processing of the default setting mode, the already set use mode, and the adjustment mode according to the adjustment operation mode signal input from the outside (step S106). Instead of selecting according to the adjustment operation mode signal, the operation mode may be set in advance, or the adjustment activation control unit 14 autonomously determines based on the elapsed time from the previous adjustment. You may do it.

  In the default setting mode, each default value prepared in advance according to an instruction from the adjustment activation control unit 14 is sent to the variable delay layers 20 (0) to (15) by the transmission side adjustment control units 16 (0) to (15). The receiving side adjustment control units 26 (0) to (15) are set as set values in the variable delay layers 24 (0) to (15), and the threshold voltage control unit 27 is set as a set value in the variable resistor 34 (step S108). In the preset use mode, the optimum set value determination unit 28 reads the previous set value stored as the preset value in the buffer 30 in accordance with an instruction from the adjustment activation control unit 14, and transmits the adjustment control unit on the transmission side. 16 (0) to (15), the reception side adjustment control units 26 (0) to (15), the threshold voltage control unit 27, and the transmission side adjustment control units 16 (0) to (15) are notified. The set values are set to the variable delay layers 20 (0) to (15), the receiving side adjustment control units 26 (0) to (15) are set to the variable delay layers 24 (0) to (15), and the threshold voltage control unit 27 is set to the variable resistor 34. (Step S110).

  On the other hand, in the adjustment mode, according to the instruction from the adjustment activation control unit 14, the transmission side adjustment control units 16 (0) to (15) send the delay setting values at the start of adjustment to the variable delay layers 20 (0) to (15). For example, the delay 0 is set, and the receiving side adjustment control units 26 (0) to (15) set the delay 0 as the delay setting value at the start of the adjustment in the variable delay layers 24 (0) to (15). The threshold voltage control unit 27 sets Th as a resistance setting value at the start of adjustment in the variable resistor 34 (step S112). These set values at the start of adjustment can be determined in advance. Then, the transmission side adjustment control units 16 (0) to (15) transmit the adjustment patterns to the SBTL signal lines 36 (0) to (15) via the transmission units 18 (0) to (15) and the like. (Step S120). In synchronization with this, since the adjustment pattern is transmitted from the other transmission circuit to the SBTL signal lines 36 (0) to (15), both transmission circuits are connected to the SBTL signal lines 36 (0) to (15). The adjustment pattern flows from. Therefore, the receiving units 22 (0) to (15) receive these adjustment patterns as reception signals via the reception side amplifier or the like (step S120). Then, the receiving units 22 (0) to (15) determine whether or not the adjustment pattern is correctly recognized, and the determination result is sent to the optimum setting value via the receiving side adjustment control units 26 (0) to (15). The data is sent to the determination unit 28. Since the adjustment pattern is determined in advance, it can be determined whether the signal has been correctly recognized by comparing the received signal with the predetermined adjustment pattern. The optimum setting value determination unit 28 sets the setting values notified from the transmission side adjustment control units 16 (0) to (15) and the reception side adjustment control units 26 (0) to (15), and the determination results corresponding thereto. Correspondingly, it is stored in the determination result table in the buffer 30 (step S122). The reception side adjustment control units 26 (0) to (15) sequentially set delays for the variable delay layers 24 (0) to (15) until the determination is completed for all delays in the variable delay layers 24 (0) to (15). The adjustment process of steps S120 and S122 is repeatedly executed while changing the value, that is, the reception side delay (steps S124 and S126).

  FIG. 4 is an explanatory diagram showing a method of adjusting the reception side delay. An example of the adjustment pattern is shown in the upper part of the figure. The adjustment pattern is a signal transmitted in a predetermined sequence such as “high / low / high / low ...”. Here, a signal for switching “high → low → high” and a signal for switching “low → high → low” are shown. When adjusting the delay on the receiving side, the delay setting values of the variable delay layers 24 (0) to (15) shown in FIG. 1 are adjusted in stages, and the receiving units 22 (0) to (15) recognize this signal. Change the timing. In the figure, an example in which the delay setting value is changed in 19 stages from delay 0 to delay 18 is shown.

  As shown in the figure, when the reception-side delay is changed, a timing at which the adjustment pattern can be correctly recognized and a timing at which it is erroneously recognized appear. Since the adjustment pattern is a known signal, it is determined whether or not the adjustment pattern is correctly recognized by determining whether or not the recognition result matches the known signal in the receiving units 22 (0) to (15). Can be determined. In the example shown in the figure, the delays 1 to 13 are timings at which signals can be correctly recognized (indicated by white circles), and others are timings at which they are erroneously recognized (indicated by black circles). A table (determination result table) for storing determination results at the time of adjustment is shown below the figure. The reception side adjustment control units 26 (0) to (15) determine whether or not the reception units 22 (0) to (15) have correctly recognized the adjustment pattern while changing the reception side delay, and set the optimum settings. The value determination unit 28 stores the determination result in the buffer 30 for each reception unit in the format shown in the figure.

  When the determination for all delays in the variable delay 24 is thus completed, the threshold voltage control unit 27 next sequentially sets the resistance setting value for the variable resistor 34, that is, the threshold voltage, until the determination for all threshold voltages is completed. While changing, the adjustment process of steps S120 to S126 is repeatedly executed (steps S128 and S130).

  FIG. 5 is an explanatory diagram showing a method for adjusting the threshold voltage. An example of the adjustment pattern is shown in the upper part of the figure. In the threshold voltage adjustment process, the variable resistor 34 shown in FIG. 1 is adjusted stepwise to change the threshold voltage. The figure shows an example in which the threshold voltage is changed in seven stages. In the figure, the reception side delay is also shown as being adjusted.

  As with the reception-side delay adjustment process, when the threshold voltage and the reception-side delay are changed, the adjustment pattern can be recognized correctly (indicated by a white circle) or incorrectly recognized (indicated by a black circle). appear. A table for storing determination results at the time of adjustment is shown below the figure. This is a two-dimensional table that stores determination results for combinations of reception-side delays and threshold voltages.

As shown in the figure, the range of the reception side delay in which the adjustment pattern can be correctly recognized varies depending on the threshold voltage. In the example shown in the figure, the threshold voltage Th1 has a wider reception side delay range in which the adjustment pattern can be correctly recognized than Th0.
Thus, when the determination is completed for all the threshold voltages on the transmission circuit 100A side and the transmission circuit 100B side (step S128, YES), the optimum setting value determination unit 28 refers to the determination result table stored in the buffer 30. A threshold voltage value at which the range of the receiving side delay that can correctly recognize the adjustment pattern is maximized is determined, the value is determined as an optimum setting value of the threshold voltage, and the optimum setting value is notified to the threshold voltage control unit 27 ( Step S132). Next, the optimum setting value determination unit 28 determines whether or not it is necessary to change the delay setting value for the variable delay layers 20 (0) to (15), that is, the transmission side delay. The transmission side adjustment control units 16 (0) to (15) are notified of the set values, and the transmission side adjustment control units 16 (0) to (15) transmit the set values to the variable delay layers 20 (0) to (15). Set to. (Steps S200 and S300)

  FIG. 6 is an explanatory diagram showing a method for adjusting the transmission side delay. That is, FIG. 6 shows the adjustment patterns as transmission signals and SBTL signals at point A (points A (0) to (15)) and point B (B (0) to (15)) in FIG. . In FIG. 6, (a) shows the state under ideal conditions, (b) shows the state under worst conditions, and (c) shows the transmission timing by adjusting the transmission side delay from the state under worst conditions of (b). The state where is corrected. In each of (a) to (c), the transmission signal at point A (that is, the transmission signal output from the transmission side amplifier of the transmission circuit 100A) and the transmission signal at point B (that is, in order from the top) (that is, , A transmission signal output from the transmission-side amplifier of the transmission circuit 100B), an SBTL signal at point A (that is, a signal obtained by combining the transmission signal and the reception signal at the transmission circuit 100A), and an SBTL signal at point B (that is, The signals obtained by combining the transmission signal and the reception signal in the transmission circuit 100B) are respectively shown.

As shown in FIG. 6A, under ideal conditions, the phase of the transmission signal at point A in the transmission circuit 100A and the phase of the transmission signal at point B in the transmission circuit 100B match each other (ie, , The voltage change points of the transmitted signals are matched). On the other hand, when the transmission signal output from the transmission circuit 100B is transmitted through the SBTL signal line 36 to the point A and becomes a reception signal in the transmission circuit 100A, the reception signal is delayed in phase by the wiring delay of the SBTL signal line 36. Signal. Moreover, since the wiring delay of the SBTL signal line 36 is set to be a multiple of the operating frequency in the transmission circuits 100A and 100B, the phase of the transmission signal and the phase of the reception signal match at point A. (That is, the voltage change point of the transmission signal coincides with the voltage change point of the reception signal). Similarly, when the transmission signal output from the transmission circuit 100A is transmitted through the SBTL signal line 36 to reach the point B and becomes a reception signal in the transmission circuit 100B, the reception signal also has a phase corresponding to the wiring delay of the SBTL signal line 36. Becomes a delayed received signal. Therefore, also at point B, the phase of the transmission signal and the phase of the reception signal coincide.
Therefore, under ideal conditions, the window period of the SBTL signal formed by combining the transmission signal and the reception signal is the maximum at both points A and B.

  On the other hand, the worst condition is as shown in FIG. As described above, in such a transmission circuit, when manufacturing variations in LSIs, signal line delay variations between LSIs, clock signal clock driver manufacturing variations applied to LSIs, clock signal line delay variations, etc. occur. Due to these variations, the unstable period of voltage becomes wide, and conversely, the window period becomes narrow accordingly. Therefore, when such a variation occurs, the window period of the SBTL signal is minimized under the worst condition.

  Specifically, as shown in FIG. 6B, the phase of the transmission signal at the point A in the transmission circuit 100A and the phase of the transmission signal at the point B in the transmission circuit 100B are equal to each other by the generated variation. There is a shift (that is, the voltage change point between the transmission signals is shifted in time). On the other hand, as described above, when the transmission signal from the transmission circuit 100B reaches the point A via the SBTL signal line 36 and becomes a reception signal in the transmission circuit 100A, the reception signal is equivalent to the wiring delay of the SBTL signal line 36. Is delayed, and the wiring delay of the SBTL signal line 36 is set to be a multiple of the operating frequency. Accordingly, the phase of the reception signal is shifted from the phase of the transmission signal at point A by the amount that the transmission signals have shifted due to variation (that is, the voltage change point of the transmission signal and the reception signal). The time point of the voltage change is shifted in time). Similarly, when the transmission signal from the transmission circuit 100A reaches the point B via the SBTL signal line 36 and becomes a reception signal in the transmission circuit 100B, the reception signal is also delayed in phase by the wiring delay of the SBTL signal line 36. Received signal. Therefore, the phase of the received signal is shifted from the phase of the transmitted signal at point B as much as the phase of the transmitted signals is shifted due to variations.

Therefore, when variation occurs, under the worst condition, the window period of the SBTL signal formed by combining the transmission signal and the reception signal at the points A and B is minimized.
Therefore, in the present embodiment, even when such a variation occurs, by changing the transmission-side delay and adjusting the transmission timing of the signal to be transmitted, as shown in FIG. , The window period of the SBTL signal is adjusted to be maximized as in the ideal condition.

  For example, the transmission circuit 100B side is left as it is, and only the transmission circuit 100A side changes the delay setting value for the variable delay layers 20 (0) to (15), that is, the transmission side delay, and outputs from the transmission side amplifier of the transmission circuit 100A. When the phase of the transmitted signal (that is, the transmission timing of the signal to be transmitted) is delayed, the phase of the transmission signal at point A in the transmission circuit 100A approaches the phase of the transmission signal at point B in the transmission circuit 100B. The phase shift between the transmission signals is reduced (that is, the time shift of the voltage change point between the transmission signals is reduced). Further, the phase of the transmission signal from the transmission circuit 100B remains as it is, and the phase of the reception signal that reaches the point A via the SBTL signal line 36 is also unchanged. As the signal becomes late, the phase of the reception signal approaches and the phase shift between the transmission signal and the reception signal also decreases (that is, the time shift between the voltage change point of the transmission signal and the voltage change point of the reception signal also decreases). Therefore, if the phase of the transmission signal output from the transmission-side amplifier of the transmission circuit 100A is delayed by the amount of phase shift caused by the variation, the phase of the transmission signal finally matches the phase of the reception signal at point A, There is no phase shift. Thereby, at the point A, the window period of the SBTL signal formed by combining the transmission signal and the reception signal can be maximized.

  On the other hand, when the phase of the transmission signal from the transmission circuit 100A is delayed, the phase of the reception signal reaching point B via the SBTL signal line 36 is also delayed. Accordingly, at point B, the phase of the received signal is delayed while the phase of the transmitted signal remains unchanged, so that the phase of the received signal approaches the phase of the transmitted signal, and the phase shift between the transmitted signal and the received signal is reduced. Therefore, as described above, when the phase of the transmission signal output from the transmission-side amplifier of the transmission circuit 100A is delayed by the phase shift generated due to the variation, the phase of the reception signal finally matches the phase of the transmission signal at point B. Then, the phase shift between the two is eliminated. Thereby, also at the point B, the window period of the SBTL signal formed by combining the transmission signal and the reception signal can be maximized.

  FIG. 7A, FIG. 7B, and FIG. 7C are explanatory diagrams showing a method for adjusting the transmission side delay. In the transmission-side delay adjustment processing, as described above, for example, on the transmission circuit 100A side, the variable delay layer 20 shown in FIG. 1 is adjusted to change the phase of the transmission signal output from the transmission-side amplifier (that is, Change the transmission timing of the signal to be transmitted). FIG. 7A shows a case where the transmission side delay is set to delay 0, and FIG. 7B shows a case where the transmission side delay is set to delay n (n is any one of 1 to 18, for example). Yes. In each figure, an example of a transmission signal and a reception signal that are adjustment patterns on the transmission circuit 100A side is shown above. In the figure, when the threshold voltage is set to a certain optimum value and the transmission side delay is changed to a certain value (for example, refer to the transmission signal in FIG. 7B), the reception side delay is also adjusted. Shown as something to do. When the transmission side delay is changed to a certain value and the reception side delay is changed, the adjustment pattern can be recognized correctly (indicated by a white circle), or it can be erroneously recognized (the black circle). Appears). FIG. 7 shows the reception side delay and the recognition result correspondingly.

  FIG. 7C shows the case where the transmission side delay is set to 0 similarly to FIG. 7A, but there are many reception side delay values that can correctly recognize the adjustment pattern, and the window size is erroneously recognized. Is shown.

  In FIG. 7A, the vicinity of the voltage change point of the transmission signal and the voltage change point of the reception signal are black circles because they are electrically unstable. On the other hand, in FIG. 7C, a black circle appears in the vicinity of the voltage change point of the received signal because of an electrically unstable state, but a white circle appears in the vicinity of the voltage change point of the transmission signal. This phenomenon appears due to the difference in degradation between the transmitted signal waveform and the received signal waveform. When the transmission waveform of the transmission circuit 100A at the point A and the reception waveform arriving through the SBTL signal line 36 of the transmission circuit 100B are compared, the reception waveform has a larger jitter than the transmission waveform, and the waveform rises (rises). (Falling) becomes dull, and various noises are superimposed to form a distorted waveform. For this reason, even in a signal with almost the same condition, there is a difference in instability in the vicinity of the voltage change point of the transmission signal and the voltage change point of the reception signal, and the window size can be correctly recognized as shown in FIG. As shown in FIG. 7C, the window size may be mistakenly recognized to cause a difference in the window size. Based on the misrecognized window size as shown in FIG. 7C, for example, the median value (for example, 6 or 7 in the figure) of the reception side delay (white circle in the figure) determined to be recognizable is determined as the reception side delay. Then, it becomes a biased position in the window during actual operation.

  Although it is possible to cope with such a problem by making the adjustment pattern sufficiently long, it is not realistic considering the processing time. In this embodiment, it is possible to confirm that the phase is shifted in a short time. In this embodiment, the voltage change point of the reception signal is more unstable than the voltage change point of the transmission signal. However, it is possible to deal with the case where the relationship is reversed.

  FIG. 3B is a flowchart showing the processing procedure of step S200. The optimum setting value determination unit 28 calculates the window size of each bit based on the information of the variable delay layers 24 (0) to (15) obtained from the reception side adjustment control units 26 (0) to (15) (step S202). These window size variations are calculated (step S204). For example, the difference between the maximum value and the minimum value of the window size of each bit is assumed to vary. If the variation in the window size obtained in this way is greater than or equal to a predetermined value, that is, if a phase difference has occurred (step S206, YES), it is determined that the transmission delay value needs to be adjusted (step S200, YES). ). For example, the states of FIG. 7A and FIG. 7C are mixed between bits, that is, when the window size is misrecognized, the optimum setting value determination unit 28 performs the transmission side adjustment. The control units 16 (0) to (15) are instructed to set a large delay value by the variable delay layers 20 (0) to (15) (step S300). The delay value set in the variable delay layer 20 may be obtained from the variation in the window size, or the set value may be changed stepwise within a predetermined width. For example, the variation obtained as described above (the difference between the maximum value and the minimum value of the window size) may be set as the delay value.

In the present embodiment, the same transmission delay value is given to the variable delay layers 20 (0) to (15), but different transmission delay values may be set for each.
If the variation is not equal to or greater than the specified value in step S200, the process proceeds to step S150.

Thus, after setting the transmission delay on the transmission circuit 100A side and the transmission delay on the transmission circuit 100B side, the reception side delay is adjusted again (S320 to 326). The transmission side adjustment control units 16 (0) to (15) transmit the adjustment pattern to the SBTL signal lines 36 (0) to (15) via the transmission units 18 (0) to (15) (step S320). . In synchronization with this, since the adjustment pattern is transmitted from the other transmission circuit to the SBTL signal lines 36 (0) to (15), both transmission circuits are connected to the SBTL signal lines 36 (0) to (15). The adjustment pattern flows from. Therefore, the receiving units 22 (0) to (15) receive these adjustment patterns as received signals via the receiving side amplifier or the like (step S320). Then, the receiving units 22 (0) to (15) determine whether or not the adjustment pattern is correctly recognized, and the determination result is sent to the optimum setting value via the receiving side adjustment control units 26 (0) to (15). The data is sent to the determination unit 28. The optimum setting value determination unit 28 sets the setting values notified from the transmission side adjustment control units 16 (0) to (15) and the reception side adjustment control units 26 (0) to (15), and the determination results corresponding thereto. Correspondingly, it is stored in the determination result table in the buffer 30 (step S322). The reception side adjustment control units 26 (0) to (15) sequentially set delays for the variable delay layers 24 (0) to (15) until the determination is completed for all delays in the variable delay layers 24 (0) to (15). The adjustment processing of steps S320 and S322 is repeatedly executed while changing the value, that is, the reception side delay (steps S324 and S326).
Steps S300 to S328 are repeatedly executed, and when it is determined in step S200 that adjustment of the transmission side delay is unnecessary, the adjustment ends.

  Thus, when the determination is completed for all the reception-side delays on the transmission circuit 100A side and the transmission circuit 100B side, the optimum setting value determination unit 28 refers to the determination result table stored in the buffer 30. Then, the median value of the receiving side delay capable of correctly recognizing the adjustment pattern in the window period is obtained, and the optimum setting value of the receiving side delay is determined in the vicinity of the median value. The median can be obtained by various methods such as the center of gravity of the region with white circles and the upper and lower limit values of the reception delay with white circles. If the median value is used, for example, the distance to the voltage change point in FIG.

  Thus, when the optimum setting value combination is determined from the determination result table, the optimum setting value determination unit 28 notifies the transmission side adjustment control unit 16 and the reception side adjustment control unit 26 of these optimum setting values, and In the buffer 30, it is rewritten as a new preset value. The transmission side adjustment control unit 16 sets the notified optimal transmission side delay setting value in the variable delay layer 20, and the reception side adjustment control unit 26 sets the notified optimal reception side delay setting value in the variable delay layer. 24, the optimum resistance set value is set in the variable resistor 34, respectively.

  As described above, when the adjustment process is completed in any one of the default setting mode, the already set use mode, and the adjustment mode, the transmission side adjustment control unit 16 and the reception side adjustment control unit 26 are configured according to an instruction from the adjustment activation control unit 14. The transmission unit 18 and the reception unit 22 are instructed to permit transmission / reception, and transmission / reception of signals between the transmission unit 18, the reception unit 22 and the functional circuit 10 is resumed (step S 150). In this way, a series of parameter adjustment processing is completed.

C. Effects of the embodiment:
As described above, in the present embodiment, even when the manufacturing variation in the LSI occurs and the window period is narrow, the transmission side delay is changed to adjust the transmission timing of the signal to be transmitted. As shown in FIG. 6C, the phase of the transmission signal and the phase of the reception signal can be matched to maximize the window period of the SBTL signal.

  In this embodiment, after determining the threshold voltages on the transmission circuit 100A side and the transmission circuit 100B side, it is determined whether or not a phase difference has occurred, and if necessary, the transmission side delay is set so that the phase difference is eliminated. Since the reception delayer is set on the transmission circuit 100A side and the transmission circuit 100B side by changing, the following effects can be expected.

For example, as shown in FIG. 6B, when the phase of the transmission signal at point A in the transmission circuit 100A is more advanced than the transmission signal at point B in the transmission circuit 100B, the transmission circuit By changing the transmission-side delay on the 100A side and delaying the phase of the transmission signal at the point A in the transmission circuit 100A, it is possible to match the phase of the transmission signal at the point B in the transmission circuit 100B. If the phase of the transmission signal at point A in the transmission circuit 100A is delayed from the phase of the transmission signal at point B in the transmission circuit 100B, the transmission side delay on the transmission circuit 100A side is changed to change the transmission circuit. Even if the phase of the transmission signal at point A in 100A is delayed, it will only deviate from the phase of the transmission signal at point B in transmission circuit 100B. Therefore, conversely, if the transmission-side delay on the transmission circuit 100B side is changed to delay the phase of the transmission signal at the point B in the transmission circuit 100B, the phase of the transmission signal at the point A in the transmission circuit 100A The phase of the transmission signal at point B in the transmission circuit 100B can be matched. As a result, the phase of the transmission signal and the phase of the reception signal can be matched, and the window period of the SBTL signal can be maximized.
Further, even when a plurality of SBTL signal lines are bundled and used in the method of this embodiment, the phase difference is obtained from the variation after adjustment, so that the window period can be appropriately maximized with less calculation resources and less calculation time. Can be.

D. Variations:
The present invention is not limited to the above-described embodiment, and can be implemented in various modes without departing from the scope of the invention.

In the above-described embodiment, there are three operation modes: the default setting mode, the already-set use mode, and the adjustment mode. However, the present invention is not limited to this, and for example, an adjustment activation signal is input. Even in such a case, a “no adjustment mode” may be provided in which the process is completed without performing adjustment. The default setting mode and the already set use mode may be omitted and only the adjustment mode may be used.
In the above-described embodiment, the threshold voltage is adjusted and determined first. However, the threshold voltage may be adjusted and determined after the transmission side delay is determined.

FIG. 10 is an explanatory view showing a state in which a parallel clock is added to FIG. In this example, the transmission circuits 100A and 100B are connected to each other with a parallel clock and used for receiving the SBTL signal. In this manner, the clock signals may be transmitted in parallel, thereby improving the tolerance of the clock jitter of the clock generation circuit 400 and improving the reliability of signal transmission. Furthermore, the adjustment range may be further widened by adjusting the transmission delay layer and the reception delay layer of the parallel clock.
In the present embodiment, the threshold voltages Thm and Tml are calculated from one variable resistor. However, the threshold voltages Thm and Tml may be individually adjusted by providing variable resistors.

  FIG. 11 is a modification of FIG. 2 in which the CPU interface units 40A and 40B are provided in the SBTL transmission / reception circuits 12A and 12B, respectively, and the CPU bus 42, the CPU 44, and the memory 46 are provided outside the transmission circuits 100A and 100B. . The CPU 44 includes a memory 46, and records adjustment values and calculates optimum values. The CPU 44 communicates with the CPU interface units 40A and 40B via the CPU bus 42. The CPU interface unit 40A transmits the transmission units 18A (0) to (15), the variable delay layers 20A (0) to (15), and the transmission unit. 22A (0) to (15) and variable delay layers 24A (0) to (15) are controlled, and the CPU interface section 40B is transmitted by the transmission sections 18B (0) to (15), variable delay layers 20B (0) to (15), The same operation as in the above embodiment may be performed by controlling the transmission units 22B (0) to (15) and the variable delay layers 24B (0) to (15).

  The present invention can be used, for example, in a transmission circuit for transmitting and receiving signals via an SBTL signal line.

10. . . Functional circuit 12. . . SBTL transceiver circuits 13 (0) to (15). . . Transmission / reception unit circuit 14. . . Adjustment start control unit 16 (0) to (15). . . Transmission-side adjustment control units 18 (0) to (15). . . Transmitters 20 (0) to (15). . . Variable delayer 22 (0)-(15). . . Receivers 24 (0) to (15). . . Variable delayer 26 (0)-(15). . . Reception side adjustment control unit 27. . . Threshold voltage adjustment control unit 28. . . Optimal set value determination unit 30. . . Buffer 32. . . PLL circuit 34. . . Variable resistors 36 (0) to (15). . . SBTL signal line 38. . . Adjustment control signal lines 40A, 40B. . . CPU interface unit 42. . . CPU bus 44. . . CPU
46. . . Memory 100. . . Transmission circuits 100A, 100B. . . Transmission circuits 200A, 200B. . . Clock driver 300. . . Clock driver 400. . . Clock generation circuit

Claims (8)

A transmission circuit that performs simultaneous bidirectional signal transmission of signals in parallel via a plurality of signal lines,
A plurality of transmission / reception unit circuits corresponding to each of the plurality of signal lines;
A set value determining unit for setting and changing a threshold voltage, a transmission delay value, and a reception delay value to predetermined values;
The transmission / reception unit circuit includes a transmission unit for transmitting a predetermined transmission signal;
A first delay unit that gives a delay corresponding to a set transmission delay value to the transmission signal from the transmission unit and outputs the delay to the signal line;
A receiver for extracting a reception signal from a received simultaneous bidirectional signal based on a set threshold voltage and the transmission signal;
A receiver for recognizing the received signal;
A second delay unit that gives a delay corresponding to a set reception delay value to the reception signal extracted by the receiver and outputs the delay to the reception unit;
The set value determining unit
For each of the plurality of transmission / reception unit circuits, a reception delay value that can sequentially change a reception delay value for each of a plurality of predetermined threshold voltages and recognize a predetermined adjustment pattern transmitted from another transmission circuit. Means for determining a fixed window width, and setting a threshold voltage at which the window width is maximum or equal to or greater than a predetermined threshold;
The window width corresponding to the threshold voltage set by the means for setting the threshold voltage is aggregated for each of the plurality of transmission / reception unit circuits, and the value indicating the variation in the window width is greater than or equal to a predetermined value The transmission circuit comprising: means for setting a transmission delay value according to a value indicating the variation or according to a predetermined value. The set value determining unit
Using the threshold voltage set by the means for setting the threshold voltage and the transmission delay value set by the means for setting the transmission delay value, the window width capable of recognizing the adjustment pattern by sequentially changing the reception delay value is set again. 2. The transmission circuit according to claim 1, further comprising means for obtaining and setting the reception delay value of the second delay device to any one of the reception delay values within the window width.   3. The transmission circuit according to claim 2, wherein the means for setting the reception delay value sets a reception delay value at or near the center value of the window width.   The transmission circuit according to claim 1, wherein the value indicating the variation is a difference between a maximum value and a minimum value of a window width of each transmission / reception unit circuit. A plurality of transmission / reception unit circuits for performing simultaneous bidirectional signal transmission of signals in parallel, and a set value determining unit for setting and changing a threshold voltage, a transmission delay value, and a reception delay value to predetermined values, A transmission / reception unit circuit for transmitting a predetermined transmission signal; and a first delay device for giving a delay corresponding to a set transmission delay value to the transmission signal from the transmission unit and outputting the delay to a signal line Based on the set threshold voltage and the transmission signal, the receiver extracts the received signal from the received simultaneous bidirectional signal, the receiver for recognizing the received signal, and the received signal extracted by the receiver. A parameter for adjusting parameters including a threshold voltage and a transmission delay value in a transmission circuit having a second delay device that gives a delay according to the received delay value and outputs the delay to the receiving unit. A chromatography data adjustment method,
For each of the plurality of transmission / reception unit circuits, a reception delay value that can sequentially change a reception delay value for each of a plurality of predetermined threshold voltages and recognize a predetermined adjustment pattern transmitted from another transmission circuit. Determining a fixed window width, and setting a threshold voltage at which the window width is a maximum or equal to or greater than a predetermined threshold;
When the window width corresponding to the threshold voltage set in the step of setting the threshold voltage is aggregated for each of the plurality of transmission / reception unit circuits, and the value indicating the variation in the window width is equal to or greater than a predetermined value And a step of setting a transmission delay value according to a value indicating the variation or according to a predetermined value. Using the threshold voltage set in the step of setting the threshold voltage and the transmission delay value set in the step of setting the transmission delay value, the reception delay value is sequentially changed to obtain the window width that can recognize the adjustment pattern again. 6. The parameter adjusting method according to claim 5, further comprising a step of setting a reception delay value to any of the reception delay values within the window width.   The parameter adjusting method according to claim 6, wherein the step of setting the reception delay value includes setting a reception delay value at or near the center value of the window width.   6. The parameter adjustment method according to claim 5, wherein the value indicating the variation is a difference between a maximum value and a minimum value of a window width of each transmission / reception unit circuit.

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