JP5206693B2 - Circuit simulator and circuit simulation method - Google Patents

Description

  The present invention relates to a circuit simulator and a circuit simulation method for simulating a power amplifier used in the microwave and millimeter wave bands.

  In recent years, the miniaturization of CMOS process technology has accelerated, and while the speed and frequency of CMOS have increased, the operating voltage of CMOS continues to decrease. The operating voltage of the CMOS is limited from the viewpoint of reliability.

  In a power amplifier composed of CMOS, when the operating voltage of CMOS decreases, the output power decreases in proportion to the square.

  Therefore, in the fine CMOS, in order to increase the output power of the power amplifier, there is a demand for using the operating voltage as high as possible even at 0.1V within the range permitted by reliability.

  For example, when the operating voltage of the CMOS is reduced from 1V to 0.7V, the output power is reduced by 50% or more.

  Therefore, a circuit simulator that simulates a power amplifier that satisfies the life and has a desired output power is required. Such a circuit simulator is disclosed in Patent Document 1 and Patent Document 2.

However, the circuit simulator for deriving the lifetime disclosed in Patent Documents 1 and 2 that are conventional techniques can predict the lifetime, but cannot derive the output power.
Japanese Patent Laid-Open No. 09-283577 JP 2005-259777 A

  An object of the present invention is to provide a circuit simulator and a circuit simulation method capable of designing a power amplifier that satisfies the above-described prior art and has a desired lifetime and has a desired output power.

  In order to achieve the above object, the first invention provides a transistor input unit for inputting a model parameter of a transistor, and an output for calculating output power with reference to the transistor model parameter supplied from the transistor input unit. Contour diagrams of a power simulation unit, a lifetime simulation unit that calculates a lifetime with reference to the transistor model parameter, an output power supplied from the output power simulation unit, and a lifetime supplied from the lifetime simulation unit, A display unit that displays on the load impedance; and a load impedance extraction unit that extracts a desired load impedance by referring to the output power and life displayed on the load impedance on the display unit. .

  According to the present invention, it is possible to design a power amplifier that satisfies the lifetime and has a desired output power by including the display unit that displays both the lifetime and the output power.

  The second invention is further characterized in that the lifetime simulation unit calculates the lifetime using a substrate current on a load impedance.

  According to the present invention, by using the substrate current on the load impedance for derivation of the lifetime, it becomes possible not only to calculate the lifetime without performing a complicated lifetime calculation, but also to use the load impedance to The output power of the amplifier can be easily derived.

It is a block diagram which shows the structure of the principal part of the circuit simulator of the 1st Embodiment of this invention. It is a flowchart which shows the process sequence performed with the circuit simulator of the 1st Embodiment of this invention. It is a figure displayed on the circuit simulator shown in FIG. It is a flowchart which shows the process sequence performed in the circuit simulator of the 2nd Embodiment of this invention. It is a figure which shows a load line. It is a figure which shows the board | substrate current on a load line.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing the configuration of the main part of the circuit simulator according to the first embodiment of the present invention.

  The circuit simulator of this embodiment is a simulator realized by a computer system that operates according to a program, and is used for designing a power amplifier.

  As shown in FIG. 1, the main part of the circuit simulator is composed of an initial condition input unit 1, a target specification input unit 2, a simulation unit 3, a display unit 4, and a determination unit (load impedance extraction unit) 5. Yes.

  As shown in FIG. 2, the initial condition input unit 1 includes a transistor input unit 11 for inputting model parameters and reliability lifetime information of a transistor to be simulated, and supplies the transistor information to the simulation unit 3.

  The target spec input unit 2 includes a target spec input unit 12 for inputting a spec value of the power amplifier, and supplies the spec value to the simulation unit 3.

  The simulation unit 3 includes an operating voltage input unit 13, an output power simulation unit 14 that calculates output power, and a life simulation unit 15 that calculates life (reliability time), and displays a calculation result of output power and life. 4 is supplied.

  As shown in FIG. 3, the display unit 4 includes a display unit 16 that displays the calculation result of the output power and the life on the load impedance, and supplies the display result to the determination unit 5.

  The determination unit 5 includes a determination unit 17 that determines whether the target output power value is obtained within the load impedance that satisfies the life. If the target output power value is obtained, the target output power value and the load are determined. The impedance value is presented to the simulation user. When the target output power value cannot be obtained, the process returns to the target specification input unit 12 to reset the target output power value and reset the operating voltage.

  The circuit simulator of this embodiment is an example of the present invention, and its configuration and operation can be changed in a timely manner. For example, in the present embodiment, only the output power is used as the specification value of the power amplifier, but it is also possible to simulate the efficiency, distortion, and gain, which are general indexes of the power amplifier, as the specification value.

(Second Embodiment)
FIG. 4 is a flowchart of the circuit simulator according to the second embodiment of the present invention. In addition, the structure of the principal part of the circuit simulator of this embodiment is the same as that of FIG.

  As shown in FIG. 4, the initial condition input unit 1 includes a transistor input unit 11 for inputting model parameters and reliability lifetime information of a transistor to be simulated, and supplies the transistor information to the simulation unit 3.

  The target spec input unit 2 includes a target spec input unit 12 for inputting a spec value of the power amplifier, and supplies the spec value to the simulation unit 3.

  The simulation unit 3 includes an operating voltage input unit 13, an output power simulation unit 14 that calculates output power, a substrate current simulation unit 18 that calculates a substrate current on the load line (see FIGS. 5 and 6), and a substrate on the load line. It comprises a life simulation unit 19 that calculates the life (reliability time) from the current, and supplies the output power and life calculation results to the display unit 4.

  The display unit 4 includes a display unit 16 that displays the output power and life calculation results on the load impedance, and supplies the display results to the determination unit 5.

  The determination unit 5 includes a determination unit 17 that determines whether the target output power value is obtained within the load impedance that satisfies the life. If the target output power value is obtained, the target output power value and the load are determined. The impedance value is presented to the simulation user. When the target output power value cannot be obtained, the process returns to the target specification input unit 12 to reset the target output power value and reset the operating voltage.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

  This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2008-016616 for which it applied on January 24, 2008, and takes in those the indications of all here.

Claims (2)

A transistor input for inputting transistor model parameters and reliability lifetime information;
An output power simulation unit that calculates output power using load impedance with reference to model parameters and reliability lifetime information of the transistor supplied from the transistor input unit;
A lifetime simulation unit that calculates the lifetime using the substrate current on the load impedance with reference to the model parameters and reliability lifetime information of the transistor;
A display unit that displays on the load impedance a region that satisfies the contours of the output power supplied from the output power simulation unit and the life supplied from the life simulation unit
A circuit simulator comprising: a load impedance extraction unit that extracts a desired load impedance by referring to the output power and life displayed on the load impedance in the display unit. A transistor input step for inputting transistor model parameters and reliability lifetime information;
An output power simulation step of calculating output power using load impedance with reference to the transistor model parameters and reliability lifetime information input in the transistor input step;
A lifetime simulation step of calculating a lifetime using a substrate current on a load impedance with reference to the model parameters and reliability lifetime information of the transistor;
A display step of displaying on the load impedance a region that satisfies the contour of the output power calculated in the output power simulation step and the life calculated in the life simulation step;
A circuit simulation method comprising: a load impedance extraction step of extracting a desired load impedance by referring to the output power and life displayed on the load impedance in the display step.

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