JP5213564B2 - Multilayer capacitor, semiconductor package incorporating the same, and manufacturing method thereof - Google Patents

Description

  The present invention relates to a multilayer capacitor in which a plurality of internal electrodes are laminated, a semiconductor package incorporating the multilayer capacitor, and a method for manufacturing the same.

  In recent years, the operating frequency of semiconductor chips has increased and the current consumption has increased. Accordingly, the operating voltage tends to decrease due to the reduction in power consumption. Therefore, in the power source that supplies power to the semiconductor chip, a large current fluctuation occurs at a higher speed, and it is very difficult to suppress the voltage fluctuation of the power source accompanying the current fluctuation within the allowable value of the power source.

  For this reason, a plurality of chip capacitors are mounted on a semiconductor package on which a semiconductor chip is mounted in order to reduce voltage fluctuations of the power supply. In other words, when the current fluctuates at a high speed, the current is supplied from the chip capacitor to the semiconductor chip by quick charge / discharge to suppress the voltage fluctuation of the power supply.

  Hereinafter, an example of a conventional semiconductor package on which a chip capacitor is mounted will be described with reference to FIG. 1 and the like. FIG. 1 is a cross-sectional view illustrating a conventional semiconductor package. Referring to FIG. 1, the semiconductor package 300 includes a multilayer wiring board 500, a semiconductor chip 400, electrode terminals 410, and an underfill resin layer 420. A support body 510 is provided at the center of the multilayer wiring board 500.

  A first wiring layer 610 a is formed on the first main surface 510 a of the support 510. The support 510 is formed with a through via 690 penetrating from the first main surface 510a to the second main surface 510b. The first wiring layer 610a is electrically connected to a later-described fourth wiring layer 610b via a through via 690. Further, a first insulating layer 520a is formed so as to cover the first wiring layer 610a, and a second wiring layer 620a is formed on the first insulating layer 520a. The first wiring layer 610a and the second wiring layer 620a are electrically connected through a via hole 520x that penetrates the first insulating layer 520a.

  Further, a second insulating layer 530a is formed so as to cover the second wiring layer 620a. A third wiring layer 630a is formed on the second insulating layer 530a. The second wiring layer 620a and the third wiring layer 630a are electrically connected through a via hole 530x that penetrates the second insulating layer 530a.

  Further, a solder resist film 550a having an opening 550x is formed so as to cover the third wiring layer 630a. The portion exposed from the opening 550x of the solder resist film 550a of the third wiring layer 630a functions as an electrode pad (hereinafter, the portion exposed from the opening 550x of the solder resist film 550a of the third wiring layer 630a is the electrode pad 630a). Sometimes). Hereinafter, the surface on which the electrode pad 630a is formed may be referred to as a first main surface of the multilayer wiring board 500.

  A fourth wiring layer 610b is formed on the second main surface 510b of the support 510, and a third insulating layer 520b is formed so as to cover the fourth wiring layer 610b. A fifth wiring layer 620b is formed on the third insulating layer 520b. The fourth wiring layer 610b and the fifth wiring layer 620b are electrically connected through a via hole 520y that penetrates the third insulating layer 520b.

  Further, a fourth insulating layer 530b is formed so as to cover the fifth wiring layer 620b. A sixth wiring layer 630b is formed on the fourth insulating layer 530b. The fifth wiring layer 620b and the sixth wiring layer 630b are electrically connected through a via hole 530y that penetrates the fourth insulating layer 530b.

  Further, a solder resist film 550b having an opening 550y is formed so as to cover the sixth wiring layer 630b. The portion of the sixth wiring layer 630b exposed from the opening 550y of the solder resist film 550b functions as an electrode pad (hereinafter, the portion of the sixth wiring layer 630b exposed from the opening 550y of the solder resist film 550b is the electrode pad 630b). Sometimes). Hereinafter, the surface on which the electrode pad 630b is formed may be referred to as a second main surface of the multilayer wiring board 500.

  Solder bumps 680 are formed on some of the electrode pads 630b. The solder bump 680 functions as an external connection terminal that is electrically connected to a corresponding terminal of the circuit board when the semiconductor package 300 is mounted on the circuit board (not shown). A chip capacitor 100 is mounted on some electrode pads 630b. The electrode pad 630b and the external electrodes 260a and 260b of the chip capacitor 100 are electrically connected.

  A semiconductor chip 400 is mounted on the first main surface of the multilayer wiring board 500. The semiconductor chip 400 is obtained by forming a semiconductor integrated circuit (not shown) and electrode pads (not shown) on a thinned semiconductor substrate (not shown) made of silicon or the like. Electrode terminals 410 are formed on electrode pads (not shown) of the semiconductor chip 400.

  Electrode pads (not shown) of the semiconductor chip 400 are electrically connected to corresponding electrode pads 630 a of the multilayer wiring board 500 by electrode terminals 410. The electrode terminal 410 is made of, for example, solder. An underfill resin layer 420 is filled between the semiconductor chip 400 and the solder resist film 550a of the multilayer wiring substrate 500.

  FIG. 2 is an enlarged cross-sectional view illustrating the chip capacitor shown in FIG. Referring to FIG. 2, the chip capacitor 100 includes a dielectric layer 210, a plurality of internal electrodes 220a and 220b, and two external electrodes 260a and 260b.

  Inside the dielectric layer 210, a plurality of internal electrodes 220a and 220b are alternately stacked in the Z direction. The plurality of internal electrodes 220a and 220b are arranged in a region sandwiched between the external electrodes 260a and 260b and substantially perpendicular to 260a1 and 260b1, which are the opposing surfaces of the external electrode 260a and the external electrode 260b. The plurality of internal electrodes 220a are connected to the external electrode 260a, and the plurality of internal electrodes 220b are connected to the external electrode 260b. Thereby, a capacitance is formed between the plurality of internal electrodes 220a and the plurality of internal electrodes 220b.

  A plurality of chip capacitors 100 shown in FIG. 2 are connected between the power supply of the semiconductor chip 400 and a reference potential (GND) in order to reduce voltage fluctuations of the power supply caused by the operating current of the semiconductor chip 400, for example. However, since it is difficult to dispose the chip capacitor 100 in the vicinity of the semiconductor chip 400, the chip capacitor 100 is a surface on the opposite side of the first main surface that is the mounting surface of the semiconductor chip 400 of the multilayer wiring substrate 500. Usually, it is mounted on two main surfaces.

  That is, the power supply and reference potential (GND) of the semiconductor chip 400 are extended to the second main surface of the multilayer wiring board 500 through the wiring layer, via hole, through via, etc., and the chip capacitor 100 is mounted there. On the second main surface of the multilayer wiring board 500, for example, 30 to 50 chip capacitors 100 each having a capacitance of 1 to 10 μF are mounted, and the multilayer wiring board 500 as a whole has a static capacity of 50 to 100 μF. By using the capacitance, voltage fluctuations of the power supply are reduced.

  When the semiconductor chip 400 operates at a high frequency, in order to reduce the voltage fluctuation of the power supply by the chip capacitor 100, it is preferable to arrange the chip capacitor 100 as close as possible to the power supply of the semiconductor chip 400 and the reference potential (GND). However, as described above, the chip capacitor 100 is connected between the power supply of the semiconductor chip 400 and the reference potential (GND) via a wiring layer, a via hole, a through via, and the like. Therefore, it is difficult to reduce the inductance caused by the wiring layer or the like, and when the semiconductor chip 400 operates at a high frequency, there is a limit to reducing the voltage fluctuation of the power source by the chip capacitor 100. This is because when the inductance is increased, the chip capacitor 100 is prevented from being charged and discharged in response to high-speed current fluctuation.

  In order to solve such a problem, a technique for forming a capacitor having the same structure as that shown in FIG. By forming a capacitor inside the multilayer wiring substrate 500, the capacitor can be brought closer to the semiconductor chip 400.

  At this time, the pitch of the external electrodes of the capacitor is made equal to the pitch of the electrode terminals 410 formed on the semiconductor chip 400, and the capacitor is formed immediately below the electrode terminals 410 corresponding to the power supply and reference potential (GND) of the semiconductor chip 400. It is preferable to do. One of the external electrodes of the capacitor is connected to the electrode terminal 410 corresponding to the power source of the semiconductor chip 400, and the other of the external electrodes of the capacitor is connected to the electrode terminal 410 corresponding to the reference potential (GND) of the semiconductor chip 400. Is preferred.

In this way, by forming capacitors in the multilayer wiring board 500 and connecting them as described above, it is possible to reduce the inductance caused by the wiring layers and the like. Even when it operates, the voltage fluctuation of the power source can be reduced (for example, see Patent Documents 1 and 2).
JP 2002-260959 A JP 2007-81166 A

  However, as the semiconductor package 300 becomes smaller and thinner, the pitch of the electrode terminals 410 formed on the semiconductor chip 400 is becoming narrower. That is, the electrode terminal 410 is becoming denser. As the pitch of the electrode terminals 410 becomes narrower, the pitch of the external electrodes of the capacitors connected to the electrode terminals 410 also needs to be reduced.

  In the conventional capacitor, the internal electrode is provided in a direction orthogonal to the thickness direction of the wiring board. Therefore, when the pitch of the external electrode of the capacitor is reduced, the area of the internal electrode of the capacitor cannot be increased. When the area of the internal electrode of the capacitor is reduced, the capacitance of the capacitor is reduced in proportion to it, and there is a problem that it is difficult to reduce the voltage fluctuation of the power supply.

The present invention has been made in view of the above, and incorporates a multilayer capacitor capable of reducing voltage fluctuations of a power source of a semiconductor chip even when electrode terminals formed on the semiconductor chip are densified. An object of the present invention is to provide a semiconductor package and a manufacturing method thereof.

The multilayer capacitor is formed on the dielectric layer having a first surface and a second surface opposite to the first surface, and penetrates the dielectric layer in the thickness direction. The first external electrode and the second external electrode, the end surfaces of which are exposed from the first surface and the second surface, and the dielectric layer are formed on the first external electrode and the second external electrode. In the sandwiched region, the first external electrode is connected, and the first external electrode and the second external electrode are arranged in parallel at a predetermined interval in parallel to the opposing surfaces of the first external electrode and the second external electrode. A plurality of first internal electrodes connected to each other , formed in the dielectric layer, connected to the second external electrode, and interleaved with the plurality of first internal electrodes, with a predetermined includes a plurality of second inner electrodes connected to each other are juxtaposed at intervals, wherein the first external electrode and the Each end face of each of the two external electrodes is flush with the first surface and the second surface of the dielectric layer, and the first external electrode, the first internal electrode, and the first internal electrode The electrodes are connected to each other through a via hole provided in a region of the dielectric layer where the second internal electrode is not formed, and the second external electrode and the second internal electrode, and said second internal electrodes to each other, it is a requirement that the are connected to each other via a via hole provided in a region where the first internal electrodes of the dielectric layer is not formed.

  According to the present invention, even when the electrode terminals formed on the semiconductor chip are densified, the multilayer capacitor capable of reducing the voltage fluctuation of the power source of the semiconductor chip, the semiconductor package incorporating the multilayer capacitor, and the manufacturing method thereof Can be provided.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

<Structure of multilayer capacitor according to the present invention>
FIG. 3 is a diagram illustrating a multilayer capacitor according to the present invention. FIG. 3A is a perspective view, and FIG. 3B is an enlarged cross-sectional view illustrating a portion A in FIG.
Referring to FIG. 3, the multilayer capacitor 10 includes a dielectric layer 21, a plurality of first internal electrodes 22a, a plurality of second internal electrodes 22b, a via hole 21x, a via hole 21y, and a plurality of first holes. External electrodes 26a and a plurality of second external electrodes 26b. In FIG. 3B, the width W1 of the first external electrode 26a and the second external electrode 26b is drawn narrower than that in FIG.

  The multilayer capacitor 10 shown in FIG. 3 has a structure having three first external electrodes 26a and three second external electrodes 26b for convenience, but is not limited to this. A structure having the external electrode 26a and the second external electrode 26b can be employed.

In FIG. 3, in the dielectric layer 21, the first external electrodes 26a and the second external electrodes 26b are alternately formed in the X direction at a predetermined cycle. In a region sandwiched between the adjacent first external electrode 26a and second external electrode 26b, a plurality of first internal electrodes 22a and a plurality of second internal electrodes 22b are connected to the first external electrode 26a and the second external electrode 26b. and arranged substantially parallel to 26a ₁ and 26b ₁ are opposing surfaces of the second external electrode 26b.

  The plurality of first internal electrodes 22a are juxtaposed at a predetermined interval in the X direction, and the first internal electrodes 22a are located in a region in the dielectric layer 21 where the second internal electrodes 22b are not formed. They are electrically connected to each other through a penetrating via hole 21y. The plurality of second internal electrodes 22b are juxtaposed at a predetermined interval in the X direction so as to be interleaved with the plurality of first internal electrodes 22a via the dielectric layer 21. The electrodes 22b are electrically connected to each other through a via hole 21x that penetrates a region of the dielectric layer 21 where the first internal electrode 22a is not formed.

  The plurality of first internal electrodes 22a that are electrically connected to each other are further electrically connected to adjacent first external electrodes 26a through via holes 21y. The plurality of second internal electrodes 22b that are electrically connected to each other are further electrically connected to adjacent second external electrodes 26b through via holes 21x. The plurality of first internal electrodes 22 a and the plurality of second internal electrodes 22 b are electrically insulated from each other by the dielectric layer 21.

  Thereby, a capacitance is formed between the plurality of first internal electrodes 22a and the plurality of second internal electrodes 22b. In the multilayer capacitor 10, a plurality of first external electrodes 26a and a plurality of second external electrodes 26b, a plurality of first internal electrodes 22a and a plurality of second internal electrodes 22b, and via holes 21x and 21y are excluded. The portion is the dielectric layer 21.

  The first external electrode 26a and the second external electrode 26b are rectangular parallelepiped electrodes, and have a wide surface substantially parallel to the YZ plane. As shown in FIG. 18 to be described later, the width W1 of the first external electrode 26a and the second external electrode 26b is arbitrarily set according to the size of the electrode terminal such as a solder bump formed on the electrode pad of the semiconductor chip. For example, it can be about 50 to 200 μm. The pitch P1 between the first external electrode 26a and the second external electrode 26b adjacent to each other can be arbitrarily determined according to the pitch of the electrode terminals of the semiconductor chip, and can be set to about 80 to 350 μm, for example. As a material of the first external electrode 26a and the second external electrode 26b, for example, Cu or Ni can be used.

  The plurality of first internal electrodes 22a and the plurality of second internal electrodes 22b are rectangular parallelepiped electrodes that are narrower than the first external electrode 26a and the second external electrode 26b, and are substantially parallel to the YZ plane. It has a wide surface. The width W2 of the plurality of first internal electrodes 22a and the plurality of second internal electrodes 22b can be, for example, about 1 to 10 μm. The pitch P2 between the adjacent first internal electrode 22a and second internal electrode 22b can be set to about 1 to 10 μm, for example. As a material of the plurality of first internal electrodes 22a and the plurality of second internal electrodes 22b, for example, Cu or Ni can be used.

The dielectric layer 21 is made of a material having a high dielectric constant. As a material of the dielectric layer 21, for example, a ceramic material such as SrTiO ₃ (strontium titanate) or BaTiO ₃ (barium titanate) can be used.

The multilayer capacitor 10 is built in the wiring board in the direction shown in FIG. 3, and one of the first external electrode 26a and the second external electrode 26b is an electrode terminal corresponding to the power supply of the semiconductor chip mounted on the wiring board. The other is connected to an electrode terminal corresponding to the reference potential (GND) of the semiconductor chip. At this time, the plurality of first internal electrodes 22a and the plurality of second internal electrodes 22b are substantially parallel to the thickness direction of the wiring board (on the surfaces where the first external electrode 26a and the second external electrode 26b face each other). Certain 26a ₁ and 26b ₁ are arranged substantially parallel to the thickness direction of the wiring board.

  Thus, in the multilayer capacitor 10 according to the present invention, when incorporated in the wiring board, the plurality of first internal electrodes 22a and the plurality of second internal electrodes 22b are arranged in the thickness direction of the wiring board (described later). Since the pitch of the electrode terminals of the semiconductor chip is narrowed and the pitch of the first external electrode 26a and the second external electrode 26b is correspondingly narrowed, the pitch between the electrode terminals of the semiconductor chip is narrow. The plurality of first internal electrodes 22a and the plurality of second internal electrodes 22b can be expanded in the thickness direction and the depth direction (Z direction and Y direction in FIG. 3) of the wiring board. A large area can be secured. As a result, since the multilayer capacitor 10 can have a sufficient capacity, it is possible to reduce voltage fluctuations of the power source of the semiconductor chip.

<Method for Manufacturing Multilayer Capacitor According to the Present Invention>
A method of manufacturing the multilayer capacitor 10 according to the present invention will be described with reference to FIGS. 4 to 17 are diagrams illustrating the manufacturing process of the multilayer capacitor according to the present invention. 4 to 17, the same components as those in FIG. 3 are denoted by the same reference numerals, and the description thereof may be omitted. First, in the step shown in FIG. 4, a support metal 20 is prepared. For example, Cu or Ni can be used as the material of the support metal 20. Moreover, you may use what plated Cu, Ni, Ag, Pd etc. to these materials.

  The support metal 20 is used as one of external electrodes (first external electrode or second external electrode) when the multilayer capacitor 10 is completed. Accordingly, the support metal 20 has the same thickness as the first external electrode 26a and the second external electrode 26b. The thickness of the support metal 20 can be 50-200 micrometers, for example. In FIG. 4, 20 a and 20 b indicate the first main surface and the second main surface of the support metal 20.

Next, in the step shown in FIG. 5, the dielectric layer 21 is formed on the first main surface 20 a and the second main surface 20 b of the support metal 20. As a material of the dielectric layer 21, for example, a ceramic material such as SrTiO ₃ (strontium titanate) or BaTiO ₃ (barium titanate) can be used. The dielectric layer 21 can be formed by sputtering, for example. Next, in the step shown in FIG. 6, a conductor layer (hereinafter, sometimes referred to as the conductor layer 22 a for convenience) is formed on the dielectric layer 21 as the first internal electrode 22 a. For example, Cu or Ni can be used as the conductor layer 22a. The conductor layer 22a can be formed by, for example, a sputtering method, a CVD method, an electrolytic plating method, or the like. The thickness of the conductor layer 22a can be, for example, about 1 to 10 μm.

  Next, in a step shown in FIG. 7, an opening 22x is formed in the conductor layer 22a. Specifically, for example, a resist film such as a dry film is formed on the conductor layer 22a, and a patterning process is performed on the resist film so as to cover a portion other than the portion where the opening 22x is to be formed. Then, the conductor layer 22a in the portion where the resist film is not formed is removed by etching. Further, the opening 22x is formed by removing the resist film.

  Next, in the step shown in FIG. 8, the dielectric layer 21 is further laminated on the dielectric layer 21 so as to cover the conductor layer 22a. Next, in the step shown in FIG. 9, a via hole 21x is formed in a portion of the dielectric layer 21 where the conductor layer 22a is not formed. The via hole 21x is formed so that the first main surface 20a and the second main surface 20b of the support metal 20 are exposed. The via hole 21x can be formed using, for example, a laser processing method or a plasma etching method.

  Next, in the step shown in FIG. 10, a conductor layer (hereinafter, sometimes referred to as a conductor layer 22b for convenience) is formed in the via hole 21x and on the dielectric layer 21 as the second internal electrode 22b. Thereby, the conductor layer 22b is electrically connected to the support metal 20 via the via hole 21x. Since the material and forming method of the conductor layer 22b are the same as those of the conductor layer 22a, the description thereof is omitted.

  Next, in the step shown in FIG. 11, an opening 22y is formed in the conductor layer 22b. Since the method of forming the opening 22y is the same as that of the opening 22x, description thereof is omitted. Next, in the step shown in FIG. 12, the dielectric layer 21 is further laminated on the dielectric layer 21 so as to cover the conductor layer 22b.

  Next, in the step shown in FIG. 13, a via hole 21y is formed in a portion of the dielectric layer 21 where the conductor layer 22b is not formed. The via hole 21y is formed so that the conductor layer 22a is exposed. The method of forming the via hole 21y is the same as that of the via hole 21x, and thus the description thereof is omitted.

  Thereafter, the structure shown in FIG. 14 is manufactured by repeating the process shown in FIG. 13 from the process shown in FIG. Next, in the step shown in FIG. 15, a conductor layer (hereinafter, sometimes referred to as a conductor layer 26 a for convenience) is formed on the dielectric layer 21 as the first external electrode 26 a. Specifically, a seed layer made of Cu or the like is formed on the dielectric layer 21 by sputtering or the like. Then, the conductor layer 26a is formed by forming, for example, Cu or Ni on the seed layer by an electrolytic plating method using the seed layer as a power feeding layer. The thickness of the seed layer can be set to 1 μm, for example. The thickness of the conductor layer 26a can be about 50-200 micrometers, for example. The conductor layer 26a may be formed only by sputtering.

  Thereafter, the structure shown in FIG. 16 is manufactured by repeating the process shown in FIG. 13 from the process shown in FIG. In FIG. 16, B indicates a position for cutting the structure shown in FIG. 16 (hereinafter referred to as cutting position B). In FIG. 16, reference numeral 26b denotes a conductor layer serving as a second external electrode (hereinafter sometimes referred to as a conductor layer 26b for convenience). The conductor layer 26b has the same structure as the conductor layer 26a, but the conductor layer 26a is connected to the conductor layer 22a via the via hole 21y, and the conductor layer 26b is connected to the conductor layer 22b via the via hole 21x. To do. Next, in the step shown in FIG. 17, the multilayer capacitor 10 is obtained by cutting the structure shown in FIG. 16 at a cutting position B with a dicing blade or the like.

The multilayer capacitor according to the present invention can also be manufactured by the following method. First, a green sheet mainly composed of a ceramic material such as SrTiO ₃ (strontium titanate) or BaTiO ₃ (barium titanate) is prepared. Next, a via hole is formed in the green sheet by a puncher or the like, and a conductive paste is embedded in the via hole, and then the conductive paste is screen-printed to form a conductor layer serving as an internal electrode. Further, a predetermined number of green sheets on which via holes and conductor layers are formed are laminated and thermocompression bonded to produce a laminate. And the multilayer capacitor | condenser which concerns on this invention can be formed by baking a laminated body in a non-oxidizing atmosphere, and cut | disconnecting and dividing | segmenting at a designated position.

<Semiconductor package according to the present invention>
A semiconductor package 30 incorporating the multilayer capacitor 10 according to the present invention will be described with reference to FIG. FIG. 18 is a cross-sectional view illustrating a semiconductor package incorporating a multilayer capacitor according to the present invention. 18, the same components as those in FIG. 3 are denoted by the same reference numerals, and the description thereof may be omitted. Referring to FIG. 18, the semiconductor package 30 includes a semiconductor chip 40, an electrode terminal 41, an underfill resin layer 42, and a wiring substrate 50.

  A support body 51 is provided at the center of the wiring board 50, and the multilayer capacitor 10 according to the present invention is built in the support body 51. The multilayer capacitor 10 is the one shown in FIG. The first external electrode 26a and the second external electrode 26b of the multilayer capacitor 10 have the same pitch P1 between the adjacent first external electrode 26a and the second external electrode 26b as the pitch of the adjacent electrode terminals 41 of the semiconductor chip 40 ( (Pitch between adjacent electrode terminals 41a and 41b) P3.

  In the wiring board 50, a first wiring layer 61 a is formed on the first main surface 51 a of the support 51. Further, a through via 69 penetrating from the first main surface 51a to the second main surface 51b is formed in the support body 51. The first wiring layer 61a is electrically connected to a later-described fifth wiring layer 61b through a through via 69. Further, a first insulating layer 52a is formed so as to cover the first wiring layer 61a, and a second wiring layer 62a is formed on the first insulating layer 52a. The first wiring layer 61a and the second wiring layer 62a are electrically connected through a first via hole 52x that penetrates the first insulating layer 52a.

  Further, the portion of the second wiring layer 62a disposed at a position corresponding to the first external electrode 26a and the second external electrode 26b of the multilayer capacitor 10 has a first via hole 52x penetrating the first insulating layer 52a. The first external electrode 26a and the second external electrode 26b of the multilayer capacitor 10 built in the support body 51 are electrically connected to each other.

  Further, a second insulating layer 53a is formed so as to cover the second wiring layer 62a. A third wiring layer 63a is formed on the second insulating layer 53a. The second wiring layer 62a and the third wiring layer 63a are electrically connected through a second via hole 53x that penetrates the second insulating layer 53a.

  Further, a third insulating layer 54a is formed so as to cover the third wiring layer 63a. A fourth wiring layer 64a is formed on the third insulating layer 54a. The third wiring layer 63a and the fourth wiring layer 64a are electrically connected through a third via hole 54x that penetrates the third insulating layer 54a.

  Further, a solder resist film 55a having an opening 55x is formed so as to cover the fourth wiring layer 64a. The portion exposed from the opening 55x of the solder resist film 55a of the fourth wiring layer 64a functions as an electrode pad (hereinafter, the portion exposed from the opening 55x of the solder resist film 55a of the fourth wiring layer 64a is the electrode pad 64a. Sometimes). Hereinafter, the surface on which the electrode pad 64a is formed may be referred to as a first main surface of the wiring board 50.

  A fifth wiring layer 61b is formed on the second main surface 51b of the support 51, and a fourth insulating layer 52b is formed so as to cover the fifth wiring layer 61b. A sixth wiring layer 62b is formed on the fourth insulating layer 52b. The fifth wiring layer 61b and the sixth wiring layer 62b are electrically connected through a fourth via hole 52y that penetrates the fourth insulating layer 52b.

  Further, a fifth insulating layer 53b is formed so as to cover the sixth wiring layer 62b. A seventh wiring layer 63b is formed on the fifth insulating layer 53b. The sixth wiring layer 62b and the seventh wiring layer 63b are electrically connected through a fifth via hole 53y that penetrates the fifth insulating layer 53b.

  Further, a sixth insulating layer 54b is formed so as to cover the seventh wiring layer 63b. An eighth wiring layer 64b is formed on the sixth insulating layer 54b. The seventh wiring layer 63b and the eighth wiring layer 64b are electrically connected through a sixth via hole 54y that penetrates the sixth insulating layer 54b.

  Further, a solder resist film 55b having an opening 55y is formed so as to cover the eighth wiring layer 64b. The portion exposed from the opening 55y of the solder resist film 55b of the eighth wiring layer 64b functions as an electrode pad (hereinafter, the portion exposed from the opening 55y of the solder resist film 55b of the eighth wiring layer 64b is the electrode pad 64b. Sometimes). Hereinafter, the surface on which the electrode pad 64b is formed may be referred to as a second main surface of the wiring board 50.

  External connection terminals 68 are formed on the electrode pads 64b. The external connection terminal 68 is, for example, a solder bump. The external connection terminal 68 functions as a connection terminal that is electrically connected to a corresponding terminal of the circuit board when the semiconductor package 30 is mounted on a circuit board (not shown).

  A semiconductor chip 40 is mounted on the first main surface of the wiring board 50. The semiconductor chip 40 is obtained by forming a semiconductor integrated circuit (not shown) and electrode pads (not shown) on a thinned semiconductor substrate (not shown) made of silicon or the like. On the electrode pad (not shown) of the semiconductor chip 40, an electrode terminal 41 serving as an electrode is formed. Electrode pads (not shown) of the semiconductor chip 40 are electrically connected to corresponding electrode pads 64 a of the wiring board 50 by electrode terminals 41. The electrode terminal 41 is made of, for example, solder. An underfill resin layer 42 is filled between the semiconductor chip 40 and the solder resist film 55 a of the wiring substrate 50.

  Among the electrode terminals 41, 41 a is an electrode terminal connected to the power supply of the semiconductor chip 40, 41 b is an electrode terminal connected to the reference potential (GND) of the semiconductor chip 40, and 41 c is connected to a signal line of the semiconductor chip 40. The electrode terminal to be used is shown.

  FIG. 19 is a bottom view illustrating the positional relationship between the arrangement of the electrode terminals of the semiconductor chip and the multilayer capacitor. FIG. 19A shows the semiconductor package 30 shown in FIG. 18 in which only the semiconductor chip 40 is viewed from the Z minus direction. As shown in FIG. 19A, in the semiconductor chip 40, the electrode terminals 41c are arranged in two rows on the outer periphery, and the electrode terminals 41a and 41b are arranged inside thereof. Six electrode terminals 41a and 41b are continuously arranged in the Y direction. The electrode terminals 41a and 41b are alternately arranged in the X direction.

  Note that the number of electrode terminals 41a to 41c is determined for the sake of convenience, and is not limited to this. It is possible to arrange the electrode terminals 41a to 41c in numbers other than those shown here. Further, the arrangement of the electrode terminals 41a to 41c is not limited to that shown in FIG. 19, and may be arranged in a dust shape, for example.

  FIG. 19B schematically shows the positional relationship between the electrode terminals 41 a and 41 b and the multilayer capacitor 10. As shown in FIG. 19B, the multilayer capacitor 10 is disposed directly below the region where the electrode terminals 41a and 41b are disposed. The plurality of first external electrodes 26 a of the multilayer capacitor 10 are electrically connected to electrode terminals 41 a connected to the power source of the semiconductor chip 40, and the plurality of second external electrodes 26 b are reference potentials (GND) of the semiconductor chip 40. It is electrically connected to the electrode terminal 41b connected to the.

  As shown in FIG. 18, between the semiconductor chip 40 and the multilayer capacitor 10, a first insulating layer 52a to a third insulating layer 54a and a second wiring layer 62a to a fourth wiring layer 64a are formed. . Therefore, the electrode terminals 41a and 41b of the semiconductor chip 40 and the first external electrode 26a and the second external electrode 26b of the multilayer capacitor 10 are electrically connected via the second wiring layer 62a to the fourth wiring layer 64a. Is done.

  Thus, in the multilayer capacitor 10 according to the present invention, the first internal electrode 22a and the second internal electrode 22b are arranged in the thickness direction (Z direction) of the wiring board 50 when incorporated in the wiring board 50. Since the pitches of the electrode terminals 41 of the semiconductor chip 40 are reduced and the pitches of the first external electrodes 26a and the second external electrodes 26b are correspondingly reduced, the first internal electrodes are arranged in parallel. Since the electrode 22a and the second internal electrode 22b can be expanded in the thickness direction and the depth direction (Z direction and Y direction in FIG. 18) of the wiring board 50, a sufficient area can be secured. . As a result, since the multilayer capacitor 10 can have a sufficient capacity, it is possible to reduce the voltage fluctuation of the power source of the semiconductor chip 40.

  For example, as the pitch of the electrode terminals 41 of the semiconductor chip 40 becomes narrower, the width of the region sandwiched between the adjacent first external electrode 26a and second external electrode 26b becomes the first external electrode 26a and Even when the width is smaller than the width W1 (see FIG. 3) of the second external electrode 26b, the multilayer capacitor 10 can have a sufficient capacity.

<Method for Manufacturing Semiconductor Package According to the Present Invention>
A method of manufacturing the semiconductor package 30 incorporating the multilayer capacitor 10 according to the present invention will be described with reference to FIGS. 20 to 30 are views illustrating the manufacturing process of the semiconductor package according to the present invention. 20 to 30, the same components as those in FIG. 18 are denoted by the same reference numerals and description thereof may be omitted.

  First, in the step shown in FIG. 20, a support 51 is prepared. The support 51 is made of an insulating material. Since the multilayer capacitor 10 is built in the support 51, the thickness of the support 51 can be arbitrarily set in consideration of the thickness of the multilayer capacitor 10. Next, in the step shown in FIG. 21, through holes 51x are provided in the support 51 using a router processing method, a laser processing method, or the like. FIG. 21A is a cross-sectional view, and FIG. 21B is a perspective view.

  Next, in the step shown in FIG. 22, the multilayer capacitor 10 according to the present invention manufactured in advance by a predetermined manufacturing method is prepared and inserted into the through hole 51 x of the support 51. FIG. 22A is a cross-sectional view, and FIG. 22B is a perspective view.

  Next, in a step shown in FIG. 23, a through via 69 penetrating the support 51 is formed by an NC drill or the like, and a conductor such as Cu is filled. Further, the first wiring layer 61 a and the fifth wiring layer 61 b are formed on the first main surface 51 a and the second main surface 51 b of the support 51. The first wiring layer 61a is electrically connected to the fifth wiring layer 61b through the through via 69. As a material of the first wiring layer 61a and the fifth wiring layer 61b, for example, Cu or the like can be used. The first wiring layer 61a and the fifth wiring layer 61b can be formed as follows, for example.

  First, a resist film such as a dry film is formed on the first main surface 51 a and the second main surface 51 b of the support 51. Next, a patterning process is performed on the resist film to form openings at portions corresponding to the positions where the first wiring layer 61a and the fifth wiring layer 61b are formed. An opening is formed in advance in the dry film resist film, and the resist film in which the opening is formed is disposed on the first main surface 51a and the second main surface 51b of the support 51. Also good. Next, a conductor layer to be the first wiring layer 61a and the fifth wiring layer 61b is formed in the opening by, for example, electroless plating, and then the first wiring layer 61a and the fifth wiring layer 61b are removed by removing the resist film. Can be formed.

  Next, in the step shown in FIG. 24, the first insulating layer 52a and the fourth insulating layer that cover the first wiring layer 61a and the fifth wiring layer 61b on the first main surface 51a and the second main surface 51b of the support 51. 52b is formed. As a material of the first insulating layer 52a and the fourth insulating layer 52b, a resin material such as an epoxy resin or a polyimide resin can be used.

  The first insulating layer 52a and the fourth insulating layer 52b, for example, after laminating a resin film on the first main surface 51a and the second main surface 51b of the support 51, press (press) the resin film, It can be formed by heat treatment at a temperature of about 190 ° C. and curing. When there is a gap between the through hole 51x and the multilayer capacitor 10, the gap is filled with the first insulating layer 52a and the fourth insulating layer 52b.

  Next, in the step shown in FIG. 25, the first via hole 52x and the first via hole 52x and the fourth insulating layer 52b are formed at predetermined positions of the first insulating layer 52a and the fourth insulating layer 52b formed on the support 51 by using a laser processing method or a plasma etching method. Four via holes 52y are formed. The first via hole 52x and the fourth via hole 52y are formed so that the first external electrode 26a and the second external electrode 26b or the first wiring layer 61a and the fifth wiring layer 61b of the multilayer capacitor 10 are exposed.

  Here, the width of the first external electrode 26a and the second external electrode 26b of the multilayer capacitor 10 is set so that the first external electrode 26a and the second external electrode 26b side of the first via hole 52x and the fourth via hole 52y are outside. It is preferably wider than the diameter. If processing deviation does not occur at all in the manufacturing process, the width of the first external electrode 26a and the second external electrode 26b of the multilayer capacitor 10 is set to be the first external electrode of the first via hole 52x and the fourth via hole 52y. It may be equal to the outer diameter on the side of 26a and the second external electrode 26b. However, in actuality, since processing deviation occurs, the width of the first external electrode 26a and the second external electrode 26b of the multilayer capacitor 10 is set to be, for example, equal to or larger than the minimum pad diameter of the interlayer connection of the wiring board 50 in consideration of this. It is preferable.

  Here, the interlayer connection minimum land diameter is, for example, that of the second wiring layer 62a formed on the side opposite to the external electrode 26a of the first via hole 52x formed on the external electrode 26a of the multilayer capacitor 10 in FIG. The diameter of the part (this part is called a pad).

  Note that a method may be used in which a photosensitive resin film is used as the first insulating layer 52a and the fourth insulating layer 52b, and the first via hole 52x and the fourth via hole 52y are formed by patterning by photolithography, or by screen printing. A method of forming the first via hole 52x and the fourth via hole 52y by patterning the resin film provided with the opening may be used.

  Next, in the step shown in FIG. 26, the first wiring layer 61a and the fifth wiring layer 61b are connected to the first insulating layer 52a and the fourth insulating layer 52b through the first via hole 52x and the fourth via hole 52y. A second wiring layer 62a and a sixth wiring layer 62b are formed. For example, Cu or the like can be used as the second wiring layer 62a and the sixth wiring layer 62b. The second wiring layer 62a and the sixth wiring layer 62b are formed by, for example, a semi-additive method.

  An example in which the second wiring layer 62a and the sixth wiring layer 62b are formed by a semi-additive method will be described in more detail. First, in the first via hole 52x and the fourth via hole 52y and by the electroless plating method or the sputtering method. After a Cu seed layer (not shown) is formed on the first insulating layer 52a and the fourth insulating layer 52b, a resist film (not shown) having openings corresponding to the second wiring layer 62a and the sixth wiring layer 62b. ). Next, a Cu layer pattern (not shown) is formed in the opening of the resist film by electrolytic plating using the Cu seed layer as a plating power supply layer.

  Subsequently, after removing the resist film, the Cu seed layer is etched using the Cu layer pattern as a mask to obtain the second wiring layer 62a and the sixth wiring layer 62b. In addition, as a formation method of the 2nd wiring layer 62a and the 6th wiring layer 62b, various methods, such as a subtractive method other than the semi-additive method mentioned above, can be used.

  Next, in the step shown in FIG. 27, by repeating the same steps as described above, the first wiring layer 61a to the fourth wiring layer 64a, the first insulating layer 52a to the third insulating layer 54a, and the fifth wiring layer 61b. The eighth wiring layer 64b and the fourth insulating layer 52b to the sixth insulating layer 54b are stacked. That is, after forming the second insulating layer 53a and the fifth insulating layer 53b covering the second wiring layer 62a and the sixth wiring layer 62b, the second insulating layer 53a on the second wiring layer 62a and the sixth wiring layer 62b. The second via hole 53x and the fifth via hole 53y are formed in the portion of the fifth insulating layer 53b.

  Furthermore, on the second insulating layer 53a and the fifth insulating layer 53b, a third wiring layer 63a and a third wiring layer 63a connected to the second wiring layer 62a and the sixth wiring layer 62b via the second via hole 53x and the fifth via hole 53y are provided. Seven wiring layers 63b are formed. As a material of the third wiring layer 63a and the seventh wiring layer 63b, for example, Cu or the like can be used. The third wiring layer 63a and the seventh wiring layer 63b are formed by, for example, a semi-additive method.

  Further, after forming the third insulating layer 54a and the sixth insulating layer 54b covering the third wiring layer 63a and the seventh wiring layer 63b, the third insulating layer 54a on the third wiring layer 63a and the seventh wiring layer 63b. The third via hole 54x and the sixth via hole 54y are formed in the portion of the sixth insulating layer 54b.

  Furthermore, on the third insulating layer 54a and the sixth insulating layer 54b, the fourth wiring layer 64a and the fourth wiring layer 64a connected to the third wiring layer 63a and the seventh wiring layer 63b through the third via hole 54x and the sixth via hole 54y, and the sixth wiring layer 64a. Eight wiring layers 64b are formed. As a material of the fourth wiring layer 64a and the eighth wiring layer 64b, for example, Cu or the like can be used. The fourth wiring layer 64a and the eighth wiring layer 64b are formed by, for example, a semi-additive method.

  In this way, a predetermined build-up wiring layer is formed on the support 51. In the present embodiment, four build-up wiring layers (the first wiring layer 61a to the fourth wiring layer 64a and the fifth wiring layer 61b to the first main surface 51a and the second main surface 51b of the support body 51, respectively. Although the eighth wiring layer 64b) is formed, an n-layer (n is an integer of 1 or more) build-up wiring layer may be formed.

  28, solder resist films 55a and 55b are formed on the third insulating layer 54a and the sixth insulating layer 54b so as to cover the fourth wiring layer 64a and the eighth wiring layer 64b. Then, the openings 55x and 55y are formed by exposing and developing the solder resist films 55a and 55b. Thus, the fourth wiring layer 64a and the eighth wiring layer 64b are exposed in the openings 55x and 55y of the solder resist films 55a and 55b.

  Next, in the process shown in FIG. 29, for example, a Ni plating layer and an Au plating layer are laminated in this order on the fourth wiring layer 64a and the eighth wiring layer 64b in the openings 55x and 55y of the solder resist films 55a and 55b. A Ni / Au plating layer or the like (not shown) is formed. Then, the external connection terminal 68 is formed on the Ni / Au plating layer or the like formed on the eighth wiring layer 64b in the opening 55y of the solder resist film 55b. The external connection terminal 68 is, for example, a solder bump.

  Next, in the step shown in FIG. 30, a semiconductor chip 40 on which the electrode terminals 41 are formed is prepared. Then, a pre-solder (not shown) is formed on the Ni / Au plating layer formed on the fourth wiring layer 64a in the opening 55x of the solder resist film 55a. The pre-solder is obtained by applying a solder paste on a Ni / Au plating layer or the like and performing a reflow process. Also, solder balls may be mounted on the Ni / Au plating layer or the like.

  Then, the electrode terminal 41 of the semiconductor chip 40 and the pre-solder formed in the opening 55x of the solder resist film 55a are electrically connected. The electrical connection between the electrode terminal 41 of the semiconductor chip 40 and the pre-solder is performed, for example, by heating to 230 ° C. and melting the solder. In addition, when the electrode terminal 41 of the semiconductor chip 40 is made of solder, the electrode terminal 41 and the pre-solder are melted to become an alloy, and one bump is formed. Next, the underfill resin 42 is filled between the semiconductor chip 40 and the solder resist film 55a, thereby completing the semiconductor package 30 shown in FIG.

  According to the present invention, when the multilayer capacitor 10 is built in the wiring board 50, the first internal electrode 22a and the second internal electrode 22b are substantially parallel (supported) in the thickness direction (Z direction) of the wiring board 50. The pitch of the electrode terminals 41 of the semiconductor chip 40 is narrowed, and the first external electrode 26a and the second external electrode 26a are correspondingly arranged in the first main surface 51a and the second main surface 51b of the body 51. Even if the pitch of the external electrodes 26b becomes narrow, the first internal electrodes 22a and the second internal electrodes 22b expand in the thickness direction and the depth direction (Z direction and Y direction in FIG. 18) of the wiring board 50. Therefore, a sufficient area can be secured. As a result, since the multilayer capacitor 10 can have a sufficient capacity, it is possible to reduce the voltage fluctuation of the power source of the semiconductor chip 40.

  In addition, the connection between the electrode terminal 41a connected to the power source of the semiconductor chip 40 and the electrode terminal 41b connected to the reference potential (GND) and the multilayer capacitor 10 can be minimized, and the parasitic inductance can be kept extremely low. Can do.

  In addition, since the multilayer capacitor 10 is built in the semiconductor package 30, the semiconductor package 30 can be thinned.

  Further, since it is not necessary to connect the first external electrode 26a and the second external electrode 26b of the multilayer capacitor 10 and the electrode terminals 41a and 41b of the semiconductor chip 40 with solder, it is possible to achieve high connection reliability. it can.

  The preferred embodiment of the present invention has been described in detail above. However, the present invention is not limited to the above-described embodiment, and various modifications can be made to the above-described embodiment without departing from the scope of the present invention. And substitutions can be added.

It is sectional drawing which illustrates the conventional semiconductor package. It is sectional drawing which expands and illustrates the chip capacitor shown in FIG. It is a figure which illustrates the multilayer capacitor concerning this invention. FIG. 3 is a diagram (part 1) illustrating a manufacturing process of the multilayer capacitor in accordance with the present invention; It is FIG. (The 2) which illustrates the manufacturing process of the multilayer capacitor which concerns on this invention. FIG. 6 is a diagram (No. 3) illustrating a manufacturing step of the multilayer capacitor in accordance with the present invention; FIG. 7 is a diagram (No. 4) illustrating the production process for the multilayer capacitor in accordance with the present invention; FIG. 5 is a diagram (No. 5) illustrating a manufacturing step of the multilayer capacitor in accordance with the present invention; It is FIG. (The 6) which illustrates the manufacturing process of the multilayer capacitor which concerns on this invention. FIG. 7 is a view (No. 7) illustrating the manufacturing step of the multilayer capacitor according to the invention; It is FIG. (The 8) which illustrates the manufacturing process of the multilayer capacitor which concerns on this invention. It is FIG. (The 9) which illustrates the manufacturing process of the multilayer capacitor which concerns on this invention. It is FIG. (10) which illustrates the manufacturing process of the multilayer capacitor which concerns on this invention. It is FIG. (The 11) which illustrates the manufacturing process of the multilayer capacitor which concerns on this invention. It is FIG. (12) which illustrates the manufacturing process of the multilayer capacitor which concerns on this invention. It is FIG. (13) which illustrates the manufacturing process of the multilayer capacitor which concerns on this invention. It is FIG. (The 14) which illustrates the manufacturing process of the multilayer capacitor which concerns on this invention. It is sectional drawing which illustrates the semiconductor package which incorporates the multilayer capacitor concerning this invention. It is a bottom view illustrating the positional relationship between the arrangement of the electrode terminals of the semiconductor chip and the multilayer capacitor. It is FIG. (The 1) which illustrates the manufacturing process of the semiconductor package which concerns on this invention. It is FIG. (The 2) which illustrates the manufacturing process of the semiconductor package which concerns on this invention. It is FIG. (The 3) which illustrates the manufacturing process of the semiconductor package which concerns on this invention. It is FIG. (The 4) which illustrates the manufacturing process of the semiconductor package which concerns on this invention. FIG. 10 is a diagram (No. 5) for exemplifying the manufacturing process for the semiconductor package according to the invention; It is FIG. (The 6) which illustrates the manufacturing process of the semiconductor package which concerns on this invention. It is FIG. (The 7) which illustrates the manufacturing process of the semiconductor package which concerns on this invention. It is FIG. (The 8) which illustrates the manufacturing process of the semiconductor package which concerns on this invention. It is FIG. (9) which illustrates the manufacturing process of the semiconductor package which concerns on this invention. It is FIG. (The 10) which illustrates the manufacturing process of the semiconductor package which concerns on this invention. It is FIG. (The 11) which illustrates the manufacturing process of the semiconductor package which concerns on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Multilayer capacitor 20 Support metal 20a 1st main surface 20b of support metal 20 2nd main surface of support metal 20 21 Dielectric layer 21x, 21y Via hole 22a 1st internal electrode 22b 2nd internal electrode 22x, 22y Opening 26a first of the first external electrode 26b second external electrodes 26a _1, 26b ₁ surface 30 semiconductor package 40 semiconductor chips 41, 41a, 41b, 41c electrode terminal 42 underfill resin layer 50 wiring substrate 51 substrate 51a support 51 Main surface 51b Second main surface 51x, 55x, 55y of support 51 Opening 52a First insulating layer 52b Fourth insulating layer 52x First via hole 52y Fourth via hole 53a Second insulating layer 53b Fifth insulating layer 53x Second via hole 53y 5th via hole 54a 3rd insulating layer 54b 6th insulating layer 54x 3 via hole 54y 6th via hole 55a, 55b Solder resist film 61a 1st wiring layer 61b 5th wiring layer 62a 2nd wiring layer 62b 6th wiring layer 63a 3rd wiring layer 63b 7th wiring layer 64a 4th wiring layer 64b 8th Wiring layer 68 External connection terminal 69 Through via A part B Cutting position P1, P2, P3 Pitch W1, W2 Width

Claims (14)

A dielectric layer having a first surface and a second surface opposite to the first surface;
A first external electrode and a second external electrode formed in the dielectric layer, penetrating through the dielectric layer in a thickness direction and having end faces exposed from the first surface and the second surface;
The first external electrode and the second external electrode are connected to the first external electrode in a region formed on the dielectric layer and sandwiched between the first external electrode and the second external electrode. A plurality of first internal electrodes arranged in parallel with each other at a predetermined interval in parallel with the opposing surfaces of the external electrodes ;
A plurality of dielectric layers formed on the dielectric layer, connected to the second external electrodes, and arranged in parallel at a predetermined interval so as to be interleaved with the plurality of first internal electrodes. and a second internal electrode,
End surfaces of the first external electrode and the second external electrode are flush with the first surface and the second surface of the dielectric layer,
The first external electrode, the first internal electrode, and the first internal electrodes are mutually connected via via holes provided in a region of the dielectric layer where the second internal electrode is not formed. Connected to
The second external electrode, the second internal electrode, and the second internal electrodes are mutually connected via via holes provided in a region of the dielectric layer where the first internal electrode is not formed. A multilayer capacitor characterized by being connected to a capacitor.   A plurality of the first external electrodes and the second external electrodes are provided, respectively, and the first external electrodes and the second external electrodes are alternately formed at a predetermined cycle. Item 11. The multilayer capacitor according to Item 1. The first external electrode and the second width of the region between the external electrodes, according to claim 1 or 2, characterized in that narrower than the width of the first external electrode and the second external electrodes The multilayer capacitor described. A semiconductor package comprising a wiring board incorporating the multilayer capacitor according to any one of claims 1 to 3 , and a semiconductor chip electrically connected to the wiring board via a plurality of electrode terminals,
The semiconductor package according to claim 1, wherein the first internal electrode and the second internal electrode of the multilayer capacitor are arranged so as to be substantially parallel to a thickness direction of the wiring board. The wiring board has a structure in which wiring layers and insulating layers are alternately stacked on a support, and the wiring layers are electrically connected to each other through via holes,
The first external electrode and the second external electrode of the multilayer capacitor are directly electrically connected to the wiring layer through the via hole ,
5. The semiconductor package according to claim 4 , wherein the multilayer capacitor is inserted into a through hole formed through the support constituting the wiring board . Among the plurality of electrode terminals, a plurality of electrode terminals corresponding to the power source of the semiconductor chip and a plurality of electrode terminals corresponding to the reference potential of the semiconductor chip are arranged in parallel at a predetermined pitch,
Wherein the predetermined pitch, rather equal to the pitch between the adjacent first external electrode and the second external electrodes,
One of the first external electrode and the second external electrode is connected to a plurality of electrode terminals corresponding to the power source of the semiconductor chip,
Other semiconductor package according to claim 4 or 5, wherein it is connected to a plurality of electrode terminals corresponding to the reference potential of the semiconductor chip of the said first external electrode and the second external electrode . One of the first external electrode and the second external electrode is disposed directly below a plurality of electrode terminals corresponding to the power source of the semiconductor chip,
The other of said first external electrode and the second external electrode of claims 4 to 6, characterized in that it is disposed directly below the vertical of the plurality of electrode terminals corresponding to the reference potential of the semiconductor chip The semiconductor package according to any one of the above. 6. The semiconductor package according to claim 5 , wherein a thickness of the multilayer capacitor is equal to or less than a thickness of the support. A method for manufacturing a multilayer capacitor according to any one of claims 1 to 3 ,
A first step of forming a first dielectric layer on both sides of a support metal composed of a conductor;
A second step of forming a conductor layer having a predetermined opening serving as a first internal electrode on the first dielectric layer;
A third step of laminating a second dielectric layer on the conductor layer serving as the first internal electrode ;
A fourth step of forming a first via hole at a position corresponding to a predetermined opening of the conductor layer serving as the first internal electrode of the first dielectric layer and the second dielectric layer;
A fifth step of forming a conductor layer having a predetermined opening to be a second internal electrode on the second dielectric layer;
A sixth step of forming a third dielectric layer on the conductor layer serving as the second internal electrode ;
A seventh step of forming a second via hole at a position corresponding to a predetermined opening of the conductor layer serving as the second internal electrode of the second dielectric layer and the third dielectric layer;
The second said from step seventh steps similar to repeated predetermined number of times, the connecting conductor layer to each other to be the first inner electrode to each other via the second via hole, said second An eighth step of connecting conductor layers to be internal electrodes to each other through the first via hole ;
A ninth step of forming a conductor layer to be a first external electrode connected to the first internal electrode;
A tenth step of forming a conductor layer to be a second external electrode connected to the second internal electrode;
Have a, the eleventh step of cutting into pieces the structure formed by the tenth step in a predetermined position,
Wherein in the eleventh step, the manufacturing method of the multilayer capacitor in each end surface of the first external electrode and the second external electrodes, characterized in Rukoto Do the end face flush of each dielectric layer. A method for manufacturing a multilayer capacitor according to any one of claims 1 to 3 ,
A first via hole is formed at a position corresponding to a predetermined opening of the conductor layer serving as the first internal electrode, and a second via hole is formed at a position corresponding to the predetermined opening of the conductor layer serving as the second internal electrode. A first step of preparing a plurality of green sheets including first to third green sheets in which via holes are formed;
A second step of forming a conductor layer having a predetermined opening serving as a first internal electrode on the first green sheet;
A third step of laminating the second green sheet on the first green sheet on which the conductive layer to be the first internal electrode has been formed in the second step;
A fourth step of forming a conductor layer having a predetermined opening serving as a second internal electrode on the second green sheet laminated in the third step;
A fifth step of laminating the third green sheet on the second green sheet on which the conductor layer to be the second internal electrode has been formed in the fourth step;
The second said from Step fifth steps similar to repeated predetermined number of times, the connecting conductor layer to each other to be the first inner electrode to each other via the second via hole, said second A sixth step of connecting conductor layers to be internal electrodes to each other through the first via hole ;
A seventh step of forming a conductor layer to be a first external electrode connected to the first internal electrode;
An eighth step of forming a conductor layer to be a second external electrode connected to the second internal electrode;
A ninth step of firing the structure formed in the eighth step in a non-oxidizing atmosphere;
Have a, a tenth step of cutting into pieces the structure was fired at the ninth step in a predetermined position,
And in the tenth step, the first external electrode and the second layered capacitor each end face of the external electrode and the end face and wherein Do Rukoto flush the dielectric layer formed from the green sheets Production method. 11. The multilayer capacitor according to claim 9, wherein the first via hole or the second via hole is formed so that a surface of the supporting metal or a surface of a conductor constituting the conductor layer is exposed. Method. A wiring board with a built-in multilayer capacitor according to any one of claims 1 to 3, a semiconductor chip electrically connected through the wiring board and a plurality of electrode terminals, in a manufacturing method of a semiconductor package having a There,
A first step of forming a through hole in a support constituting the wiring board;
A second step of disposing the multilayer capacitor in the through hole so that the first internal electrode and the second internal electrode of the multilayer capacitor are substantially parallel to a thickness direction of the wiring board;
A third step of forming an insulating layer on the support so as to cover the multilayer capacitor;
A fourth step of forming a via hole penetrating the insulating layer so that the first external electrode and the second external electrode of the multilayer capacitor are exposed;
And a fifth step of forming a wiring layer on the first external electrode and the second external electrode exposed in the via hole. A sixth step of further laminating an insulating layer and a wiring layer on the insulating layer and the wiring layer;
A seventh step of forming a via hole penetrating the insulating layer;
13. The method of manufacturing a semiconductor package according to claim 12 , further comprising an eighth step of forming an electrode pad connected to the first external electrode and the second external electrode of the capacitor through the via hole. . Furthermore, one of the first external electrode and the second external electrode is connected to a plurality of electrode terminals corresponding to the power source of the semiconductor chip,
Ninth connecting the electrode pad and the semiconductor chip such that the other of the first external electrode and the second external electrode is connected to a plurality of electrode terminals corresponding to the reference potential of the semiconductor chip. 14. The method of manufacturing a semiconductor package according to claim 13 , further comprising: a step.

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