JP5228752B2 - Chip-type electronic components - Google Patents

Description

  The present invention relates to a chip-type electronic component.

The chip-type electronic component includes a rectangular parallelepiped chip element including internal circuit elements, and a plurality of external electrodes that are electrically connected to the internal circuit elements and disposed on the outer surface of the chip element. Those are known (for example, see Patent Document 1). In the chip-type electronic component disclosed in Patent Document 1, by setting the length of the external electrode extending from the short side of the lower surface of the chip body to be longer than the length of the external electrode extending from the long side of the lower surface, The external electrode is prevented from being damaged, and the impact resistance of the chip-type electronic component is improved.
JP 2008-147349 A

  However, as a result of the research by the present inventors, the chip-type electronic component disclosed in Patent Document 1 may not be able to sufficiently improve the impact resistance. In particular, the chip body has cracks. It was found to occur.

  An object of the present invention is to provide a chip-type electronic component that prevents cracks from occurring in a chip body and has extremely excellent impact resistance.

  The inventors have a rectangular parallelepiped chip element including internal circuit elements, and a plurality of external electrodes that are electrically connected to the internal circuit elements and disposed on the outer surface of the chip element body. A mold type electronic component was prepared, the chip type electronic component was mounted on a circuit board, and a substrate bending resistance test in which the circuit board was bent, a so-called deflection test was performed. In the prepared chip-type electronic component, the chip body has the first and second main surfaces so as to connect the first and second main surfaces of the rectangular shape facing each other and the first and second main surfaces. The first and second side surfaces extending in the long side direction of the surface and facing each other, and the first and second main surfaces extending in the short side direction so as to connect the first and second main surfaces and facing each other And a plurality of external electrodes formed on the first and second side surfaces, respectively, such that the end portions wrap around the first and second main surfaces. 1 external electrode, and a second external electrode formed on each of the third and fourth side surfaces so that the end portion wraps around the first and second main surfaces. In the deflection test, the chip-type electronic component was mounted with the second main surface as a mounting surface and facing the circuit board.

  As a result of the deflection test, it was found that cracks occurred in the chip body. When a crack occurs in the chip body, the electrical characteristics are adversely affected, such as disconnection of internal circuit elements, moisture permeation from the crack, and short circuit.

  The present inventors investigated the cause of cracking. As a result, when the circuit board is bent, stress is applied to the end portion of the portion that wraps around the second main surface (mounting surface) of the second external electrode formed on the third and fourth side surfaces. It was found that cracks occurred in the chip body starting from this end. Since the third and fourth side surfaces oppose each other in the long side direction of the first and second main surfaces, and the second external electrode is located at the longitudinal end of the chip body, the circuit The force that the second external electrode receives from the circuit board when the board is bent increases. The force received from the circuit board is concentrated as stress on the edge of the portion that wraps around the second main surface (mounting surface), particularly in the vicinity of the edge in the opposing direction of the third and fourth side surfaces. Therefore, if the stress can be suppressed from being concentrated at a specific location when the circuit board is bent, the occurrence of cracks can be prevented.

  Accordingly, the present invention has been made in view of the above-described phenomenon, and is a rectangular parallelepiped chip element including internal circuit elements, and is electrically connected to the internal circuit elements and disposed on the outer surface of the chip element. A chip-type electronic component comprising a plurality of external electrodes, wherein the chip body has, as an outer surface, rectangular first and second main surfaces facing each other, and first and second main surfaces. First and second side surfaces extending in the long side direction of the first and second main surfaces so as to connect the surfaces and facing each other, and the first and second main surfaces are connected to each other. A third external surface extending in the short side direction of the second main surface and facing each other, and the plurality of external electrodes are formed on the first and second side surfaces, respectively. An electrode, a second external electrode formed on each of the third and fourth side surfaces, and a second main surface. Together they comprise a third and a third external electrode extending in the opposing direction of the fourth side connecting the second external electrodes each other, the.

  In the chip-type electronic component according to the present invention, the second external electrodes formed on the third and fourth side surfaces are formed on the second main surface and the opposing direction of the third and fourth side surfaces Are connected by a third external electrode extending in the direction. For this reason, even when the chip-type electronic component according to the present invention is mounted on the circuit board with the second main surface as the mounting surface, the second and third external electrodes on the second main surface include the third and third external electrodes. A portion corresponding to the edge does not exist when viewed in the opposing direction of the fourth side surface. Therefore, according to the present invention, the second and third external electrodes cannot have a portion where stress is concentrated, and it is possible to prevent the chip body from being cracked.

  Preferably, the width of the third external electrode is set to be narrower than the width of the second external electrode. In this case, the distance between the third external electrode and the first external electrode becomes relatively large, and the occurrence of a short circuit between the third external electrode and the first external electrode can be prevented.

  Preferably, the width of the third external electrode is set wider than the width of the second external electrode. In this case, the mounting strength can be improved by connecting the third external electrode to the electrode on the circuit board.

  ADVANTAGE OF THE INVENTION According to this invention, it can suppress that a chip | tip body generate | occur | produces a crack and can provide the chip-type electronic component which was extremely excellent in impact resistance.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted.

  The chip-type electronic component according to the present embodiment will be described with reference to FIGS. In this embodiment, the multilayer filter 10 is illustrated as a chip-type electronic component. 1 and 2 are perspective views showing the multilayer filter according to the present embodiment. FIG. 3 is an exploded perspective view showing the chip body shown in FIGS. 1 and 2 in an exploded manner for each layer. FIG. 4 is a circuit diagram showing the multilayer filter according to the present embodiment.

  As shown in FIGS. 1 and 2, the multilayer filter 10 is a multilayer filter array component in which four L-type filter elements each composed of an inductor and a capacitor are provided in parallel. The multilayer filter 10 includes a substantially rectangular parallelepiped chip body 12. The multilayer filter 10 includes four pairs of terminal electrodes 14a to 14d and 16a to 16d, a pair of ground terminal electrodes 18a and 18b, and one connection electrode 18c as a plurality of external electrodes.

  The chip body 12 has first and second main surfaces 12a and 12b and first to fourth side surfaces 12c to 12f. The first and second main surfaces 12a and 12b are opposed to each other and have a rectangular shape. The first and second side surfaces 12c and 12d extend in the long side direction of the first and second main surfaces 12a and 12b so as to connect the first and second main surfaces 12a and 12b and face each other. Yes. The third and fourth side surfaces 12e and 12f extend in the short side direction of the first and second main surfaces 12a and 12b so as to connect the first and second main surfaces 12a and 12b and face each other. Yes. The second main surface 12b is a mounting surface for other components (for example, a circuit board or an electronic component).

  The terminal electrodes 14a, 14b, 14c, and 14d are sequentially provided on the first side surface 12c, and each has a shape extending in the stacking direction of the chip body 12. Similarly, the terminal electrodes 16a, 16b, 16c, and 16d are sequentially provided on the second side surface 12d, and each has a shape extending in the stacking direction of the chip body 12. That is, the terminal electrodes 14a, 14b, 14c, and 14d and the terminal electrodes 16a, 16b, 16c, and 16d each form a pair of terminal electrodes, and are formed on the outer surface of the chip body 12 so as to face each other. Yes. The terminal electrodes 14a to 14d and 16a to 16d are formed so that a part thereof wraps around the first and second main surfaces 12a and 12b, and end portions thereof are the first and second main surfaces 12a and 12b. Is located.

  The ground terminal electrode 18 a is provided at the center portion of the third side surface 12 e and has a shape extending in the stacking direction of the chip body 12. Similarly, the ground terminal electrode 18b is provided in the center portion of the fourth side surface 12f and has a shape extending in the stacking direction of the chip body 12. That is, the ground terminal electrode 18a and the ground terminal electrode 18b form a pair of ground terminal electrodes, and are formed on the outer surface of the chip body 12 so as to face each other. Part of the ground terminal electrodes 18a and 18b is formed so as to wrap around the first main surface 12a, and one end portion thereof is located on the first main surface 12a.

  The connection electrode 18c is provided at a central portion of the second main surface 12b in the opposing direction of the first and second side surfaces 12c and 12d, and is located on the second main surface 12b of the terminal electrodes 14a to 14d. Between the end portion of the terminal electrodes 16a to 16d and the end portion of the terminal electrodes 16a to 16d located on the second main surface 12b, the opposing direction of the third and fourth side surfaces 12e and 12f, that is, the first and second main surfaces. It has a shape extending in the long side direction of the surfaces 12a and 12b. In the present embodiment, the connection electrode 18c has a shape extending linearly in the long side direction of the first and second main surfaces 12a and 12b. The connection electrode 18c is formed integrally with the pair of ground terminal electrodes 18a and 18b.

  One end of the connection electrode 18c is continuous with the other end of the ground terminal electrode 18a, and the other end of the connection electrode 18c is continuous with the other end of the ground terminal electrode 18a. The terminal electrodes 18a and 18b are connected to each other. The width of the ground terminal electrodes 18a, 18b (the length in the facing direction of the first and second side surfaces 12c, 12d) and the width of the connection electrode 18c (also in the facing direction of the first and second side surfaces 12c, 12d). Is set to be substantially the same. The other ends of the ground terminal electrodes 18a and 18b may wrap around the first main surface 12a and be positioned on the first main surface 12a.

  A plurality of functional layers are stacked on the chip body 12, and the chip body 12 has a first region A and a second region B along the stacking direction of the plurality of functional layers. . Functional layers having different functions are laminated in the first region A (inductor portion) and the second region B (varistor portion) in the chip body 12. Hereinafter, the configuration of the chip body 12 will be described in detail.

  As shown in FIG. 2, a plurality of functional layers 20, 21, 22, 23, 24, 25, 22, 23, and 26 are sequentially stacked in the first region A of the chip body 12. The functional layers 20 to 26 are made of a ceramic material mainly composed of ZnO. The ceramic material constituting the functional layer contains, in addition to ZnO as a main component, metal elements such as Pr, K, Na, Cs, and Rb as additives.

  In the second region B of the chip body 12, a plurality of functional layers 27, 28, 29, and 30 are sequentially stacked. The functional layers 27 to 30 are made of a dielectric material. In the present embodiment, the functional layers 27 to 30 are made of a dielectric ceramic material containing ZnO as a main component and exhibiting voltage nonlinear characteristics. This ceramic material further contains at least one element selected from the group consisting of Pr and Bi, Co and Al as additives.

  Since the functional layers 27 to 30 contain Co in addition to Pr, the functional layers 27 to 30 have excellent voltage nonlinear characteristics and a high dielectric constant (ε). Moreover, since Al is further included, it becomes low resistance. The functional layers 27 to 30 may further contain metal elements other than those described above (for example, Cr, Ca, Si, K, etc.) as additives for the purpose of further improving the characteristics.

  In the actual chip body 12, the functional layers 20 to 26 and the functional layers 27 to 30 are integrated to such an extent that the boundary between them cannot be visually recognized.

  Next, the configuration of the first region A of the chip body 12 will be described in detail. Four conductor patterns 41, 42, 43, 44, 45, 42, 43, 46 are formed on one main surface of the plurality of functional layers 21, 22, 23, 24, 25, 22, 23, 26, respectively. It is provided one by one. The four conductor patterns 41 are juxtaposed in the direction perpendicular to the laminating direction of the functional layers 20 to 26 and in the opposing direction of the third and fourth side faces 12e and 12f. Similarly, four conductor patterns 42 to 46 are also juxtaposed in the facing direction of the third and fourth side faces 12e and 12f.

  The conductor patterns 41 and 46 are provided to lead out terminal electrodes, and the conductor patterns 42 to 45 are coiled to increase the inductance. In other words, the conductor patterns 42 to 45 have a U-shape formed along a substantially rectangular side.

  One end 41a of each of the four conductor patterns 41 is provided along one edge of the functional layer 21 forming a part of the first side surface 12c shown in FIG. 2, and the terminal electrodes 14a, 14a shown in FIG. 14b, 14c, and 14d, respectively. The other ends 41b of the four conductor patterns 41 are respectively connected to one ends 42a of the four conductor patterns 42 via through-hole conductors. The other end 42b of the four conductor patterns 42 is connected to one end 43a of the four conductor patterns 43 via the through-hole conductors, and the other end 43b of the four conductor patterns 43 is connected to the through-hole conductors. To one end 44a of each of the four conductor patterns 44. The other ends 44b of the four conductor patterns 44 are respectively connected to one ends 45a of the four conductor patterns 45 through the through-hole conductors, and the other ends 45b of the four conductor patterns 45 are connected to the through holes. Each of the four conductor patterns 42 is connected to one end 42a via a conductor.

  Similarly, the other ends 42b of the four conductor patterns 42 are respectively connected to one ends 43a of the four conductor patterns 43 via through-hole conductors, and the other ends 43b of the four conductor patterns 43 are connected to the through holes. Each of the four conductor patterns 46 is connected to one end 46a via a hole conductor. The other ends 46b of the four conductor patterns 46 are provided along one edge of the functional layer 26 forming a part of the second side surface 12d shown in FIG. 1, and the terminal electrode 16a shown in FIG. , 16b, 16c, and 16d.

  As described above, the conductor patterns 42 to 46 adjacent to each other in the stacking direction of the chip body 12 are connected in series to form four inductor conductors 48a, 48b, 48c, and 48d.

  Next, the configuration of the second region B of the chip body 12 will be described in detail. A plurality of internal electrodes 51, 52, 53, 54, 55 are arranged between the functional layers 27-30 so as to face each other in the stacking direction of the functional layers 27-30. Specifically, four first electrode conductors 51, 52, 53, 54 are provided on one main surface of the functional layer 29, and the second electrode conductor 51, 52, 53, 54 is provided on one main surface of the functional layer 28. The electrode conductor 55 is provided.

  The four first electrode conductors 51 to 54 are juxtaposed in the direction orthogonal to the stacking direction of the functional layers 27 to 30 and in the opposing direction of the third and fourth side surfaces 12e and 12f. One ends 51a, 52a, 53a, and 54a of the four first electrode conductors 51 to 54 are provided along one edge of the functional layer 29 that forms a part of the second side surface 12d shown in FIG. And connected to the terminal electrodes 16a, 16b, 16c, and 16d shown in FIG. That is, the one ends 51a to 54a of the four first electrode conductors 51 to 54 are connected to one ends of four different inductor conductors 48a to 48d, respectively.

  The other end portions 51 b to 54 b of the first electrode conductors 51 to 54 face the second electrode conductor 55 in the stacking direction of the functional layers 27 to 30. In other words, the second electrode conductor 55 is arranged with respect to the first electrode conductors 51 to 54, and the other end portions 51b and 52b of the first electrode conductors 51 and 52 and the first electrode conductor. The pair of ground terminal electrodes 18a and 18b extend in the facing direction so as to face the other end portions 53b and 54b of 53 and 54, respectively.

  One end 55a of the second electrode conductor 55 is provided along one edge of the functional layer 28 forming a part of the third side surface 12e shown in FIG. 1, and is connected to the ground terminal electrode 18a shown in FIG. Has been. The other end 55b of the second electrode conductor 55 is provided along one edge of the functional layer 28 that forms a part of the fourth side surface 12f shown in FIG. 2, and is connected to the ground terminal electrode 18b shown in FIG. It is connected.

  A surge absorbing element 58a is formed by one end 51b of the first electrode conductor 51, a part of the second electrode conductor 55 (a portion facing the one end 51b) 55c, and the functional layer 28 therebetween. A surge absorbing element 58b is formed by one end portion 52b of the first electrode conductor 52, a part of the second electrode conductor 55 (a portion facing the one end portion 52b) 55d, and the functional layer 28 therebetween. Similarly, the surge absorbing element 58c is formed by the one end portion 53b of the first electrode conductor 53, a part of the second electrode conductor 55 (a portion facing the one end portion 53b) 55e, and the functional layer 28 therebetween. The surge absorbing element 58d is formed by one end 54b of the first electrode conductor 54, a part of the second electrode conductor 55 (a portion facing the one end 54b) 55f, and the functional layer 28 therebetween. ing.

In the multilayer filter 10 as described above, a direction identification mark Mk for identifying the vertical direction of the multilayer filter 10 is provided on the surface of the chip body 12 on the functional layer 20 side. The direction identification mark Mk has a rectangular shape (in the present embodiment, a rectangular shape), and is positioned approximately at the center of the surface of the chip body 12 on the functional layer 20 side. Here, the surface to which the direction identification mark Mk is attached in the chip body 12 is the upper surface with respect to a circuit board (not shown) to be mounted. The direction identification mark Mk is made of ZnO and ZrO ₂ . The direction identification mark Mk made of ZnO and ZrO ₂ is formed by simultaneous firing (described later) with the chip body 12.

  As shown in FIG. 4, the multilayer filter 10 is formed with four L-type filter elements each composed of inductor conductors 48a, 48b, 48c, 48d and surge absorbing elements 58a, 58b, 58c, 58d. The

Next, a method for manufacturing the multilayer filter 10 described above will be described. First, a plurality of inductor green sheets that become the functional layers 20 to 26 in the first region A of the chip body 12 are prepared. These inductor green sheets are made of, for example, a slurry using a mixed powder of ZnO, Pr ₆ O ₁₁ , Cr ₂ O ₃ , CaCO ₃ , SiO ₂ and K ₂ CO ₃ as a raw material, for example, with a thickness of about 20 μm. It is formed by coating on a film by the doctor blade method.

In addition, a plurality of varistor green sheets to be the functional layers 27 to 30 in the second region B of the chip body 12 are prepared. These varistor green sheets are made of, for example, a slurry using a mixed powder of ZnO, Pr ₆ O ₁₁ , CoO, Cr ₂ O ₃ , CaCO ₃ , SiO ₂ , K ₂ CO ₃ and Al ₂ O ₃ as a raw material. The film is formed on the film by a doctor blade method so that the thickness becomes about 30 μm.

  Subsequently, through holes are formed by laser processing or the like at predetermined positions of the inductor green sheets to be the functional layers 21 to 25 (that is, positions where through holes are to be formed with respect to the conductor patterns 41 to 46).

  Subsequently, conductor patterns 41 to 46 for the inductor conductors 48a to 48d are formed on the inductor green sheets to be the functional layers 21 to 26. The conductor patterns 41 to 46 are formed so as to have a thickness after firing of, for example, about 14 μm by screen-printing a conductor paste mainly composed of Ag and Pd on the inductor green sheet. The through-holes formed in the inductor green sheets serving as the functional layers 21 to 25 are filled with the conductor paste for the through-hole conductors by screen printing of the conductor paste on the inductor green sheets.

  In addition, conductor patterns corresponding to the second electrode conductor 55 and the first electrode conductors 51 to 54 are formed on the varistor green sheet to be the functional layers 28 and 29. This conductor pattern is formed by screen-printing a conductor paste mainly composed of Ag and Pd on a varistor green sheet, for example, so that the thickness after firing becomes about 3 μm.

Also, a mark paste for forming the direction identification mark Mk is prepared, and this mark paste is screen-printed at a predetermined position on the inductor green sheet to be the functional layer 20. Mark paste, mixed powder of ZnO and ZrO _2, consisting of a binder, and a solvent or the like. At this time, the inductor green sheet is whitish because it is a green sheet made of a material containing ZnO as a main component. The mark paste is also whitish because it contains a large amount of ZnO. For this reason, when the white mark paste is printed on the inductor green sheet as it is, image recognition of the mark paste becomes difficult. Therefore, it is desirable to color the mark paste by mixing a small amount of carbon black or an organic pigment (for example, amaranth) with the mark paste. Since carbon black and organic pigments are scattered by firing described later, they do not remain after firing. For this reason, after baking, the direction identification mark Mk will be in a white state.

  Subsequently, the inductor green sheets to be the functional layers 20 to 26 and the varistor green sheets to be the functional layers 27 to 30 are laminated and pressed in a predetermined order to obtain a green sheet laminate. When laminating each varistor green sheet, the inductor green sheet on which the mark paste is printed (inductor green sheet to be the functional layers 20 to 26) is placed with the surface on which the mark paste is printed facing downward. Each green sheet is laminated so as to be a lower layer.

  Subsequently, the obtained green sheet laminate is cut into chips so as to have a desired size, and then fired at a predetermined temperature (for example, a temperature of about 1100 to 1200 ° C.) to obtain the chip body 12. .

  Subsequently, four pairs of terminal electrodes 14a to 14d, 16a to 16d, a pair of ground terminal electrodes 18a and 18b, and a connection electrode 18c are formed on the outer surface of the chip body 12, and the multilayer filter 10 is completed. . The terminal electrodes 14a to 14d, the terminal electrodes 16a to 16d, the ground terminal electrodes 18a and 18b, and the connection electrode 18c are applied to the outer surface of the chip body 12 with a conductor paste mainly composed of Ag at a predetermined temperature ( For example, baking was performed at a temperature of 700 ° C. to 800 ° C., and Ni / Sn, Cu / Ni / Sn, Ni / Au, Ni / Pd / Au, Ni / Pd / Ag, or Ni / Ag was used. It is formed by applying electroplating. For applying the conductive paste, a printing method, a transfer method (dip method), or the like can be used. The completed dimensions of the multilayer filter 10 are a length of 2.0 mm, a width of 1.0 mm, and a thickness of 0.8 mm (2010 type).

  Subsequently, a mounting structure using the multilayer filter 10 having the above-described configuration will be described with reference to FIGS. 5 and 6. 5 and 6 are perspective views for explaining a mounting structure using the multilayer filter of the present embodiment.

  As shown in FIGS. 5 and 6, the multilayer filter 10 is arranged so that the second main surface 12 b faces the circuit board 60 as a mounting surface. A plurality of pairs (four pairs in the present embodiment) of signal land portions 61 and 62 and a ground land portion 63 are arranged on the circuit board 60 at intervals. The signal land portions 61 and 62 are located at the end portions of the corresponding signal conductor patterns 64. The ground land portion 63 is located at the end of the corresponding ground conductor pattern 65.

  The land portions 61, 62, 63, the terminal electrodes 14a-14d, 16a-16d, and the pair of ground terminal electrodes 18a, 18b corresponding to the land portions 61, 62, 63 are soldered (solder fillets are not shown). Are physically and electrically connected. The end portions of the connection electrode 18c in the opposing direction of the third and fourth side surfaces 12e and 12f are also physically and electrically connected to the ground land portion 63 by soldering. As a result, the multilayer filter 10 is mounted on the circuit board 60.

  As described above, in the present embodiment, the pair of ground terminal electrodes 18a and 18b are connected to each other on the second main surface 12b by the connection electrode 18c. For this reason, even when the multilayer filter 10 is mounted on the circuit board 60 with the second main surface 12b as a mounting surface, the ground terminal electrodes 18a and 18b and the connection electrode 18c are not connected to the third main surface 12b. In addition, when viewed in the opposing direction of the fourth side surfaces 12e and 12f, there is no portion corresponding to the edge. For this reason, the ground terminal electrodes 18a and 18b and the connection electrode 18c cannot have a portion where stress is concentrated, and the chip body 12 can be prevented from cracking.

  By the way, the end portions of the terminal electrodes 14a to 14d and 16a to 16d wrap around the second main surface 12b and are positioned on the second main surface 12b. For this reason, when the circuit board 60 bends, the ends of the terminal electrodes 14 a to 14 d and 16 a to 16 d also receive force from the circuit board 60. However, since the terminal electrodes 14a to 14d and 16a to 16d are positioned in the short direction of the chip body, the force received from the circuit board 60 is small, and this force is stressed as the terminal electrodes 14a to 14d and 16a to 16d. Even when concentrated on the end of the chip, no cracks are generated in the chip body 12.

  Next, a modified example of the mounting structure using the multilayer filter 10 according to the present embodiment will be described with reference to FIGS. 7 and 8 are perspective views illustrating modifications of the multilayer filter according to the present embodiment.

  In the modification shown in FIG. 7, the ground terminal electrodes 18 a and 18 b are formed so that part of the ground terminal electrodes 18 a and 18 b wrap around the first and second main surfaces 12 a and 12 b, and the end portions are the first and first 2 on the main surfaces 12a and 12b. One end of the connection electrode 18c is continuous with the other end of the ground terminal electrode 18a, and the other end of the connection electrode 18c is continuous with the other end of the ground terminal electrode 18a. The terminal electrodes 18a and 18b are connected to each other. The width of the connection electrode 18c (the length in the facing direction of the first and second side faces 12c and 12d) is the width of the ground terminal electrode 18a and 18b (similarly, the facing direction of the first and second side faces 12c and 12d). It is set to be narrower than

  In this case, the distance between the end portions of the terminal electrodes 14a to 14d and 16a to 16d located on the second main surface 12b and the connection electrode 18c (in the opposing direction of the first and second side surfaces 12c and 12d). The interval) is relatively large, and it is possible to prevent occurrence of a short circuit between the terminal electrodes 14a to 14d and 16a to 16d and the connection electrode 18c (ground terminal electrodes 18a and 18b).

  The distances between the terminal electrodes 14a to 14d, 16a to 16d and the connection electrode 18c in the modification shown in FIG. 7 are set such that the terminal electrodes 14a to 14d, 16a to 16d and the connection electrode 18c in the multilayer filter 10 shown in FIG. When the width of the connection electrode 18c is narrow, the length of the connection electrode 18c that wraps around the second main surface 12b of the terminal electrodes 14a to 14d and 16a to 16d can be set long. In this case, the mounting area of the terminal electrodes 14a to 14d and 16a to 16d is increased, and the mounting strength of the multilayer filter 10 is improved.

  In the modification shown in FIG. 8, the width of the connection electrode 18c is set wider than the width of the ground terminal electrodes 18a and 18b. In this case, the mounting strength of the multilayer filter 10 can be improved by connecting not only the ground terminal electrodes 18a and 18b but also the connection electrode 18c to the ground conductor pattern 65 of the circuit board 60.

  The preferred embodiments of the present invention have been described above. However, the present invention is not necessarily limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

  In the present embodiment and each modification, the connection electrode 18c has a shape extending linearly in the opposing direction of the third and fourth side surfaces 12e and 12f, but does not necessarily have a shape extending linearly. There is no need to be. For example, the connection electrode 18c may have a curved or meandering shape as long as the connection electrode 18c extends in the direction opposite to the third and fourth side surfaces 12e and 12f as a whole. In consideration of short-circuiting or the like, it is preferable that the connection electrode 18c has a linearly extending shape in terms of securing the distance between the terminal electrodes 14a to 14d, 16a to 16d and the connection electrode 18c.

  In the present embodiment, the present invention is applied to the multilayer filter 10 having an inductor and a surge absorbing element. However, the present invention is not particularly limited to this, and a multilayer inductor (array), multilayer capacitor (array) ), And other chip-type electronic components such as a multilayer varistor (array).

It is a perspective view which shows the multilayer filter which concerns on this embodiment. It is a perspective view which shows the multilayer filter which concerns on this embodiment. It is a disassembled perspective view which decomposes | disassembles and shows a chip | tip body for every layer. It is a circuit diagram which shows the multilayer filter which concerns on this embodiment. It is a perspective view for demonstrating the mounting structure using the multilayer filter of this embodiment. It is a perspective view for demonstrating the mounting structure using the multilayer filter of this embodiment. It is a perspective view which shows the modification of the multilayer filter which concerns on this embodiment. It is a perspective view which shows the modification of the multilayer filter which concerns on this embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Multilayer filter, 12 ... Chip body, 12a ... 1st main surface, 12b ... 2nd main surface, 12c ... 1st side surface, 12d ... 2nd side surface, 12e ... 3rd side surface, 12f ... 4th side surface, 14a-14d, 16a-16d ... terminal electrode, 18a, 18b ... ground terminal electrode, 18c ... connection electrode.

Claims (3)

A chip-type electronic component comprising: a rectangular parallelepiped chip element including an internal circuit element; and a plurality of external electrodes electrically connected to the internal circuit element and disposed on an outer surface of the chip element body There,
The chip element body includes the first and second main surfaces that are connected to each other as the outer surface, and the first and second main surfaces having a rectangular shape facing each other, and the first and second main surfaces. Extending in the short side direction of the first and second main surfaces so as to connect the first and second main surfaces and the first and second side surfaces extending in the long side direction of the surface and facing each other; Third and fourth side surfaces facing each other, and the second main surface is a mounting surface,
The plurality of external electrodes include a first external electrode formed on each of the first and second side surfaces, a second external electrode formed on each of the third and fourth side surfaces, and a mounting surface. A third external electrode formed only on the second main surface and extending in the opposing direction of the third and fourth side surfaces to connect the second external electrodes ;
A chip-type electronic component, wherein the second and third external electrodes do not have a portion corresponding to an edge when viewed in the opposing direction of the third and fourth side surfaces .   2. The chip-type electronic component according to claim 1, wherein a width of the third external electrode is set narrower than a width of the second external electrode.   The chip-type electronic component according to claim 1, wherein a width of the third external electrode is set wider than a width of the second external electrode.

Images