JP5322062B2 - Wiring board - Google Patents

Description

  The present invention relates to a wiring board for mounting a semiconductor integrated circuit element.

  Conventionally, a wiring board formed by a build-up method is known as a wiring board for mounting a semiconductor integrated circuit element. FIG. 9 is a schematic cross-sectional view showing an example of a conventional wiring board formed by the build-up method, and FIG. 10 is a schematic top view of the main part of the wiring board shown in FIG. In FIG. 9, hatching is omitted.

  As shown in FIG. 9, the conventional wiring substrate 30 has the build-up insulating layers 22 and the build-up wiring layers 23 alternately stacked on the upper and lower surfaces of the core substrate 21, and the semiconductor integrated circuit element S at the center of the upper surface. Has a mounting portion 30a.

  A core conductor layer 24 made of copper foil or a copper plating layer is deposited on the upper and lower surfaces of the core substrate 21. In addition, a large number of through-holes 25 are formed from the upper surface to the lower surface of the core substrate 21 to which a copper plating layer that functions as a part of the core conductor layer 24 is deposited.

  A plurality of via holes 26 are formed in each of the build-up insulating layers 22, and a build-up wiring layer 23 made of a copper plating layer is deposited on the surface of each build-up insulating layer 22 including the via holes 26. Yes. The build-up wiring layer 23 is electrically connected to the through-hole 25 while the upper and lower layers are connected to each other through the via hole 26. Further, a part of the buildup wiring layer 23 deposited on the outermost buildup insulating layer 22 on the upper surface side is electrically connected to the electrode terminal T of the semiconductor integrated circuit element S in the mounting portion 30a. The circular semiconductor element connection pads 27 are formed, and these semiconductor element connection pads 27 are arranged in a lattice pattern corresponding to the electrode terminals T of the semiconductor integrated circuit element S as shown in FIG. . Further, a part of the lower surface side deposited on the outermost buildup insulating layer 22 is a circular external connection pad 28 that is electrically connected to the wiring conductor of the external electric circuit board. A plurality of lines 28 are arranged in a lattice pattern.

  Further, a solder resist layer 29 for exposing the semiconductor element connection pads 27 and the external connection pads 28 is deposited on the outermost buildup insulating layer 22 and the buildup wiring layer 23 thereon. The electrode terminal T of the semiconductor integrated circuit element S is electrically connected to the exposed portion of the semiconductor element connection pad 27, and the wiring conductor of the external electric circuit board (not shown) is connected to the exposed portion of the external connection pad 28 via the solder ball. Are electrically connected.

  By the way, the semiconductor integrated circuit element S is provided with a large number of grounding and power supply electrode terminals T alternately in the center of the lower surface thereof in order to ensure sufficient power supply from the wiring board 30 and a signal is provided on the outer peripheral portion of the lower surface. In many cases, a terminal arrangement having a large number of electrode terminals is employed. When such a semiconductor integrated circuit element S is mounted, the arrangement of the semiconductor element connection pads 27 on the wiring board 30 is also arranged at the center of the mounting portion 30a corresponding to the electric terminal T of the semiconductor integrated circuit element S and for power supply. A large number of semiconductor element connection pads 27 are arranged, and a large number of signal semiconductor element connection pads 27 are arranged on the outer peripheral portion of the mounting portion 30a.

  FIG. 11 shows only the grounding and power supply semiconductor element connection pads 27 in the central portion of the mounting portion 30a. In FIG. 11, the semiconductor element connection pad 27 indicated by G is a ground semiconductor element connection pad 27G, and the semiconductor element connection pad 27 indicated by P is a power supply semiconductor element connection pad 27P. As shown in FIG. 11, the semiconductor element connection pads 27G for grounding and the semiconductor element connection pads 27P for power supply are alternately arranged in a grid-like arrangement so as to form diagonal rows. At the same time, the semiconductor element connection pads 27 in each row are integrated one by one as a band-like integrated pattern.

  These grounding and power supply semiconductor element connection pads 27 are electrically connected to the through holes 25 through the underlying buildup wiring layer 23 as shown in FIG. FIG. 12 is a perspective view showing a part of the semiconductor element connection pads 27 and the corresponding lower build-up wiring layer 23 and core conductor layer 24 shown in FIG. The position of the via 26 to be connected to is indicated, and the mark x indicates the position to which the via 26 from the upper layer is connected.

  The next build-up wiring layer 23 to which the semiconductor element connection pad 27 is connected is mainly a ground plane 23G, in which a via land 23L connected to the power supply semiconductor element connection pad 27P is arranged via a clearance 23C. It is installed. The via lands 23L are arranged in a one-to-one manner so as to form a row at a position corresponding to the power supply semiconductor element connection pad 27P of each row, and the clearance 23C of each row of the via land 23L is connected to one. Therefore, the ground plane 23G is in a state of being separated in a strip shape so as to correspond to each row of the grounding semiconductor element connection pads 27G by a single clearance 23C. The grounding semiconductor element connection pad 27G is connected to the band-shaped portion sandwiched by the clearance 23C of the ground plane 23G via the via 26 from each grounding semiconductor element connection pad 27G, and the semiconductor element connection for power supply The pads 27P are connected to the corresponding via lands 23L via the vias 26 on a one-to-one basis.

  The lower build-up wiring layer 23 is mainly a power plane 23P, and a via land 23L connected to the upper ground plane 23G is disposed therethrough via a clearance 23C. The via lands 23L are arranged in a one-to-one manner so as to form a row at a position corresponding to the grounding semiconductor element connection pad 27G in each row, and in the same manner as in the upper build-up wiring layer 23, each via land 23L has a row. The clearance 23C is connected to one. Therefore, the power supply plane 23P is in a state of being separated in a band shape so as to correspond to each row of the power supply semiconductor element connection pads 27 by a single clearance 23C. The upper ground plane 23G is connected to the via land 23L corresponding to the ground semiconductor element connection pad 27G via the via 26, and is connected to the power semiconductor element connection pad 27P. The via land 23L is connected to a band-like portion sandwiched by the clearance 23C of the power plane 23P via a via 26 from the upper via land 23L.

  The lower core conductor layer 24 is mainly a ground plane 24G, and the ground plane 24G is connected to a grounding through hole 25G and a through hole land 24L connected to a power supply through hole 25P therein. Is disposed via a clearance 24C. The upper via land 23L connected to the ground plane 23G is connected to the ground plane 24G via the via 26, and the upper power plane 23P is connected to the through-hole land 34L via the via 26. As a result, the grounding semiconductor element connection pad 27G is electrically connected to the grounding through hole 25G, and the power supply semiconductor element connection pad 27P is electrically connected to the power supply through hole 25P. Become.

  However, since the pitch of the through holes 25 is generally larger than the pitch of the semiconductor element connection pads 27, for example, taking the row of the semiconductor element connection pads 27P for power supply indicated by A in FIG. The through hole 25P for power supply is not located below the band-like portion of the power supply plane 23P connected to the semiconductor element connection pad 27P in this column. As a result, in this portion, the current path to the power supply through hole 25P largely bypasses the clearance 23C of the power supply plane 23P. Since a large number of vias 26 for connection to the power source semiconductor element connection pads 27P of the column A are connected to this portion, a large current flows in a concentrated manner in this largely detoured current path. As a result, sufficient power cannot be supplied to the semiconductor element connection pads 27P for power supply in the column A through this current path, and good operation of the semiconductor integrated circuit element S is impaired.

JP 2003-332377 A

  The problem to be solved by the present invention is that the power supply path from the through hole of the core substrate to the semiconductor element connection pad is not largely detoured in the power plane, thereby providing sufficient power supply to the semiconductor integrated circuit element. Accordingly, it is an object of the present invention to provide a wiring board capable of operating a semiconductor integrated circuit element satisfactorily.

  The wiring board of the present invention includes a core substrate having a plurality of first through holes connected to the first potential and a plurality of second through holes connected to the second potential, and an upper surface of the core substrate. A plurality of stacked build-up insulating layers and a plurality of one-by-one or a plurality of build-up insulating layers arranged in a grid pattern on the upper surface of the uppermost build-up insulating layer are arranged in a row, A first semiconductor element connection pad electrically connected to the first through hole and a second semiconductor element connection pad electrically connected to the second through hole, and the buildup insulating layer. And a belt-shaped via connection portion that is connected to a via for electrically connecting to the first semiconductor element connection pad at a position corresponding to each column of the first semiconductor element connection pad. 1 power plane And via lands to which vias for electrically connecting to the second semiconductor element connection pads are connected at positions corresponding to the respective columns of the second semiconductor element connection pads, and surrounding the via lands, A wiring board having a clearance separating the first through-holes, wherein the first through-holes are located below each row of the via connection portions, and the via-connection portions in each row and the first through-holes therebelow. Are electrically connected through vias connected to the via connection portions in each row.

  According to the wiring board of the present invention, in the above configuration, the first through hole is located below each row of the via connection portion, and the via connection portion of each row and the first through hole below the via connection portion. Are electrically connected via vias connected to the via connection portions of the respective columns, the power supply path from the first through hole to the first semiconductor element connection pad is the first. There is no major detour in the power plane, and as a result, the concentration of current in the power supply path is alleviated and sufficient power can be supplied to the semiconductor integrated circuit element, so that the semiconductor integrated circuit element can be operated well. it can.

FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. FIG. 2 is a schematic top view of the main part of the wiring board shown in FIG. FIG. 3 is an enlarged view of a main part of FIG. FIG. 4 is an exploded perspective view of main parts of the wiring board shown in FIGS. 1 and 2. FIG. 5 is a schematic sectional view showing another example in the embodiment of the wiring board of the present invention. 6 is a schematic top view of the main part of the wiring board shown in FIG. FIG. 7 is an enlarged view of a main part of FIG. FIG. 8 is an exploded perspective view of a main part of the wiring board shown in FIGS. 5 and 6. FIG. 9 is a schematic cross-sectional view showing a conventional wiring board. FIG. 10 is a schematic top view of the main part of the wiring board shown in FIG. FIG. 11 is an enlarged view of a main part of FIG. FIG. 12 is an exploded perspective view of a main part of the wiring board shown in FIGS. 9 and 10.

  Next, an example of an embodiment of the wiring board according to the present invention will be described with reference to FIGS. FIG. 1 is a schematic cross-sectional view showing an example of the wiring board of this example formed by the build-up method, and FIG. 2 is a schematic top view of the main part of the wiring board shown in FIG. 3 is an enlarged view of a main part in FIG. 2, and FIG. 4 is an exploded perspective view of a main part in the wiring board shown in FIGS. In FIG. 1, hatching is omitted.

  As shown in FIG. 1, a wiring board 10 of this example has build-up insulating layers 2 and build-up wiring layers 3 alternately stacked on the upper and lower surfaces of a core substrate 1, and a semiconductor integrated circuit element at the center of the upper surface. A mounting portion 10a for mounting S is provided.

  The core substrate 1 has a thickness of about 50 to 800 μm, and is made of an electrically insulating material in which a glass cloth in which glass fiber bundles are woven vertically and horizontally is impregnated with a thermosetting resin such as bismaleimide triazine resin or epoxy resin. A large number of core conductor layers 4 made of copper foil or copper plating layers are deposited on the upper and lower surfaces, and copper plating layers that function as a part of the core conductor layers 4 are deposited from the upper surface to the lower surface of the insulating substrate. A through hole 5 is formed. The diameter of the through hole 5 is about 100 to 300 μm, and the inside is filled with resin.

  The build-up insulating layer 2 is made of an insulating material containing a thermosetting resin such as an epoxy resin, and a plurality of via holes 6 are formed in each, and the surface of each build-up insulating layer 2 including the via holes 6 is plated with copper. A build-up wiring layer 3 composed of layers is deposited. The build-up wiring layer 3 is electrically connected to the through hole 5 while being connected to each other through the via hole 6. Further, a part of the buildup wiring layer 3 deposited on the outermost buildup insulating layer 2 on the upper surface side is electrically connected to the electrode terminal T of the semiconductor integrated circuit element S in the mounting portion 10a. The circular semiconductor element connection pads 7 are formed, and these semiconductor element connection pads 7 are formed in a lattice arrangement corresponding to the electrode terminals T of the semiconductor integrated circuit element S as shown in FIG. . The semiconductor element connection pads 7 have a large number of grounding and power supply semiconductor element connection pads 7 arranged at the center of the mounting part 10a, and a large number of signal semiconductor element connection pads 7 arranged at the outer periphery of the mounting part 10a. ing. Also, a part of the lower surface side deposited on the outermost buildup insulating layer 2 is a circular external connection pad 8 that is electrically connected to the wiring conductor of the external electric circuit board. A plurality of grids 8 are formed in a grid.

  Further, a solder resist layer 9 for exposing the semiconductor element connection pads 7 and the external connection pads 8 is deposited on the outermost buildup insulating layer 2 and the buildup wiring layer 3 thereon. The electrode terminal T of the semiconductor integrated circuit element S is electrically connected to the exposed portion of the semiconductor element connection pad 9, and the wiring conductor of the external electric circuit board (not shown) is connected to the exposed portion of the external connection pad 8 via the solder ball. Are electrically connected.

  FIG. 3 shows only the grounding and power supply semiconductor element connection pads 7 in the center of the mounting portion 10a. In FIG. 3, the semiconductor element connection pad 7 indicated by G is a semiconductor element connection pad 7G for grounding, and the semiconductor element connection pad 7 indicated by P is a semiconductor element connection pad 7P for power supply. As shown in FIG. 3, the semiconductor element connection pads 7G for grounding and the semiconductor element connection pads 7P for power supply are alternately arranged in a grid-like arrangement so as to form diagonal rows. At the same time, the semiconductor element connection pads 7 in each row are integrated as a single band-like pattern one row at a time. In this example, the semiconductor element connection pads 7 in each row are integrated as a single band-like pattern one row at a time. However, each semiconductor element connection pad 7 may be an independent pattern. The invention is applied even in such a case.

  These grounding semiconductor element connection pads 7G and power supply semiconductor element connection pads 7P are electrically connected to the through holes 5 through the underlying buildup wiring layer 3 as shown in FIG. Yes. FIG. 4 is a perspective view showing a part of the semiconductor element connection pads 7 in FIG. 3 and the corresponding build-up wiring layer 3 and core conductor layer 4 corresponding to the extracted semiconductor element connection pads 7. The position of the via 6 to be connected to is indicated, and the mark x indicates the position to which the via 6 from the upper layer is connected.

  The next build-up wiring layer 3 to which the semiconductor element connection pads 7 are connected is mainly the ground plane 3G, and the ground semiconductor element connection pads 7G are arranged at positions corresponding to the respective columns of the ground semiconductor element connection pads 7G. Power supply semiconductor element connection pad 7P at a position corresponding to each column of power supply semiconductor element connection pads 7P. Via land 3L to which via 6 for electrical connection is connected, and clearance 3C surrounding them and separating via connection 3V. The grounding semiconductor element connection pad 7G is connected to the via connection portion 3V of the ground plane 3G via the via 6 from each grounding semiconductor element connection pad 7G, and the power supply semiconductor element connection pad 7P is connected to the via land 3L. Are connected via vias 6.

  The underlying buildup wiring layer 3 is mainly a power plane 3P, and a via for electrically connecting the power supply semiconductor element connection pad 7P to a position corresponding to each column of the power supply semiconductor element connection pads 7P. 6 is connected to the grounding semiconductor element connection pad 7G at a position corresponding to each column of the grounding semiconductor element connection pad 7G. 6, via land 3 </ b> L, and clearance 3 </ b> C surrounding the via land 3 </ b> V and separating the via connection 3 </ b> V. The upper ground plane 3G is connected to the via land 3L via the via 6, and the upper via land 3L connected to the power semiconductor element connection pad 7P is connected to the power plane 3P via the via 6 from the upper via land 3L. Connected.

  The lower core conductor layer 4 is mainly a ground plane 4G. The ground plane 4G is connected to a grounding through hole 5G, and a through hole land 4L connected to a power supply through hole 5P therein. Is disposed via a clearance 4C. The upper via land 3L connected to the ground plane 3G is connected to the ground plane 4G via the via 6, and the upper power plane 3P is connected to the through-hole land 4L via the via 6. As a result, the grounding semiconductor element connection pad 7G is electrically connected to the grounding through hole 5G, and the power supply semiconductor element connection pad 7P is electrically connected to the power supply through hole 5P. Become.

  In the wiring board of this example, an additional power supply through hole 5Pa is provided so that the power supply through hole 5P is located below each row of the via connection portion 3V of the power supply plane 3P. Therefore, the power supply path from the power supply through hole 5P to the power supply semiconductor element connection pad 7P is not greatly detoured in the power supply plane 3P. As a result, the concentration of current in the power supply path is alleviated and the semiconductor integrated circuit is integrated. The semiconductor integrated circuit element S can be satisfactorily operated by supplying sufficient power to the circuit element S. According to a simulation performed by the present inventor using a DC current density simulator, it was confirmed that the voltage drop when a transient current flows in the power supply to the semiconductor integrated circuit element S was significantly improved. If it is difficult to provide an additional power supply through hole 5Pa in terms of design, by replacing some of the grounding through holes 5G and the power supply through holes 5P, the via connection portion 3V of the power plane 3P is provided. A through hole 5P for power supply may be positioned below each row.

  Next, another example of the embodiment of the wiring board according to the present invention will be described with reference to FIGS. FIG. 5 is a schematic cross-sectional view showing an example of the wiring board of this example formed by the build-up method, and FIG. 6 is a schematic top view of the main part of the wiring board shown in FIG. 7 is an enlarged view of a main part in FIG. 6, and FIG. 8 is an exploded perspective view of a main part in the wiring board shown in FIGS. In FIG. 5, hatching is omitted.

  As shown in FIG. 5, in the wiring board 20 of this example, the build-up insulating layers 12 and the build-up wiring layers 13 are alternately laminated on the upper and lower surfaces of the core substrate 11, and the semiconductor integrated circuit element is located at the center of the upper surface. A mounting portion 20a for mounting S is provided.

  The core substrate 11 has a core conductor layer 14 made of copper foil or a copper plating layer applied to the upper and lower surfaces thereof, and a copper plating layer that functions as a part of the core conductor layer 14 from the upper surface to the lower surface of the insulating substrate. A number of through-holes 15 are formed.

  A plurality of via holes 16 are formed in each of the build-up insulating layers 12, and a build-up wiring layer 13 made of a copper plating layer is deposited on the surface of each build-up insulating layer 12 including the via holes 16. . The build-up wiring layer 13 is electrically connected to the through hole 15 while the upper and lower layers are connected to each other through the via hole 16. Further, a part of the buildup wiring layer 13 deposited on the outermost buildup insulating layer 12 on the upper surface side is electrically connected to the electrode terminal T of the semiconductor integrated circuit element S in the mounting portion 20a. The circular semiconductor element connection pads 17 are formed, and these semiconductor element connection pads 17 are arranged in a lattice shape corresponding to the electrode terminals T of the semiconductor integrated circuit element S as shown in FIG. . The semiconductor element connection pads 17 have a large number of grounding and power supply semiconductor element connection pads 17 arranged at the center of the mounting portion 20a, and a large number of signal semiconductor element connection pads 17 arranged at the outer periphery of the mounting portion 20a. ing. Further, a part of the lower surface side deposited on the outermost buildup insulating layer 12 is a circular external connection pad 18 that is electrically connected to the wiring conductor of the external electric circuit board. A plurality of 18 are formed in a grid.

  Further, a solder resist layer 19 that exposes the semiconductor element connection pads 17 and the external connection pads 18 is deposited on the outermost buildup insulating layer 12 and the buildup wiring layer 13 thereon. The electrode terminal T of the semiconductor integrated circuit element S is electrically connected to the exposed portion of the semiconductor element connection pad 17, and the wiring conductor of the external electric circuit board (not shown) is connected to the exposed portion of the external connection pad 18 via the solder ball. Are electrically connected.

  FIG. 7 shows only the grounding and power supply semiconductor element connection pads 17 in the central portion of the mounting portion 20a. In FIG. 7, the semiconductor element connection pad 17 indicated by G is a semiconductor element connection pad 17G for grounding, and the semiconductor element connection pad 17 indicated by P is a semiconductor element connection pad 17P for power supply. As shown in FIG. 7, the grounding semiconductor element connection pads 17G and the power supply semiconductor element connection pads 17P are alternately arranged in groups of four in a grid-like arrangement. In addition, the grounding semiconductor element connection pads 17G of each set are integrated as a net-like integrated pattern, and the power supply semiconductor element connection pads 17P of each set are integrated as four patterns. Integrated.

  The grounding semiconductor element connection pad 17G and the power supply semiconductor element connection pad 17P are electrically connected to the through hole 15 via the underlying buildup wiring layer 13 as shown in FIG. Yes. 8 is a perspective view showing a part of the semiconductor element connection pads 17 in FIG. 7 and the corresponding build-up wiring layer 13 and core conductor layer 14 corresponding to the semiconductor element connection pads 17 in FIG. The position of the via 16 to be connected to is indicated, and the mark x indicates the position to which the via 16 from the upper layer is connected.

  The next build-up wiring layer 13 to which the semiconductor element connection pads 17 are connected is mainly the ground plane 13G, and the ground semiconductor element connection pads 17G are arranged at positions corresponding to the respective columns of the ground semiconductor element connection pads 17G. Power supply semiconductor element connection pad 17P at a position corresponding to each column of power supply semiconductor element connection pads 17P. A via land 13L to which a via 16 for electrical connection is connected, and a clearance 13C surrounding the via land 13L and separating the via connection portion 13V. The ground semiconductor element connection pad 17G is connected to the via connection portion 13V of the ground plane 13G via the via 16 from each ground semiconductor element connection pad 17G, and the power supply semiconductor element connection pad 17P is connected to the via land 13L. Are connected via vias 16.

  The underlying buildup wiring layer 13 is mainly a power plane 13P, and a via for electrically connecting to the power supply semiconductor element connection pad 17P at a position corresponding to each column of the power supply semiconductor element connection pads 17P. 16 is connected to the grounding semiconductor element connection pad 17G at a position corresponding to each column of the grounding semiconductor element connection pad 17G. A via land 13L to which 16 is connected and a clearance 13C surrounding the via land 13L and separating the via connection portion 13V. The upper ground plane 13G is connected to the via land 13L via the via 16, and the upper via land 13L connected to the power semiconductor element connection pad 17P is connected to the power plane 13P via the via 16 from the upper via land 13L. Connected.

  The lower core conductor layer 14 is mainly a ground plane 14G. The ground plane 14G is connected to a grounding through hole 15G, and a through hole land 14L connected to a power supply through hole 15P therein. Is disposed via a clearance 14C. The upper via land 13L connected to the ground plane 13G is connected to the ground plane 14G via the via 16, and the upper power plane 13P is connected to the through-hole land 14L via the via 16. As a result, the grounding semiconductor element connection pad 17G is electrically connected to the grounding through hole 15G, and the power supply semiconductor element connection pad 17P is electrically connected to the power supply through hole 15P. Become.

  In the wiring board of this example, an additional power supply through hole 15Pa is provided so that the power supply through hole 15P is positioned below each row of the via connection portion 13V of the power supply plane 13P. Therefore, the power supply path from the power supply through hole 15P to the power supply semiconductor element connection pad 17P is not greatly detoured in the power supply plane 13P. As a result, the concentration of current in the power supply path is reduced and the semiconductor is reduced. The semiconductor integrated circuit element S can be operated satisfactorily by supplying sufficient power to the integrated circuit element S. If it is difficult to provide an additional power supply through hole 5Pa in terms of design, by replacing some of the grounding through holes 15G and the power supply through holes 15P, the via connection portion 13V of the power plane 13P is provided. A through hole 15P for power supply may be positioned below each row. Needless to say, the present invention is also applied to the case where the grounding potential and the power supply potential are interchanged.

DESCRIPTION OF SYMBOLS 1,11 Core board | substrate 2,12 Buildup insulating layer 3,13 Buildup wiring layer 3C, 13C Clearance 3L, 13L Via land 3V, 13V Via connection part 5,15 Through hole 6,16 Via 7,7 Semiconductor element connection pad

Claims (1)

A core substrate having a plurality of first through-holes connected to the first potential and a plurality of second through-holes connected to the second potential, and a multi-layer build stacked on the upper surface of the core substrate The upper insulating layer and the uppermost build-up insulating layer are arranged in a grid pattern on the upper surface so that one or more of them are alternately arranged in rows. A first semiconductor element connection pad electrically connected and a second semiconductor element connection pad electrically connected to the second through-hole, and the buildup insulating layer; A first power supply plane having a strip-like via connection portion to which a via for electrically connecting to the first semiconductor element connection pad is connected at a position corresponding to each column of one semiconductor element connection pad; 2 semiconductors A via land to which a via for electrically connecting to the second semiconductor element connection pad is connected at a position corresponding to each row of the child connection pads, and a clearance surrounding the via land and separating the via connection portion from each other. The first through holes are located below each row of the via connection portions, and the via connection portions in each row and the first through holes therebelow are arranged in each row. A wiring board characterized in that it is electrically connected through a via connected to a via connection portion.

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