JP5363511B2 - Multi-valued logic circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multivalue logic circuit which can be constituted even if a normally-on insulated gate FET is not used, can perform a manner of a multivalue logic output such as "output is opened", can recognize its function from the name of the multivalue logic circuit, and has a multivalue logic function which can be expressed by a human language. <P>SOLUTION: The multivalue logic circuit includes: a determination means (connected body of transistors 1, 2 and the like) to determine whether an input numerical number is equal to a specific value (integer) m corresponding to specific potential Vm; a unidirectional output potential pull means comprising a reverse blocking switch (a series circuit of transistors 3, 6 and diodes 9, 12) connected between a power line Vm of the specific potential vm and an output terminal Out; an on/off-drive means (a connection body of transistors 1, 2, resistors 15, 16 and the like) for subjecting the output potential pull means to on/off-drive based on its determination output signal and the like. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

In the present invention , each integer from 0 to (N−1) of N value (N ≧ 3) is a constant potential ( or a power line, etc.) of the first constant potential supply means to the Nth constant potential supply means ( or a power line or the like). Kakujo voltage) and one after the other concerning the multi-level logic circuit is defined with a corresponding one-to-one (or multi-numeration system logic circuit) to each other.
The inventor has brought the concept of “specific value (preset integer value)” to the multi-value logic, but in the present invention, it is limited to “1 ≦ specific value ≦ (N−2)”. Yes.
In the multi-value logic circuit of the present invention, “when these constant potentials increase in the order of numbers from the first constant potential to the Nth constant potential” and “in the opposite order from the first constant potential to the Nth constant potential”. There are cases where these constant potentials become lower, but the latter case corresponds to “a multi-value logic circuit such as a negative logic circuit with respect to positive logic in the case of a binary logic circuit”.
These multi-value logic circuits are multi-value arithmetic circuits (or multi-adic arithmetic circuits), multi-value computers (or multi-adic computers, especially 4, 8, “10”, 16, 32, 64, “100”, 128. It can be used for a decimal computer or the like, or a multi-value control means (or a multi-adic control means).

In the present invention, the present inventor brings the concept of “specific value (= specific integer) ” and “output release” to multi-valued logic, for example, “If the input integer is 1,“ the input integer ”, the input When there are a plurality of integers, “all of the plurality of input integers” or “at least one of the plurality of input integers” is one of integers 1 to (N−2) . and for a particular value "determined" whether or not equal to ", or" if they are equal and outputs a specific constant potential corresponding to the specific value (or a specific constant voltage), to open its output otherwise " “If the opposite is equal, the output is released, otherwise the specific constant potential is output”. The present inventor is limited to such unique functions.


In the present invention, the exit means (eg, output terminals, etc.) of a plurality of multi-value logic circuits are connected {and possibly the entrance means (eg: input terminals, etc.)} to connect the logic functions. It can be developed and strengthened. The present invention has such a degree of freedom, and is a free-opening / evolving type multi-value logic circuit.
Further, “output open” is an output method called an open collector or the like in a binary logic circuit.

The present inventor names and calls each of the above-described multi-valued logic circuits having unique functions. Specifically, each circuit name and its function are as follows.
(1) First, the number of input integers is one, and that one input integer is the object of discrimination.
A) "Multi-valued specific value EQUAL (equal) circuit" is a "multi-valued logic circuit that determines whether the one input integer is" equal or not ", that is," equal or not equal ". is there. Equal its one input integers and its specific value and outputs the specified value (if = integer other than the specific value) Otherwise, such Kere if opening its output.
B) Since the “multi-value specific value NOT circuit” is a “ negative circuit of the multi-value specific value EQUAL circuit”, the output method is opposite . If the one input integer is equal to the specific value, the output is released; otherwise, the specific value is output (if it is an integer other than the specific value).

■■ Next, there is a case where there are a plurality of input integers, and the plurality of input integers are to be discriminated.
C) “Multi-valued specific value AND circuit” is “a multi-valued logic circuit that determines whether or not all its input integers are equal to the specific value”. Its equal and JP value of all the input integer pixel and outputs the specific value, "Otherwise, such Kere if" or "if at least one input integers integer other than the specific value" open its output To do.
D) Since the “multi-value specific value NAND circuit” is a “ negative circuit of the multi-value specific value AND circuit”, the output method is the opposite . If all the input integers are equal to the specific value, the output is released. If not, the specific value is output "if the at least one input integer is an integer other than the specific value".

■■ Similarly, there are a plurality of input integers, and the plurality of input integers are to be discriminated.
E) “Multi-valued specific value OR circuit” is a “ multi-valued logic circuit that determines whether or not the at least one input integer is equal to the specific value ” . Equal and JP value of the at least one input integer pixel and outputs the specific value, "Otherwise, such Kere if" or "if all of its inputs integers integer other than the specific value" open its output To do.
F) Since the “multi-value specific value NOR circuit” is a “ negative circuit of the multi-value specific value OR circuit”, the output method is opposite . If the at least one input integer is equal to the specific value, the output is released. If not, that is, if the input integer is an integer other than the specific value, the specific value is output.

In the multi-value logic circuit disclosed in Japanese Patent Application Laid-Open No. 2003-204259, basically two switching means are connected in series between both ends of a power source, and furthermore, both input driving units are completely independent, thereby causing a power supply short circuit due to simultaneous ON. It cannot be used with combinations of input signals and input variables, and it is necessary to pay particular attention to the usage. Moreover, the potential difference (= voltage) between the power supply potential corresponding to the integer and the power supply potential is not constant. In other words, since the potential differences are not equal, a common logic noise margin (noise margin) is not considered even in a binary logic circuit, and the logic circuit is incomplete.
For example, in the case of ternary 3 inputs (FIG. 1 of this prior patent), there are only 4 combinations in the truth table (FIG. 2 of this prior patent) even though there are 27 combinations of input variables. It is not described and is extremely inefficient as a multi-value logic processing function. Further, the power supply potentials corresponding to the three values are “0”, “3.0”, and “3.5” volts, and the potential differences are not equal and are offset, and malfunctions easily occur due to noise. Furthermore, the combinations of input variables that cause a power supply short circuit occupy nearly half of all combinations, and if the power supply potential difference is set equal, the number of occupations of the power supply short circuit combination becomes larger than the majority of the total.

On the other hand, there is a multi-value logic circuit of the special table 2002-517937 which can be said to have a multi-value logic processing function. FIG. 21 shows a basic circuit (three-value one-input) of this Omoto which has been simplified for the sake of explanation. The circuit diagram of the patent publication is correct because it is an error (the normally-on display and the normally-off display of the gate-insulated FET are opposite to each other).
In the circuit of FIG. 21 , two normally-on (depletion mode) P- and N-channel gate-insulated FETs (Q2 and Q3) are used as output means for outputting an intermediate potential v1 between the highest potential v2 and the lowest potential v0. Bidirectional switching means in which are connected in series is used. In addition, the circuit of FIG. 21 can also determine whether the “input integer corresponding to the input potential” corresponds to the “integer corresponding to the intermediate potential” by “zero gate voltages of both transistors Q2 and Q3”. “On driving”, that is, “a characteristic that both transistors Q2 and Q3 are turned on when the potential difference (= voltage) between the input potential and the intermediate potential v1 is zero” is used.
The combined use of the output means and the determination means has an advantage that the number of parts is small for the logical function and the circuit configuration is simple. In the operation, if the input potential is v0, the output potential is v2, if the input potential is v1, the output potential is v1, and if the input potential is v2, the output potential is v0.

Note that two P- and N-channel junction FETs cannot be used in place of these gate-insulated FETs. This is because the flow when the transistor Q3 is of the junction type FET of a P-channel, when the transistor Q1 at the input potential v0 is on, the power supply short-circuit current to the input terminal T _in through the drain-gate PN junction of the transistor Q3 from the transistor Q1 Because it is. On the other hand, when the transistor Q2 is an N-channel junction FET, the gate-drain PN junction of the transistor Q2 clamps the upper limit of the input potential to the power supply potential v1, and a power supply short circuit current flows again. In addition, since the gates and sources of the transistors Q2 and Q3 are connected in parallel, when a junction FET is used, both PN junctions are connected in reverse parallel, and a sufficient gate reverse bias voltage is applied to each. Because it is not possible.

However, since “any multi-value logic circuit disclosed in JP 2002-517937A” gives priority to “small number of parts” and its functions are fixed, Multi-value logic circuit "and output terminal T _out I can't connect each other. If it is connected forcibly, a power supply short circuit will occur. For example, the output terminal T _out The output potential (or output voltage) cannot be changed by connecting a pull-up resistor, pull-down resistor, or the like. Moreover, even though the number of disclosed multi-valued logic circuits is large, it is insignificant if it is considered from the following “super-explosive enormous number of types of multi-valued logic processing”. .
Therefore, if there is an output method (for example, an output method called an open collector or the like in a binary logic circuit) in the multi-value logic output method, the output of “open the output” is used. Freely connect outlet means (eg, output terminal, output electrode, drain electrode, etc.) {In some cases, connect inlet means (eg: input terminal, input electrode, gate electrode, etc.) freely. }, It is possible to supplement and supplement the functions that are deficient with each other, and to flexibly develop and enhance the multi-value logic function in accordance with the “required multi-value logic processing”. In addition, for example, the output potential (or output voltage) can be freely changed by connecting a pull-up resistor or a pull-down resistor to the outlet means.
Its flexible function development / enhancement ability and function change ability are very advantageous in responding flexibly to the following “ultra-explosive enormous number of types of multi-valued logic processing”.
That's why "You can't connect other multi-value logic circuits and exit means to develop and enhance multi-value logic functions, and you can't change functions", that is, "Multi-value logic that opens output" The problem of “it is desirable to be able to output” is in the conventional multi-value logic circuit.
( Task )

Here, a description will be given of the above-mentioned is considered mathematically "super-explosive Bou-sized Is the kind of multi-valued logic process". In the case of a binary 2-input logic circuit, there are 4 combinations of input variables, that is, the square of 2 = 4 sets, and there are two ways of output in each of the 4 sets, integers “0” and “1”. Therefore, there are 16 kinds of logic processing and logic functions, that is, the second power of 2 = 16.
"Introduction to Transistor Circuit Lecture 5: Digital Circuit Concept" published by OHM Co., Ltd. on May 20, 1986. Supervision: Yoshifumi Amemiya and Nori Koshiba. Authors: Kensuke Shimizu and Masahiro Masakazu. p. 34 “Table 3. 8 Logical functions consisting of two input variables”.

Similarly, in the case of a ternary two-input multi-value logic circuit, there are three combinations of input variables: the square of 3 = 9 sets, and in each of the nine sets, the output method is an integer “0”, “1”, Since there are three types of “2”, the types of logical processing and logical functions are 3 9 = 19,683 types.
Similarly, in the case of a quaternary 2-input multi-value logic circuit, there are also 4 16 ≈4,294,968,000 types, and in the case of a 5-value 2-input multi-value logic circuit, 5 25 ≈2. 980233 × (10 to the 17th power) types.
Thus, as the number of multi-values (for example, N for N values, 10 for 10 values, and so on) is increased, the types of multi-value logic processing increase super-explosively. This means that if a multi-value logic circuit having a multi-value logic processing function optimal for “required logic processing” is realized and selected, even a small number of circuits can cope with “various logic processing required”. This is similar to software programming in terms of problem-handling ability and suggests that new and tremendous possibilities may be buried in multi-valued logic and multi-valued logic. . Perhaps multi-digit computers, especially decimal computers, may outperform binary quantum computers.
It should be noted that logical functions and logical processing seem to have “meaningful” and “nonsense”, so even if the number of “significant logical processing” is a fraction of the total, There is no change in the increase in super and explosive.

JP-A-6-276087 (multi-value logic circuit) JP-A-7-38420 (multi-value logic circuit) JP2001-267910 (multi-valued logic circuit) JP2003-204259 (multi-valued logic circuit) Special table 2002-517937 (multi-valued logic circuit) Japanese Patent Application No. 2003-109619 (Prior application of the present inventor, same invention) Japanese Patent No. 3423780 (Bidirectional insulated switch and unidirectional insulated switch of the present inventor) Japanese Patent No. 2853041 (multi-value storage means) Japanese Patent Application No. 2003-203347 (multi-value storage means) FIG. 1 of JP-A-5-035660 (bidirectional buffer in which two unidirectional buffers are connected in reverse parallel) FIG. 3 of JP-A-5-120209 (bidirectional buffer in which two unidirectional buffers are connected in antiparallel) FIG. 1 of JP-A-5-233524 (bidirectional buffer in which two unidirectional buffers are connected in reverse parallel) FIG. 2 of JP-A-7-183517 (bidirectional switch in which two unidirectional thyristors are connected in reverse parallel)

"Introduction to Transistor Circuit Lecture 5: Digital Circuit Concept" published by OHM Co., Ltd. on May 20, 1986. Supervision: Yoshifumi Amemiya and Nori Koshiba. Authors: Kensuke Shimizu and Masahiro Masakazu. p. 34 “Table 3. 8 Logical functions consisting of two input variables”. Mathematical Sciences February Issue (1980, No.200) Special Issue Multivalued Logic, published by Science Co., Ltd. on February 1, 1980. Technical article of the Nikkei Sangyo Shimbun (Tokyo edition): “High-tech classroom, multi-valued logic circuit, increasing IC integration, not going binary or ternary”. Published by Nikkei Sangyo Shimbun on Friday, November 22, 1985. Written by Ishizuka Yoshihiko. "Multi-value information processing-Post binary electronics-", authors: Tatsuo Higuchi and Michitaka Kameyama. Published in June 1989 by Shokodo. "Transistor Technology September 1997" published by CQ Publishing Co., Ltd. on September 1, 1997. P. 374-p. 375 “Attic Resource Room Multilevel Logic”. Author: Hidekazu Inoue. “Digital Digital Circuits Understandable”, p. 76-p. 80 [[1] logic level to [2] noise margin]. Author: Keitaro Sekine. Issued by Ohm Co., Ltd. on July 25, 1997. “Introduction to Logic Circuits”, p. 126-p. 128 “6.4 IC characteristics (1) Signal voltage value and noise margin”. Author: Ryoji Hamabe. Published on September 28, 2001 by Morikita Publishing Co., Ltd. “Pulse Digital Circuit”, p. 125-p. 130 “5. Basic characteristics of circuit 5.1 Amplitude characteristics of pulse digital circuit ”. Author: Akira Kawamata. Published by Nikkan Kogyo Shimbun on February 15, 1995. “Pulse and digital circuit”, p. 128 “Threshold Level” and p. 129 “Logical Level”. Edit: Masao Yoneyama. Author: Shigeyuki Ohara, Sumio Yoshikawa, Toshio Shinozaki, Shiro Takahashi. Published by Tokai University Press on April 5, 2001. “Practical Introduction Series: How to Use CMOS Circuit [1]”, “Element Threshold Voltage” on page 44 and “Circuit Threshold Voltage” on page 50. Author: Yasoji Suzuki. Published on October 15, 1997 by the Industrial Research Committee.

◆◆ “Bidirectional buffer with two parallel unidirectional buffers connected in reverse parallel” ◆◆
“Hitachi TTL '80 SEMICONDUCTOR DATA BOOK TTL”, p. 206-p. 216 “HD74LS240 to HD74LS245” one-way buffer and two-way buffer. A 1980 TTL data book by Hitachi, Ltd. “Illustration: How to Use Microcomputer Z-80”, p. 44-p. 45 “22 Bus Buffer”, author: Eiichi Yokota. OHM Co., Ltd. issued the first edition of the first edition on May 20, 1986, and the first edition of the second edition on June 20, 1981. ＊＊＊ ◆◆ “Bidirectional switch with two unidirectional thyristors connected in reverse parallel” ◆◆ “SCR and its applications”, p. 176 in FIGS. 9 and 26 and FIGS. 9 and 27. Author: Kenji Tsukiji and Hiroshi Aikawa. Published by Nikkan Kogyo Shimbun (May 20, 1965, first edition), March 25, 1975, 12th edition. “University Lecture Power Electronics”, p. 111-126 “6 AC power control”. Author: Miyata Shouta. Maruzen Co., Ltd. (issued on March 30, 1974) issued the second edition on April 20, 1976 and issued the sixth edition on the second edition on January 20, 1986. “Easy-to-understand thyristor circuit basics”, p. 90-103 "3.1 Single-phase antiparallel circuit". Author: Shoji Iida. Tokyo Denki University Press issued the 20th edition of the first edition on February 20, 1976 and the 15th edition of the first edition on February 20, 1996. “Thyristor Basics and Applications”, p. 168 in FIG. Editor: Atsujiro Ozu, Authors: Shuzo Saeki, Isao Shigesato, Satoshi Higuchi, Hiroshi Yokota. OHM Co., Ltd. issued the first edition and first print on January 30, 1978. “The University of Electrical Engineers, Power Electronics Fundamentals”, p. 70 in FIGS. 2 and 33 (b), p. 111-117 “3.4 AC phase control circuit” and p. 170-172 “4.4 Power Electronics as a Switch”. Editor: The Institute of Electrical Engineers of Japan. Author: Yoshiaki Ikeda, Kouichi Kitamura, Eisuke Masada, and many other publishing committee members and many correspondence education committee members. Published by the Institute of Electrical Engineers on April 20, 1993. “Semiconductor Power Conversion Circuit”, p. 10 “Table 2.2.1 Types of semiconductor switches”, p. 11 “Table 2.3.1 Semiconductor conversion circuit and semiconductor switch” and p. 13 “Table 2.3.2 Conversion Circuit Composed of a Single Switch”, etc. Author: Many members of the IEEJ Semiconductor Power Conversion Method Research Committee, Editor: The Institute of Electrical Engineers of Japan. Published by the Institute of Electrical Engineers of Japan on March 31, 1987, and released by Ohm Co., Ltd.

Therefore, it is not possible to develop and enhance the multi-value logic function by connecting other multi-value logic circuits and exit means, and the function cannot be changed. The conventional multi-value logic circuit has a problem that it is desirable to be able to do this .

That is , the present invention
When a predetermined plural number of 3 or 3 is represented by N and a predetermined natural number is represented by S,
"" N constant potentials that increase or decrease in numerical order from the first constant potential to the Nth constant potential "are supplied, and each constant potential and 0 to (N- 1) a first constant potential supply means to an Nth constant potential supply means defined such that each integer in 1) corresponds to the first constant potential one-to-one in order from the integer 0;
“First to Sth Inlet Means for Incoming S Input Potential Signals”,
“Exit means for exiting output potential signal”;
“Of the second constant potential supply means to the (N−1) th constant potential supply means, connected between one specific constant potential supply means and the exit means, and when turned on, the potential of the exit means Is pulled up or down to the specified constant potential of the specified constant potential supply means, and when it is driven off, at least the output means of the outlet means `` pull `` Output potential pull switching means to release the output in the up direction, pull down direction if pulling down '',
“When S = 1, an integer corresponding to one of the input potential signals, and when S ≧ 2, [all S integers corresponding to each of the S input potential signals] or [S Whether at least one of S integers corresponding to each of the input potential signals] is equal to “a specific value corresponding to the specific constant potential among the integers 1 to (N−2)”. It is determined whether or not it is the same based on “both threshold potentials on the positive side and the negative side determined in advance with reference to the specific constant potential” or “one higher than the specific constant potential” The negative threshold potential determined in advance with reference to the constant potential and the positive threshold potential determined in advance with reference to the constant potential one lower than the specific constant potential. Numeric discriminator that determines whether it is not based on And ",
“Controlled by the numerical discriminating means,“ if the output potential pull / switching means is turned on if they are equal, otherwise the output potential pull / switching means is driven off ”or“ if they are equal, the output potential pull / switching means is turned off ”.・ Turn off the switching means, otherwise turn on the output potential pull switching means ”on / off drive means”,
Is a multi-valued logic circuit.
However, one said means may serve as several said means.

As a result, first of all, as described above, “when these constant potentials increase in numerical order from the first constant potential to the Nth constant potential” and “from the first constant potential to the Nth constant potential in the opposite direction”. There are cases where these constant potentials decrease in the order of numbers ”, but the latter case corresponds to“ a multi-value logic circuit such as a negative logic circuit with respect to a positive logic in terms of a binary logic circuit ”.
→→ Reference: ● c) in the last supplementary explanation [paragraph number 0049].
Secondly, the present inventor has brought the concept of “specific value (= integer value set in advance)” and “output release” into multi-value logic. Specifically, “if the input integer is one,“ the input integer ”, if there are a plurality of input integers,“ all of the plurality of input integers ”or“ of the plurality of input integers, "At least one" "is determined to be" equal or not "with respect to" one specific value from integer 1 to integer (N-2) ", and" if the determination result is equal, it corresponds to that specific value " The specific constant potential (or the specific constant voltage) is output, otherwise the output is released "or" the output is released if it is equal to the opposite, otherwise the specific constant potential is output ". The present inventor is limited to such unique functions.
Of course, “output opening” is an output method called an open collector or the like in a binary logic circuit.
However, although the inventor has brought the concept of “specific value (specific integer)” to the multi-valued logic, in the present invention, it is limited to “1 ≦ specific value ≦ (N−2)”.

As a result, the numerical value discriminating unit discriminates the contents to be discriminated, and the on / off driving unit drives the output potential pull switching unit on / off based on the discrimination result. The logic circuit “outputs the specific constant potential” or “opens the output”.
Therefore, the multi-value logic circuit of the present invention has the effect that “the multi-value logic output method of releasing the output can be performed ”. (Effect of the present invention )
For this reason, the exit means (eg, output terminal, output electrode, drain electrode, etc.) of a plurality of multi-value logic circuits of the present invention can be freely connected to each other {in some cases, the entrance means (eg: input terminal, input) Electrodes, gate electrodes, etc.) can also be freely connected} to supplement each other's deficient functions and flexibly develop and strengthen their multi-value logic functions in accordance with "required multi-value logic processing". be able to. Further, for example, a pull-up resistor or a pull-down resistor can be connected to the outlet means, and the output potential (or output voltage) can be freely changed. The present invention has such a degree of freedom, and is a free-opening / evolving type multi-value logic circuit.

Note that N (≧ 3) indicates a multi-value number N of N values, and the integer used is 0 to (N−1). The first constant potential corresponds to the integer 0, the second constant potential corresponds to the integer 1,..., And the Nth constant potential corresponds to the integer (N−1).
The correspondence between each integer and each logic / potential level is as follows.
When the potential increases in numerical order from the first constant potential to the Nth constant potential
If a potential signal is lower than “a positive threshold potential with respect to the first constant potential”, the potential signal corresponds to the integer 0 . If a potential signal is “between the negative threshold potential and the positive threshold potential with reference to the second constant potential”, the potential signal corresponds to the integer 1 . Similarly, a certain potential signal is sequentially “ between the positive and negative threshold potentials based on the respective constant potentials from the third constant potential to the (N−1) th constant potential”. For example, the potential signal sequentially corresponds to “ each integer from integer 2 to integer (N−2) ”. If a potential signal is higher than “a negative threshold potential based on the Nth constant potential”, the potential signal corresponds to an integer (N−1) .
When the potential decreases in numerical order from the first constant potential to the Nth constant potential
If a potential signal is higher than “a negative threshold potential with respect to the first constant potential”, the potential signal corresponds to the integer 0. If a potential signal is “between the negative threshold potential and the positive threshold potential with reference to the second constant potential”, the potential signal corresponds to the integer 1. Similarly, a certain potential signal is sequentially “between the positive and negative threshold potentials based on the respective constant potentials from the third constant potential to the (N−1) th constant potential”. For example, the potential signal sequentially corresponds to “each integer from integer 2 to integer (N−2)”. If a potential signal is lower than “a positive threshold potential with reference to the Nth constant potential”, the potential signal corresponds to an integer (N−1).

Therefore, in general, in both cases, the negative threshold potential of the logic level of the specific value (= specific integer) is “specific constant potential”, “specific constant potential”, and “specific constant potential”. On the other hand, the positive side threshold potential of the logic level of the specific value is set to “a constant potential one level higher than the specific constant potential and the middle potential of the specific constant potential”. It is set during “specific constant potential”.
As described above, when the potential increases in numerical order from the first constant potential to the Nth constant potential, it corresponds to “a multi-value logic circuit like a positive logic circuit in the case of a binary logic circuit”. On the other hand, when the potential decreases in numerical order from the first constant potential to the Nth constant potential, it corresponds to “a multi-value logic circuit like a negative logic circuit in terms of a binary logic circuit”. To do. Both have a symmetrical relationship with respect to the voltage direction or voltage polarity.
→→ ● c) in the last supplementary explanation [paragraph 0049].

“Introduction to Transistor Circuit Lecture 5: Digital Circuits”, p. 46-p. 47 “4.6 Notes on using logic circuits [1] Logic voltage level and noise margin”. Supervision: Yoshifumi Amemiya and Nori Koshiba. Authors: Kensuke Shimizu and Masahiro Masakazu. Issued on May 20, 1981 by Ohm Co., Ltd. “Digital Digital Circuits Understandable”, p. 76-p. 80 [[1] logic level to [2] noise margin]. Author: Keitaro Sekine, published by OHM Co., Ltd. on July 25, 1997. “Introduction to Logic Circuits”, p. 126-p. 128 “6.4 IC characteristics (1) Signal voltage value and noise margin”. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd. on September 28, 2001. “Pulse Digital Circuit”, p. 125-p. 130 “5. Basic characteristics of circuit 5.1 Amplitude characteristics of pulse digital circuit ”. Author: Akira Kawamata. Published by Nikkan Kogyo Shimbun on February 15, 1995. “Pulse and digital circuit”, p. 128 “Threshold Level” and p. 129 “Logical Level”. Edit: Masao Yoneyama. Author: Shigeyuki Ohara, Sumio Yoshikawa, Toshio Shinozaki, Shiro Takahashi. Published by Tokai University Press on April 5, 2001. “Practical Introduction Series: How to Use CMOS Circuit [1]”, “Element Threshold Voltage” on page 44 and “Circuit Threshold Voltage” on page 50. Author: Yasoji Suzuki. Published on October 15, 1997 by the Industrial Research Committee.

For this reason, the numerical value discriminating means discriminates the contents to be discriminated, and the on / off driving means drives the output potential pull switching means on / off based on the discrimination result. The value logic circuit “outputs the specific constant potential” or “opens the output”.
Therefore, the multi-value logic circuit of the present invention has the effect that “the multi-value logic output method of releasing the output can be performed ”. (Effect of the present invention )
For this reason, the exit means (eg, output terminal, output electrode, drain electrode, etc.) of a plurality of multi-value logic circuits of the present invention can be freely connected to each other {in some cases, the entrance means (eg: input terminal, input) Electrodes, gate electrodes, etc.) can also be freely connected} to supplement each other's deficient functions and flexibly develop and strengthen their multi-value logic functions in accordance with "required multi-value logic processing". be able to. Further, for example, the output potential (or output voltage) can be freely changed by connecting a pull-up resistor or a pull-down resistor to the outlet means. The present invention has such a degree of freedom, and is a free-opening / evolving type multi-value logic circuit.

Thru (or) Each figure is a circuit diagram showing each embodiment of the present invention one by one. It is a circuit diagram which shows an example of the multi-value logic circuit which is not the Example of this invention. It is a circuit diagram which shows an example of the multi-value logic circuit which is not the Example of this invention. It is a circuit diagram which shows the basic circuit of Omoto (Omoto) of the multi-value logic circuit of prior invention.

The Re accompanying drawings Nishitagatteko to explain the present invention will be described in more detail. However, in each figure, n corresponds to the above-described N, and m corresponds to the above-described specific value (= specific integer).
In each embodiment, there is a relationship of “n ≧ 3”, “n−1 ≧ m + 1”, and “m−1 ≧ 0”.
Further, a description will be given mainly of “a case where the potential increases in numerical order from the first constant potential to the Nth constant potential (corresponding to positive logic)”, but “number from the first constant potential to the Nth constant potential”. In the case where the potential decreases in order (corresponding to negative logic), in each embodiment, the level of each power supply potential is made opposite to each other, and each controllable switching means is set to “controllable switching means in a complementary relationship (example) : P-channel MOS • FET for N-channel MOS • FET) one by one, and the direction of each directional component (eg, diode) reversed, “Voltage direction relative to the original embodiment The “embodiment having a symmetrical relationship with respect to the voltage polarity” corresponds to that case. However, when it corresponds to the negative logic, the function may be the same as the original (corresponding to the positive logic), or may be different.
Then, the power supply line _{V 0,} ......, specific power supply line _{V m,} ......, power supply lines _{V n-1} of the power source potential supply to turn potential _{v 0,} ......, certain power supply potential _v m, ......, The power supply potential is represented by v _n−1 .
In each embodiment, each diode indicated by a dotted line may be present or absent.

The first embodiment (output pull-down type) shown in FIG. 1 is a multi-value logic circuit named by the present inventor as a “multi-value specific value EQUAL circuit” , and its input integer N _in is equal to the specific value m. pull down the output voltage _{v out} of the output terminal _{T out} to a specific power supply voltage _{v m,} opens its output otherwise.
In the embodiment of FIG. 1 corresponds to the following as the components described above (in paragraph number [0016]) each constituting unit (= constituent unit according to claim 1 Symbol Nonaka), an S = 1.

● a) "power line _{V 0,} ......, power supply line _{V m-1,} a specific power supply line _{V m,} the power supply line _{V m + 1,} ......, power supply lines _{V n-1"} respectively mentioned above, "first constant potential supply Means to Nth constant potential supply means ".
● b) input terminal T _in is to enter the mouth means described above.
● c) to exit means that the output terminal T _out has been described above.
D) The specific power supply line _Vm is the specific constant potential supply means described above.
● e) a specific power supply potential v _m to the particular constant potential described above.
F) “ One- way switching means connected between the specific power line V _m and the output terminal T _out and constituted by the transistors 3 and 6 and the diodes 9 and 12” is the output potential pull switching means described above .
☆ In the case that the switch terminals, the on-off drive unit during off-drive (gate, source unit) between the completely off bidirectionally, the off state of the unidirectional switching means the potential of the switch terminal Is not affected at all. (Reference: Patent No. 3,423,780)
G) “Connected body of the power supply line V _{m + 1} , the power supply line V _m−1 and the transistors ₁ and 2” and the like are the numerical value discriminating means described above .

H) “Connected body of transistors 1 and 2, Zener diodes 13 and 14 and resistors 15 and 16” and the like are the on / off driving means described above .

★ Caution 1: In the case of the unidirectional switching means in FIG. 1, each switch terminal and its on / off drive part (gate, source part) are completely turned off in both directions at the time of off driving. It is not affected at all by the potential of each switch terminal. (Reference: Patent No. 3,423,780)
★ Caution 2: The on / off threshold potential of the specific value (= specific integer) m for the on / off operation of the numerical discrimination means in the above item ● g) is the power line V _m-1 Of the transistor 2 and the on / off threshold voltage of the transistor 2, and the positive on / off threshold potential of the specific value m is the power line V _{m + 1} And the magnitude of the on / off threshold voltage of the transistor 1.
* Note 3: The above-mentioned [paragraph number 0019] “correspondence between each integer and each logic / potential level (in the case of positive logic)” is repeated as follows. A potential signal is “the first constant potential (= power supply potential v ₀ ), The potential signal corresponds to the integer 0. A potential signal is “the second constant potential (= power supply potential v ₁ ) Between the negative threshold potential and the positive threshold potential, the potential signal corresponds to the integer 1. Similarly, a certain potential signal is sequentially “the third constant potential (= power supply potential v ₂ ) To (N-1) constant potential (= power supply potential v) _n-2 ) Between the positive and negative threshold potentials with reference to each constant potential until)), the potential signal is sequentially changed to “each integer from integer 2 to integer (N−2)”. Correspond. A potential signal is “the Nth constant potential (= power supply potential v _n-1 ), The potential signal corresponds to an integer (N−1).
* Note 4: For this reason, not only in the first embodiment of FIG. 1, but generally, the negative threshold potential of the logic level of the specific value m is “specific power supply potential v _m "And" specific power supply potential v _m And power supply potential v _m-1 On the other hand, the positive threshold potential of the logic level of the specific value m is set to “power supply potential v” _{m + 1} And specific power supply potential v _m Middle potential "and" specific power supply potential v _m ”Is set.

The circuit operation of the first embodiment shown in FIG. 1 is as follows. Enter potential v _in the minus side on-off threshold potential and the plus-side on and off, which was the basis of the "specific power potential v _m of (Note 2. ★ in front and paragraph number) above the input terminal T _in If it is between the “threshold potentials”, the transistors 1 and 2 are simultaneously turned on, so that the transistors 3 and 6 are turned on. As a result, the output terminal T _out becomes conductive to a specific power supply line _{V m} and one-way, the output potential v _out of the output terminal T _out is pulled down to a specific power supply voltage _{v m,} the output terminal T _out certain power and it outputs a potential _{v m.}
On the other hand, if there is no potential of the input terminal T _in to "the (★ Note 2. in front and paragraph number) both on and off threshold potential between", one or both of the transistors 1 and 2 is turned off, the resistance Since the transistors 15 and 16 drive the transistors 3 and 6 off, the output terminal T _out is opened. Only one-on transistors 1 Waso can not turn on the driving transistor 3 and 6 with respect to the unidirectional switching means. That is, the transistors 1 and 2 can drive the transistors 3 and 6 on only when the transistors 1 and 2 are on at the same time.

On the other hand, with respect to the logical operation of the first embodiment of FIG. 1, a particular value m when the input integer _{N in} (integer corresponding to the input potential v _in signal) is equal to the specific value m (integer corresponding to a particular power supply potential v _m) When the input integer N _in is not equal to the specific value m, the output is released.
Therefore, the relationship with the logic (potential) level is as follows. When determining whether or not the input integer N _in is equal to the specific value m, whether the input potential v _in signal is “ between the positive and negative threshold potentials with respect to the specific power supply potential v _m ”. It will be determined. On the other hand, when it is determined whether the input integer N _in is not equal to the specific value m, the input potential v _in signal is “ a negative threshold value based on the power supply potential v _{m + 1} that is one higher than the specific power supply potential v _m. It is determined whether it is higher than “potential” or lower than “plus-side threshold potential with reference to the power supply potential v _m−1 that is one lower than the specific power supply potential v _m ”.

Note that “the output terminal T _out is pulled through a pull-up resistor or the like to “ another power line having a higher potential than the specific power line V _m ”or“ the potential higher than the specific power line V _m and the power line V _{m + 1} to It is also conceivable to use “ connect to an additional / power supply line other than V _n-1 ”. Further, "the Example 1 of the specific power supply potential v _m are different from each other 1 to plural available to connect the input terminal T _in to each other, to connect the output terminal T _out each other" use is also contemplated that. Furthermore, the diodes 7 and 8 may be omitted and the Zener diodes 13 and 14 may be omitted if the relationship of “power supply potential v ₀ ≦ output potential v _out ≦ power supply potential v _n−1 ” is satisfied. .
Then, instead of the resistors 15 and 16, a “ junction FET or normally-on MOS FET ” in which the gate and the source are directly connected can be used one by one as the resistance means. In place of the diodes 9 and 12 , “ normally-off type MOS FETs whose gates, back gates and sources are directly connected” can be used one by one. The same applies to each of Examples 2 to 18 shown in FIGS. In addition, have used the N-channel IGBT instead of the transistor 3, using a P-channel type IGBT in place of the transistor motor 6 Ukoto are possible. In this case, the diodes 9 and 12 are not required if each IGBT is a reverse blocking type.

The second embodiment (output pull-up type) shown in FIG. 2 uses “transistors 3 and 6 and diode 9, in order to change the output pull-down function to the output pull-up function in the first embodiment shown in FIG. "Specific power supply line V" connected to each switch terminal of "unidirectional switching means 12" _m And output terminal T _out The two connections are simply swapped with each other.
For this reason, the description other than the change of the output pull function is the same as the description of the first embodiment of FIG. Except for the function change, the input integer N _in Output potential v when is equal to the specific value m _out Specific power supply potential v _m Pull up to, otherwise release its output.
"Output terminal T _out Via a pull-down resistor, etc. _m Other power line with lower potential "or" specific power line V _m Lower potential, power line V ₀ ~ V _m-1 It is also possible to use "connect to an additional power supply line".

In the third embodiment (output pull-down type) of FIG. 3 named by the present inventor as a “multi-value specific value EQUAL circuit”, the transistor 4 is turned on only when both the transistors 1 and 2 are turned on. 17 detects whether the transistor 2 is on or off . When both the transistors 1 and 2 are on, the series circuit of the transistors 1 and 17 drives the transistor 4 on .
Example 3 of FIG. 3 with respect to the logical operation is the same as Example 1 of FIG. 1, and outputs a specific value m when the input integer N _in is equal to the specific value m, to open its output when unequal. Of course, when a specific value m is output, a pull-down operation is performed.

In the fourth embodiment (output pull-up type) of FIG. 4 named by the present inventor as a “multi-value specific value EQUAL circuit”, the transistor 6 is turned on only when both the transistors 1 and 2 are on. 18 detects whether the transistor 1 is on or off. When both transistors 1 and 2 are on, the series circuit of transistors 18 and 2 drives transistor 6 on.
In terms of the logical operation, the fourth embodiment of FIG. 4 is the same as the second embodiment of FIG. _in When is equal to the specific value m, the specific value m is output, and when it is not equal, the output is released. Of course, when a specific value m is output, a pull-up operation is performed.

The fifth embodiment (output pull-down type) in FIG. 5 named by the present inventor as a “multi-value specific value EQUAL circuit” is composed of a bipolar transistor or the like, and its logical operation is the same as that of the first embodiment in FIG. is there.

The sixth embodiment (output pull-up type) in FIG. 6 named by the inventor as "multi-value specific value EQUAL circuit" is composed of bipolar transistors and the like, and its logical operation is the same as that in the second embodiment in FIG. is there.

Real施例7 of FIG. 7 by the inventors named "multilevel specific value NOT circuit" (output pull-down) is obtained by using a different number determination method of the input voltage v _in. Except particular power supply line V _m are not shown. Instead of the diode 9 using the "PNP or NPN transistor is directly connected to the collector and base" may be. Also, may be had use the BSIT instead of P-channel preparative transistor 82 (bipolar mode static induction transistor) or GTBT (bipolar lateral FET with a channel-shaped electrode grounded), bets transistor 81 and 83 respective BSIT and GTBT of N-channel type may be used one by one instead. These replacement can be said similarly for Example 13 in Figure 13 discussed later.
As its output opens when regarding logical operation Example 7 the input integer N _in 7 equal to the specified value m, and outputs a specific value m when the input integer N _in is not equal to the specific value m. Of course, when a specific value m is output, a pull-down operation is performed.

Example 8 (output pull-up type) of FIG. 8 named by the inventor as “multi-value specific value NOT circuit” is also the input potential v. _in The other numerical discrimination method is used. Specific power line V _m Other than that, illustration is omitted. Instead of the diode 12, a “PNP or NPN transistor in which a collector and a base are directly connected” may be used. Instead of each of the transistors 84 and 86, a P-channel type BSIT (bipolar mode static induction transistor) or GTBT (bipolar FET having a grounded groove electrode) may be used one by one. Instead of the transistor 85, an N-channel type BSIT or GTBT may be used. These replacements can be similarly applied to Example 14 of FIG. 14 described later.
Regarding the logical operation, the input integer N in the eighth embodiment of FIG. _in When is equal to a specific value m, the output is released and the input integer N _in When is not equal to the specific value m, the specific value m is output. Of course, when a specific value m is output, a pull-up operation is performed.

Example 9 of FIG. 9 by the inventors named "multilevel specific value NOT circuit" (output pull-down) is obtained by realizing the seventh embodiment of FIG. 7 in MOS-FET, a specific power supply line V Illustrations are omitted except for _m . In addition, an embodiment _in which the input terminal T _in is connected to the power supply line V _{m + 1} through a pull-up resistor and at the same time the input terminal T _in is connected to the power supply line V _m−1 through a pull-down resistor is also possible. It is.
Example 9 of FIG. 9 with respect to the logical operation is the same as in Example 7 in FIG. 7, the same time to open its output input integer N _in the the specific value m, when the input integer N _in is different from the specific value m The specific value m is output. Naturally, when a specific value m is output, a pull-down operation is performed.

The embodiment 10 (output pull-up type) of FIG. 10 named by the present inventor as a “multi-value specific value NOT circuit” is the implementation of the embodiment 8 of FIG. _m Other than that, illustration is omitted. The input terminal T _in Through the pull-up resistor _{m + 1} To the input terminal T at the same time _in Through the pull-down resistor _m-1 Embodiments connected to can also be possible.
The tenth embodiment of FIG. 10 is the same as the eighth embodiment of FIG. _in When the value is the same as the specific value m, the output is released and the input integer N _in When is different from the specific value m, the specific value m is output. Naturally, when outputting the specific value m, a pull-up operation is performed.

The eleventh embodiment (output pull-down type) of FIG. 11 named by the present inventor as “multi-value specific value AND circuit” is replaced with “three transistors of the same type” instead of the transistor 1 in the first embodiment of FIG. _Are connected in series, and instead of the transistor 2, “three transistors of the same type” are connected in series, and three input terminals T _in1 , T _in2 , and T _in3 are provided.
Input terminal _{T in1,} T in2, each potential of the _{T in3} is above (paragraph [0026] in ★ Note 2.) the "specific power supply potential _v negative side on-off threshold potential relative to the _m plus if during the side on-off threshold potential ", while the output terminal T _out is to output a specific power supply potential _{v m,} the input terminal T _{in1, T in2,} the potential of _{T in3 v in1, v in2,} v in3 If at least one of them is not “between both ON / OFF threshold potentials (★ CAUTION 2 in paragraph [0026] ” ) , the output terminal T _out is opened.
Example 11 Figure 11 with respect to its logical operation, three input integers _{N in1, N in2, N in3} all outputs a specific value m when equal to a particular value m, three input integers _{N in1, N in2,} N of _in3, it opens the output time not equal to at least one particular value m. Naturally, when a specific value m is output, a pull-down operation is performed.

Example 12 (output pull-up type) shown in FIG. 12 uses “transistors 3 and 6 and diode 9, in order to change the output pull-down function to the output pull-up function in Example 11 of FIG. "Specific power supply line V" connected to each switch terminal of "unidirectional switching means 12" _m And output terminal T _out The two connections are simply swapped with each other.
For this reason, the description other than the change of the output pull function is exactly the same as the description of the embodiment 11 of FIG. Naturally, when outputting the specific value m, a pull-up operation is performed.

Example 13 Figure 13 by the inventors named "multilevel specific value NAND circuit" (output pull-down), the one using the N PN transistors 87 of the multi-emitter capacitor, the embodiment of FIG. 7 7 is applied. The base portion of the NPN transistor 83 with grounded emitter is a binary diode OR circuit, but instead of this combination, “a binary grounding device in which four NPN transistors with collectors and emitters connected to each other are grounded with emitters” is used. A “transistor OR circuit” can be used .
In Example 13 of Figure 13 with respect to its logical operation, four input integer _{N in1, N in2, N in3} , N in4 all opens the output time equal to the specific value m, 4 inputs integers _{N in1, N in2,} N in3, among _{N in4,} and outputs the specific value m when at least one of not equal to a particular value m. When outputting a specific value m, a pull-down operation is performed.

The embodiment 14 (output pull-up type) of FIG. 14 named by the present inventor as a “multi-value specific value NAND circuit” uses a multi-emitter PNP transistor 88. The embodiment 8 of FIG. It is applied. The base part of the PNP transistor 86 with grounded emitter is a binary diode OR circuit. Instead of this combination, “a binary circuit with four emitters connected to each other and four PNP transistors connected to each other and the emitters” is used. A “transistor OR circuit” can be used.
Also, with respect to its logical operation, the embodiment 14 of FIG. _in1 , N _in2 , N _in3 , N _in4 When all are equal to a specific value m, the output is released and the four input integers N _in1 , N _in2 , N _in3 , N _in4 When at least one of them is not equal to the specific value m, the specific value m is output. When outputting a specific value m, a pull-up operation is performed.

In Example 15 of Figure 15 that the present inventor has termed "multilevel specific value OR circuit" (output pull-down), the input terminal T _{in1, T in2,} the potential of _{T in3 v in1, v in2,} v in3 of, even one above (paragraph [0026] in ★ Note 2.) minus side on-off threshold potential to the "reference a specific power supply potential v _m and the plus-side on-off threshold potential , The output terminal T _out outputs a specific power supply potential v _m , while the potentials v _in1 , v _in2 , and v _{in3 of} the input terminals T _in1 , T _in2 , and T _in3 are all “ on / off both of them ”. if there is to the outside of the threshold potential (paragraph [0026] in ★ Note 2.) between ", the output terminal T _out is open. In this circuit, the conductors denoted by symbols a, b, and c are in a connected state.
In Example 15 of Figure 15 with respect to the logical operation of the three input integers _{N in1, N in2, N in3} , and outputs a specific value m when equal to at least one specific value m, the three input integers When all of N _in1 , N _in2 and N _in3 are different from the specific value m, the output is _released . When outputting a specific value m, a pull-down operation is performed.

Example 16 (output pull-up type) shown in FIG. 16 is different from Example 15 of FIG. 15 in that the output pull-down function is changed to the output pull-up function. "Specific power supply line V" connected to each switch terminal of "unidirectional switching means 12" _m And output terminal T _out The two connections are simply swapped with each other.
Therefore, the description other than the change of the output pull function is exactly the same as the description of the fifteenth embodiment of FIG. Naturally, when outputting the specific value m, a pull-up operation is performed.

2 In Example 17 of Figure 17, the present inventor has termed "multilevel specific value NOR circuit" (output pull-down), the resistor 57 as a "transistor 39 in the first embodiment 5 of FIG 5 are connected in series A value inverter circuit "is used to invert the on / off drive signal to output the complementary output of the multi-value specific value OR circuit. Accordingly, even in this circuit, the conductive wires denoted by symbols a, b, and c are in a connected state.
That embodiment 17 of FIG. 17 with respect to the logic operations, three input integers _{N in1,} N _in2, of _{N in3,} opened when the output is equal to at least one of a particular value m, the three input integers _{N in1,} When all of N _in2 and N _in3 are different from the specific value m, the specific value m is output. When outputting a specific value m, a pull-down operation is performed.

In Example 18 (output pull-up type) shown in FIG. 18, in order to change the output pull-down function to the output pull-up function in Example 17 of FIG. 17, “transistors 3, 6 and diode 9, "Specific power supply line V" connected to each switch terminal of "unidirectional switching means 12" _m And output terminal T _out The two connections are simply swapped with each other.
For this reason, the description other than the change of the output pull function is exactly the same as that of the embodiment 17 of FIG. Naturally, when outputting the specific value m, a pull-up operation is performed.

As described in the section “c) of“ Last Supplement ”to be described later (paragraph number [0049]), each embodiment has“ a multi-value logic circuit having a symmetrical relationship with respect to the voltage direction or voltage polarity ”. .
In this case, as described above (paragraph numbers [0016 to 0017, 0019]), these constant potentials increase in numerical order from the first constant potential to the Nth constant potential. These constant potentials decrease in numerical order from the first constant potential to the Nth constant potential, and the polarities of the threshold potentials are switched in opposite directions.
As a result, each multi-value logic circuit of the present invention “when these constant potentials decrease in numerical order from the first constant potential to the N-th constant potential”, these are “positive logics in the case of a binary logic circuit”. This corresponds to a negative logic multi-value logic circuit such as a negative logic circuit for a logic logic circuit.

Incidentally, FIG. 19 shows that “ a multi-value logic circuit for the power supply line V _{n−1 having} the highest power supply potential v _n−1 which is not an embodiment of the present invention (this inventor calls a multi-value specific value AND circuit). Is shown. If the binary inverter circuit is connected in the middle, the multi-value logic circuit of FIG. 19 becomes a “ multi- value logic circuit called a multi- value specific value NAND circuit ” for the power supply line V _n−1 having the highest power supply potential v _n−1. Become. Each diode indicated by a dotted line may or may not be present. Naturally, there is a negative logic multi-value logic circuit as compared to the multi-value logic circuit of FIG.
On the other hand, FIG. 20 shows a “ multi-valued logic circuit for the power supply line V _{0 having} the lowest power supply potential v ₀ (which is called the multi-value specific value AND circuit)” which is not an embodiment of the present invention. If the binary inverter circuit is connected halfway, the multi-value logic circuit of FIG. 20 becomes a “multi-value logic circuit called a multi- value specific value NAND circuit ” for the power supply line V ₀ having the lowest power supply potential v ₀ . Each diode indicated by a dotted line may or may not be present. Naturally, there is a negative logic multi-value logic circuit for the multi-value logic circuit of FIG.

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Finally, the following will be supplemented.
A) Indicates that each diode indicated by a dotted line may or may not be present in each embodiment.
B) In each embodiment, instead of each diode, “bipolar transistor with its collector and base directly connected”, “junction FET with its drain and source directly connected”, “bipolar mode with its drain and gate directly connected” "SIT or GTBT", "Normally off-type MOS FET with its gate, back gate and source connected" or "Back gate potential between the drain and back gate, so that the source and back gate are not conductive. Can be used one by one, normally-off type MOS FET having its drain and gate connected.
C) In each embodiment, the level of each power supply potential is reversed, and each controllable switching means is defined as “controllable switching means in a complementary relationship (eg, P-channel MOS • FET with respect to N-channel MOS • FET). "Each embodiment having a symmetrical relationship with respect to the voltage direction or voltage polarity with respect to the original embodiment" in which the direction of each directional component (e.g., diode) is reversed is replaced one by one. Is possible. However, in that case, the function may be the same as the original or may be different.

D) “Multi-value specific value EQUAL circuit” may be called “multi-value specific value SAME circuit” or “multi-value specific value determination circuit” .
E) In the case of the present invention, there is no need to change the circuit configuration regardless of the number of multi-values (N of N values), and the same circuit configuration can be used for 5 values, 10 values, or 100 values. Good, flexible, flexible and responsive. You just need to change the connection of the power line to connect.
● f) In the present invention, since it is the way of multi-valued logic output of "opening the output" exit means (eg. Such as an output terminal) "identify like" pull-up resistor or pull-down resistors " constant potential supply means _(eg. a particular power supply line V m) other than the constant potential supplier "or" constant potential supply means V ₀ ~V additional non _n-1 · connected to a constant potential supply unit "" output voltage pull switching means can freely change the output voltage level "when off.
Specifically, in the case of each pull-down type multi-value logic circuit, the output terminal T _out is connected to “ another power line having a higher potential than the specific power line V _m ” or “ higher potential than the specific power supply line _{V m,} connected to the add-power line "other than the power line _{V m + 1 ~V n-1} .
On the other hand, in the case of each pull-up type multi-value logic circuit, its output terminal T _out is connected to “ another power line having a lower potential than the specific power line V _m ” or “specific power source” via a pull-down resistor or the like. The potential is lower than that of the line V _m and is connected to an additional / power line other than the power lines V _{0 to} V _m−1 ”.

● g) In the mathematical explanation regarding the “ excessive number of types of multi-valued logic processing / explosive size” described above (paragraph numbers 0010 to 0011) , it has been conservatively explained in the case of two digits in one digit. In addition, the number of digits and the number of inputs will increase to become “super, super… .super, explosive”. For example, even in the case of 10 values, 1 digit and 3 inputs, there are 10 kinds of multi-value logic processing and multi-value logic functions, which are astronomical numbers.
● h) Semiconductor (substrate) multi-layer technology (= 3D IC technology) and low-voltage technology are "multi-adic logic circuit, multi-adic arithmetic circuit, multi-adic memory circuit, multi-adic computer, etc." Powerfully assist in the practical application of If semiconductor multi-layer technology, low-voltage drive and withstand voltage maintenance technology, energy-saving technology, cooling technology, etc. continue to advance, 64, 100, and 128 logic circuits, arithmetic circuits, and memory circuits Or a computer etc. will be possible, and the super-ultra-super computer of 64 base, 100 base, 128 base may appear.
● i) By the way, the decimal computer “DC” (Decimal Computer) eliminates, prevents, or alleviates the “syndrome called“ computer over-adaptation ”caused by the current binary computer” Or it is expected to be cured. “Computer over-adaptation” makes it impossible to communicate with “others who leave ambiguous room” by identifying them with the binary thinking of computers that have only “0” or “1”. Gets worse.
Reference: p. Of the morning edition dated March 11, 2002 of the Nihon Keizai Shimbun (Tokyo edition). 34 “Mushiba Mu Techno Stress”.
This means that “multiple, especially decimal, is better for building human-friendly, human-friendly computers, neurocomputers or artificial intelligence”, and “multi-adic, especially 10 for fuzzy control. It suggests that the decimal system is better.
However, these things may apply to Asians, such as Japan, which has “an ambiguous expression culture”, and may not apply to Western countries, which have “a clear culture of YES, NO”. If so, “Isn't the multi-adic computer, etc. suitable for Asians such as Japan, and is a specialty? ]

● j) Multi-ary logic circuits, multi-ary computers, etc. have higher performance and advantages than those of binary systems even if they consume more power or have more parts. If it is, there is value in practical use. One of the advantages of the above-mentioned “human-friendly” is that the amount of information that can be sent is the same number of data lines, there is no binary / decimal conversion error in decimal, and the number of carry-overs. The advantage is that there are few. There are others.
● k) In terms of power loss, the power supply voltage is intuitively considered that the decimal circuit has a power loss as large as the square of the binary circuit voltage 10 times the square = 100 times. In the case of a decimal circuit, the number of power supplies required for 10 power supply potentials is 9, and the total voltage is 9 times. In addition, since each signal does not always fully swing between the lowest potential and the highest potential, statistical processing is required to calculate the power loss. In addition, do each of the power lines have their own electrostatic shielding effect and shielding effect? What happens to the effect of floating capacitance such as signal lines related to charge / discharge energy?


L) There is a possibility that the clock frequency and the like can be lowered by multi-leveling. This is because there is a large amount of information that can be sent and handled. Lowering the frequency reduces the number of charge / discharge cycles such as the capacitance between the gate and source of the C / MOS / FET, thereby reducing the power consumption.
M) As a matter of course, in each of the embodiments of FIGS. 3, 5, 7, 9, and 13, if the potential of the output terminal T _out is not lower than the potential v _m of the power supply line V _m , There is no need to connect blocking diodes 9 and 10. Similarly, in each of the embodiments shown in FIGS. 4, 6, 8, 10, and 14, when the potential at the output terminal T _out does not become higher than the potential v _m of the power supply line V _m , There is no need to connect the diode 12.

Claims (1)

3 or 3 or more predetermined plurality expressed by N, predetermined natural number when expressed in S,
"" The first constant potential of these in numerical order from the constant potential to the N-th constant potential becomes higher, or, N pieces of subjecting the sheet to a constant potential "which becomes lower, 0 and each of its constant potential (N -1), the first constant potential supply means to the Nth constant potential supply means defined as one-to-one correspondence with the first constant potential in order from the integer 0 , "
The "first input mouth means, second S of the incoming mouth means comprising an inlet for the S input potential signal",
And "exit means that the exit of the output potential signal",
"Among the second constant potential supply unit - the first (N-1) constant potential supply means, coupled between the one specific constant potential supply means and the exit means, said outlet means when it is ON-driven When the potential is pulled up or down to the specific constant potential of the specific constant potential supply means, and when it is driven off, at least the "extracting if pulling up during on driving" up direction, the output potential pull switching means for opening the output of the pull-down direction "," If you pull down,
“When S = 1, an integer corresponding to one of the input potential signals, and when S ≧ 2, [all S integers corresponding to each of the S input potential signals] or [S Whether at least one of S integers corresponding to each of the input potential signals] is equal to “a specific value corresponding to the specific constant potential among the integers 1 to (N−2)”. It is determined whether or not it is the same based on “both threshold potentials on the positive side and the negative side determined in advance with reference to the specific constant potential” or “one higher than the specific constant potential” The negative threshold potential determined in advance with reference to the constant potential and the positive threshold potential determined in advance with reference to the constant potential one lower than the specific constant potential. Numeric discriminator that determines whether it is not based on And ",
“Controlled by the numerical discriminating means, “ if the output potential pull / switching means is turned on if they are equal, otherwise the output potential pull / switching means is driven off ”or“ if they are equal, the output potential pull / switching means is turned off ”.・ Turn off the switching means, otherwise turn on the output potential pull switching means ” on / off drive means”,
Multivalued logic circuit and having a.
However, one said means may serve as several said means.

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