JP5391962B2 - Software error detection tool - Google Patents

Description

The present invention relates to a tool for detecting software source code creation mistakes in the development and design stage of software built in an electronic device or the like.

A GPIO (general-purpose input / output port) built in an electronic device or the like has programmable general-purpose input / output pin state settings, input pin state / output pin state settings, and internal pull-up / pull-down of general-purpose input / output pins. / No Pull status setting can be set by software built in the electronic device. Even if a software designer mistakenly creates software in a different state with respect to the design specifications determined in advance,
In actual device tests of electronic devices, it is often difficult to find software creation errors.

As a technique for reducing creation mistakes, there is a method in which a table describing design specifications is provided in software built in an electronic device, and setting to GPIO is performed by calling the table. However, the software designer only needs to execute the method of calling and setting the table without fail, but forgetting to set it directly in GPIO, it may be set differently from the design specification. Yes, it cannot be prevented. In particular, it cannot be surely guaranteed by other software designers designing or taking over leakage.

As patent literature, there is a register setting value monitoring module, system, and method for detecting a register setting value error in the initial stage of software development (see, for example, Patent Literature 1).
. This system (actual machine) includes a register setting value monitoring module 4 and a function module 6-6 in addition to the conventional CPU 2 and function module 6-8 (DMA controller, timer, etc.).
8 includes expected value registers 228 and 229 in which expected values to be set to 8 are stored in advance.

Then, in the actual machine, the register set value monitoring module 4 has the function module 6 of the CPU 2.
The setting value accessed by software in -8 and the expected value registers 228 and 229 are compared, and a software error is found.

JP 2006-293641 A (Page 5-12, FIG. 35)

The system of Patent Document 1 needs to newly provide a register set value monitoring module 4 and expected value registers 228 and 229 in an actual machine, and there is a problem that the scale of the actual machine becomes large for testing. In addition, register access must be delayed during the comparison process at the time of the test, and the IO access to the peripheral of the CPU 2 itself is slowed down. 4 must be passed to guarantee normal access.

The present invention provides a software error detection tool that detects a source code error in an electronic device and detects the error externally by reading the source code without changing the internal configuration of the electronic device. For the purpose.

In order to achieve the above object, a software error detection tool of the present invention is a software error detection tool that reads software data of an electronic device that controls a circuit of an external electronic device and detects an error in the software data. A software data storage unit in which the software data is read and stored; a hardware data storage unit in which hardware data of the circuit of the electronic device is read and stored; and software specifications corresponding to the hardware data A specification table for storing data; a search condition data storage unit for storing search condition data defined based on a language of the hardware data; and software specification data in the specification table corresponding to the search condition data are extracted. , With this extracted software specification data It compares the serial software data, characterized by comprising a code generator error detecting means for detecting errors in the software data.

According to the present invention, a software error in an electronic device can be found by an external software error detection tool without changing the internal configuration of the electronic device.

The circuit diagram (related to GPIO21) of the electronic device 100 which concerns on each Example of this invention. A time chart of a data signal and a clock signal of a standard I2C bus. Hardware data (related to GPIO21) of the electronic device 100 according to each embodiment of the present invention. The figure (GPIO21 relation) explaining the HW / SW specification table 6 (correct / incorrect table) of the electronic device 100 which concerns on each Example of this invention. The figure explaining an example of the software data of the electronic device 100 which concerns on each Example of this invention (GPIO21 connection). The block diagram of the software mistake detection tool 200 which concerns on each Example of this invention. The operation | movement flowchart of the determination process module 8 of the software error detection tool 200 which concerns on Example 1 of this invention. The operation | movement flowchart of the determination process module 8 of the software error detection tool 200 which concerns on Example 2 of this invention.

FIG. 1 is a circuit diagram of a relevant portion of a GPIO 21 (general purpose IO) of an electronic device 100 according to each embodiment of the present invention. This configuration is not an example of the present invention, and a design error of software (program stored in the ROM 26) built in the electronic device 100 will be described as an example that is difficult to find in an actual machine test of the electronic device 100 itself. Particularly in such a case, it is useful to find a software design error in the electronic device 100 using the software error detection tool 200 (FIG. 6) of the present invention described later. Of course, the software error detection tool 2 of the present invention
00 need not be limited to cases where it is difficult to find in actual machine tests, and can also be applied to other ordinary software.

Hereinafter, the configuration and operation of the GPIO 21 related part of the electronic device 100 will be described. The GPIO 21 related portion of the electronic device 100 includes a GPIO 21, an electronic component 22, an electronic component 23, a resistor 24 (external Pull Up), a control unit 25, a ROM 26, and the like.

1 is a notation on the circuit diagram of the printed circuit board on which the circuit diagram portion is mounted, and hardware data (NET list and IC pin table at the time of hardware design of the printed circuit board). ), All the components, pins, and signal lines are represented, but in FIG. 1, the HW data notation is omitted for the control unit 25, the ROM 26, the CPU bus, and the like.

The control unit 25 includes a CPU, a RAM, and the like (not shown), and executes a program stored in the ROM 26. In this example, the control unit 25 executes internal settings, input / output control, and I2C control functions of the GPIO 21 based on a program stored in the ROM 26. The ROM 26 stores a machine language in which a source code of a program designed by a software designer is compiled and assembled.

GPIO 21 is a general-purpose IO, and shows examples of a plurality of input / output pins, here, two input / output pins of pin number (1) and pin number (2). The pin number (1) is a pin name (GPIO_1), and the pin number (2) is a pin name (GPIO_2). Mode setting is possible for each input / output pin, and input pin / output pin setting for operating as an input pin or as an output pin is programmable. Also, Internal PullUp / Internal Pull
The setting of lDown / internal NoPull is programmable. Although it is programmable because of the general-purpose IO, it also causes a setting error.

The internal configuration of the programmable input / output pins of the GPIO 21 is well known, and includes a driver 31 (35), a receiver 32 (36), an internal PullUp resistor 33 (37), an internal P
This is composed of an all-down resistor 34 (38), a switch, and the like, whereby the above-described input pin / output pin setting, internal PullUp / internal PullDown / internal NoPull can be set.

The following two examples will be described as examples in which the design error of the source code of the ROM 26 program for setting the GPIO 21 is difficult to find in the actual device test of the electronic device 100.

“1. Normal output port”
In this example, the pin number (1) of the GPIO 21 is set as a normal output pin. GPIO2
The pin number (1) of 1 is connected to the pin number (1) of the electronic component 22 by the signal line name (A_OUT). The electronic component 22 is a controlled object controlled by the output of the pin number (1) of the GPIO 21, and may be anything such as lamp lighting, buzzer ringing, or other signal transmission.

When the pin number (1) of GPIO 21 is set as an output pin, the driver 31 is in an active state, and the internal pull-up resistor 33 and the internal pull-down resistor 34 are high.
There is no need to control the / Low level. Therefore, the internal NoPull setting may be set.

However, if the software designer makes a mistake, the internal PullUp state or the internal PullDo
Even when the wn state is set, the logical output level of the pin number (1) is determined by the output of the driver 31, so that no trouble in logical operation occurs. However, the internal PullU
Since current flows through the p resistor 33 and the internal PullDown resistor 34, there is a problem in that current consumption increases. This wrong state is extremely difficult to find in an actual device test of the electronic device 100.

"2. Bus master of I2C bus"
In this example, the pin number (2) of GPIO 21 is used as the bus master of the I2C bus.
Use a special way. As is well known, the I2C bus is composed of two signal lines of a data signal and a clock signal, and the GPIO 21 and the electronic component 23 are connected to the data signal and the clock signal.
Although they are connected by a signal line, only the clock signal is shown in FIG. 1, and the data signal having the same configuration is not shown. The pin number (2) side of the GPIO 21 is a bus master (hereinafter referred to as master), and the pin number (1) side of the electronic component 23 is a bus slave (hereinafter referred to as slave).

This I2C bus is determined by the standard, and will be described next.
FIG. 2 is a time chart of standard I2C bus data signals and clock signals.
The data signal and the clock signal are synchronized, and the slave captures the data signal at the rising edge of the clock signal.

The data signal is bidirectional between the master and the slave, and the data signal has a serial configuration of a start bit S, slave addresses A7-A1, R / W, ACK, and data D7-D0. Of these, the S, A7-A1, and R / W bits are output by the bus master.
After confirming the R / W, the slave specified by A7-A1 is the AC level of L level for 1 bit time.
K is returned and output. D7-D0 is output by the slave if R / W is Read, and is output by the master if R / W is Wright.

The clock signal is always output by the master. However, in the situation where the clock stretch described below occurs during the ACK period, the master continues to output the clock signal as shown by the dotted line, but the slave also uses the same clock signal as the clock signal shown by the solid line at the ACK timing. Although both signals collide with each other, the clock signal line needs to be configured to be a clock signal indicated by a solid line.

Next, this clock stretching will be described. The aforementioned slave is a data signal AC
The timing at which K is returned and output is strictly defined. Before the master sets the clock signal to the dotted H level, that is, the clock signal is at the L level, the slave needs to return and output the L level ACK. is there.

However, the slave may be delayed in outputting this ACK during some processing. In order to cope with this, the slave performs a process called clock stretching. That is, the slave outputs the clock signal at the L level when the master output clock signal for the ACK bit is at the L level. Even if the L level of the master output and the L level of the slave output are both low impedance outputs and bus fight, the clock signal line is at the L level because the L level is the same.

Even when the clock signal of the master output becomes H level as indicated by a dotted line, the slave sets the clock signal to L level (clock stretching). Although the H level and the L level are bus-fighted, it is necessary to configure the hardware so that the clock signal line is forced to the L level of the slave output in this state, which will be described later (FIG. 1).

The master monitors the clock signal while outputting the clock signal. If the L level is monitored even if the H level is output as indicated by the dotted line, the master waits for the clock signal to become the H level. When the monitored clock signal becomes H level, the master checks the data signal and if it is L level (ACK), the master knows that the designated slave exists. Then, the master sets the clock signal to L level, ends the ACK confirmation phase, and enters the subsequent phase D7-D0.

Although not shown, clock stretching can be performed in the same manner as ACK in the phase D7-D0.

Returning to FIG. 1 again, a configuration for the clock signal at the time of bus fight to be the predetermined level by the clock stretch will be described. GPIO21 pin number on the master side (
2) is connected to the pin number (1) of the electronic component 23 on the slave side by the signal line name (I2C_SCL) which is the clock signal line of the I2C bus. The clock signal line is pulled up externally by a resistor 24 (part number (R1)).

Programmable setting by the control unit 25 and the ROM 26 for the pin number (2) of the GPIO 21 on the master side needs to be performed as follows.
When performing L level output, it is a general usage method of GPIO, and output pin setting and internal NoPull setting are performed, and then L level output is performed. That is, a low impedance L level output by the driver 35. Therefore, even if the external PullUp resistor 24 is present, the clock signal line is at the L level. In this state, the electronic component 23 on the slave side
Even if the pin number (1) of the low level outputs L level with low impedance, the bus level does not occur because the level is the same L level, and the clock signal line is at the L level.

• When performing H level output, use GPIO specially. That is, although the output is performed, the input pin setting and the internal NoPull setting are set. Driver 35 is Hi
-Z (high impedance), so the clock signal line is external PullUp
The resistor 24 becomes H level. In this state, the pin number of the electronic component 23 on the slave side (
When 1) performs L level output with low impedance, the clock signal line becomes L level due to this L level output having impedance lower than that of the resistor 24. Although the master is outputting the H level, since it is the input pin setting and the internal NoPull setting, the state of the clock signal line can be monitored by the receiver 36 and the slave L level output can be known.

With the above configuration, the pin number (2) of the GPIO 21 can be used as the master of the clock signal of the I2C bus.

By the way, when performing H-level output for the I2C bus, setting the input pin and setting the internal NoPull is rare as a general usage of the GPIO 21 in spite of the output, except for the I2C bus. Normally, when H level output is performed, the output pin is set to H
It is normal to use level output.

For that reason, when the software designer performs the H level output of the GPIO 21, there is a possibility that the software designer will design as an H level output by setting the output pin. If this design is mistakenly performed, the clock impedance will cause the low impedance H level output at the master output pin setting and the slave low impedance L level output to bus fight, resulting in a clock fight. The H / L level of the signal line becomes indefinite and causes a malfunction.

However, in the actual device operation test of the electronic device 100, the steady operation of the I2C bus can be easily generated and tested, but an event that the clock ACK response is delayed due to the ACK response of the irregular non-steady operation slave is generated. It is difficult to do so, and there are cases where software testing mistakes are missed without being tested.

In both the case where the GPIO 21 is used as a normal output port and the case where the GPIO 21 is used as a bus master of the I2C bus, it is difficult to find a software design error in the actual device operation test of the electronic device 100. In particular, the software error detection tool 200 of the present invention that is external to the electronic device 100 is effective.

Next, hardware data and software data of a circuit of the electronic device 100 used in the software error detection tool 200 will be described.

FIG. 3 is a diagram illustrating hardware data of a circuit of the electronic device 100 according to each embodiment of the present invention. Data obtained at the time of circuit design by a hardware development tool (not shown).
Only the part (in parentheses) written in the circuit of FIG. 1 will be described. FIG. 3A is a NET list representing circuit connections in hardware data. FIG. 3B is a pin table of the IC among the hardware data, and is data representing a pin number and its pin name.

The NET list in FIG. 3A is a list showing all parts connected to this signal line and pin numbers of the parts for each signal line, and is expressed as a list corresponding to the number of pins connected to one signal line. The If there are two pins connected to one signal line, it is represented as two lists, and if there are three pins connected to one signal line, it is represented as three lists.
List “Signal line name”: “Part name”: “Part number”: “Pin number”
For parts without a part name, the “part name” part is deleted.

Specifically, as the pin number (1) related to GPIO21 (example of normal output port),
N1 “A_OUT”: “CHIPSET”: “IC001”: “1”
N2 “A_OUT”: “MODULE_A”: “IC002”: “1”
That is, N1 represents that the signal line name (A_OUT) is connected to the component name (CHIPSET) and the pin number (1) of the component number (IC001). N2 is the same signal line name (A_O
UT) is connected to the part name (MODULE_A) and the pin number (1) of the part number (IC002).

As for pin number (2) of GPIO21 (example of I2C bus master)
N3 “I2C_SCL”: “CHIPSET”: “IC001”: “2”
N4 “I2C_SCL”: “MODULE_B”: “IC003”: “1”
N5 “I2C_SCL:“ R1 ”:“ 2 ”
・ N6 “L26V”: “R1”: “1”
It becomes.

In the IC pin table of FIG. 3B, the IC part number, all its pin numbers, and their pin names are expressed as follows.
・ Part name Part number (The first level is the part name and part number)
・ Pin number: Pin name (From the second stage onwards, all pin numbers and pin names)
・ Pin number: Pin name ・ Pin number: Pin name Specifically,
・ CHIPSET IC001
・ 1: GPIO_1
-2: GPIO_2
・ MODULE_A IC002
・ 1: A_1
・ MODULE_B IC003
・ 1: I2C_CLK
It becomes.

FIG. 4 is a diagram illustrating an input / output pin-related H of the GPIO 21 of the electronic device 100 according to each embodiment of the invention.
It is a figure explaining the W / SW specification table 6 (correction table), and corresponds to a predetermined design specification of the electronic device 100. It is a figure which shows the correct software data (source code) which should control an input-output pin, and incorrect software data (source code). This table is input to the software error detection tool 200 described later (FIG. 6).

The HW / SW specification table 6 includes a GPI in the IC pin table for each signal line connected to the GPIO 21.
O pin name, software data (source code) correct / incorrect.

T1 is a case where the input / output pin (1) is used as a normal output pin, and the signal line name (A_O
UT) and pin name (GPIO_1).
T11 is a correct source code of the mode setting for this pin name (GPIO_1), sets the pin name (GPIO_1) as an output pin (out), and sets it to internal NoPull (nopull). Thereby, no extra current is consumed.
T12 and T13 are incorrect source codes for mode setting for the pin name (GPIO_1), and the pin name (GPIO_1) is changed to the internal PullUp (pulple) or the internal Pu.
It is set to llDown (pulldown), and an extra current is consumed.

T2 is a case where the input / output pin (2) is used as a bus master of the clock signal of the I2C bus, and has a signal line name (I2C_SCL) and a pin name (GPIO_2).
T21 is the correct source code of the H level output for this pin name (GPIO_2), and the pin name (GPIO_2) is set (set) as an input pin (in), and is set to internal NoPull (nopull). This is a special use in I2C that can be monitored by an external PullUp resistor 24 (FIG. 1) and can be monitored only by setting the input pin to output the H level.

The source code of the pair of T22 is an incorrect source code of the H level output for the pin name (GPIO_2), and the pin name (GPIO_2) is first set to the output pin (out) (s
et), and then the H level (H) is output (out). This is a general usage except for I2C, but in I2C, a bus fight causes a malfunction.

The source code of the pair of T23 is a correct source code of the L level output for the pin name (GPIO_2), and the pin name (GPIO_2) is first set to the output pin (out) (s
et), and then the L level (L) is output (out). This is the same as general usage other than I2C.

FIG. 5 is a diagram for explaining an example of software data for controlling the GPIO 21 of the electronic device 100 according to each embodiment of the present invention. This is an excerpt of a part of the enormous source code obtained when designing software with a software development tool (not shown). This source code is compiled and assembled, and an equivalent machine language is stored in the ROM 26.

Since the correct source code shown in FIG. 4 is originally given as the software external specification, the software designer does not cause a software error if the design is performed according to the correct source code. However, it is not always possible to design according to the correct source code when various modifications are made at the development stage or when the software designer changes. In particular,
Although control of GPIO input / output pins is generally simple, it is possible to make a mistake.

FIG. 5A shows a case where the pin name (GPIO_1) of GPIO 21 is used as a normal output pin, and the mode setting command of C1 is correct as described with reference to FIG. C2 is an H output command, and C3 is an L output command. The C4 mode setting command is incorrect.

FIG. 5B shows a case where the pin name (GPIO_2) of GPIO 21 is used as the bus master of the I2C bus, and C5 is correct as described in FIG. The pair C6 and C7 is wrong. The pair of C8 and C9 is correct.

The hardware data (NET list and IC pin table) of FIG. 3 and the software data (source code) of FIG. 5 described above are used as design information of the electronic device 100 as a hardware design tool (not shown) or a software design tool ( (Not shown).

These data are stored in the software error detection tool 200 described later (FIG. 6).
Is input and stored. Also, the HW / SW specification table 6 (correct / error table) of FIG. 4 is also input to the software error detection tool 200 and stored.

Next, a software error detection tool 200 that detects software errors from these data will be described.
FIG. 6 is a block diagram of the software error detection tool 200 according to each embodiment of the present invention. The software error detection tool 200 is a PC (personal computer) or the like,
HW data folder 1, SW data folder 2, keyboard 3, miss detection module 10
And the display unit 11 and the like.

The error detection module 10 is a module installed in the software error detection tool 200, and includes an HW data input module 4 and an SW data input module 5 inside.
, HW / SW specification table 6, search condition input module 7, determination processing module 8, determination result store module 9, and the like.

The user first stores the hardware data NET list (FIG. 3A) and the IC pin table (FIG. 3B) designed by the hardware design tool (not shown) into the HW data folder 1, for example, \ C Save to ¥ HW.

Further, the user saves the source code (FIG. 5) of the software data designed by the software design tool (not shown) in the SW data folder 2, for example, \ C \ SW. This software data is preferably stored every time the software data is changed in order to detect software errors.

Further, the user inputs the HW / SW specification (FIG. 4) from the keyboard 3 and is written in the HW / SW specification table 6. This HW / SW specification is a standard for software error detection, and is input reliably. The electronic device 100 is fixed as long as there is no system change. The HW / SW specification may be saved in a folder. In order to make the software error detection tool 200 a versatile tool, the HW / SW specification table 6 may be provided, and the contents thereof may be rewritten according to the contents of the electronic device 100.

And the user who performs software mistake detection inputs the search condition from the keyboard 3,
It is written in the search condition input module 7. The search conditions will be described later (FIGS. 7 to 8).

These hardware data (corresponding to FIG. 3), software data (corresponding to FIG. 5), HW /
SW specification data (corresponding to FIG. 4) and search condition data are sent to the HW by the miss detection module 10.
The data is read into the determination processing module 8 via the data input module 4, the SW data input module 5, the search condition input module 7 or directly.

Based on these pieces of information, the determination processing module 8 determines a software error and records the determination result in the determination result store module 9 as described later (FIGS. 7 to 8).
To display.

FIG. 7 is an operation flowchart of the determination processing module 8 of the software error detection tool 200 according to the first embodiment of the present invention. In the first embodiment, the user inputs search condition data based on the software source code as a search condition.

When the user wants to confirm the setting error of Internal PullUp / Internal PullDown / Internal NoPull at the time of setting the output pin of GPIO, that is, to check the excess current consumption, the keyboard 3 uses “gpio_set (?, out,?)” Based on the source code. Enter from.

As shown in the source code of FIG. 4, “gpio_set (GPIO pin name,
out, internal pull state) ”, the first“? ”means any GPIO pin name, and the second“? ”means any internal pull state.

The determination processing module 8 first confirms the search conditions input from the keyboard 3 (step S1). Here, if “gpio_set (?, Out,?)” Is confirmed, software data (entire FIG. 5) is searched under this condition, and the following is detected (step S2).
・ C1 ・ gpio_set (GPIO_1, out, nopull)
・ C4 ・ gpio_set (GPIO_1, out, pullup)
・ C6 ・ gpio_set (GPIO_2, out, nopull)
・ C8 ・ gpio_set (GPIO_2, out, nopull)
Then, the determination processing module 8 applies H to the source code detected in step S2.
Judgment is made based on the errata in the W / SW specification table 6 (FIG. 4), and C4 is judged as NG, and other than C4 is judged as OK. Since it is not a search condition for the GPIO I2C bus, C6 is also determined to be OK (step S3) and recorded in the determination result store module 9.

Then, it is displayed that there is a mistake in C4 and that C4 is corrected to the internal NoPull (step S4). If C8 is set to internal PullUp, it is also detected as a miss.

The user corrects C4 “pullup” of the software (source code) of the electronic device 100 to “nopull” by using a software design tool (not shown), and the electronic device 10
By correcting the ROM 26 of 0, it is possible to suppress a wasteful increase in current consumption of the electronic device 100.

According to the first embodiment, since the search is performed based on the search condition based on the source code, the determination is made for the entire source code, and as described above, the determination of the source code for all the output pin settings of GPIO can be performed. it can.

FIG. 8 is an operation flowchart of the determination processing module 8 of the software error detection tool 200 according to the second embodiment of the present invention. In the second embodiment, the user inputs a signal line name of a hardware NET list as search condition data as a search condition.

When the source code is searched as in the first embodiment, the entire source code is determined, but as an application when setting the output pin of GPIO, whether all internal NoPulls are correct, depending on the application, for example, Internal PullU to increase output pin drive capability
There is also an application for p.

In the second embodiment, including such a case, the GPIO input / output pin is used for each application, that is, N
The signal line name in the ET list is used as a search condition. Since the same signal line does not exist in the circuit diagram, one signal line can be designated.

For example, in a case where the GPIO input / output pin is used as an I2C bus master, the user detects a software error of the signal line name “I2C_
“SCL” is input from the keyboard 3.

The determination processing module 8 first confirms the search conditions input from the keyboard 3 (step S11). If “I2C_SCL” is confirmed, the NET list (entire FIG. 3A) is searched under this condition, and the following is detected (step S12).
N3 “I2C_SCL”: “CHIPSET”: “IC001”: “2”
N4 “I2C_SCL”: “MODULE_B”: “IC003”: “1”
・ N5 ・ “I2C_SCL:“ R1 ”:“ 2 ”
Next, the determination processing module 8 selects the signal line name “I” from the detected NET list.
The components and pin numbers connected to “2C_SCL” are confirmed, and the following is obtained (step S13).
“CHIPSET”: “IC001”: “2”
“MODULE_B”: “IC003”: “1”
・ "R1": "2"
Next, the determination processing module 8 confirms the pin names in the IC pin table (FIG. 3B) among the above components, and the following is obtained (step S14).
・ GPIO_2
・ I2C_CLK
Next, the determination processing module 8 confirms that the extracted pin name is GPIO, and “GPIO_2” is confirmed (step S15).
As described above, it can be seen that the pin name of GPIO that controls the signal line “I2C_SCL” is “GPIO_2”.

Next, the determination processing module 8 determines the pin name “GP” from all the software data in FIG.
The source code including “IO_2” is detected, and the following is obtained (step S16).
C5: gpio_set (GPIO_2, in, nopull)
C6: gpio_set (GPIO_2, out, nopull)
C7: gpio_out (GPIO_2, H)
C8: gpio_set (GPIO_2, out, nopull)
C9: gpio_out (GPIO_2, L)
Then, the determination processing module 8 performs the process on the source code detected in step S16.
Judgment is made based on the errata table T2 for “I2C_SCL” in the HW / SW specification table 6 (FIG. 4) (step S17), and the same C6 as the source code of the error pair T22 in the HW / SW specification table 6 (FIG. 4). And the pair of C7 are determined to be misses, and are recorded in the determination result store module 9.

Then, it is displayed that the pair of C6 and C7 is a mistake and that the pair of C6 and C7 is corrected to the same content as the correct source code of T21 in the HW / SW specification table 6 (FIG. 4) (step) S18).

The user modifies the pair of C6 and C7 of the software (source code) of the electronic device 100 to the input pin setting (same as T21) and the ROM 26 of the electronic device 100 by using a software design tool (not shown). Thus, the I2C function of the electronic device 100 can be made normal.

When the user inputs “A-OUT” as a search condition, the determination processing module 8
Is "A-OUT", ie, the software for GPIO_1, H
The determination is made based on the errata table T1 of “A-OUT” in the W / SW specification table 6 (FIG. 4).

According to the second embodiment, since the signal line name in the NET list is searched as a search condition, GPIO
Can detect software mistakes that match the purpose of each individual I / O pin.

When the user inputs both search conditions of the first embodiment and the second embodiment, the determination processing module 8 performs both searches and error detection.

Further, although the HW / SW specification table 6 is provided, if the software error detection tool 200 is a tool limited to a specific electronic device 100, the HW / SW specification table 6 is not provided, and the software error detection tool 200 shown in FIGS. The determination condition may be directly incorporated into the steps of the operation flowchart.

In addition, as an example of the electronic device 100, GPIO normal output pin use and I2C bus use have been described, but other uses of GPIO may be used. In addition, CP other than GPIO
Any peripheral device that can be operated by a program, such as a U peripheral, for example, a DMAC or a counter, may be used. In the above description, the case where it is difficult to find a software design error in the actual device test of the electronic device 100 has been described. However, the tool of the present invention is effective for any software.

As described above, according to the present invention, it is possible to detect software errors that are difficult to find in the actual machine test of the electronic device 100 with the external software error detection tool 200.

DESCRIPTION OF SYMBOLS 1 HW data folder 2 SW data folder 3 Keyboard 4 HW data input module 5 SW data input module 6 HW / SW specification table 7 Search condition input module 8 Judgment processing module 9 Judgment result store module 10 Miss detection module 11 Display unit 21 GPIO
22, 23 Electronic component 24 Resistance (external PullUp)
25 Control unit 26 ROM
31 Driver 32 Receiver 33 Internal PullUp Resistor 34 Internal PullDown Resistor 35 Driver 36 Receiver 37 Internal PullUp Resistor 38 Internal PullDown Resistor 100 Electronic Device 200 Software Miss Detection Tool

Claims (5)

A software error detection tool for reading software data of the electronic device that controls a circuit of an external electronic device and detecting a mistake in the software data,
A software data storage unit in which the software data is read and stored;
A hardware data storage unit in which hardware data of a circuit of the electronic device is read and stored;
A specification table for storing software specification data corresponding to the hardware data;
A search condition data storage unit for storing search condition data defined based on the language of the hardware data;
Code creation error detection means for extracting software specification data of the specification table corresponding to the search condition data, comparing the extracted software specification data with the software data, and detecting a mistake in the software data; A software error detection tool comprising: Furthermore, it has an operation input means,
The search condition data, the software error detecting tool of claim 1 or 1, wherein the input from the operation input means. The software data is the source code, the hardware data according to claim 1 software error detecting tool, wherein it is a net list of the circuit. Software specification data of the specification table, correct data or incorrect claim 1, wherein the software error detecting tool, characterized in that it is defined as data. The hardware data and software data, according to claim 1, wherein the software error detecting tool, characterized in that the data is related to the input and output switching pins for general input and output ports.

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