JP5458770B2 - Transistor and transistor manufacturing method - Google Patents

Description

  The present invention relates to a transistor and a method for manufacturing the transistor.

In a conventional transistor (for example, a transistor; thin film transistor), amorphous silicon (amorphous silicon) is generally used for a semiconductor layer in which a channel region is formed.
In addition, for the purpose of improving the on-state current of the transistor, an attempt to use crystalline silicon, particularly microcrystalline silicon (microcrystalline silicon: crystalline (polycrystalline) silicon having a crystal grain size of approximately 50 to 100 nm) for the semiconductor layer. However, when crystalline silicon is used, there is a problem that leakage current increases.
This is because the surface of the semiconductor layer made of crystalline silicon has many irregularities, and the interface with the channel protective film formed on the semiconductor layer is disturbed by the irregularities, which causes the generation of interface leakage current. Because.
In order to reduce this leakage current, a technique is known in which a semiconductor layer formed by stacking an amorphous silicon layer and a crystalline silicon layer is applied to a transistor (see, for example, Patent Document 1).

Japanese Patent Laying-Open No. 2005-167051

  However, in the case of the above-mentioned Patent Document 1, for example, as shown in FIGS. 24A and 24B, the crystalline silicon layer 561 is covered with an amorphous silicon layer 562 so that the surface unevenness of the semiconductor layer 56b is suppressed. Although the disturbance of the interface with the channel protective film 56d can be reduced, the crystalline silicon layer 561 is included in the depleted region on the drain end side of the semiconductor layer 56b where the electric field is concentrated, and the depleted crystal Since the conductive silicon layer 561 is included in the current path, a leak current may occur there. This is because crystalline silicon has many inherent electrical defects, and in the crystalline silicon layer 561 depleted by electric field concentration, hole electron pairs (electron-hole pairs) may be generated using the defects as nuclei. This is because it causes a leak current.

  An object of the present invention is to improve on-current and reduce leakage current.

In order to solve the above problems, one embodiment of the present invention is a transistor,
A gate electrode formed on the substrate;
An insulating film covering the gate electrode;
A first semiconductor film made of crystalline silicon provided on the insulating film; a second semiconductor film made of amorphous silicon covering the first semiconductor film on the insulating film;
A protective film covering at least a partial region of the second semiconductor film;
A pair of impurity semiconductor films opposed in the channel length direction with the protective film interposed therebetween;
A source electrode and a drain electrode formed on the pair of impurity semiconductor films;
With
The second semiconductor film, and a single-layer region, which does not overlap with the first semiconductor film and the heavy going on stacking region and the first semiconductor film,
The boundary between one end of the stacked region and the single layer region of the second semiconductor film is located inside the protective film end , and the other end of the stacked region is the pair of impurity semiconductor films. Located on the lower surface side of one impurity semiconductor film in
The single layer region of the second semiconductor film is located on a lower surface side of the other impurity semiconductor film in the pair of impurity semiconductor films .
Preferably, said one end of said product layer region is located 0.2~2μm inside than the protective film ends.
Preferably, the length of the protective film in the channel length direction is equal to or shorter than the length of the gate electrode in the channel length direction .
The transistor, the pair of impurity semiconductor layer of the other of the impurity semiconductor film side of the single layer area from the current flow in one direction towards the single-layer region of said one impurity semiconductor film side through the deposition area drive element Used as

Another aspect of the present invention is a method for manufacturing a transistor,
A first semiconductor film that forms a first semiconductor film made of crystalline silicon by disposing at least one end on a position corresponding to the upper side of the gate electrode on an insulating film covering the substrate on which the gate electrode is formed Forming process;
A second semiconductor layer made of amorphous silicon is formed on the insulating film so as to overlap the first semiconductor film, and the stacked region in which the second semiconductor film overlaps the first semiconductor film and the first semiconductor film are formed. a second semiconductor layer forming step of forming to have a single-walled region, which does not overlap with the first semiconductor film,
A protective film forming step of forming a protective film on the stacked region of the second semiconductor layer, located above the gate electrode;
A pair of impurity semiconductors facing each other in the channel length direction with the protective film sandwiched between the semiconductor layer on which the protective film is formed, an impurity semiconductor layer is formed, the impurity semiconductor layer and the semiconductor layer are patterned A semiconductor film forming step of forming a film and a second semiconductor film disposed under the film,
A source / drain formation step of forming a source electrode and a drain electrode on the pair of impurity semiconductor films;
With
The boundary between the single-layer region of the second semiconductor film with hand end of the deposition area is located inside the said protective film end, other end of the stack area is the pair of impurity semiconductor The single-layer region of the second semiconductor film is located on the lower surface side of one impurity semiconductor film in the film and the lower surface side of the other impurity semiconductor film in the pair of impurity semiconductor films. And

  According to the present invention, the on-state current and the leakage current of a transistor can be improved.

It is a top view which shows the arrangement configuration of the pixel of an EL panel. It is a top view which shows schematic structure of EL panel. It is a circuit diagram showing a circuit corresponding to one pixel of an EL panel. It is the top view which showed 1 pixel of EL panel. It is arrow sectional drawing of the surface along the VV line of FIG. It is arrow sectional drawing of the surface along the VI-VI line of FIG. It is explanatory drawing which shows the gate formation process in the manufacture process of a transistor. It is explanatory drawing which shows the two-layer film-forming process in the manufacture process of a transistor. It is explanatory drawing regarding the patterning performed to the semiconductor layer formed on the 1st insulating film in the manufacture process of a transistor. It is explanatory drawing which shows the resist formed on the semiconductor layer in the manufacture process of a transistor. It is explanatory drawing which shows the 1st semiconductor film formation process in the manufacture process of a transistor. It is explanatory drawing which shows the semiconductor layer film-forming process in the manufacture process of a transistor. It is explanatory drawing which shows the protective insulating film film-forming process in the manufacture process of a transistor. It is explanatory drawing which shows the protective film formation process in the manufacture process of a transistor. It is explanatory drawing which shows the impurity semiconductor layer film-forming process in the manufacture process of a transistor. It is explanatory drawing which shows the semiconductor film formation process in the manufacture process of a transistor. It is explanatory drawing which shows the source / drain formation process in the manufacture process of a transistor. It is a circuit diagram showing a circuit of an EL panel including three transistors in one pixel. It is a front view which shows an example of the mobile telephone by which EL panel was applied to the display panel. They are the front side perspective view (a) which shows an example of the digital camera with which the EL panel was applied to the display panel, and a rear side perspective view (b). It is a perspective view which shows an example of the personal computer by which EL panel was applied to the display panel. It is explanatory drawing regarding a depletion layer, and has shown about the transistor structure (a), the inversion layer (b) in a semiconductor layer, and the width | variety (c) of a depletion layer. It is explanatory drawing (a) regarding the current path of a switch transistor, and explanatory drawing (b) which shows the range depleted in a current path. It is explanatory drawing (a) regarding the current path in the transistor of a prior art, and explanatory drawing (b) which shows the range depleted in a current path.

  Hereinafter, preferred embodiments for carrying out the present invention will be described with reference to the drawings. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples.

  FIG. 1 is a plan view illustrating an arrangement configuration of a plurality of pixels P in an EL panel 1 that is a light emitting device, and FIG. 2 is a plan view illustrating a schematic configuration of the EL panel 1.

As shown in FIGS. 1 and 2, in the EL panel 1, a plurality of pixels P that respectively emit R (red), G (green), and B (blue) are arranged in a matrix with a predetermined pattern. .
In the EL panel 1, a plurality of scanning lines 2 are arranged so as to be substantially parallel to each other along the row direction, and the plurality of signal lines 3 are arranged along the column direction so as to be substantially orthogonal to the scanning lines 2 in plan view. They are arranged so as to be substantially parallel to each other. A voltage supply line 4 is provided along the scanning line 2 between the adjacent scanning lines 2. A range surrounded by the two signal lines 3 adjacent to the scanning lines 2 and the voltage supply lines 4 corresponds to the pixel P.
Further, the EL panel 1 is provided with a bank 13 that is a grid-like partition wall so as to cover the scanning line 2, the signal line 3, and the voltage supply line 4. A plurality of substantially rectangular openings 13a surrounded by the banks 13 are formed for each pixel P, and predetermined carrier transport layers (a hole injection layer 8b and a light emitting layer 8c described later) are formed in the openings 13a. ) Are provided and become a light emitting region of the pixel P. The carrier transport layer is a layer that transports holes or electrons when a voltage is applied.

  FIG. 3 is a circuit diagram showing a circuit corresponding to one pixel of the EL panel 1 operating in the active matrix driving method.

  As shown in FIG. 3, the EL panel 1 is provided with a scanning line 2, a signal line 3 intersecting with the scanning line 2, and a voltage supply line 4 along the scanning line 2. For each pixel P, a switch transistor 5 that is a transistor, a drive transistor 6 that is a transistor, a capacitor 7, and an EL element 8 are provided.

  In each pixel P, the gate of the switch transistor 5 is connected to the scanning line 2, one of the drain and source of the switch transistor 5 is connected to the signal line 3, and the other of the drain and source of the switch transistor 5 is It is connected to one electrode of the capacitor 7 and the gate of the driving transistor 6. One of the source and drain of the driving transistor 6 is connected to the voltage supply line 4, and the other of the source and drain of the driving transistor 6 is connected to the other electrode of the capacitor 7 and the anode of the EL element 8. Note that the cathodes of the EL elements 8 of all the pixels P are kept at a constant voltage Vcom (for example, grounded).

  Further, in the periphery of the EL panel 1, each scanning line 2 is connected to a scanning driver, each voltage supply line 4 is connected to a constant voltage source or a driver that outputs an appropriate voltage signal, and each signal line 3 is connected to a data driver. The EL panel 1 is driven by these drivers by an active matrix driving method. The voltage supply line 4 is supplied with predetermined power by a constant voltage source or a driver.

  Next, the circuit structure of the EL panel 1 and the pixel P will be described with reference to FIGS. Here, FIG. 4 is a plan view corresponding to one pixel P of the EL panel 1, FIG. 5 is a cross-sectional view taken along the line V-V in FIG. 4, and FIG. It is arrow sectional drawing of the surface along the VI-VI line. In FIG. 4, electrodes and wiring are mainly shown.

  As shown in FIG. 4, the switch transistor 5 and the drive transistor 6 are arranged along the signal line 3, the capacitor 7 is disposed in the vicinity of the switch transistor 5, and the EL element 8 is disposed in the vicinity of the drive transistor 6. ing. Further, a switch transistor 5, a drive transistor 6, a capacitor 7, and an EL element 8 are disposed between the scanning line 2 and the voltage supply line 4.

  As shown in FIGS. 4 to 6, a first insulating film 11 serving as a gate insulating film is formed on one surface of the transistor substrate 10, and a second insulating film 12 is formed on the first insulating film 11. It is filmed. The signal line 3 is formed between the first insulating film 11 and the transistor substrate 10, and the scanning line 2 and the voltage supply line 4 are formed between the first insulating film 11 and the second insulating film 12.

  As shown in FIGS. 4 and 6, the switch transistor 5 is an inverted staggered transistor. The switch transistor 5 includes a gate electrode 5a, a semiconductor film 5b, a channel protective film 5d, impurity semiconductor films 5f and 5g, a drain electrode 5h, a source electrode 5i, and the like.

The gate electrode 5 a is formed between the transistor substrate 10 and the first insulating film 11. The gate electrode 5a is made of, for example, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, or an AlTiNd alloy film. An insulating first insulating film 11 is formed on the gate electrode 5a, and the first insulating film 11 covers the gate electrode 5a.
The first insulating film 11 has, for example, optical transparency and is made of silicon nitride or silicon oxide. An intrinsic semiconductor film 5b is formed on the first insulating film 11 at a position corresponding to the gate electrode 5a, and the semiconductor film 5b is opposed to the gate electrode 5a with the first insulating film 11 interposed therebetween.
The semiconductor film 5b is, for example, a first semiconductor film 51 made of crystalline silicon formed on the first insulating film 11, and a non-film formed so as to cover the first semiconductor film 51 on the first insulating film 11. A second semiconductor film 52 made of crystalline silicon, and a channel is formed in the semiconductor film 5b. The stacked region where the first semiconductor film 51 and the second semiconductor film 52 overlap is located above the gate electrode 5a in the semiconductor film 5b, and both sides of this stacked region are the second semiconductor film 52. It is a single layer region.
An insulating channel protective film 5d is formed on the central portion of the semiconductor film 5b. The channel protective film 5d covers the stacked region of the semiconductor film 5b where the first semiconductor film 51 and the second semiconductor film 52 overlap, and both end sides of the channel protective film 5d are single layer regions near the stacked region. A part of the two semiconductor films 52 is covered. The channel protective film 5d is made of, for example, silicon nitride or silicon oxide.
Further, the impurity semiconductor film 5g is formed so as to partially overlap the channel protective film 5d on the second semiconductor film 52 on the one end side of the semiconductor film 5b, and on the other end side of the semiconductor film 5b. On the second semiconductor film 52, an impurity semiconductor film 5f is formed so as to partially overlap the channel protective film 5d. The impurity semiconductor films 5f and 5g are formed on both ends of the semiconductor film 5b so as to be separated from each other, and the impurity semiconductor films 5f and 5g are opposed to each other on the semiconductor film 5b with the channel protective film 5d interposed therebetween. Formed in the arrangement. The impurity semiconductor films 5f and 5g are n-type semiconductors, but are not limited thereto, and may be p-type semiconductors.
A drain electrode 5h is formed on the impurity semiconductor film 5f. A source electrode 5i is formed on the impurity semiconductor film 5g. The drain electrode 5h and the source electrode 5i are made of, for example, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, or an AlTiNd alloy film.
An insulating second insulating film 12 is formed on the channel protective film 5d, drain electrode 5h, and source electrode 5i, and the channel protective film 5d, drain electrode 5h, and source electrode 5i are covered with the second insulating film 12. Has been. The switch transistor 5 is covered with the second insulating film 12. The second insulating film 12 is made of, for example, silicon nitride or silicon oxide.

As described above, the switch transistor 5 used as a drive element in the EL panel 1 includes the first semiconductor film 51 and the second semiconductor film 52 covering the first semiconductor film 51 as shown in FIG. The semiconductor film 5b is included. A laminated region where the first semiconductor film 51 and the second semiconductor film 52 overlap is located on the center side of the semiconductor film 5b, and the impurity semiconductor films 5f and 5g are opposed to each other with the channel protective film 5d interposed therebetween. Single-layer regions of the second semiconductor film 52 are located on both sides of the laminated region along.
Further, the channel protective film 5d of the switch transistor 5 is a single layer region on the side of the laminated region on both ends of the channel protective film 5d while covering the laminated region corresponding to the first semiconductor film 51 portion in the semiconductor film 5b. A part of the second semiconductor film 52 is covered. The single layer region in the semiconductor film 5b is covered with the impurity semiconductor films 5f and 5g.
That is, the stacked region where the first semiconductor film 51 and the second semiconductor film 52 overlap in the semiconductor film 5b is located on the lower surface side of the channel protective film 5d, and the single layer region in the semiconductor film 5b is on both sides of the stacked region. The impurity semiconductor films 5f and 5g are located on the lower surface side, and the boundary between the both ends of the stacked region and the single-layer region in the semiconductor film 5b is located on the lower surface side of the channel protective film 5d.
The length of the channel protective film 5d located above the gate electrode 5a and the length along the direction in which the pair of impurity semiconductor films 5f and 5g oppose (channel length direction) is the stacked region in the semiconductor film 5b. It is formed so as to be longer than the length of the first semiconductor film 51 and not more than the length of the gate electrode 5a.
In addition, it is preferable that the edge part of the lamination | stacking area | region corresponded to the 1st semiconductor film 51 part is located in the channel length direction from the edge part of the channel protective film 5d inside each one end about 0.2-2 micrometers.

The semiconductor film 5b serving as a channel region includes a first semiconductor film 51 made of crystalline silicon and a second semiconductor film 52 made of amorphous silicon, but an impurity semiconductor serving as a source / drain region. The films 5f and 5g are in contact with the single layer region of the second semiconductor film 52 in the semiconductor film 5b, and are not in direct contact with the first semiconductor film 51.
The impurity semiconductor films 5f and 5g are not in contact with the first semiconductor film 51 made of crystalline silicon but are in contact with the second semiconductor film 52 made of amorphous silicon and are electrically connected to the semiconductor film 5b. Compared with the case where the semiconductor films 5f and 5g are in direct contact with the crystalline silicon portion, the leakage current is less likely to occur.
Furthermore, since the first semiconductor film 51 is covered with the second semiconductor film 52 and the unevenness on the surface of the first semiconductor film 51 is covered with the second semiconductor film 52, the etching formed on the semiconductor layer 5b is performed. Since the disorder of the interface with the channel protective film 5d as a stopper is suppressed, the occurrence of leakage current at the interface between the semiconductor layer 5b and the channel protective film 5d is reduced.

As shown in FIGS. 3 and 4, the switch transistor 5 has a drain electrode 5 h connected to the signal line 3, a source electrode 5 i connected to the gate electrode 6 a of the driving transistor 6, and the EL element 8. Although the direction of the current between the source and the drain accompanying switching for causing light emission is not fixed, the impurity semiconductor films 5f and 5g are not in direct contact with the first semiconductor film 51 made of crystalline silicon. The occurrence of electronic defects due to the internal defects is suppressed.
As a result, a current (current from one single layer region to the other single layer region through the stacked region) from the drain electrode 5h and the impurity semiconductor film 5f to the source electrode 5i and the impurity semiconductor film 5g flows to the semiconductor film 5b. Even when the current flows from the source electrode 5i and the impurity semiconductor film 5g to the drain electrode 5h and the impurity semiconductor film 5f (current from the other single layer region to one single layer region through the stacked region) flows to the semiconductor film 5b. Even so, it is possible to perform suitable current control in which generation of leakage current is suppressed.
The on-current is improved by providing a current path in the stacked region of the semiconductor film 5b to the first semiconductor film 51 made of crystalline silicon.

Here, the merit that the end portion of the stacked region corresponding to the first semiconductor film 51 portion is positioned inward by about 0.2 to 2 μm at one end in the channel length direction from the end portion of the channel protective film 5d will be described.
For example, in the transistor schematically shown in FIG. 22A, when a negative bias of −20 V is applied to the gate (G) (see FIG. 22B), the hole concentration (n _h ) in the channel is as follows: It is required as follows.
Q = CV
= (1 / d) × ε · ε ₀ × 20
= (1 / 4E-5) × (6.5 × 8.86E-14) × 20
= 2.88E-7 [C]
As shown in FIG. 22B, when an inversion layer of 50 [Å] is generated in the semiconductor layer (a-Si) and the hole charge is 1.6E-19,
n _h = Q / {(1.6E-19) × (5E-7)}
= 3.6E18 [/ cm ³ ]
In contrast, the impurity semiconductor layer (n +) electron concentration in the _{(n e)} is of the order of ^{1E-20 [/ cm 3]} . (For example, the gas flow rate during film formation of the impurity semiconductor is SiH ₄ / H ₂ / PH ₃ = 30/240/60 [sccm], the lattice constant of Si is 5.43 [Å], and the atomic density is 6.25E21. In the case of [/ cm ³ ].)
Since the difference between the hole concentration (n _h ) and the electron concentration (n _e ) is large, the width W of the depletion layer shown in FIG. 22C can be approximated by a well-known one-sided step junction, and is represented by the following formula 1. It can be obtained by an expression.

_{Then, K s = 11.7, ε 0} = 8.86E-18 [F / μm], q = 1.6E-19 [C], N A = n h = 3.6E18 [/ cm 3] = 3 .6E6 [/ μm ³ ], φ _B = 0.7 [V], and source-drain voltage V = 10 [V], W≈0.06 <0.1 [μm] according to the equation shown in Equation 1. Then, the width W of the depletion layer in the semiconductor layer (a-Si) can be estimated.

Since the width W of the depletion layer that is depleted on the drain end side of the semiconductor layer where the electric field is concentrated in this way is 0.1 [μm] or less, as shown in FIGS. If the end of the stacked region corresponding to one semiconductor film 51 portion is located 0.2 [μm] inward in the channel length direction from the end of the channel protective film 5d, the depleted range is not The semiconductor layer portion that is not included in the stacked region and is depleted is composed of the second semiconductor film 52 made of amorphous silicon with few intrinsic defects, and thus is caused by electronic defects of crystalline silicon. The generation of leakage current can be reduced.
Considering the channel resistance at the time of ON, since the channel length of a general TFT is about 10 [μm], the formation region of the second semiconductor film 52 (single layer region) occupying the channel region is 2 [μm on one side. ] (4 [μm] on both sides) is preferable from the viewpoint of preventing a decrease in on-current. That is, since it is necessary for the on-current to be increased that the proportion of the first semiconductor film 51 (laminated region) in the channel region is 60% or more, the formation region of the second semiconductor film 52 (single layer region) The upper limit of 2 [μm] is an upper limit value at which the end portion of the stacked region enters inside the end portion of the channel protective film 5d.
From the above consideration, the end of the stacked region corresponding to the first semiconductor film 51 portion has a dimension of 0.2 [μm] or more and 2 [μm] or less in the channel length direction from the end of the channel protective film 5d. If the switch transistor 5 is formed so as to be located on the inner side, it is possible to suitably reduce the leakage current caused by the electronic defects of the crystalline silicon.

  As shown in FIGS. 4 and 5, the drive transistor 6 is an inverted staggered transistor. The drive transistor 6 includes a gate electrode 6a, a semiconductor film 6b, a channel protective film 6d, impurity semiconductor films 6f and 6g, a drain electrode 6h, a source electrode 6i, and the like.

The gate electrode 6a is made of, for example, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, or an AlTiNd alloy film, and is formed between the transistor substrate 10 and the first insulating film 11 similarly to the gate electrode 5a. Yes. The gate electrode 6a is covered with a first insulating film 11 made of, for example, silicon nitride or silicon oxide.
A semiconductor film 6b in which a channel is formed is provided on the first insulating film 11 at a position corresponding to the gate electrode 6a. The semiconductor film 6b sandwiches the first insulating film 11 with the gate electrode interposed therebetween. Relative to 6a.
The semiconductor film 6 b is, for example, a first semiconductor film 61 made of crystalline silicon formed on the first insulating film 11 and a non-film formed so as to cover the first semiconductor film 61 on the first insulating film 11. A second semiconductor film 62 made of crystalline silicon, and a channel is formed in the semiconductor film 6b. Note that the stacked region where the first semiconductor film 61 and the second semiconductor film 62 overlap is located in the range from the upper center side of the gate electrode 6a to the impurity semiconductor film 6g side in the semiconductor film 6b. Both sides of the first semiconductor film 62 are single-layer regions of the second semiconductor film 62. Note that one end side of the stacked region and the lower surface side of the impurity semiconductor film 6g is a relatively small single layer region, and the other end side of the stacked region and the lower surface side of the impurity semiconductor film 6f is a relatively large single layer region. ing.
An insulating channel protective film 6d is formed on the central portion of the semiconductor film 6b. The channel protective film 6d covers the laminated region portion where the first semiconductor film 61 and the second semiconductor film 62 located above the gate electrode 6a and located on the center side of the semiconductor film 6b overlap, and the channel protective film 6d. One end side of the channel protection film is on the laminated region, and the other end side of the channel protective film 6d covers a part of a relatively large single layer region. The channel protective film 6d is made of, for example, silicon nitride or silicon oxide.
The impurity semiconductor film 6g is formed so as to partially overlap the channel protective film 6d on the stacked region on the one end side of the semiconductor film 6b and the second semiconductor film 62, and the other end of the semiconductor film 6b. On the second semiconductor film 62 on the part side, an impurity semiconductor film 6f is formed so as to partially overlap the channel protective film 6d. The impurity semiconductor films 6f and 6g are formed on both ends of the semiconductor film 6b so as to be separated from each other, and the impurity semiconductor films 6f and 6g are opposed to each other on the semiconductor film 6b with the channel protective film 6d interposed therebetween. Formed in the arrangement. The impurity semiconductor films 6f and 6g are n-type semiconductors, but are not limited thereto, and may be p-type semiconductors.
A drain electrode 6h is formed on the impurity semiconductor film 6f. A source electrode 6i is formed on the impurity semiconductor film 6g. The drain electrode 6h and the source electrode 6i are made of, for example, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, or an AlTiNd alloy film.
An insulating second insulating film 12 is formed on the channel protective film 6d, the drain electrode 6h, and the source electrode 6i, and the channel protective film 6d, the drain electrode 6h, and the source electrode 6i are covered with the second insulating film 12. Has been. The drive transistor 6 is covered with the second insulating film 12.

As described above, the driving transistor 6 used as a driving element in the EL panel 1 includes the first semiconductor film 61 and the second semiconductor film 62 covering the first semiconductor film 61 as shown in FIG. The semiconductor film 6b is included. A laminated region where the first semiconductor film 61 and the second semiconductor film 62 overlap is located from the channel protective film 6d side of the semiconductor film 6b to the impurity semiconductor film 6g side which is one end side of the semiconductor film 6b. A single layer region of the second semiconductor film 62 is located on both sides of a stacked region along a direction in which the impurity semiconductor films 6f and 6g face each other with the channel protective film 6d interposed therebetween. A relatively small single layer region is located on the lower surface side of one impurity semiconductor film 6g, and a relatively large single layer region is located on the lower surface side of the other impurity semiconductor film 6f.
The channel protective film 6d of the drive transistor 6 covers a relatively large single layer region on the impurity semiconductor film 6f side at the other end of the channel protective film 6d while covering the stacked region portion located above the gate electrode 6a. It covers a part. In addition, a relatively small single layer region in the semiconductor film 6b and a laminated region portion on one end side that is not covered with the channel protective film 6d are covered with the impurity semiconductor film 6g, and a relatively large single layer region in the semiconductor film 6b is The semiconductor layer is covered with the impurity semiconductor film 6f.
That is, in the semiconductor film 6b, the stacked region where the first semiconductor film 61 and the second semiconductor film 62 overlap is along the channel length direction, and one of the pair of impurity semiconductor films from the lower surface side in the channel region of the channel protective film 6d. The relatively small single layer region in the semiconductor film 6b located on the lower surface side of the impurity semiconductor film 6g is located on the lower surface side of the other impurity semiconductor film 6g in the pair of impurity semiconductor films. The relatively large single layer region in the semiconductor film 6b is located on the lower surface side of the other impurity semiconductor film 6f in the pair of impurity semiconductor films.
Note that the boundary between one end of the stacked region and the relatively small single layer region is located on the lower surface side of one impurity semiconductor film 6g, and the boundary between the other end of the stacked region and the relatively large single layer region is channel protection. It is located on the lower surface side in the channel region of the film 6d. In particular, the other end portion of the stacked region corresponding to the first semiconductor film 61 portion is preferably located on the inner side by about 0.2 to 2 μm in the channel length direction from the end portion of the channel protective film 6d. The advantage that the leakage current can be reduced when the other end of the stacked region is located about 0.2 to 2 μm inward in the channel length direction from the end of the channel protective film 6d is the case of the switch transistor 5 described above. Since it is the same as that, description is abbreviate | omitted.
Further, the length of the stacked region along the direction in which the pair of impurity semiconductor films 6 f and 6 g face in the semiconductor film 6 b is longer than the length of the stacked region of the semiconductor film 5 b of the switch transistor 5.

The semiconductor film 6b serving as the channel region includes the first semiconductor film 61 composed of crystalline silicon and the second semiconductor film 62 composed of amorphous silicon, but the impurity semiconductor serving as the source / drain regions. The films 6f and 6g are in contact with the second semiconductor film 62 in the semiconductor film 6b, and are not in direct contact with the first semiconductor film 61. In particular, the boundary between the other end of the stacked region and the relatively large single layer region is located on the lower surface side in the channel region of the channel protective film 6d, and crystalline silicon is formed on the lower surface side of the impurity semiconductor film 6f. The first semiconductor film 61 to be formed is not disposed.
Here, the impurity semiconductor film 6f is not positioned above the first semiconductor film 61, but is in contact with the single layer region of the second semiconductor film 62 made of amorphous silicon and is electrically connected to the semiconductor film 6b. As compared with the case where the impurity semiconductor film 6f is in direct contact with the crystalline silicon portion, the leakage current is less likely to occur.
Furthermore, since the first semiconductor film 61 is covered with the second semiconductor film 62 and the surface roughness of the first semiconductor film 61 is covered with the second semiconductor film 62, the etching formed on the semiconductor layer 6b is performed. Since the disorder of the interface with the channel protective film 6d as a stopper is suppressed, the occurrence of leakage current at the interface between the semiconductor layer 6b and the channel protective film 6d is reduced.

As shown in FIGS. 3 and 4, the drive transistor 6 has a drain electrode 6 h connected to the voltage supply line 4 and a source electrode 6 i connected to the EL element 8, so that the EL element 8 emits light. The direction of the current between the source and the drain due to the switching drive is determined in one direction from the relatively large single layer region on the impurity semiconductor film 6f side to the relatively small single layer region on the impurity semiconductor film 6g side, Further, since the impurity semiconductor film 6f is not in direct contact with the first semiconductor film 61 made of crystalline silicon, generation of electrical defects due to defects in the crystalline silicon can be suppressed.
Accordingly, a current (current from a relatively large single layer region to a relatively small single layer region through the stacked region) from the drain electrode 6h and the impurity semiconductor film 6f to the source electrode 6i and the impurity semiconductor film 6g flows to the semiconductor film 6b. In this case, it is possible to carry out suitable current control while suppressing the occurrence of leakage current.
The current path in the stacked region of the semiconductor film 6b is taken to the first semiconductor film 61 side made of crystalline silicon, thereby improving the on-current.
In particular, in the case of the driving transistor 6 in which the direction of current is fixed, the portion of the semiconductor film 6b that is in contact with the impurity semiconductor film 6f that is on the upstream side (drain side) of the current is a single portion of the second semiconductor film 62 made of amorphous silicon. When the layer region is used and the boundary between the stacked region and the single layer region on the drain side is provided on the lower surface side of the channel protective film 6d, it is possible to suitably suppress the occurrence of leakage current and to minimize the decrease in on-current. At this time, on the source side, the length of the stacked region protruding from the lower surface side of the channel protective film 6d to the impurity semiconductor film 6g side along the direction in which the pair of impurity semiconductor films 6f and 6g opposes is 0.5 [μm]. The above is preferable, more preferably 2 [μm] or more, and may reach the end of the impurity semiconductor film 6g.
In addition, by increasing the length of the stacked region including the first semiconductor film 61 made of crystalline silicon in the current direction, the current can easily flow through the transistor. That is, even if the transistor size is reduced, it is possible to flow a larger current, so that the light emission luminance of the EL element 8 can be improved and the display performance of the EL panel 1 can be improved.

  The capacitor 7 is connected between the gate electrode 6a and the source electrode 6i of the driving transistor 6, and one electrode is provided between the transistor substrate 10 and the first insulating film 11 as shown in FIGS. 7a is formed, the other electrode 7b is formed between the first insulating film 11 and the second insulating film 12, and the electrodes 7a and 7b are opposed to each other with the first insulating film 11 that is a dielectric interposed therebetween. .

The signal line 3, the electrode 7a of the capacitor 7, the gate electrode 5a of the switch transistor 5, and the gate electrode 6a of the driving transistor 6 are formed of a conductive metal film formed over the transistor substrate 10 by photolithography and etching. It is formed in a lump by shape processing by a method or the like.
In addition, the scanning line 2, the voltage supply line 4, the electrode 7 b of the capacitor 7, the drain electrode 5 h and source electrode 5 i of the switch transistor 5, and the drain electrode 6 h and source electrode 6 i of the driving transistor 6 are on the first insulating film 11. The conductive metal film is formed by shape processing by a photolithography method, an etching method, or the like.

In the first insulating film 11, a contact hole 11a is formed in a region where the gate electrode 5a and the scanning line 2 overlap, and a contact hole 11b is formed in a region where the drain electrode 5h and the signal line 3 overlap. A contact hole 11c is formed in a region where 6a and the source electrode 5i overlap, and contact plugs 20a to 20c are buried in the contact holes 11a to 11c, respectively. The contact plug 20a electrically connects the gate electrode 5a of the switch transistor 5 and the scanning line 2, the contact plug 20b electrically connects the drain electrode 5h of the switch transistor 5 and the signal line 3, and the contact plug 20c electrically connects the switch transistor. 5 source electrode 5i and capacitor 7 electrode 7a are electrically connected, and source electrode 5i of switch transistor 5 and gate electrode 6a of drive transistor 6 are electrically connected. The scanning line 2 may be in direct contact with the gate electrode 5a, the drain electrode 5h may be in contact with the signal line 3, and the source electrode 5i may be in contact with the gate electrode 6a without using the contact plugs 20a to 20c.
Further, the gate electrode 6a of the driving transistor 6 is integrally connected to the electrode 7a of the capacitor 7, the drain electrode 6h of the driving transistor 6 is integrally connected to the voltage supply line 4, and the source electrode 6i of the driving transistor 6 is connected to the capacitor. 7 is integrally connected to the electrode 7b.

The pixel electrode 8 a is provided on the transistor substrate 10 via the first insulating film 11 and is formed independently for each pixel P. The pixel electrode 8a is a transparent electrode, for example, tin-doped indium oxide (ITO), zinc-doped indium oxide, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), or cadmium − It consists of tin oxide (CTO). The pixel electrode 8a partially overlaps the source electrode 6i of the driving transistor 6, and the pixel electrode 8a and the source electrode 6i are connected.
4 and 5, the second insulating film 12 includes the scanning line 2, the signal line 3, the voltage supply line 4, the switch transistor 5, the driving transistor 6, the peripheral edge of the pixel electrode 8a, the capacitor 7 It is formed so as to cover the electrode 7 b and the first insulating film 11. An opening 12a is formed in the second insulating film 12 so that the center of each pixel electrode 8a is exposed. Therefore, the second insulating film 12 is formed in a lattice shape in plan view.

  A panel in which the scanning line 2, the signal line 3, the voltage supply line 4, the switch transistor 5, the driving transistor 6, the capacitor 7, the pixel electrode 8a, and the second insulating film 12 are formed on the surface of the transistor substrate 10 is a transistor array. It is a panel.

  As shown in FIGS. 4 and 5, the EL element 8 includes a pixel electrode 8a as a first electrode serving as an anode, a hole injection layer 8b that is a compound film formed on the pixel electrode 8a, and a hole. A light emitting layer 8c, which is a compound film formed on the injection layer 8b, and a counter electrode 8d as a second electrode formed on the light emitting layer 8c are provided. The counter electrode 8d is a single electrode common to all the pixels P, and is continuously formed in all the pixels P.

The hole injection layer 8b is a functional layer made of, for example, PEDOT (poly (ethylenedioxy) thiophene) that is a conductive polymer and PSS (polystyrene sulfonate) that is a dopant. This is a carrier injection layer that injects holes from the electrode 8a toward the light emitting layer 8c.
The light emitting layer 8c includes a material that emits any one of R (red), G (green), and B (blue) for each pixel P. For example, the light emitting layer 8c is made of a polyfluorene light emitting material or a polyphenylene vinylene light emitting material. This is a layer that emits light upon recombination of electrons supplied from the electrode 8d and holes injected from the hole injection layer 8b. For this reason, the pixel P that emits R (red), the pixel P that emits G (green), and the pixel P that emits B (blue) have different light emitting materials for the light emitting layer 8c. The R (red), G (green), and B (blue) pattern of the pixel P may be a delta arrangement or a stripe pattern in which the same color pixels are arranged in the vertical direction.

The counter electrode 8d is made of a material having a work function lower than that of the pixel electrode 8a. For example, the counter electrode 8d is made of a simple substance or an alloy containing at least one of indium, magnesium, calcium, lithium, barium, and a rare earth metal.
The counter electrode 8d is an electrode common to all the pixels P, and covers a bank 13 described later together with a compound film such as the light emitting layer 8c.

As described above, the light emitting layer 8 c serving as a light emitting portion is partitioned for each pixel P by the second insulating film 12 and the bank 13.
And in the opening part 13a, the positive hole injection layer 8b and the light emitting layer 8c as a carrier transport layer are laminated | stacked on the pixel electrode 8a.

Specifically, when the hole injection layer 8b and the light emitting layer 8c are formed by a wet method, the bank 13 is adjacent to a liquid material in which a material for forming the hole injection layer 8b or the light emitting layer 8c is dissolved or dispersed in a solvent. It functions as a partition wall that prevents the pixel P from bleeding.
For example, as shown in FIG. 5, an opening 13 a is formed in the bank 13 provided on the second insulating film 12 inside the opening 12 a of the second insulating film 12.
Then, a liquid containing a material to be the hole injection layer 8b is applied on each pixel electrode 8a surrounded by each opening 13a, and the transistor is heated together with the transistor substrate 10 to dry the liquid. The compound film thus formed becomes the hole injection layer 8b which is the first carrier transport layer.
Further, a liquid material containing a material to be the light emitting layer 8c is applied on each hole injection layer 8b surrounded by the openings 13a, and the transistor is heated together with the transistor substrate 10 to dry the film. The compound film thus formed becomes the light emitting layer 8c which is the second carrier transport layer.
A counter electrode 8 d is provided so as to cover the light emitting layer 8 c and the bank 13.

In the EL panel 1, the pixel electrode 8a, the transistor substrate 10 and the first insulating film 11 are transparent, and light emitted from the light emitting layer 8c is transmitted through the pixel electrode 8a, the first insulating film 11 and the transistor substrate 10. Then exit. Therefore, the back surface of the transistor substrate 10 becomes a display surface.
The display surface may be the opposite side instead of the transistor substrate 10 side. In this case, the counter electrode 8d is a transparent electrode, the pixel electrode 8a is a reflective electrode, and light emitted from the light emitting layer 8c is transmitted through the counter electrode 8d and emitted.

The EL panel 1 is driven as follows to emit light.
In a state where a predetermined level of voltage is applied to all the voltage supply lines 4, the scanning driver sequentially applies voltages to the scanning lines 2, thereby sequentially selecting the scanning lines 2.
When each scanning line 2 is selected, if a voltage of a level corresponding to the gradation is applied to all the signal lines 3 by the data driver, the switch transistor 5 corresponding to the selected scanning line 2 is turned on. Therefore, a voltage of a level corresponding to the gradation is applied to the gate electrode 6a of the drive transistor 6.
The potential difference between the gate electrode 6a and the source electrode 6i of the drive transistor 6 is determined according to the voltage applied to the gate electrode 6a of the drive transistor 6, and the magnitude of the drain-source current in the drive transistor 6 is determined. The EL element 8 emits light with brightness according to the drain-source current.
Thereafter, when the selection of the scanning line 2 is released, the switch transistor 5 is turned off, so that the charge according to the voltage applied to the gate electrode 6a of the driving transistor 6 is stored in the capacitor 7 and the driving transistor 6 The potential difference between the gate electrode 6a and the source electrode 6i is maintained.
For this reason, the drive transistor 6 keeps flowing the drain-source current having the same current value as that at the time of selection, and maintains the luminance of the EL element 8.

  Next, a method for manufacturing a transistor used as a drive element in the EL panel 1 according to the present invention will be described using the switch transistor 5 as an example.

First, a gate metal layer is deposited on the transistor substrate 10 by sputtering and patterned by a photolithography method, an etching method, or the like to form a gate electrode 5a as shown in FIG. 7 (gate formation step).
The gate electrode 6a of the drive transistor 6, the signal line 3, and the electrode 7a of the capacitor 7 are formed on the transistor substrate 10 together with the gate electrode 6a (see FIGS. 5 and 6).

  Next, as shown in FIG. 8, the first insulating film 11 such as silicon nitride and the semiconductor layer 91b which becomes the first semiconductor film in the semiconductor film 5b (6b) made of crystalline silicon (microcrystal silicon) by plasma CVD. Are continuously deposited to form a two-layer film (a two-layer film forming step).

Next, as shown in FIG. 9, a positive type photoresist layer 40 is formed on the semiconductor layer 91b.
Further, as shown in FIG. 9, a photomask 50 having a mask portion 50a is disposed above the photoresist layer 40, and patterning is performed by a photolithography method, an etching method, or the like. As shown in FIG. A resist 40a is formed on the semiconductor layer 91b above the electrode 5a. The size of the resist 40a corresponds to the range of the stacked region in the semiconductor film 5b. Note that a resist corresponding to the range of the stacked region in the semiconductor film 6b is also formed on the semiconductor layer 91b above the gate electrode 6a of the driving transistor 6.

Then, after dry etching or wet etching is performed on the semiconductor layer 91b on which the resist 40a is formed, the resist 40a is peeled off to form a first semiconductor film 51 made of crystalline silicon as shown in FIG. It forms on the 1st insulating film 11 (1st semiconductor film formation process). The first semiconductor film 51 has a size corresponding to the range of the stacked region in the semiconductor film 5b, and both ends thereof are located above the gate electrode 5a.
The first semiconductor film 61 in the semiconductor film 6b of the driving transistor 6 is also formed on the first insulating film 11 in the same manner, and the first semiconductor film 61 is formed according to the range of the stacked region of the semiconductor film 6b. One end portion protrudes from above the gate electrode 6a, and the other end portion is positioned above the gate electrode 6a.

Next, as shown in FIG. 12, a semiconductor layer 92b made of amorphous silicon is formed on the first insulating film 11 so as to overlap the first semiconductor film 51 (semiconductor layer forming step). Similarly, a semiconductor layer 92b made of amorphous silicon is formed on the first semiconductor film 61 of the driving transistor 6.
The semiconductor layer 92b formed here has a thickness at least equal to that of the first semiconductor film 51 (61), and more preferably slightly thicker than the thickness of the first semiconductor film 51 (61). Have The formed semiconductor layer 92b covers the upper surface of the first semiconductor film 51 (61) and covers the unevenness of the surface of the first semiconductor film 51 (61).
For example, the film thickness of the semiconductor layer 91b to be the first semiconductor film 51 (61) and the film thickness of the semiconductor layer 92b are 20 [nm] or more in order to form an excellent continuous semiconductor film. In order to enable suitable current control, such as suppressing an increase in leakage current due to an excessive increase in film thickness, or preventing a decrease in on-current due to resistance in the film thickness direction, 100 [nm] It is preferable that

Next, as shown in FIG. 13, a protective insulating film 9d such as silicon nitride serving as a channel protective film is formed on the semiconductor layer 92b by a CVD method or the like.
Then, as shown in FIG. 14, the protective insulating film 9d is patterned by a photolithography method, an etching method, or the like to form a channel protective film 5d (protective film forming step). The channel protective film 5d covers a region overlapping the first semiconductor film 51 in the semiconductor layer 92b located above the gate electrode 5a.
The channel protective film 6d of the driving transistor 6 is formed in the same manner, and the channel protective film 6d covers a region overlapping the first semiconductor film 61 in the semiconductor layer 92b located above the gate electrode 6a. Yes.

Next, as shown in FIG. 15, an impurity semiconductor layer 9f to be an impurity semiconductor film is formed by a CVD method or the like on the semiconductor layer 92b on which the channel protective film 5d is formed (impurity semiconductor layer forming step).
Next, as shown in FIG. 16, the impurity semiconductor layer 9f and the semiconductor layer 92b are successively patterned by photolithography to form the impurity semiconductor films 5f and 5g and the second semiconductor film 52 (semiconductor film forming step). Then, the semiconductor film 5 b including the second semiconductor film 52 and the first semiconductor film 51 covered with the second semiconductor film 52 is formed.
Here, the channel protective film 5d covers the stacked region of the semiconductor film 5b where the first semiconductor film 51 and the second semiconductor film 52 overlap, and is a single layer on the stacked region side at both ends of the channel protective film 5d. A portion of the second semiconductor film 52 that is a region is covered. The single layer region of the second semiconductor film 52 in the semiconductor film 5b is covered with the impurity semiconductor films 5f and 5g.
Further, contact holes 11a to 11c are formed by photolithography, and contact plugs 20a to 20c are formed in the contact holes 11a to 11c.

  In the semiconductor film formation step, the impurity semiconductor films 6f and 6g and the second semiconductor film 62 of the driving transistor 6 are formed in the same manner, and the second semiconductor film 62 and the first semiconductor film covered with the second semiconductor film 62 are formed. A semiconductor film 6b having 61 is formed (see FIG. 5). The channel protective film 6d of the drive transistor 6 is on one end side, covering the stacked region portion where the first semiconductor film 61 and the second semiconductor film 62 overlap in the semiconductor film 6b, and the other end of the channel protective film 6d. Covers a part of a relatively large single layer region on the impurity semiconductor film 6f side. In addition, a relatively small single layer region in the semiconductor film 6b and a laminated region portion on one end side that is not covered with the channel protective film 6d are covered with the impurity semiconductor film 6g, and a relatively large single layer region in the semiconductor film 6b is The semiconductor layer is covered with the impurity semiconductor film 6f.

Next, as shown in FIG. 17, a metal film covering the impurity semiconductor films 5f and 5g, the channel protective film 5d, the semiconductor film 5b, and the first insulating film 11 on the transistor substrate 10 is formed by sputtering. The metal film is patterned by photolithography to form the source electrode 5i and the drain electrode 5h on the pair of impurity semiconductor films 5f and 5g (source / drain formation step).
Thus, the switch transistor 5 is manufactured. The source electrode 6i and the drain electrode 6h of the drive transistor 6 are formed in the same manner, and the drive transistor 6 is manufactured.

In addition to the source electrode and the drain electrode, the scanning line 2, the voltage supply line 4, and the electrode 7b of the capacitor 7 are formed (see FIGS. 5 and 6).
Further, after the switch transistor 5 and the drive transistor 6 are formed, an ITO film is deposited and then patterned to form the pixel electrode 8a (see FIG. 5).
Next, a second insulating film 12 is formed so as to cover the switch transistor 5 and the drive transistor 6 (see FIGS. 5 and 6). The second insulating film 12 is formed by depositing silicon nitride or the like by plasma CVD, as with the first insulating film 11. The second insulating film 12 is patterned by photolithography to form an opening 12a through which the central portion of the pixel electrode 8a is exposed (see FIG. 5).
Next, after depositing a photosensitive resin such as polyimide, exposure is performed to form a lattice bank 13 having an opening 13a through which the pixel electrode 8a is exposed (see FIG. 5).
Next, a liquid material in which a material for forming the hole injection layer 8b and the light emitting layer 8c is dissolved or dispersed in a solvent is applied to the opening 13a of the bank 13, and the liquid material is dried to form a carrier transport layer. A hole injection layer 8b and a light emitting layer 8c are sequentially formed (see FIG. 5).
Next, the EL element 8 is manufactured by forming the counter electrode 8d on the entire surface of the bank 13 and the light emitting layer 8c (see FIGS. 5 and 6), and the EL panel 1 is manufactured.

As described above, the switch transistor 5 includes the second semiconductor in which both ends of the stacked region where the first semiconductor film 51 of crystalline silicon and the second semiconductor film 52 of amorphous silicon overlap each other are amorphous silicon. The semiconductor film 5b is a single-layer region of the film 52, and the channel protective film 5d covers the stacked region in the semiconductor film 5b and is on both sides of the channel protective film 5d. Covers part of the layer area.
The length of the channel protective film 5d along the direction in which the pair of impurity semiconductor films 5f and 5g face each other is longer than the length of the stacked region where the first semiconductor film 51 and the second semiconductor film 52 overlap in the semiconductor film 5b. It is long and shorter than the length of the gate electrode 5a.
The impurity semiconductor films 5f and 5g serving as source / drain regions are not in direct contact with the first semiconductor film 51 made of crystalline silicon, and the second semiconductor film 52 which is a single layer area of amorphous silicon in the semiconductor film 5b. Since the drain electrode 5h and the source electrode 5i are electrically connected to the semiconductor film 5b through the impurity semiconductor films 5f and 5g, the generation of electrical defects due to defects in the crystalline silicon is suppressed. As a result, leakage current is less likely to occur. Further, the on-current is improved by providing the first semiconductor film 51 made of crystalline silicon in the current path in the stacked region of the semiconductor film 5b.

The driving transistor 6 includes a semiconductor film 6 b composed of a first semiconductor film 61 made of crystalline silicon and a second semiconductor film 62 made of amorphous silicon, and the first semiconductor film 61 and the second semiconductor film 62. Are stacked from the channel protective film 6d to the lower surface of the impurity semiconductor film 6g, and from the other end of the channel protective film 6d to the lower surface of the impurity semiconductor film 6f, a single layer region of amorphous silicon. The second semiconductor film 62 is disposed.
In the driving transistor 6, the direction of the current between the source and the drain is changed from a single layer region (second semiconductor film 62) on the impurity semiconductor film 6f side to a single layer region (second semiconductor film 62) on the impurity semiconductor film 6g side. The impurity semiconductor film 6f on the upstream side of the current is not in direct contact with the first semiconductor film 61 of crystalline silicon, and is a single layer of amorphous silicon in the semiconductor film 6b. It is in contact with the second semiconductor film 62 which is a region.
Since the drain electrode 6h and the source electrode 6i are electrically connected to the amorphous silicon second semiconductor film 62 in the semiconductor film 6b through the impurity semiconductor films 6f and 6g, the hole electrons caused by crystalline silicon. Generation of a pair is suppressed, and a leak current is hardly generated. Further, since the first semiconductor film 61 made of crystalline silicon is provided in the current path in the stacked region of the semiconductor film 6b, the on-current is improved.
In particular, the length of the stacked region in which the first semiconductor film 61 made of crystalline silicon and the second semiconductor film 62 made of amorphous silicon overlap with each other in the current direction is made longer, and the crystalline silicon in the semiconductor film 6b is made longer. By increasing the ratio, it becomes easier for current to flow through the transistor. Therefore, even if the transistor size is reduced, it is possible to flow a larger current, so that the light emission luminance of the EL element 8 is improved and the EL panel 1 is improved. Display performance can be improved.

  Thus, the switch transistor 5 and the drive transistor having the semiconductor films (5b, 6b) composed of the first semiconductor films (51, 61) made of crystalline silicon and the second semiconductor films (52, 62) made of amorphous silicon. 6 can be said to be a suitable transistor that achieves both a high on-current and a low leakage current because the on-current is improved by crystalline silicon and the leakage current is reduced.

  As shown in FIG. 18, in the case of an EL panel provided with three transistors (switch transistor 5, drive transistor 6, and holding transistor 55), capacitor 7, and EL element 8 for each pixel P, the holding transistor is used. Similarly to the switch transistor 5, the direction of the current between the source and the drain is not fixed, so that the first layer of crystalline silicon and the second layer of amorphous silicon overlap each other. What is necessary is just to set it as the transistor provided with the semiconductor film of the same type as the switch transistor 5 in which both end sides are single layer regions of amorphous silicon.

The EL panel 1 formed and manufactured as described above is used as a display panel for various electronic devices.
For example, the display panel 1a of the mobile phone 200 shown in FIG. 19, the display panel 1b of the digital camera 300 shown in FIGS. 20A and 20B, the display panel 1c of the personal computer 400 shown in FIG. The EL panel 1 can be applied.

  In the above embodiment, the semiconductor layer 91b made of crystalline silicon (microcrystal silicon) is formed on the first insulating film 11, and the semiconductor layer 91b is patterned to form the first semiconductor film 51, However, the present invention is not limited to this. For example, after the first semiconductor films 51 and 61 of amorphous silicon are formed, the amorphous silicon is crystallized into crystalline silicon. Processing may be performed to form the first semiconductor films 51 and 61 made of crystalline silicon.

  Further, in the above embodiment, when there is a relatively small single layer region on one end side of the stacked region in the semiconductor film 6b of the drive transistor 6, and there is a relatively large single layer region on the other end side of the stacked region. However, the present invention is not limited to this. For example, there may be no single-layer region on one end side of the stacked region, and the stacked region may reach the end of the impurity semiconductor film 6g on the source side.

  In the above embodiment, since the width of the depletion layer depleted on the drain end side of the semiconductor layer where the electric field is concentrated is 0.1 [μm] or less, the stack corresponding to the first semiconductor film portion. If the end of the region is located 0.2 [μm] inward in the channel length direction with respect to the end of the channel protective film, the depleted range does not include the stacked region and is depleted. Since the semiconductor layer portion is composed of the second semiconductor film made of amorphous silicon with few intrinsic defects, it is possible to reduce the occurrence of leakage current due to electronic defects of crystalline silicon. However, it is not necessary that the entire semiconductor layer portion to be depleted is composed of the second semiconductor film made of amorphous silicon, and the constituent region of the second semiconductor film occupying the semiconductor layer portion to be depleted is The higher the leakage current Can be further reduced.

  In addition, it is needless to say that other specific detailed structures can be appropriately changed.

1 EL panel 2 Scan line 3 Signal line 4 Voltage supply line 5 Switch transistor (transistor)
6 Drive transistor (transistor)
5a, 6a Gate electrode 5b, 6b Semiconductor film 51, 61 First semiconductor film 52, 62 Second semiconductor film 5d, 6d Channel protective film (protective film)
5f, 6f Impurity semiconductor film 5g, 6g Impurity semiconductor film 5h, 6h Drain electrode 5i, 6i Source electrode 7 Capacitor 8 EL element 91b, 92b Semiconductor layer 9d Protective insulating film 9f Impurity semiconductor layer 10 Transistor substrate 11 First insulating film 12 First Two insulating films 13 Bank 55 Holding transistor (transistor)

Claims (5)

A gate electrode formed on the substrate;
An insulating film covering the gate electrode;
A first semiconductor film made of crystalline silicon provided on the insulating film; a second semiconductor film made of amorphous silicon covering the first semiconductor film on the insulating film;
A protective film covering at least a partial region of the second semiconductor film;
A pair of impurity semiconductor films opposed in the channel length direction with the protective film interposed therebetween;
A source electrode and a drain electrode formed on the pair of impurity semiconductor films;
With
The second semiconductor film, and a single-layer region, which does not overlap with the first semiconductor film and the heavy going on stacking region and the first semiconductor film,
The boundary between one end of the stacked region and the single layer region of the second semiconductor film is located inside the protective film end , and the other end of the stacked region is the pair of impurity semiconductor films. Located on the lower surface side of one impurity semiconductor film in
The transistor, wherein the single-layer region of the second semiconductor film is located on a lower surface side of the other impurity semiconductor film in the pair of impurity semiconductor films . The transistor of claim 1 wherein one end of said product layer region, characterized in that located 0.2~2μm inside than the protective film ends.   3. The transistor according to claim 1, wherein a length of the protective film in a channel length direction is equal to or less than a length of the gate electrode in a channel length direction. The transistor, the pair of impurity semiconductor layer of the other of the impurity semiconductor film side of the single layer area from the current flow in one direction towards the single-layer region of said one impurity semiconductor film side through the deposition area drive element The transistor according to claim 1 , wherein the transistor is used as a transistor. A first semiconductor film that forms a first semiconductor film made of crystalline silicon by disposing at least one end on a position corresponding to the upper side of the gate electrode on an insulating film covering the substrate on which the gate electrode is formed Forming process;
A second semiconductor layer made of amorphous silicon is formed on the insulating film so as to overlap the first semiconductor film, and the stacked region in which the second semiconductor film overlaps the first semiconductor film and the first semiconductor film are formed. a second semiconductor layer forming step of forming to have a single-walled region, which does not overlap with the first semiconductor film,
A protective film forming step of forming a protective film on the stacked region of the second semiconductor layer, located above the gate electrode;
A pair of impurity semiconductors facing each other in the channel length direction with the protective film sandwiched between the semiconductor layer on which the protective film is formed, an impurity semiconductor layer is formed, the impurity semiconductor layer and the semiconductor layer are patterned A semiconductor film forming step of forming a film and a second semiconductor film disposed under the film,
A source / drain formation step of forming a source electrode and a drain electrode on the pair of impurity semiconductor films;
With
The boundary between the single layer area is located inside the said protective film end and the other end of the pair of impurity semiconductor film of the laminated area of the one end portion and the second semiconductor film of the laminated area Wherein the single-layer region of the second semiconductor film is located on the lower surface side of the other impurity semiconductor film of the pair of impurity semiconductor films. A method for manufacturing a transistor.

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