JP5478342B2 - Information processing device - Google Patents

Description

  The present invention relates to a processing request transmission circuit that requests a data processing unit to perform processing, and an information processing apparatus.

  In recent years, the system has become large-scale, and various components are interspersed within the system, and the interface speed is improved, so that it is not necessary to place importance on the relationship between the order of data processing and the physical arrangement. Rather, it is desirable that there are no physical placement restrictions.

  As a result, arbitration processing is required to avoid congestion when multiple components share a high-speed communication path, or to avoid congestion when components share other components. Control as a whole has become difficult.

  Conventionally, the following technique is known as a method for avoiding congestion in a data processing network (see, for example, Patent Document 1). This technique includes a plurality of transmission source nodes having two or more priority queues for each destination, a switch that outputs the output equally for each destination for all inputs, and a plurality of destinations that receive data from the switch. A switch fabric composed of nodes is used.

  Then, if the receiving buffer free capacity for each destination of the switch managed by the transmission source node is equal to or less than the set congestion threshold, the destination is considered to be congested, and data output from the priority queue is output to the destination. The bandwidth is limited to a preset bandwidth according to the priority, and if the reception buffer free space for each destination is equal to or higher than the congestion release threshold set, it is considered that the congestion of the destination has been released, and the bandwidth according to the priority. The congestion is avoided by releasing the restriction.

JP 2008-166888 A

  By the way, from the viewpoint of system expandability and flexibility, connection to a de facto system and adoption of de facto connection means (communication interface) have become essential. Therefore, even for system designers, the arbitration method cannot be freely changed due to the necessity of using existing and standard components, and it is difficult to optimize the arbitration method for the system.

  For example, in a system using a microprocessor, a memory control circuit for controlling access to a memory has been designed so that a system designer adapts to the system. However, in recent years, general-purpose microprocessors have built-in memory control circuits, and today, when such microprocessors have become mainstream, system designers are free to adapt specifications in the vicinity of memory control circuits to the system. Can no longer be designed.

  As described above, when an arbitrator that arbitrates memory access is built in the microprocessor in advance, the arbitrator mounted in the microprocessor is “general-purpose” and is not specialized for the system. In particular, even when trying to improve the operating rate and bring out the performance of each component close to the limit, a general-purpose arbiter that is not optimized for the system can draw out the performance of each component and improve the performance of the entire system. Have difficulty.

  Even in the congestion avoidance method in the above-described data processing network (Patent Document 1), regardless of the difference in data contents, that is, the difference in the processing amount at the data transmission destination, depending on whether the free capacity of the reception buffer is greater than or equal to a certain threshold value, Only the data transmission bandwidth is limited to a preset bandwidth.

  Therefore, the above-described congestion avoidance method in the data processing network is capable of avoiding congestion even when the data processing amount reaches a maximum, that is, bandwidth limitation that can avoid congestion regardless of the data processing amount at the data transmission destination. Since it is necessary to limit the bandwidth, the bandwidth is excessively limited. As a result, the system performance cannot be sufficiently obtained.

  An object of the present invention is to provide a processing request transmission circuit and an information processing apparatus that can easily extract system performance while reducing the possibility of congestion occurring in a data processing unit.

An information processing apparatus according to the present invention is an information processing apparatus including a processing request transmission circuit, a data processing unit, and an information processing unit that outputs an access request to the data processing unit, wherein the processing request transmission circuit includes: A request receiving unit that receives in parallel a plurality of processed data strings that request processing from a data processing unit that processes data, and a plurality of processed data strings that are received by the request receiving unit in turn, the data processing unit A processing request transmission unit that performs arbitration among a plurality of requests, a data length counting unit that counts the data length of the processed data string, and a data length Ld counted by the data length counting unit Td = a × Ld + b, where a and b are approximated by constant equations, and the processing time Td required for the data processing unit to process the processed data string is calculated as Td = a × Ld + b The processing request transmission unit transmits the one processed data string to the data processing unit, and then transmits the processed data string to the data processing unit. An interval equal to or longer than the processing time calculated by the processing time calculation unit based on the data length counted by the data length counting unit for the column, and the data processing unit uses the plurality of processing units connected in series. An interface circuit for transmitting a data string to be processed output from the processing request transmission unit, a memory, and a memory control for accessing the memory as the plurality of processing units; And an access request from the information processing unit and a data string to be processed transmitted by the interface circuit. An arbitration unit that arbitrates a relationship between a request for data and a data string to be processed, and executes access to the memory by the memory control unit in the order of the arbitration, and the interface among the plurality of processing units The circuit is a processing unit that becomes a bottleneck of throughput, and the arbitration unit arbitrates a relationship between an access request from the information processing unit and a data string to be processed in accordance with a preset priority. those who processed data sequence has been transmitted by said interface circuit than the access request from the information processing unit, the priority is rather high, the constants a, b is that is experimentally determined by the least square method It is.

  According to this configuration, the request receiving unit receives a data string to be processed which is a processing request to the data processing unit. Then, the data length of the data string to be processed is counted by the data length counting unit, and the processing time required for the data processing unit to process the data having the counted data length is calculated by the processing time calculation unit. Then, the processing request transmission unit transmits the one processed data string to the data processing unit, and then transmits the processed data string to the data processing unit until the next processing data string is transmitted to the data processing unit. An interval equal to or greater than the processing time calculated by the processing time calculation unit is provided based on the data length counted by the above.

As a result, there is a time interval until the next processed data string is transmitted for the processing time calculated according to the data length of the processed data string transmitted last time. The possibility of congestion occurring between the processed data string and the next transmitted processed data string is reduced. Since the time interval at which the processed data string is transmitted is set according to the data length of the previous processed data string, that is, the data processing amount in the data processing unit, the congestion avoidance method described in the background art In this way, it is possible to reduce the risk of performance degradation due to excessive band limitation. Therefore, it becomes easy to extract the performance of the data processing unit while reducing the possibility of congestion occurring in the data processing unit.
In addition, according to this configuration, since the transmission to the data processing unit of the plurality of processed data strings received in parallel by the request receiving unit is arbitrated by the processing request transmitting unit, the processing request to the data processing unit Even when there are a plurality of components to be processed, the data string to be processed can be asynchronously output to the request receiving unit, and the design becomes easy.
In addition, according to this configuration, the processing time calculation unit can calculate the processing time Td by performing a simple linear function calculation process using the above formula, and thus the circuit configuration of the processing time calculation unit It is easy to simplify.
In addition, according to this configuration, the processing request transmission circuit, the information processing unit, the arbitration unit, the memory control unit, the memory, and the interface that transmits the processed data sequence output from the processing request transmission unit to the arbitration unit In an information processing apparatus including a circuit, in an interface circuit, an arbitration unit, a memory control unit, and a data processing unit including a memory, it becomes easy to draw out performance while reducing the possibility of congestion.
Further, according to this configuration, when the access request from the information processing unit and the processed data sequence from the processing request transmission unit compete in the arbitration unit, the processed data sequence from the processing request transmission unit is given priority. . As a result, the processing request transmission unit requests the access to the memory from the information processing unit even though the processing time interval is set as the transmission interval of the data string to be processed so that congestion does not occur in the data processing unit. due to, causing that the processed data sequence can not be processed within the processing time, a possibility that congestion occurs is Ru are reduced.

  According to this configuration, since the transmission to the data processing unit of the plurality of processed data strings received in parallel by the request receiving unit is arbitrated by the processing request transmission unit, a processing request is made to the data processing unit. Even if there are a plurality of components, the data string to be processed can be asynchronously output to the request receiving unit, and the design becomes easy.

Further, the processing request transmitting circuit further comprising a data sequence generator outputting to said request receiving unit and generates the processed data sequence, the processing unit serving as the bottleneck, immediately after the processing request transmitting unit It is preferable that the processing unit that is connected and becomes the bottleneck receives the entire processing target data string to be processed from the processing request transmission unit.

  According to this configuration, among the data processing paths including a plurality of processing units, a processing unit that is a bottleneck of throughput is connected immediately after the processing request transmission unit, and the processing unit that is the bottleneck is a processing target The processing target data string that is output from the component other than the processing request transmitting unit to the processing unit that is the bottleneck may be congested. There is no.

  The data length counting unit is provided with one processed data string on a path from the processing request transmission unit to the data processing unit, and the data length counting unit transmits the processed data string transmitted from the processing request transmission unit. It is preferable to count the data length.

  According to this configuration, the data length is compared with the case where a plurality of data length counting units are provided in a plurality of paths through which a plurality of processed data strings are input to the request receiving unit and the data length of each processed data string is counted. Since the number of counting units can be reduced, the circuit can be easily simplified.

  According to this configuration, the processing time calculation unit can calculate the processing time Td by performing a calculation process of a simple linear function using Expression (1). It is easy to simplify.

  According to this configuration, the processing request transmission circuit, the information processing unit, the arbitration unit, the memory control unit, the memory, and the interface circuit that transmits the processed data string output from the processing request transmission unit to the arbitration unit, In the data processing unit including the interface circuit, the arbitrating unit, the memory control unit, and the memory of the information processing apparatus including the above, it becomes easy to draw out performance while reducing the possibility of occurrence of congestion.

  According to this configuration, in the arbitration unit, when the access request from the information processing unit and the processed data sequence from the processing request transmission unit compete, the processed data sequence from the processing request transmission unit has priority. As a result, the processing request transmission unit requests the access to the memory from the information processing unit even though the processing time interval is set as the transmission interval of the data string to be processed so that congestion does not occur in the data processing unit. Due to the above, the possibility that the processing target data string cannot be processed within the processing time is reduced, thereby reducing the possibility of congestion.

  According to the processing request transmission circuit and the information processing apparatus configured as described above, the processing data string is transmitted for the next processing time calculated according to the data length of the processing data string transmitted last time. Since the time interval is free, the possibility that congestion will occur between the processed data sequence transmitted last time and the processed data sequence transmitted next in the data processing unit is reduced. Since the time interval at which the processed data string is transmitted is set according to the data length of the previous processed data string, that is, the data processing amount in the data processing unit, the congestion avoidance method described in the background art In this way, it is possible to reduce the risk of performance degradation due to excessive band limitation. Therefore, it becomes easy to extract the performance of the data processing unit while reducing the possibility of congestion occurring in the data processing unit.

It is a block diagram which shows an example of the information processing apparatus using the process request transmission circuit which concerns on one Embodiment of this invention.

  Embodiments according to the present invention will be described below with reference to the drawings. In addition, the structure which attached | subjected the same code | symbol in each figure shows that it is the same structure, The description is abbreviate | omitted. FIG. 1 is a block diagram showing an example of an information processing apparatus using a processing request transmission circuit according to an embodiment of the present invention.

  An information processing apparatus 1 illustrated in FIG. 1 includes a microprocessor 2, an ASIC (Application Specific Integrated Circuit) 3, and a memory 4.

  The microprocessor 2 includes, for example, a CPU core 21 (CPU; Central Processing Unit) (information processing unit), an arbitration unit 22, a memory controller 23 (memory control unit), and an external bus I / F 24 (interface circuit). Configured. The microprocessor 2 is, for example, a general-purpose product, and the designer of the information processing apparatus 1 cannot freely change the design of the microprocessor 2. As the microprocessor 2, for example, ARM926EJ-S manufactured by ARM can be used.

  The ASIC 3 includes a processing request transmission circuit 30 and an external bus I / F 35 (interface circuit). The processing request transmission circuit 30 includes a plurality of functional modules A, B, and C (data string generation unit), a request reception unit 31, a processing request transmission unit 32, a data length counting unit 33, and a processing time calculation unit 34. It is configured with. The ASIC 3 is a dedicated circuit that can be freely designed by the designer of the information processing apparatus 1 according to the information processing apparatus 1.

  The external bus I / Fs 24 and 35, the arbitration unit 22, the memory controller 23, and the memory 4 constitute an example of the data processing unit 5.

  The external bus I / Fs 24 and 35 are bus interface circuits that transmit and receive data between the microprocessor 2 and the ASIC 3. The external bus I / Fs 24 and 35 may be a parallel bus or a serial bus, and various interface circuits can be used.

  The CPU core 21 accesses the memory 4 as the program is executed. When the CPU core 21 accesses the memory 4, the CPU core 21 outputs an access request to the memory controller 23 via the arbitration unit 22, and the memory controller 23 executes memory access to the memory 4.

  The arbitration unit 22 is an arbitration circuit that performs arbitration when the access request to the memory 4 from the CPU core 21 and the access request to the memory 4 from the external bus I / F 24 conflict. The arbitration unit 22 includes a priority setting register 221, and the external bus I / F 24 rather than an access request to the memory 4 from the CPU core 21 according to the priority set in the priority setting register 221 in advance. The access request to the memory 4 from is given priority.

  The priority setting register 221 is a register for storing the priority setting of the CPU core 21 and the external bus I / F 24, and the priority of the external bus I / F 24 is set higher than that of the CPU core 21 in advance. In the information processing apparatus 1, even if the access request to the memory 4 from the external bus I / F 24 is prioritized over the access request to the memory 4 from the CPU core 21, the external bus I / F The occupation ratio of the memory 4 by F24 is set to about 70% or less.

  The memory controller 23 receives an access request to the memory 4 from the CPU core 21 and an access request to the memory 4 from the external bus I / F 24 via the arbitration unit 22, and the memory controller 23 responds to the access request. 4 is accessed.

  The access request may be either a read access or a write access. Hereinafter, a write access will be described as an example for easy understanding.

  Each of the functional modules A, B, and C performs various types of information processing in order to realize the functions of the information processing apparatus 1, generates a processed data string as an execution result of the information processing, and sends it to the request reception unit 31. Output. The functional modules A, B, and C do not need to be included in the processing request transmission circuit 30, and the request receiving unit 31 may be configured to receive the data string to be processed from outside the ASIC 3.

  The request receiving unit 31 includes a queue buffer that temporarily stores data strings to be processed received from the function modules A, B, and C, for example. For example, the request receiving unit 31 receives data strings to be processed output from the function modules A, B, and C in parallel and stores them in the queue buffer. The queue buffer can be read from the processing request transmission unit 32.

  The processing request transmission unit 32 receives the processed data string received from the functional modules A, B, and C by the request reception unit 31 and stored in the queue buffer, for example, in the order received by the request reception unit 31 or the function. Modules A, B, and C are read in a predetermined order such as a preset order of priority, and are sequentially transmitted to the data processing unit 5.

  Specifically, the processing request transmission unit 32 outputs, for example, one processed data string read from the queue buffer of the request reception unit 31 to the external bus I / F 35, and from the external bus I / F 35 to the external bus I / F. Send to F24. As a result, the data string to be processed received by the external bus I / F 24 is arbitrated with the memory access of the CPU core 21 by the arbitration unit 22, output to the memory controller 23, and written to the memory 4 by the memory controller 23. It has become.

  Then, the processing request transmission unit 32 finishes outputting one processed data string to the external bus I / F 35 and then exceeds the processing time tw calculated by the processing time calculating unit 34 for the one processed data string. After the interval, transmission of the next data string to be processed to the external bus I / F 35 is started.

  The data length counter 33 counts the data length Ld of the processed data string output from the processing request transmitter 32 to the external bus I / F 35 and outputs the counted data length Ld to the processing time calculator 34. The data length Ld may be a bit length, a byte length, or a word length.

  Instead of providing the data length counting unit 33 between the processing request transmission unit 32 and the external bus I / F 35, the functional modules A, B, C, between the functional modules A, B, C and the request reception unit 31 are provided. Three data length counters 33 may be provided corresponding to C to count each of the data lengths Ld of the data strings to be processed output from the functional modules A, B, and C.

  However, as shown in FIG. 1, if one data length counting unit 33 is provided on the path from the processing request transmitting unit 32 to the data processing unit 5, the number of data length counting units 33 is reduced. It is easy to simplify.

  The processing time calculation unit 34 calculates the processing time Td using the data length Ld output from the data length counting unit 33 using the following equation (1).

Processing time Td = a × Ld + b (1)
However, a and b are constants.

  As for the constants a and b, the processing time Td required for the data processing unit 5 to process the processed data sequence having the data length Ld, that is, the processed data sequence output from the processing request transmitting unit 32 is written in the memory 4. The processing time Td required for this is a value that is obtained and set in advance, for example, experimentally or by theoretical calculation so as to be approximated by the equation (1).

  The processing time Td is the processing time (throughput) of the data processing unit 5 as a whole. In many cases, the processing time Td is equal to the processing time of the processing unit that is a bottleneck in the data processing unit 5. Therefore, for example, the processing time of the processing unit that becomes a bottleneck in the data processing unit 5 may be set as the processing time Td.

  The processing time Td is as follows if it is to be calculated strictly. For example, the data string to be processed having the data length Ld output from the processing request transmission unit 32 to the external bus I / F 35 is converted into a predetermined communication format in the external bus I / F 35, and, for example, a header, a preamble, a control bit, etc. In addition, the amount of data increases. Therefore, the amount of data transmitted from the external bus I / F 35 to the external bus I / F 24 is expressed as fx (Ld) by the function fx.

  When the data string to be processed having the data amount of fx (Ld) is received by the external bus I / F 24, it is converted into a data format that can be processed by the arbitration unit 22 in the external bus I / F 24. Is expressed as fy (fx (Ld)) using the function fy.

  Here, the communication processing time by the external bus I / F 35, 24 is expressed as Tx (fx (Ld)). The processing time for transferring the data string to be processed from the external bus I / F 24 to the memory controller 23 via the arbitration unit 22, that is, the processing time of the arbitration unit 22 is expressed as Ty (fy (fx (Ld))). The

  Next, in the memory controller 23, the processed data string having the original data length Ld is extracted from the processed data string whose data amount is fy (fx (Ld)) and written into the memory 4. At this time, the write processing time of the memory 4 by the memory controller 23 is expressed as Tz (Ld).

  Then, from the viewpoint of the throughput of the data processing unit 5, the processing time Td required for the processing target data string output from the processing request transmission unit 32 to be written to the memory 4 is Tx (fx (Ld)), Ty (fy (Fx (Ld))) and Tz (Ld).

  However, when Tx (fx (Ld)), Ty (fy (fx (Ld))), and Tz (Ld) are calculated and the maximum value is obtained, for example, the external bus I / F 35, 24, Processing such as dynamically detecting Tx (fx (Ld)), Ty (fy (fx (Ld))), and Tz (Ld) by operating the arbitration unit 22 and the memory controller 23 is required. Therefore, the calculation process of the processing time Td becomes very complicated, which is undesirable because it results in an increase in the circuit scale of the calculation circuit and an increase in the calculation time.

  Therefore, the processing time of the entire data processing unit 5 is obtained by, for example, experimentally obtaining the constants a and b in the equation (1) by a method such as a least square method, or by obtaining the constants a and b in advance by theoretical calculation. Thus, the processing time Td can be obtained in a short time by a simple circuit by a simple linear function calculation process according to the equation (1).

  Here, in general, of Tx (fx (Ld)), fy (fx (Ld)), and Tz (Ld), the communication processing time by the external bus I / F 35, 24, that is, Tx (fx (Ld) )) Is the maximum. In this case, among the external bus I / F 35, 24, the arbitration unit 22, and the memory controller 23, the external bus I / F 35, 24 is a bottleneck in the data processing unit 5.

  Next, the operation of the information processing apparatus 1 configured as described above will be described. First, from the functional modules A, B, and C, requests for write access to the processed data string Da having the data length Lda, the processed data string Db having the data length Ldb, and the processed data string Dc having the data length Ldc are requested almost simultaneously. It is assumed that it has been output to the reception unit 31.

  Then, the processed data string Da, the processed data string Db, and the processed data string Dc are stored in the queue buffer of the request receiving unit 31.

  Next, the processing request transmission unit 32 reads the data string Da to be processed from the queue buffer of the request reception unit 31 according to the priority order set in advance in the order of the functional modules A, B, C, for example, and the data length The data is output to the external bus I / F 35 via the counting unit 33.

  Then, in the process of transferring the data string Da to be processed from the processing request transmitter 32 to the external bus I / F 35, the data length counter 33 counts the data length Lda of the data string Da to be processed and indicates the data length Lda. Information is output to the processing time calculation unit 34.

  Then, the processing time calculation unit 34 calculates the processing time Td using the formula (1), and the calculated processing time Td is output to the processing request transmission unit 32.

  On the other hand, the external bus I / F 35 receives the processed data string Da and outputs it to the external bus I / F 24. Then, the processed data string Da received by the external bus I / F 24 is output to the memory controller 23 through arbitration by the arbitration unit 22, and written to the memory 4 by the memory controller 23.

  Here, if the processing request transmitting unit 32 outputs the next processed data string Db to the external bus I / F 35 continuously immediately after outputting the processed data string Da to the external bus I / F 35, data processing is performed. In the unit 5, the processing of the data string Db to be processed catches up during the processing of the data string Da to be processed that has been output first, and the data processing unit 5 may be congested.

  Therefore, after the processing request transmission unit 32 finishes outputting the processed data string Da to the external bus I / F 35 and the processing time Td calculated by the processing time calculation unit 34 has elapsed, The next data string Db to be processed is read from the queue buffer and output to the external bus I / F 35 via the data length counter 33.

  As a result, the data processing unit 5 has a time interval until the next processing target data string Db is transmitted by the processing time Td calculated according to the data length Lda of the processing target data string Da transmitted last time. The possibility that congestion will occur between the data string Da to be processed transmitted last time and the data string Db to be processed next transmitted is reduced.

  Further, in the data processing unit 5, the time interval until the next processing becomes long if the data processing amount is large, and the time interval until the next processing becomes short if the data processing amount is small. As in the avoidance method, it is possible to reduce the possibility that the bandwidth is excessively limited and the performance is deteriorated. Therefore, it becomes easy to extract the performance of the information processing apparatus 1 while reducing the possibility of congestion occurring in the data processing unit 5.

  Thereafter, based on the processed data string Db output to the external bus I / F 35, the data processing unit 5 executes the same process as in the case of the processed data string Da, and writes to the memory 4. Is called.

  Next, the processing time Td is calculated by the processing time calculation unit 34 from the data length Ldb measured by the data length counting unit 33 for the processed data string Db.

  Then, after the processing request transmission unit 32 finishes outputting the data string Db to be processed to the external bus I / F 35, the processing time Td calculated by the processing time calculation unit 34 has elapsed, and then the request receiving unit 31 The next data string Dc to be processed is read from the queue buffer and output to the external bus I / F 35 via the data length counter 33. Thereafter, the same processing as in the case of the processed data strings Da and Db is repeated.

  In this case, among the data processing paths including the functional modules A, B, and C, the external bus I / Fs 24 and 35, the arbitration unit 22, and the memory controller 23, the external bus I / Fs 24 and 35 that are the bottleneck of the throughput are Since the external bus I / F 35 is connected immediately after the processing request transmission unit 32 and does not receive the processing target data string to be processed from other than the processing request transmission unit 32, the external bus I / F 35 is not connected to the processing request transmission unit 32. Congestion does not occur due to the processed data string output from the component to the external bus I / F 35.

  In the priority setting register 221, the priority of the external bus I / F 24 is set higher than that of the CPU core 21, and the arbitration unit 22 receives an access request from the CPU core 21 to the memory 4 and the external bus. When the access request to the memory 4 from the I / F 24 conflicts, the access request to the memory 4 from the external bus I / F 24 is given priority, so that the processing request transmission unit 32 has the external bus I / Fs 24, 35, Access to the memory 4 from the CPU core 21 despite the interval of the processing time Td between the data strings to be processed so that congestion does not occur in the data processing path including the arbitration unit 22 and the memory controller 23 The possibility that congestion will occur due to the fact that the data string to be processed cannot be processed within the processing time Td due to the request is reduced.

  In addition, although the data processing part showed the example comprised from each processing part of external bus I / F24,35, the arbitration part 22, and the memory controller 23, as each processing part, external bus I / F24,35, The configuration is not limited to the arbitration unit 22 and the memory controller 23, and various components can be used.

1 Information processing device 2 Microprocessor 3 ASIC
4 Memory 5 Data Processing Unit 21 CPU Core 22 Arbitration Unit 23 Memory Controller 24, 35 External Bus I / F
30 Processing Request Transmission Circuit 31 Request Accepting Unit 32 Processing Request Transmitting Unit 33 Data Length Counting Unit 34 Processing Time Calculation Unit 221 Priority Setting Register A, B, C Functional Module Da, Db, Dc Processed Data Sequence Ld, Lda, Ldb , Ldc Data length Td Processing time

Claims (3)

An information processing apparatus comprising a processing request transmission circuit, a data processing unit, and an information processing unit that outputs an access request to the data processing unit,
The processing request transmission circuit includes:
A request accepting unit that accepts, in parallel, a plurality of data strings to be processed that request processing from a data processing unit that processes data;
A processing request transmission unit that performs arbitration between a plurality of requests by sequentially transmitting a plurality of processed data strings received by the request reception unit to the data processing unit,
A data length counter for counting the data length of the processed data string;
Td = a × Ld + b, where a and b are approximated by constant expressions, for the processing time Td required for the data processing unit to process the processed data string of the data length Ld counted by the data length counting unit. And a processing time calculation unit for calculating
The processing request transmitter
After the one processed data string is transmitted to the data processing unit, the one processed data string is counted by the data length counting unit until the next processed data string is transmitted to the data processing unit. An interval equal to or greater than the processing time calculated by the processing time calculation unit based on the data length,
The data processing unit is configured to execute the requested processing using a plurality of processing units connected in series, and as the plurality of processing units,
An interface circuit that transmits a data string to be processed output from the processing request transmission unit;
Memory,
A memory control unit for accessing the memory;
The access request from the information processing unit and the processed data string transmitted by the interface circuit are received, and the relationship between the received access request and the processed data string is arbitrated, in the order in which the arbitration is performed. And an arbitration unit that executes access to the memory by the memory control unit,
Among the plurality of processing units, the interface circuit is a processing unit that becomes a bottleneck of throughput,
The mediation unit
According to a preset priority, the relationship between the access request from the information processing unit and the data string to be processed is arbitrated,
Towards the processed data sequence has been transmitted by said interface circuit than the access request from the information processing unit, the priority is rather high,
The information processing apparatus according to claim 1, wherein the constants a and b are experimentally obtained by a least square method . The processing request transmission circuit further includes a data sequence generation unit that generates the processed data sequence and outputs the generated data sequence to the request reception unit,
The processing unit that is the bottleneck is connected immediately after the processing request transmission unit,
The information processing apparatus according to claim 1 , wherein the processing unit serving as the bottleneck receives the entire processing target data string to be processed from the processing request transmission unit. The data length counter is
One processed data string is provided on a path from the processing request transmission unit to the data processing unit, and the data length of the processed data string transmitted from the processing request transmission unit is counted. The information processing apparatus according to claim 1 or 2 .

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