JPH0654483B2 - Memory access method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an access method for a memory bus of a multi-port memory included in a communication processor.

Prior art When accessing the local memory of a communication processor,
In addition to the transmission and reception processing from the communication processor, there is access from the CPU, an external CPU, and the like, and the number of ports is increased. Therefore, it is necessary to arbitrate the memory bus for accessing the local memory. Therefore, FIG. 5 shows that the access to the local memory of the communication processor is prioritized (for example, JP-A-63-52255).

In FIG. 5, the local memory 4 is accessed from an external device connected to the CPU 3 and the system bus 200 via the communication processor 1, the bus arbiter 5 and the system bus I / F unit 2. When the communication processor 1 connected to the network 100 accesses the local memory 4 for transmitting and receiving data, the local memory is irrespective of access to the local memory 4 via the CPU 3 or the system bus I / F unit 2. Read and write to 4. When the CPU 3 accesses the local memory 4, the CPU 3 issues an access request to the local memory 4 to the bus arbiter 5. The bus arbiter 5 that has received the access request from the CPU 3 monitors the access status of the communication processor 1 to the local memory 4, and if there is a free space, notifies the CPU 3 of the access permission to the local memory 4. Upon receiving the notification from the bus arbiter 5, the CPU 3 accesses the local memory 4 via the bus arbiter 5. When the local memory 4 is accessed from an external device connected to the system bus 200 via the system bus 200, an access request to the local memory 4 is sent to the bus arbiter 5 via the system bus I / F unit 2. Show. System bus I / F section 2
When the bus arbiter 5 receives the access request to the local memory 4 from the communication processor 1 and the CPU 3 monitors the access status to the local memory 4, both of them do not use the local memory 4 and the memory bus becomes empty. , Notifies access permission to the system bus I / F unit. The system bus I / F unit 2 that has received the access permission from the bus arbiter 5 accesses the local memory 4 via the bus arbiter 5.

Thus, according to the conventional method, the communication processor, CP
U and arbitration for accessing the local memory from the system bus.

However, in such a conventional method, when the communication processor is accessing the local memory, the C
Since it is not possible to access the local memory via the PU and the system bus, those access requests are made to wait until the processing of the communication processor is completed,
There is a problem that the wait time of the local memory access of the CPU is increased and the actual performance of the CPU is degraded. In addition, when the CPU is accessing the local memory, the communication processor accesses the local memory by receiving data from the network, so that the CP
There is a problem that access data from U to the local memory may be lost.

In view of the above problems, the present invention improves the performance of the entire system by preventing the loss of data when the CPU accesses the local memory and reducing the wait time when the CPU accesses the local memory. It is an object of the present invention to provide a memory access method that enables the above.

Means for Solving the Problems The present invention relates to a communication processor in the arbitration of a local memory bus in accessing a local memory of a multi-port communication processor accessible from the outside through a CPU, a communication processor and a system bus. A time-division local memory bus is configured between local memories, and transmission / reception of a communication processor is performed in synchronization with each slot of the time-division local memory bus, access from a CPU and access from an external device, and a local memory from the CPU. Access to the local memory from the CPU is always activated, and if the next slot is an empty slot that is not accessed by the communication processor, the CPU access permission signal is activated to change the empty slot period. Synchronously C PU accesses local memory.

Further, the present invention makes the priority of access from the CPU to the local memory higher than the access to the local memory via the communication processor and the system bus, and when the access request from the CPU to the local memory is detected, the communication processor is detected. Even if there is a request to access the local memory via the system bus, the first slot of the time-division local memory bus is forcibly assigned to the CPU, and the CPU accesses the local memory in synchronization with the slot.

Effect of the Invention With the above configuration, the present invention prevents the loss of data in the access from the CPU to the local memory, and improves the performance of the entire system by reducing the wait time when the CPU accesses the local memory. It is possible to do.

Embodiments FIG. 1 and FIG. 2 are block diagrams of the first and second embodiments according to the memory access method of the present invention, and FIGS. 3 and 4 are state examples of a local memory bus in each embodiment. Show. The same elements as those in FIG. 5 are designated by the same reference numerals.

In FIG. 1, a transmission / reception control unit 10, a memory bus arbiter 20, a local memory I / F unit 30, and a CP
The communication processor 1 including the U access control unit 40, the system bus I / F unit 2 and the CPU 3 access the local memory 4. In the local memory I / F unit 40 in the communication processor 1, four time division local memory buses are configured by controlling the data width when accessing the local memory 4. When data is transmitted / received from the network 100, the transmission / reception control unit 10 in the communication processor 1
Sends to the memory bus arbiter 20 an access request to the local memory 4 for transmission and reception. The memory bus arbiter 20 synchronizes with the first two slots of the time division local memory bus and the local memory I / F unit 40.
To access the local memory 4 via. When accessing the local memory 4 from the CPU 3, the CPU access control unit 40 in the communication processor 1 always sends an access request from the CPU 3 to the memory bus arbiter 20. The memory bus arbiter 20, which has received the access request from the CPU access control unit 40, determines the position of the slot following transmission and reception by the CPU access control unit 40.
To notify. CPU access control unit 40 that received the notification
Generates and notifies a CPU access permission signal to the CPU 3. When the CPU access permission signal becomes active, the CPU 3 accesses the local memory 4 in synchronization with the corresponding slot. At this time, the system bus I /
Even if an access request to the local memory 4 is sent to the memory bus arbiter 20 in the communication processor via the F unit 2, it is kept waiting until the access from the CPU 3 to the local memory 4 is completed. In FIG. 3, the network 100, CPU 3,
If there is an access request from the system bus I / F section 2, the network 100 in synchronization with slot _T 11 60
Access regarding reception from is made.

At this time, the CP is requested due to the transmission request to the network 100.
The U access permission signal 70 is inactive. Access for transmission to the network 100 is made in synchronization with the slot T ₁₂ 61. The CPU access permission signal 70 becomes active because the reception and transmission processing is completed in this slot. As a result, the next slot T
₁₃ 62 in synchronization with the access to the local memory 4 from CPU3 made. Finally, the system bus I / F section 2
The local memory 4 is accessed via the.

In FIG. 2, a communication processor 1 including a transmission / reception control unit 10, a memory bus arbiter 20, a local memory I / F unit 30, and a CPU access request detection unit 50, and a system for receiving a request from a device connected to a system bus 200. The bus I / F unit 2 and the CPU 3 access the local memory 4. As described above, the local memory I
Four time division local memory buses are formed between the / F unit 30 and the local memory 4. When transmitting / receiving from the network 100, the transmission / reception control unit 10 in the communication processor 1 causes the memory bus arbiter 20 to store the local memory 4 in the memory bus arbiter 20.
Send an access request to. Upon receiving the access request from the transmission / reception control unit 10, the memory bus arbiter 20
The signal from the PU access request detection unit 50 is monitored, and the CP
When there is no access from U3 to the local memory 4, the first two slots of the four time division local memory buses configured by the local memory I / F unit 30 are set to the CPU3.
When the access request from the local memory 4 is detected, two slots are acquired from the other three slots except the first slot, and the local memory 4 is accessed through the local memory I / F unit 30 in synchronization with the two slots. I do. When accessing the local memory 4 from the CPU 3, the CPU 3
An access request to the local memory 4 is sent to the CPU access request detection unit 50. The CPU access request detection unit 50, which has detected the access request from the CPU 3,
The memory bus arbiter 20 is notified that the PU3 has requested access to the local memory 4. The memory bus arbiter 20 that has received the notification allocates the first slot of the four time-division local memory buses to the access from the CPU 3 even if there is a request to access the local memory 4 in the transmission / reception processing from the network 100. Based on that assignment, the CP is synchronized with the first slot
U3 accesses the local memory 4. In FIG. 4, CPU access request 81 and network 100
If receive requests 82 from
Slot T in the memory bus arbiter 20 of FIG.
₁₁ 60, assigned to the access from the CPU 3,
The CPU 3 synchronizes with the slot and the local memory 4
To access. The reception request is waited, the next slot T ₁₂ 61 is allocated, and the communication processor 1 accesses the local memory 4 in synchronization with it. In this example, slot T ₁₃ 62 and slot T ₁₄ 6
3 is an empty slot.

In this way, the transmission and reception processing from the network and the access from the system bus are surely performed at the same time as the access from the CPU to the local memory, data loss is prevented, and the wait time of the access from the CPU to the local memory is prevented. Can be reduced, so that the performance of the entire system can be improved.

As described above, according to the present invention, when the local memory of the communication processor is externally accessed via the CPU, the communication processor, and the system bus, the time sharing is performed between the communication processor and the local memory. If the local memory bus is configured to access the local memory from the CPU by transmitting / receiving the communication processor in synchronization with each slot of the time-divided local memory bus, performing access from the CPU and accessing from the external device, Always request access to local memory from
When the next slot is an empty slot that is not accessed by the communication processor or the outside, the CPU accesses the local memory in synchronization with the next empty slot period by activating the CPU access permission signal, or the CPU When the access request from the CPU to the local memory is made higher than the access to the local memory via the communication processor and the system bus, and the access request from the CPU to the local memory is detected, the access is sent via the communication processor or the system bus. Even if there is a request to access the local memory, the first slot of the time division local memory bus is forcibly assigned to the CPU, and the CPU accesses the local memory in synchronization with the assigned first slot. Access to local memory To prevent the loss of kicking data, also,
By reducing the wait time at the time of accessing the local memory of the CPU, it is possible to improve the performance of the entire system.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment according to the memory access system of the present invention, FIG. 2 is a block diagram of another embodiment of the memory access system of the present invention, and FIG.
FIG. 4 is a state example diagram of a memory bus in the embodiment shown in FIG.
FIG. 5 is a state diagram of the memory bus in the embodiment shown in FIG. 2, and FIG. 5 is a block diagram relating to the conventional memory access system. 1 ... communication processor, 2 ... system bus I / F section, 3
...... CPU, 4 ...... Local memory, 10 ...... Transmission / reception control unit, 20 ...... Memory bus arbiter, 30 ...... Local memory I / F unit, 40 ...... CPU access control unit, 50
...... CPU access request detection unit, 100 ...... Network, 200 ...... System bus.

Claims (2)

[Claims] 1. A arbitration of a local memory bus in accessing a local memory of a multi-port communication processor which is accessible from an external device through a CPU, a communication processor and a system bus, and the communication processor and the local memory. A time-divisional local memory bus is formed between them, and transmission / reception of the communication processor, access from the CPU, and access from the external device are performed in synchronization with each slot of the time-divisional local memory bus. Access to the local memory from the CPU always activates the access request from the CPU to the local memory, and activates the CPU access permission signal when the next slot is an empty slot which is not accessed from the communication processor. By doing Memory access method, wherein the CPU in synchronization with the vacant slot period to access the local memory. 2. In the arbitration of a local memory bus in accessing a multiport local memory accessible from an external device via a CPU, a communication processor and a system bus, time division is performed between the communication processor and the local memory. Of the local memory bus, the transmission / reception of the communication processor, the access from the CPU, and the access from the external device are performed in synchronization with each slot of the time-divided local memory bus. The access to the local memory from the CPU has a higher priority than the access to the local memory via the communication processor and the system bus,
When an access request from the CPU to the local memory is detected, the first slot of the time division local memory bus is forced even if there is an access request to the local memory via the communication processor or the system bus. A memory access method in which the CPU accesses the local memory in synchronization with the first slot.