JP5479537B2 - Game machine - Google Patents

Description

  The present invention includes variable display means capable of variably displaying a plurality of types of identification information that can identify each of the identification information. After a predetermined variable display execution condition is satisfied, the variable display start condition is satisfied. The present invention relates to a gaming machine such as a pachinko gaming machine that starts variable display of identification information and shifts to a specific gaming state advantageous to the player when the display result of variable display of identification information becomes a specific display result.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are paid out to the player. There is something to be done. Furthermore, there is provided a variable display unit capable of changing the display state, and configured to give a predetermined game value to the player when the display result of the variable display unit is in a predetermined specific display mode. is there.

  The game value is the right that the state of the variable winning ball apparatus provided in the gaming area of the gaming machine becomes advantageous for a player who is easy to win, and the right for becoming advantageous for a player. In other words, or a condition for winning a prize ball is easily established.

  In the gaming machine, when a predetermined transition condition is established, the gaming state is shifted to a specific gaming state that is advantageous to the player. For example, in a pachinko gaming machine, a combination of a specific display mode in which a display result of a variable display unit that displays a special symbol is a predetermined combination is generally referred to as “big hit”. When the big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the game shifts to a big hit gaming state where the hit ball is easy to win.

  Game progress in the gaming machine is controlled by game control means such as a microcomputer. When a game value such as a specific game state is given, it is easy for a player to obtain a prize. For this reason, an act of illegally obtaining a game value may occur. As such an action, for example, there is an action of modifying a game control program executed by a microcomputer so that a “hit” is likely to occur. It is also conceivable that the payout control program is modified so that the prize game medium is paid out even though the prize game medium payout condition is not satisfied. In order to prevent game control and the like from being executed by a modified illegal program, a microcomputer generally has a security check function for determining whether or not the program is valid. The microcomputer is configured not to execute the game control program or the like if the security check function determines that the program is not valid.

  However, an illegal act such as removing a regular microcomputer with a built-in program and installing a microcomputer with a built-in fraudulent program that is likely to cause a big hit is conceivable. In a microcomputer incorporating such a malicious program, the security check function does not exist, or even if it exists, it is modified so that the malicious program is determined as a legitimate program. Therefore, there is a possibility that a game due to an unauthorized program cannot be prevented only by the security check function.

  There is a gaming machine that authenticates whether it is a regular microcomputer and determines whether the microcomputer is different from a regular microcomputer such as a microcomputer with a built-in illegal program (for example, see Patent Document 1). .

JP 2004-33453 A

  However, in addition to a regular board on which a regular microcomputer with a built-in program is mounted, a fraudulent circuit board (spoofed board) with a microcomputer with a built-in fraudulent program that is likely to cause a big hit like a regular board When a fraudulent act such as wiring and installing is performed, since a legitimate board is mounted, in the gaming machine described in Patent Document 1, the game is progressed by a microcomputer incorporating a fraudulent program I can't detect what I'm doing.

  Therefore, an object of the present invention is to make it possible to easily find that an unauthorized circuit board is installed in a gaming machine.

Gaming machine according to the present invention performs Yu technique using a game medium (e.g., game balls), when a specific condition is satisfied (e.g., when determined to be a big hit) favorable specific game state for the player (E.g., a big hit gaming state) that is controlled by a payout control board and a payout control microcomputer equipped with a payout control microcomputer that executes payout control processing for paying out game media. , and a state informing means for performing recognizable notifying the status, the payout control microcomputer, includes a state notification control means for controlling the notification manner of state informing means, the state notification control means, depending on the state with different notification manner of state informing means Te, dispensing control board is accommodated in the opening incapable sealed the substrate box, state informing unit, the substrate box Characterized in that it is housed in.

  The state notification control unit changes the notification mode of the state notification unit when the gaming state is the specific gaming state (for example, the fast flashing shown in FIG. 42C) in the state other than the specific gaming state (for example, FIG. It is preferable to make it different from the blinking continued shown in FIG. 42 (A) and the slow blinking shown in FIG. 42 (B) (see FIG. 43).

  A variable display means (for example, a special symbol display 8 or a variable display device 9) capable of variably displaying a plurality of types of identification information (for example, special symbols and decorative symbols) that can identify each of them is provided, and a predetermined variable is provided. After a display execution condition (for example, winning a game ball to the start winning opening 14) is established, variable display means based on establishment of a variable display start condition (for example, final stop of special symbol and end of jackpot game) The identification information variable display is started, and the specific gaming state (for example, jackpot gaming state) advantageous to the player when the display result of the variable identification information display becomes a specific display result (for example, jackpot symbol). The gaming control microcomputer causes the variable display means to start variable display of the identification information based on the establishment of the variable display start condition, and Even if it is configured to include variable display control means (for example, a part for executing the processing of steps S301 to S303 in the game control microcomputer 560) that performs control to stop the variable display of the identification information when the display time has elapsed. Good.

  The state notification control means variably displays the notification mode of the state notification means (for example, the slow blinking shown in FIG. 42B) when the gaming state is a variable display state in which the variable display of the identification information is performed. It is preferable to make it different from the notification mode in a state other than the middle state (for example, the blinking continuation shown in FIG. 42A and the high-speed blinking shown in FIG. 42C) (see FIG. 43).

  The state notification control means is a notification state of the state notification means when the gaming state is a state in which the variable display of the identification information is not performed and is not a specific gaming state (for example, FIG. 42A). It is preferable that the flashing continuation shown in FIG. 4 be different from the notification mode (for example, slow flashing shown in FIG. 42B and high-speed flashing shown in FIG. 42C) in a state other than the normal state (see FIG. 43).

  The state notification control means sets a period during which the notification by the state notification means is not performed to a predetermined time or less in a state where power is supplied to the payout control board (for example, a period when the light is turned off is set to 5 seconds or less). Is preferred.

In the present invention, is controlled by the payout controlling microcomputer, includes a state notification means for performing a recognizable notifying the status, state informing control means in the payout control microcomputer is informed of the state notification means in accordance with the state is configured so as to vary the aspect, by detecting that the notification manner of a state notification control means is different from the embodiment of normal according to the state, it is possible to discover unauthorized substrate easily. In addition, forgery of the state notification means, or an illegal act to the state notification means (for example, an act of providing a spoofing board and not causing the payout control board to perform payout control and causing the state notification means to execute a normal notification mode) ) Can be prevented.

  The state notification control means is configured to make the notification mode of the state notification means when the gaming state is the specific gaming state different from the notification mode in the state other than the specific gaming state, so that the specific gaming state is determined at the time of inspection. By generating and confirming whether or not the notification mode of the state notification control means is a notification mode according to the specific gaming state, it is possible to easily find the illegal board.

  When the display result of the variable display of the identification information becomes the specific display result, the game control microcomputer shifts to a specific game state advantageous to the player, and the game control microcomputer performs variable display means based on the establishment of the variable display start condition Display of variable display of the identification information by including variable display control means for starting the variable display of the identification information and stopping the variable display of the identification information when a predetermined variable display time elapses. An illegal board can be easily found in a gaming machine that shifts to a specific gaming state advantageous to the player when the result is a specific display result.

  The state notification control means is configured to make the notification mode of the state notification means when the gaming state is a variable display state in which the variable display of the identification information is performed different from the notification mode in a state other than the variable display state. By configuring, the execution condition of variable display is established at the time of inspection, and it is possible to easily make an illegal substrate by checking whether the notification mode of the state notification control means is a notification mode according to the variable display state. Can be found.

  When the state notification control means is a normal state in which the game state is a state in which the variable display of the identification information is not performed and is not a specific gaming state, the state notification means is in a state other than the normal state. By being configured to be different from the notification mode, the execution condition of variable display is established at the time of inspection, and variable information is displayed, and the notification mode of the state notification control unit is changed from the notification mode according to the normal state. By confirming whether or not, the illegal substrate can be easily found.

  When the state notification control means is in a state where electric power is supplied to the payout control board, the period during which the state notification means is not notified is set to a predetermined time or less, thereby supplying power to the gaming machine. By starting and confirming whether or not the state notification control means exhibits any notification mode, it is possible to easily find the illegal substrate.

It is the front view which looked at the pachinko game machine from the front. It is a front view which shows the front surface of the game board in the state which removed the glass door frame. It is the rear view which looked at the gaming machine from the back. It is a block diagram which shows the structural example of a game control board (main board). It is a block diagram showing a circuit configuration of the main board and a signal line of an effect control command transmitted from the main board to the effect control board. It is a block diagram which shows the structural example of a random number circuit. It is explanatory drawing which shows the example of an update rule selection register. It is explanatory drawing which shows the example of an update rule memory. It is explanatory drawing which shows the example in case a count value permutation change circuit changes the permutation of the count value which a counter outputs. It is explanatory drawing which shows the example of a count value permutation change register. It is explanatory drawing which shows the example of a random number maximum value setting register. It is explanatory drawing which shows the example of a period setting register. It is explanatory drawing which shows the example of a count value update register. It is explanatory drawing which shows the example of a random value taking-in register. It is explanatory drawing of an example of the random number update system selection register and the random number update system selection data written in the random number update system selection register. It is explanatory drawing which shows the example of a random number circuit starting register. It is a circuit diagram which shows one structural example of a random value memory circuit. It is a timing chart which shows the timing when each signal is input into a random value storage circuit, and the timing when a random value storage circuit outputs each signal. It is explanatory drawing which shows an example of the address map of the storage area in the microcomputer for game control. It is explanatory drawing which shows an example of the address map in a user program management area. It is explanatory drawing which shows an example of initial value change system setting data. It is explanatory drawing which shows the structural example of a user program. It is explanatory drawing which shows the structural example of a random number circuit setting program. It is explanatory drawing which shows the operation | movement which updates the value of random R, or reads the value of random R, when the 1st random number update system is selected. It is explanatory drawing which shows the operation | movement which updates the value of random R, or reads the value of random R, when the 2nd random number update system is selected. It is explanatory drawing which shows each memory with which the microcomputer for game control is provided. It is explanatory drawing which shows the example of the table memory for jackpot determination. It is a block diagram which shows the example of the state by which the impersonation board | substrate was installed in the gaming machine. It is a front view which simplifies and shows a game control board box. It is explanatory drawing which shows the example of the mounting state of an interruption button. It is a flowchart which shows the main process which the microcomputer for game control performs. It is a flowchart which shows the main process which the microcomputer for game control performs. It is a flowchart which shows a random circuit setting process. It is a flowchart which shows a random number maximum value reset process. It is a flowchart which shows an initial value change process. It is a timing chart which shows the timing when each signal is input into a random number circuit, and the timing when each signal is generated in a random number circuit. It is a flowchart which shows a timer interruption process. It is a flowchart which shows an initial value update process. It is a flowchart which shows a count value permutation change process. It is a flowchart which shows an example of a special symbol process process. It is a flowchart which shows a starting port switch passage process. It is explanatory drawing which shows the relationship between the lighting state of state alert LED and a game state. It is a flowchart which shows an example of a status alert | report LED control process. It is a block diagram which shows the structural example of a game control board (main board). It is explanatory drawing which shows an example of the content of the payout control signal. It is a block diagram which shows the signal line etc. which are used for transmission / reception of a payout control signal. It is a timing diagram which shows an example of how to output a payout control signal. It is a flowchart which shows a prize ball process. It is explanatory drawing which shows the structural example of a prize ball number table. It is a flowchart which shows a prize ball number addition process. It is a flowchart which shows a prize ball control process. It is a flowchart which shows a standby process. It is a flowchart which shows payout number signal transmission processing. It is a flowchart which shows a reception confirmation signal ON waiting process. It is a flowchart which shows a reception confirmation signal OFF waiting process. It is a flowchart which shows a payout operation signal on waiting process. It is a flowchart which shows the signal off waiting process during payout operation. It is a timing diagram which shows an example of how to output a payout control signal. It is a flowchart which shows the main process which the microcomputer for payout control performs. It is a flowchart which shows the timer interruption process which the microcomputer for payout control performs. It is a flowchart which shows a payout motor control process. It is a flowchart which shows a main control communication process. It is a flowchart which shows a standby process. It is a flowchart which shows payout REQ signal OFF waiting processing. It is a flowchart which shows payout operation start waiting processing. It is a flowchart which shows the process during payout operation. It is a flowchart which shows payout number signal OFF waiting processing. It is a flowchart which shows a prize ball lending control process. It is a flowchart which shows the payout start waiting process. It is a flowchart which shows a payout motor stop waiting process. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows payout passage waiting processing. It is a block diagram which shows the other structural example of a random number circuit. It is a block diagram which shows the structure of the main board | substrate in 4th Embodiment. It is a flowchart which shows a part of main process which the microcomputer for game control in 4th Embodiment performs. It is a flowchart which shows the main process which the microcomputer for production control performs. It is explanatory drawing which shows the structure of a command reception buffer. It is a flowchart which shows a command analysis process. It is the front view which looked at the slot machine from the front.

Embodiment 1 FIG.
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front, and FIG. 2 is a front view showing the front of the game board. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and can be applied to other gaming machines such as a slot machine.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding a game board described later). Is a structure including

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hit ball supply tray 3 and a hitting operation handle (operation knob) 5 for launching the game balls are provided. A game board 6 is detachably attached to a position corresponding to the back surface of the glass door frame 2 of the outer frame. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  Near the center of the game area 7, there is provided a variable display device (decorative symbol display device) 9 including a plurality of variable display portions each variably displaying an effect decorative symbol. The variable display device 9 has, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. The variable display device 9 performs variable display of a decorative symbol as a symbol for decoration (production) during the variable symbol display period of the special symbol by the special symbol indicator 8. The variable display device 9 that performs variable display of decorative symbols is controlled by an effect control microcomputer mounted on the effect control board.

  At the bottom of the variable display device 9, four special symbol hold memory indicators 18 for displaying the number of valid winning balls that have entered the start winning opening 14, that is, the number of hold memories (also referred to as start memory or start prize memory), are provided. ing. The special symbol reservation storage display 18 displays up to four reservation storage numbers in the order of winning. The special symbol hold storage display 18 increases the number of LEDs in the lit state by 1 each time there is a start winning in the start winning opening 14. Then, each time the special symbol display 8 starts variable display, the special symbol hold storage indicator 18 reduces the number of LEDs in the lit state by 1 (that is, turns off one LED). Specifically, the special symbol hold storage display 18 shifts the lighting state each time variable display is started on the special symbol display 8. In this example, the upper limit number (up to 4) is provided for the number of starting memories by winning to the start winning opening 14, but the upper limit number may be four or more.

  A special symbol display (special symbol display device) 8 that variably displays a special symbol as identification information is provided on the variable display device 9. In this embodiment, the special symbol display 8 is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9, for example. The special symbol display 8 may be configured to variably display a larger number of numbers such as 0 to 99 in order to make it difficult for the player to grasp a specific stop symbol. In addition, the variable display device 9 performs variable display of a decorative symbol as a symbol for decoration (for production) during the variable symbol display period of the special symbol by the special symbol indicator 8. The special symbol variable display and the decorative symbol variable display are synchronized (the variable display start time and the variable display end time are the same).

  Below the variable display device 9 is provided a variable winning ball device 15 that forms a start winning opening 14. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 14a. The variable winning ball device 15 is opened by a solenoid 16.

  Below the variable winning ball apparatus 15, a special variable winning ball apparatus 20 (large winning opening) that is opened by a solenoid 21 in a specific gaming state (big hit gaming state) is provided. The special variable winning ball device 20 has an opening / closing plate, and the special variable winning ball device 20 is opened when the opening / closing plate is controlled to be opened. The winning ball that has won the special variable winning ball device 20 is detected by the count switch 23.

  When the game ball passes through the gate 32 and is detected by the gate switch 32a, variable display of the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting left and right lamps (designs can be visually recognized when lit). For example, if the left lamp is lit at the end of variable display, it is a hit. When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In the vicinity of the normal symbol display 10, a normal symbol start memory display 41 having a display unit with four LEDs for displaying the number of winning balls that have passed through the gate 32 is provided. Each time there is a game ball passing through the gate 32, the normal symbol start memory display 41 increases the number of LEDs to be turned on by one. Each time the variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one.

  The game board 6 is provided with a plurality of winning holes 29, 30, 33, 39, and winning of game balls to the winning holes 29, 30, 33, 39 is performed by winning hole switches 29a, 30a, 33a, 39a, respectively. Detected. Each winning opening 29, 30, 33, 39 constitutes a winning area provided in the game board 6 as an area for accepting game media and allowing winning. The start winning opening 14 and the big winning opening also constitute a winning area that accepts game media and allows winning. Around the left and right of the game area 7, there are provided decorative lamps 25 blinking and displayed during the game, and at the lower part there is an outlet 26 for absorbing a game ball that has not won a prize. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided. Further, a decoration LED is installed around each structure (such as a big prize opening) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decoration LED are examples of a decorative light emitter provided in the gaming machine.

  In this example, a prize ball lamp 51 that is lit during award ball payout is provided in the vicinity of the left frame lamp 28b, and a ball break lamp 52 that is lit when the supply ball is cut in the vicinity of the top frame lamp 28a. Is provided. Further, a prepaid card unit (hereinafter referred to as “card unit”) 50 that enables lending a ball by inserting a prepaid card is installed adjacent to the pachinko gaming machine 1.

  The card unit 50 includes, for example, a usable display lamp that indicates whether or not the card unit 50 is in a usable state, a connection table direction indicator that indicates which side of the pachinko gaming machine 1 corresponds to the card unit, and a card unit. When checking the card insertion indicator lamp indicating that a card is inserted in the card, the card insertion slot into which the card as a recording medium is inserted, and the card reader / writer mechanism provided on the back of the card insertion slot A card unit lock for releasing the card unit is provided.

  A game ball launched from the ball striking device by the player's operation enters the game area 7 through the hit ball rail, and then descends the game area 7. When the game ball enters the start winning port 14 and is detected by the start port switch 14a, the special symbol on the special symbol display unit 8 starts variable display (variation) and is variable if the variable symbol display can be started. The decorative design on the display device 9 starts variable display (variation). If the variable display of the symbol cannot be started, the number of reserved memories is increased by one.

  The variable display of the special symbol on the special symbol display 8 and the variable display of the decorative symbol on the variable display device 9 are stopped when a certain time has passed. If the special symbol (stop symbol) at the time of stoppage is a jackpot symbol (specific display result), the game shifts to a jackpot gaming state. That is, the special variable winning ball apparatus 20 is released until a predetermined time elapses or a predetermined number (for example, 10) of gaming balls wins. The opening of the special variable winning ball apparatus 20 is allowed a predetermined number of times (for example, 15 rounds).

  When the special symbol on the special symbol display 8 at the time of stoppage is a jackpot symbol (probability variation symbol) with a probability variation, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in the probability variation state.

  When the game ball wins the gate 32, the normal symbol display unit 10 is in a state where the normal symbol is variably displayed. When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the probability variation state, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased. Further, in the short time state (the game state in which the variable symbol display time for special symbols is shortened), the opening time and the number of opening times of the variable winning ball device 15 may be increased.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. FIG. 3 is a rear view of the gaming machine as seen from the back side.

  As shown in FIG. 3, on the back side of the gaming machine, a variable display control unit 49 including an effect control board 80 on which an effect control microcomputer for controlling the variable display device 9 is mounted, a game control microcomputer and the like are mounted. A game control board (main board) 31 is installed. In addition, a payout control board 37 on which a payout control microcomputer for performing ball payout control is mounted is installed. The production control microcomputer controls the variable display device 9 provided on the game board 6, and various decoration LEDs, a decoration lamp 25, a top frame lamp 28a, a left frame lamp 28b provided on the frame side, and The lighting of the right frame lamp 28c is controlled, and the sound generation from the speaker 27 is controlled. A board on which a microcomputer other than the main board 31 is mounted may be referred to as an electric component control board or a sub board.

  Further, a power supply substrate 910 and a touch sensor substrate 91 on which a power supply circuit for generating DC30V, DC21V, DC12V, and DC5V is mounted are provided.

  On the back side of the gaming machine, a terminal board 160 provided with terminals for outputting various information to the outside of the gaming machine is installed above. Further, an information terminal board (information output board) 36 having terminals for outputting various information from the main board 31 to the outside of the gaming machine is installed near the center.

  The game balls stored in the storage tank 38 pass through the guide rails, and reach the ball payout device covered with the payout case 40A through the curve cage. A ball break switch 187 as a game medium break detection means is provided on the upper part of the ball payout device. When the ball break switch 187 detects a ball break, the dispensing operation of the ball dispensing device stops. The ball break switch 187 is a switch for detecting the presence or absence of a game ball in the game ball passage, but the ball break detection switch for detecting the shortage of supply balls in the storage tank 38 is also an upstream portion of the guide rail (close to the storage tank 38). Part). When the shortage of balls detection switch detects a shortage of game balls, the game balls are replenished from the replenishment mechanism provided on the gaming machine installation island.

  When a large number of game balls as prizes based on winning a prize and game balls based on a ball lending request are paid out and the hitting ball supply tray 3 is full, the game balls are guided to the surplus ball receiving tray 4 through the surplus ball passage. When the game ball is further paid out, a sensing lever (not shown) presses a full tank switch (not shown) as a storage state detection means, and the full tank switch as a storage state detection means is turned on. In this state, the rotation of the payout motor in the ball payout device is stopped, the operation of the ball payout device is stopped, and the driving of the ball hitting device is also stopped.

  FIG. 4 is a block diagram illustrating an example of a circuit configuration in the main board 31. 4 also shows a payout control board 37, a lamp driver board 35, an audio output board 70, an interface board 66, a relay board 77, and an effect control board 80 mounted on the gaming machine. In this embodiment, the effect control means (configured by the effect control microcomputer) mounted on the effect control board 80 receives the effect control command from the game control microcomputer 560 via the relay board 77. The display control and the like of the variable display device 9 that receives and variably displays decorative symbols are performed.

  A game control microcomputer (corresponding to game control means) 560 for controlling the pachinko gaming machine 1 according to a program is mounted on the main board 31. The game control microcomputer 560 includes a ROM 54 for storing a game control (game progress control) program and the like, a RAM 55 as storage means used as a work memory, a CPU 56 for performing control operations in accordance with the program, and an I / O port unit 57. including. In this embodiment, the ROM 54 and the RAM 55 are built in the game control microcomputer 560. That is, the game control microcomputer 560 is a one-chip microcomputer. The one-chip microcomputer only needs to incorporate at least the CPU 56 and the RAM 55, and the ROM 54 may be external or built-in. The I / O port unit 57 may be externally attached. The game control microcomputer 560 further includes a random number circuit 503 that generates hardware random numbers (random numbers generated by the hardware circuit).

  In the game control microcomputer 560, the CPU 56 executes control in accordance with the program stored in the ROM 54, so that the game control microcomputer 560 (or CPU 56) executes (or performs processing) hereinafter. Specifically, the CPU 56 executes control according to a program. The same applies to microcomputers mounted on substrates other than the main substrate 31.

  Further, the main board 31 includes an input driver circuit 58 for supplying a signal from the gate switch 32a, the start port switch 14a, the count switch 23, the winning port switches 29a, 30a, 33a and 39a to the basic circuit 53, and a variable winning ball apparatus. An output circuit 59 for driving the solenoid 16 for opening / closing 15 and the solenoid 21 for opening / closing the special variable winning ball apparatus 20 according to a command from the game control microcomputer 560, and a game control microcomputer 560 in accordance with an operation by a game clerk or the like. And an interruption button 361 for interrupting the game control process. The interrupt button 361 outputs a game control process interrupt signal to the game control microcomputer 560 in response to being pressed.

  The main board 31 is also provided with an LED circuit 60 that provides a drive signal to the state notification LED 61 for notifying the gaming state of the gaming machine in accordance with the control of the gaming control microcomputer 560. In this embodiment, the state notification LED 61 is provided on the main board 31. In this embodiment, the state notification LED 61 is used as a light emitter for state notification, but a light emitter other than the LED may be used. The number of light emitters is not limited to one, and a plurality of light emitters may be used for notification. Further, notification may be made by a dot matrix display, a 7-segment display, a liquid crystal display, an EL, or the like. Moreover, you may use alerting means (for example, a speaker, a buzzer, etc.) other than a light-emitting body.

  Further, in this embodiment, “lighting” and “blinking” are illustrated as different notification modes, but the different notification modes are not limited thereto. For example, the notification modes may be different by changing colors using full-color LEDs or the like. You may make it let.

  Note that the switches such as the gate switch 32a, the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a may be referred to as sensors. That is, the name of the game medium detection means is not limited as long as it is a game medium detection means (game ball detection means in this example) that can detect a game ball. Each of the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a that perform winning detection is also a winning detection means that detects the winning of a game ball in the winning area.

  The game control microcomputer 560 transmits and receives various data to and from the microcomputer mounted on each board (the payout control board 37 and the effect control board 80). In this embodiment, expressions such as “the microcomputer transmits and receives” are used. Specifically, for example, when data transmission is performed, the CPU sets data in the transmission data register of the serial communication circuit, and The serial communication circuit transmits the data set in the transmission data register. In addition, the CPU transmits data via the I / O port unit. For example, when data reception is performed, the reception data is written into the reception data register of the serial communication circuit, and the CPU reads the reception data from the reception data register. In addition, the CPU receives data via the I / O port unit.

  In this embodiment, the case where the game control microcomputer 560 performs serial communication with the payout control microcomputer 370 mounted on the payout control board 37 will be described.

  The RAM 55 is a backup RAM as a non-volatile storage means, part or all of which is backed up by a backup power source created on the power supply substrate 910. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 is stored for a predetermined period (until the capacitor as the backup power supply is discharged and the backup power supply cannot be supplied). In this embodiment, it is assumed that the entire RAM 55 is backed up.

  Further, a power-off signal indicating that the power supply voltage from the power supply board 910 has decreased to a predetermined value or less is input to the input port of the game control microcomputer 560. In addition, a clear signal indicating that the clear switch for instructing to clear the contents of the RAM is operated is input to the input port.

  As shown in FIG. 4, a collator 365 can be connected to the main board 31. The collator 365 determines whether or not the main board 31 is a legitimate board based on a board ID uniquely assigned to the main board 31 (for example, an ID number unique to the game control microcomputer 560). This is a device that displays the determination result. In the ROM 54 provided in the main board 31, a board ID uniquely assigned to the main board 31 itself is registered. The collator 365 stores in advance a board ID uniquely assigned to the main board 31. The collator 365 collates the board ID sent from the main board 31 via the collation terminal 354 (see FIG. 5) and the board ID of the main board 31 stored by itself, and if they match, the collation is OK. The lamp on the side is turned on, and the lamp on the verification NG side is turned on if they do not match.

  FIG. 5 is a block diagram showing a circuit configuration of the main board 31 and signal lines of an effect control command transmitted from the main board 31 to the effect control board 80. As shown in FIG. 5, in this embodiment, the game control microcomputer 560 mounted on the main board 31 produces an effect control command using eight signal lines CD0 to CD7 for transmitting the effect control signal. Transmit to the control board 80. In addition, a signal line of an effect control INT signal for transmitting and receiving a strobe signal is also wired between the main board 31 and the effect control board 80.

  FIG. 5 shows a start port switch 14a among various switches for detecting a winning of the game ball shown in FIG. Also shown are a solenoid 16 for opening and closing the variable winning ball apparatus 15 and a solenoid 21 for opening and closing the special variable winning ball apparatus 20.

  FIG. 5 shows that a verification terminal 364 is provided on the main board 31. FIG. 5 shows a more detailed configuration of the game control microcomputer 560. The game control microcomputer 560 operates in accordance with a clock circuit 501, a reset controller 502 that functions as system reset means, random number circuits 503a and 503b, a ROM 54 that stores a game control program, a RAM 55 that is used as a work memory, and a program. CPU 56, CPU 56 for sending an interrupt request signal (interrupt request signal by timer interrupt) to CPU 56, and I / O port unit 57 are incorporated.

The clock circuit 501 outputs a reference clock signal CLK having a predetermined period generated by dividing the system clock signal by 2 ⁷ (= 128) to the random number circuits 503a and 503b. When a low level signal is input for a predetermined period, the reset controller 502 outputs a predetermined initialization signal to the CPU 56 and the random number circuits 503a and 503b to reset the game control microcomputer 560. The random number circuits 503a and 503b are part of the random number circuit 503 shown in FIG.

  Further, in this embodiment, as shown in FIG. 5, the game control microcomputer 560 is equipped with two random number circuits 503a and 503b having different ranges of random value values that can be generated. The random number circuit 503a is a random number circuit (hereinafter also referred to as a 12-bit random number circuit) that generates a 12-bit pseudo-random number. The 12-bit random number circuit 503a has a function of generating a random number having a value within a range that can be generated by 12 bits (that is, a range from 0 to 4095). The random number circuit 503b is a random number circuit (hereinafter also referred to as a 16-bit random number circuit) that generates a 16-bit pseudo-random number. The 16-bit random number circuit 503b has a function of generating a random number having a value in a range that can be generated in 16 bits (that is, a range from 0 to 65535). In this embodiment, the case where the game control microcomputer 560 includes two random number circuits is described. However, the game control microcomputer 560 may include three or more random number circuits. In this embodiment, when the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are comprehensively expressed, or when indicating either the 12-bit random number circuit 503a or the 16-bit random number circuit 503b, This is called a random number circuit 503.

  Next, the configuration of the random number circuit 503 will be described. FIG. 6 is a block diagram illustrating a configuration example of the random number circuit 503. In this embodiment, the basic configurations of the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are the same. As shown in FIG. 6, the random number circuit 503 includes a counter 521, a comparator 522, a count value permutation changing circuit 523, a clock signal output circuit 524, a count value update signal output circuit 525, a random value read signal output circuit 526, and a random number update. A system selection signal output circuit 527, a selector 528, a random number circuit activation signal output circuit 530, a random value storage circuit 531, an inversion circuit 532, a latch signal generation circuit 533, and a timer circuit 534 are included.

  In this embodiment, the random number circuit 503 determines whether or not the display result of variable display of a plurality of types of identification information is a specific display result (for example, the combination of display symbols of the special symbol display device 8 is a combination of jackpot symbols) A random number for jackpot determination is generated. When the CPU 56 of the game control microcomputer 560 determines that the specific display result is based on the random number generated by the random number circuit 503, the game state is changed to a specific game state advantageous to the player (for example, a big hit game state). Transition. In this embodiment, the random numbers for determination other than the jackpot determination, such as the random number for determining the probability change for determining whether or not to change the probability, the random number for determining the special symbol for determining the special symbol (big hit symbol), etc. As described later, software random numbers (random numbers generated by the CPU 56 operating according to a random number generating program) are used.

  The counter 521 receives a predetermined signal selected by the selector 528 and outputs a count value C in response to the signal input from the selector 528. In this case, the counter 521 inputs a predetermined initial value, and cyclically updates the count value C from the initial value to a predetermined final value according to a certain rule, and outputs it. Further, when the count value C is updated to the final value, the counter 521 outputs a notification signal indicating that the count value C has been updated to the final value to the CPU 56. In this embodiment, when a notification signal is output from the counter 521, the CPU 56 updates the initial value.

  In this embodiment, every time a signal is input from the selector 528 (every time a rising edge in the signal from the selector 528 is input), the counter 521 increments the count value C from “0” to “4095” by one. Count up. Further, when the counter 521 counts up the count value C to “4095”, the counter 521 outputs a notification signal indicating that the count value C has been updated to the final value to the CPU 56. Then, the CPU 56 inputs a notification signal from the counter 521 and updates the initial value. Then, the counter 521 counts up the count value C again from the initial value updated by the CPU 56 to “4095”. Further, when counting up to “4095”, the counter 521 starts counting from “0” again. Then, the counter 521 outputs a notification signal to the CPU 56 when it counts up to a value (final value) immediately before the updated initial value. In this embodiment, the comparator 522 outputs a notification signal to the counter 521 when all the count values are input, as will be described later. In this case, when the notification signal is input from the comparator 522, the counter 521 resets the count value to “0”.

  The comparator 522 determines whether the input count value is larger than the random number maximum value set in the random number maximum value setting register 535, and the count value is larger than the random number maximum value (exceeded the random number maximum value). ), A notification signal may be output to the counter 521. In this case, for example, when the comparator 522 determines that the count value exceeds the random number maximum value, the notification signal is output to the counter 521 before the clock signal output circuit 524 next outputs the random number generation clock signal SI1. . For example, consider a case where the random number maximum value “256” is set in the random number maximum value setting register 535. In this case, when the counter 521 counts up from “0” to “256” and further outputs the count value “257”, the comparator 522 determines that the input count value “257” exceeds the random number maximum value “256”. Determine and output a notification signal to the counter 521. When the notification signal is input from the comparator 522, the counter 521 updates the count value to “258” and outputs it without waiting for the input of the random number generation clock signal SI1 from the clock signal output circuit 524. By repeatedly executing the above processing, the comparator 522 determines that the count value exceeds the random number maximum value while inputting from the count value “257” to “4095”. Output a notification signal. The counter 521 repeatedly updates and outputs the count value without waiting for the input of the random number generation clock signal SI1 from the clock signal output circuit 524 while the notification signal is input from the comparator 522. By doing so, until the clock signal output circuit 524 next outputs the random number generation clock signal SI1, the count value is controlled to be counted up from “257” to “4095” at a high speed, Control is performed so that random numbers from “257” to “4095” are skipped (not stored in the random value storage circuit 531).

  The count value permutation change circuit 523 includes a count value permutation change register (RSC) 536, an update rule selection register (RRC) 542, and an update rule memory 543. The count value permutation change register 536 count data permutation change data “01 (H)” for changing the permutation (order of arrangement from the initial value to the final value), which is the update order of the count value C counted up by the counter 521. Is stored. Note that (H) indicates a hexadecimal number. When the numerical value permutation change data “01 (H)” is stored in the count value permutation change register 536, the count value permutation change circuit 523 counts the permutation of the count value C that the counter 521 counts up and updates. The permutation change data “01 (H)” is changed to a permutation different from that when the permutation change data “01 (H)” is not stored. In this case, the count value permutation change circuit 523 switches the update rule used to change the permutation of the count values when the numerical permutation change data “01 (H)” is stored. When the counter 521 starts updating the count value after switching the update rule used to change the count value permutation, the count value permutation change data in the count value permutation change register 536 is “01 (H)” by the CPU 56. ”To the initial value“ 0 (= 00 (H)) ”(cleared).

  Instead of clearing the count value permutation change data by the CPU 56, the random number circuit 503 may clear the count value permutation change data. For example, when the register value is set in the update rule selection register (RRC) 542 based on the count value permutation change data “01 (H)” written in the count value permutation change register 536, the count value permutation change The circuit 523 may clear the register value of the count value permutation change register 536.

  FIG. 7 is an explanatory diagram illustrating an example of the update rule selection register 542. The update rule selection register 542 is a register that sets an update rule used for rearranging the order of count values output from the counter 521 (changing the permutation). In this embodiment, an update rule used for changing the permutation of count values output from the counter 521 is set by setting a register value in the update rule selection register 542. As shown in FIG. 7, the update rule selection register 542 is an 8-bit register, and the initial value is set to “0 (= 00 (H))”. The update rule selection register 542 is configured in a state where bits 0 to 3 can be written and read. In addition, the update rule selection register 542 is configured in a state where bits 4 to 7 cannot be written or read. Therefore, even if control is performed to write a value to bits 4 to 7 of the update rule selection register 542, the value is invalid and all the values read from bits 4 to 7 are “0 (= 0000 (B))”. Note that (B) indicates a binary number.

  The value (register value) of the update rule selection register 542 is set to “0 (= 00 (H) when the count value permutation change data“ 01 (H) ”is written in the count value permutation change register 536. )) ”To“ 15 (= 0F (H)) ”. That is, each time the count value permutation data “01 (H)” is written to the count value permutation change register 536, the register value of the update rule selection register 542 is incremented by “1” from “0” to “15”. Then, it returns to “0” again.

  FIG. 8 is an explanatory diagram showing an example of the update rule memory 543. As shown in FIG. 8, the update rule memory 543 stores the value (register value) of the update rule selection register 542 and the count value update rule in association with each other. In the example shown in FIG. 8, for example, when the register value 1 is set in the update rule selection register 542, it can be seen that the permutation of the count values output by the counter 521 is changed using the update rule B. In FIG. 8, the update rule A is the same update rule as that for the counter 521 to update the count value C, and is stored in the update rule memory 543 in association with the register value “0”. Also, in the update rule memory 543, update rules B to P different from the update rule in which the counter 521 updates the count value C are stored in association with the register values “1” to “15”.

  When the count value permutation change data “01 (H)” is written in the count value permutation change register 536, the count value permutation change circuit 523 first inputs the final count value “4095” from the counter 521 first. The count value is output as it is according to the currently set update rule. The count value permutation changing circuit 523 changes the count value update rule when the final value “4095” of the count value is input from the counter 521. When the initial value is changed by the CPU 56, the count value permutation changing circuit 523 inputs the final value after the change (the value immediately before the initial value) from the counter 521, and updates the count value. Will be changed.

  The count value permutation change circuit 523 selects an update rule corresponding to the register value of the update rule selection register 542 from the update rule memory 543, and sets it as an update rule used for changing the count value permutation. The count value permutation changing circuit 523 changes the permutation from the initial value of the count value to the final value according to the set update rule when the counter 521 starts updating the count value again from the initial value “0”. To do. When the initial value is changed by the CPU 56, the count value permutation changing circuit 523 starts counting in accordance with the set update rule when the counter 521 starts updating the count value in order from the changed initial value. The permutation from the initial value to the final value will be changed. Then, the count value permutation change circuit 523 outputs a count value according to the changed permutation.

  In this embodiment, when the maximum random number to be generated is limited by setting the maximum random number in a random number maximum value setting register 535 described later, the count value permutation changing circuit 523 counts The value C is limited to the maximum random number or less, and the permutation is changed and output. For example, it is assumed that the random number maximum value “256” is set in the random number maximum value setting register 535, and the count value permutation changing circuit 523 changes the update rule A to the update rule B to change the count value permutation. Shall. In this case, the count value permutation changing circuit 523 changes the count value permutation to “256 → 255” according to the update rule B based on the random number maximum value “256” set in the random number maximum value setting register 535 of the comparator 522. → → → 0 "and output.

  As described above, when the count value permutation change data “01 (H)” is written in the count value permutation change register 536, the count value permutation change circuit 523 switches the update rule to use the count value C Change the permutation of and output. Therefore, the randomness of the random number generated by the random number circuit 503 can be improved.

  FIG. 9 is an explanatory diagram illustrating an example in which the count value permutation changing circuit 523 changes the permutation of count values output from the counter 521. As shown in FIG. 9, the CPU 56 writes the count value permutation change data “01 (H)” into the count value permutation change register 536 at a predetermined timing. Then, 1 is added to the register value of the update rule selection register 542. For example, the register value of the update rule selection register 542 is updated from “0” to “1”. When the register value is updated, the count value permutation changing circuit 523 updates the “update rule A” corresponding to the register value “0” before the update until the final value “4095” of the count value is input from the counter 521 for the first time. The count value is updated according to "." At this time, the count value permutation changing circuit 523 outputs the count values in a permutation of “0 → 1 →... → 4095” according to the update rule A.

  When the final value “4095” of the count value is input from the counter 521, the count value permutation changing circuit 523 selects “update rule B” corresponding to the updated register value “1” from the update rule memory 543. To set. When the count value permutation changing circuit 523 starts to input the count values after the initial value “0” from the counter 521 again, the count value permutation changing circuit 523 changes the permutation of the count values according to the selected “update rule B” and outputs it. In this example, the count value permutation changing circuit 523 changes the permutation from “0 → 1 →... → 4095” to “4095 → 4094 →... → 0” and outputs the count value.

  Thereafter, the count value permutation change register 536 is reset in response to the count value permutation change circuit 523 starting the count value updating operation in accordance with the updated update rule, as will be described later. Then, until the count value permutation change data “01 (H)” is written to the count value permutation change register 536, the count value permutation change circuit 523 keeps “4095 → 4094 →. The count value continues to be output.

  When the count value permutation change data “01 (H)” is written again to the count value permutation change register 536 by the CPU 56, the register value of the count value permutation change register 536 is updated from “1” to “2”. When the final value “4095” of the count value is input from the counter 521, the count value permutation changing circuit 523 selects and sets “update rule C” corresponding to the register value “2” from the update rule memory 543. . When the count value permutation changing circuit 523 starts to input the count value after the initial value “0” again from the counter 521, the count value permutation changing circuit 523 updates and outputs the count value permutation in accordance with the “update rule C” selected and set. In this example, the count value permutation changing circuit 523 changes the permutation from “4095 → 4094 →... → 0” to “1 → 3 →... → 4095 → 0 →. Is output.

  As described above, after the count value permutation change register 536 is reset, the count value permutation data “01 (H)” is written again in the count value permutation change register 536, so that the count value permutation can be further changed. .

  FIG. 10 is an explanatory diagram illustrating an example of the count value permutation change register 536. The count value permutation change register 536 is a register that sets count value permutation change data “01 (H)” for changing the permutation of count values counted up by the counter 521. As shown in FIG. 10, the count value permutation change register 536 is a readable 8-bit register, and the initial value is set to “0 (= 00 (H))”. Further, count value permutation change register 536 is configured such that only bit 0 can be written and read. That is, count value permutation change register 536 is configured such that bits 1 to 7 cannot be written or read. Therefore, even if control is performed to write a value to bits 1 to 7 of the count value permutation change register 536, the value is invalid and all the values read from bits 1 to 7 are “0 (= 0000000 (B))”.

  Note that the value of the count value permutation change register 536 is reset by the CPU 56 in response to the count value permutation change circuit 523 starting a count value update operation in accordance with the updated update rule. In this case, the CPU 56 returns the value written in the count value permutation change register 536 from the count value permutation change data “01 (H)” to the initial value “0 (= 00 (H))”.

  The comparator 522 includes a random number maximum value setting register (RMX) 535 that stores random number maximum value setting data for designating a maximum value (random number maximum value) of a random R (random number generated by the random number circuit 503). The comparator 522 limits the update range of the count value updated by the counter 521 according to the random number maximum value indicated in the random number maximum value setting data stored in the random number maximum value setting register 535. In this embodiment, the comparator 522 has the random number maximum value indicated by the count value input from the counter 521 and the random number maximum value setting data (for example, “00FF (H)”) stored in the random number maximum value setting register 535. (For example, “256”). When the comparator 522 determines that the input count value is equal to or less than the random number maximum value, the comparator 522 outputs the input count value to the random value storage circuit 531.

  In this embodiment, the comparator 522 specifically performs the following control. The comparator 522 obtains the initial value of the count value from the CPU 56 when updating the initial value of the count value, and obtains the number of count values from the initial value to the maximum random number. For example, when the initial value of the count value is “157” and the maximum random number value is “256”, the comparator 522 calculates the number of count values from the initial value to the maximum random number value as “100”. Further, the comparator 522 counts up how many count values are input from the initial value as the count values are input from the count value permutation changing circuit 523. When the number of input count values from the initial value reaches “100”, the comparator 522 determines that all count values from the initial value “157” to the maximum value “256” have been input. Then, the comparator 522 outputs a notification signal indicating that all count values have been input to the counter 521. By determining based on the number of count values, even when the count value permutation circuit 523 has changed the count value permutation, the comparator 522 limits the update range of the count value to the maximum random number or less. When all count values are input, a notification signal can be output to the counter 521.

  An operation in which the comparator 522 limits the update range of the count value will be described. In this example, a case where the count value permutation changing circuit 523 selects the update rule A and the random number maximum value “256” is set in the random number maximum value setting register 535 will be described.

  While the counter 521 is updating the count value from “0” to “256”, the count value permutation changing circuit 523 updates based on the random number maximum value “256” set in the random number maximum value setting register 535. In accordance with rule A, the count values from “0” to “256” are output to the comparator 522 as they are. In this case, the count value permutation changing circuit 523 receives the value of the random number maximum value “256” from the comparator 522, determines whether the count value input from the counter 521 is larger than the random number maximum value, and the update rule is changed. Even when it is set (for example, update rule B), the count values from “257” to “4095” are compared based on the random number maximum value “256” set in the random number maximum value setting register 535. The data is not output to the device 522. For example, when the initial value is set to “0” and the count value is updated to the final value “256”, the counter 521 outputs a notification signal to the CPU 56. When the notification signal is output, the CPU 56 changes the initial value of the count value of the counter 521. In this example, it is assumed that the initial value is changed to “50” by the CPU 56.

  Note that the comparator 522 may determine whether the count value is greater than the random number maximum value “256”, instead of the count value permutation changing circuit 523. In this case, for example, the comparator 522 determines whether or not the count value is greater than the random number maximum value set in the random number maximum value setting register 535, and determines that the count value is greater than the random number maximum value. Is output to the counter 521. When the comparator 522 determines that the count value exceeds the random number maximum value, the comparator 522 outputs a notification signal to the counter 521 before the clock signal output circuit 524 next outputs the random number generation clock signal SI1. By doing so, the comparator 522 counts up the count value from “257” to “4095” at high speed until the clock signal output circuit 524 next outputs the random number generation clock signal SI1. Thus, the counter 521 is controlled. By doing so, the count value is output to the random value storage circuit 531 only when the value from the count value permutation changing circuit 523 is less than “257”, and the value from the count value permutation changing circuit 523 is “257”. When it is above, the count value can be updated at high speed.

  Based on the update rule A, while the count value is input from “0” to “255” from the count value permutation changing circuit 523, the comparator 522 inputs the count value below the maximum random number “256”. Therefore, the input count value is output to the random value storage circuit 531 as it is. Next, when the count value input from the count value permutation changing circuit 523 reaches “256”, the comparator 522 outputs the input count value to the random value storage circuit 531 and all the values from the initial value to the maximum value. A notification signal indicating that the count value is input is output to the counter 521. Specifically, the comparator 522 receives an initial value (“0” in this example) of the count value from the CPU 56 when changing the initial value of the count value, and the random number maximum value (the main value) from the initial value “0”. In the example, the number of count values up to “256” (in this example, “257”) is obtained. When the number of count values input from the count value permutation changing circuit 523 reaches 257, a notification signal indicating that all count values have been input is output to the counter 521. In this example, since the CPU 56 changes the initial value to “50”, the counter 521 does not reset the count value even when the notification signal is input from the comparator 522, and the changed initial value “50”. The count value is updated.

  While the counter 521 updates the count value from the changed initial value “50” to “256”, the count value permutation changing circuit 523 sets the random number maximum value “256” set in the random number maximum value setting register 535. Based on the update rule A, the count values from “50” to “256” are output to the comparator 522 as they are. Further, the count value permutation changing circuit 523 does not output the count values from “257” to “4095” to the comparator 522 based on the random number maximum value “256” set in the random number maximum value setting register 535. When the count value to be updated by the counter 521 makes one round (when updated 257 times), when the count value permutation change data is written in the count value permutation change register 536, the count value permutation change circuit 523 Change the permutation of count values and output. For example, when the update rule is changed to the update rule B, the count value permutation changing circuit 523 changes the count value permutation from “256 → 255 →... → 50” and outputs the result.

  While the count values from “256” to “50” are input from the count value permutation changing circuit 523, the comparator 522 outputs the input count value as it is to the random value storage circuit 531. Next, when the count value input from the count value permutation change circuit 523 reaches “50”, the comparator 522 outputs the input count value to the random value storage circuit 531 and all the values from the initial value to the maximum value. A notification signal indicating that the count value is input is output to the counter 521. Specifically, the comparator 522 receives the initial count value (“50” in this example) from the CPU 56 when the initial count value is changed, and the random number maximum value (this In the example, the number of count values up to “256” (in this example, “207”) is obtained. When the number of count values input from count value permutation changing circuit 523 reaches 207, a notification signal indicating that all count values have been input is output to counter 521.

  Even when the count value permutation changing circuit 523 changes the count value permutation, the comparator 522 outputs a notification signal to the counter 521 when the number of count values reaches 207. By doing so, even if the permutation of the count values is changed, the notification signal is counted based on the input of all the count values from the initial value “50” to the maximum value “256”. 521 can be output.

  When the notification signal is input from the comparator 522, the counter 521 resets the initial value of the count value and returns it to “0”. Then, the counter 521 updates the count value from “0”. When the value of the counter 521 is updated again from “0”, the count value permutation changing circuit 523 outputs the count values from “49” to “0” to the comparator 522 based on the count value from the counter 521. The comparator 522 outputs the count value to the random value storage circuit 531 based on the count value input from the count value permutation changing circuit 523. When the counter 521 updates the count value to the final value (“49” in this example), the counter 521 outputs a notification signal to the CPU 56. When the notification signal is output, the initial value of the count value of the counter 521 is changed again by the CPU 56.

  By repeating the operation as described above, the comparator 522 causes the counter 521 to continuously count up the count value from “0” to the random number maximum value “256”, and the value from “0” to “256”. Is stored in the random value storage circuit 531 as a random R (random number value). In other words, the comparator 522 limits the update range of the count value to the random number maximum value “256” or less, and causes the counter 521 to update the count value.

  FIG. 11 is an explanatory diagram showing an example of the random number maximum value setting register 535. FIG. 11A shows an example of the random number maximum value setting register 535 installed in the 12-bit random number circuit 503a. FIG. 11B shows an example of the random number maximum value setting register 535 installed in the 16-bit random number circuit 503b. First, the random number maximum value setting register 535 mounted in the 12-bit random number circuit 503a will be described. As shown in FIG. 11A, in the 12-bit random number circuit 503a, the random number maximum value setting register 535 is a 16-bit register, and the initial value is set to “4095 (= 0FFF (H))”. The random number maximum value setting register 535 is configured so that bits 0 to 11 can be written and read. The random number maximum value setting register 535 is configured such that bits 12 to 15 cannot be written or read. Therefore, in the 12-bit random number circuit 503a, even if control is performed to write values to bits 12 to 15 of the random number maximum value setting register 535, the values read from bits 12 to 15 are all “0 (= 0000 ( B)) ”.

  The random number maximum value set in the random number maximum value setting register 535 has a predetermined lower limit value. In this embodiment, when random number maximum value setting data “0000 (H)” to “00FE (H)” for designating a value smaller than the lower limit value “256” is written in the random number maximum value setting register 535, the CPU 56 Then, the random number maximum value setting data “0FFF (H)” for designating the initial value “4095” is reset in the random number maximum value setting register 535. That is, the random number maximum value that can be set in the random number maximum value setting register 535 is from “256” to “4095”, and when the CPU 56 determines that a value smaller than the lower limit value “256” is set, the random number maximum value Is reset to a predetermined value “4095”. The CPU 56 controls the random number maximum value setting register 535 in which the random number maximum value setting data is written to be unwritable until the game control microcomputer 560 is system-reset by the reset controller 502. Instead of controlling the CPU 56 to disable writing, the random number maximum value setting register 535 may be formed so that writing is not possible until a reset signal is input after data is written.

  Next, the random number maximum value setting register 535 mounted in the 16-bit random number circuit 503b will be described. As shown in FIG. 11B, in the 16-bit random number circuit 503b, the random number maximum value setting register 535 is a 16-bit register, and the initial value is set to “65535 (= FFFF (H))”. Further, in the 16-bit random number circuit 503b, the random number maximum value setting register 535 is configured in a state in which all of the bits 0 to 15 can be written and read.

  When random number maximum value setting data “0000 (H)” to “00FE (H)” for designating a value smaller than the lower limit value “512” is written in the random number maximum value setting register 535, the CPU 56 determines the random number maximum value. The random number maximum value setting data “FFFF (H)” for specifying the initial value “65535” is reset in the setting register 535. That is, the random number maximum value that can be set in the random number maximum value setting register 535 is from “512” to “65535”, and when the CPU 56 determines that a value smaller than the lower limit value “512” is set, the random number maximum value Is reset to a predetermined value “65535”. The CPU 56 controls the random number maximum value setting register 535 in which the random number maximum value setting data is written to be unwritable until the game control microcomputer 560 is system-reset by the reset controller 502.

  The clock signal output circuit 524 includes a cycle setting register (RPS) 537 for storing cycle setting data for designating the cycle of the clock signal output to the selector 528 and the inverting circuit 532 (that is, the count value update cycle). The clock signal output circuit 524 divides the reference clock signal CLK input from the clock circuit 501 mounted on the game control microcomputer 560 based on the cycle setting data stored in the cycle setting register 537, and generates a random number circuit. A clock signal (random number generating clock signal SI1) used to generate a random number value is generated inside 503. By doing so, the clock signal output circuit 524 operates to output the random number generation clock signal SI1 for updating the count value C to the counter 521 on condition that the clock signal has been input a predetermined number of times. . The period setting data is data for setting how many times the reference clock signal CLK input from the clock circuit 501 is to be divided. The clock output circuit 524 outputs the generated random number generating clock signal SI1 to the selector 528 and the inverting circuit 532. For example, when the cycle setting data “0F (H) (= 16)” is written in the cycle setting register 537, the clock signal output circuit 524 divides the reference clock signal CLK input from the clock circuit 501 by 16. A random number generating clock signal SI1 is generated. In this case, the cycle of the random number generating clock signal SI1 generated by the clock signal output circuit 524 is “cycle of system clock signal × 128 × 16”.

  FIG. 12 is an explanatory diagram showing an example of the cycle setting register 537. As shown in FIG. 12, the period setting register 537 is an 8-bit register, and the initial value is set to “256 (= FF (H))”. The cycle setting register 537 is configured in a state where both writing and reading are possible.

  In addition, a predetermined lower limit value is determined for the value of the cycle setting data set in the cycle setting register 537. In this embodiment, when period setting data “00 (H) to 06 (H)” specifying a value smaller than the lower limit value “system clock signal period × 128 × 7” is written in the period setting register 537, The CPU 56 resets the period setting data “07 (H)” for designating the lower limit value “system clock signal period × 128 × 7” in the period setting register 537. That is, the period that can be set in the period setting register 537 is “system clock signal period × 128 × 7” to “system clock signal period × 128 × 256”, and the CPU 56 is set to a value smaller than the lower limit value. If it is determined that the cycle setting data is correct, the cycle setting data is reset. The CPU 56 controls the period setting register 537 in which the period setting data is written to be unwritable until the game control microcomputer 560 is system-reset by the reset controller 502. Instead of controlling the CPU 56 to disable writing, the period setting register 537 may be formed so that writing is not possible until a reset signal is input after data is written.

  Note that, without setting the cycle setting data as the lower limit value in the cycle setting register 537, the clock signal output circuit 524, for example, directly supplies the reference clock signal CLK to the counter 521 and the inverting circuit 532 based on the set cycle setting data. You may make it output. In this case, the CPU 56 does not need to perform processing for setting the value of the cycle setting data set in the cycle setting register 537 by comparing it with the lower limit value. The counter 521 updates the count value C every time the reference clock signal CLK is input from the clock signal output circuit 524.

  The count value update signal output circuit 525 includes a count value update register (RGN) 538 that stores count value update data “01 (H)”. The count value update data is data for requesting update of the count value. Count value update signal output circuit 525 outputs count value update signal SI 3 to selector 528 in response to count value update data “01 (H)” being written to count value update register 538.

  FIG. 13 is an explanatory diagram illustrating an example of the count value update register 538. As shown in FIG. 13, the count value update register 538 is an unreadable 8-bit register and is configured so that only bit 0 can be written. Therefore, even if control is performed to write a value to bits 1 to 7 of the count value update register 538, it is invalidated.

  The random value read signal output circuit 526 includes a random value take-in register (RLT) 539 for storing random value take-in data “01 (H)”. The random value acquisition data is data for requesting acquisition of the count value to the random value storage circuit 531. The random value read signal output circuit 526 outputs a random value read signal for requesting reading of the random value in response to the random value fetch data “01 (H)” being written in the random value fetch register 539. The data is output to the latch signal generation circuit 533.

  FIG. 14 is an explanatory diagram showing an example of the random value fetch register 539. As shown in FIG. 14, the random value fetch register 539 is an unreadable 8-bit register. The random value fetch register 539 is configured so that only bit 0 can be written. In other words, even if control is performed to write a value to bits 1 to 7 of the random value fetch register 539, it is invalidated.

  The random number update method selection signal output circuit 527 includes a random number update method selection register (RTS) 540 that stores random number update method selection data. The random number update method selection data is data for designating one of the random number update methods that is a method for updating the value of the random R. The random number update method selection signal output circuit 527 responds to the random number update method selection data written in the random number update method selection register 540 with a random number corresponding to the random number update method specified by the written random number update method selection data. The update method selection signal is output to the selector 528 and the latch signal generation circuit 533.

  FIG. 15A is an explanatory diagram illustrating an example of the random number update method selection register 540. As shown in FIG. 15A, the random number update method selection register 540 is an 8-bit register, and the initial value is set to “00 (H)”. The random number update method selection register 540 is configured in a state where bits 0 to 1 can be written and read. The random number update method selection register 540 is configured in a state where bits 2 to 7 cannot be written or read. Therefore, even if control is performed to write a value to bits 2 to 7 of the random number update method selection register 540, it is invalid, and all the values read from bits 2 to 7 are “0 (= 000000 (B))”.

  FIG. 15B is an explanatory diagram of an example of random number update method selection data written to the random number update method selection register 540. As shown in FIG. 15B, the random number update method selection data is composed of 2-bit data. The random number update method selection data “01 (B)” is used for designating the first random number update method. Further, the random number update method selection data “10 (B)” is used for designating the second random number update method. In this embodiment, the first random number update method is a method of updating the count value triggered by the output of the count value update signal SI3 from the count value update signal output circuit 525. The second random number update method is a method of updating the count value triggered by the output of the random number generation clock signal SI1 from the clock signal output circuit 524. Further, when the random number update method selection data “01 (B)” or “10 (B)” is written in the random number update method selection register 540, the random number circuit 503 is ready to be activated. On the other hand, when the random number update method selection data “00 (B)” or “11 (B)” is written in the random number update method selection register 540, the random number circuit 503 becomes inactivated.

  The selector 528 selects either the count value update signal SI 3 output from the count value update signal output circuit 525 or the random number generation clock signal SI 1 output from the clock signal output circuit 524 and outputs the selected signal to the counter 521. When a random number update method selection signal (also referred to as a first random number update method selection signal) corresponding to the first random number update method is input from the random number update method selection signal output circuit 527, the selector 528 outputs a count value update signal. The count value update signal SI3 output from the circuit 525 is selected and output to the counter 521. On the other hand, when a random number update method selection signal (also referred to as a second random number update method selection signal) corresponding to the second random number update method is input from the random number update method selection signal output circuit 527, the selector 528 outputs a clock signal. The random number generation clock signal SI 1 output from the circuit 524 is selected and output to the counter 521. When the first update method selection signal is input from the random number update method selection signal output circuit 527, the selector 528 receives a clock signal according to the count value update signal SI3 output from the count value update signal output circuit 525. A numerical value update instruction signal for instructing update of numerical data synchronized with the random number generation clock signal SI1 output from the output circuit 524 may be output to the counter 521.

  The random number circuit activation signal output circuit 530 includes a random number circuit activation register (RST) 541 that stores random number circuit activation data “80 (H)”. The random circuit activation data is data for requesting activation of the random number circuit 503. When the random number circuit activation data “80 (H)” is written in the random number circuit activation register 541, the random number circuit activation signal output circuit 530 outputs a predetermined random number circuit activation signal to the counter 521 and the clock signal output circuit 537. 521 and the clock signal output circuit 524 are turned on. The random number circuit 503 is activated by starting the count value updating operation by the counter 521 and the internal clock signal output operation by the clock signal output circuit 524.

  FIG. 16 is an explanatory diagram illustrating an example of the random number circuit activation register 541. As shown in FIG. 16, the random number circuit activation register 541 is an 8-bit register, and the initial value is set to “00 (H)”. The random number circuit activation register 541 is configured such that only bit 7 can be written and read. The random number circuit activation register 541 is configured in a state in which bits 0 to 6 cannot be written or read. That is, even if control is performed to write a value to bit 0 to bit 6 of the random number circuit activation register 541, it is invalid, and all the values read from bit 0 to bit 6 are “0 (= 000000 (B))”.

  The random value storage circuit 531 is a 16-bit register, for example, and stores a random R value that is a random number used in the jackpot determination in the game control process. The random value storage circuit 531 stores the count value C output from the counter 521 via the comparator 522 as a random R value in response to the input of the latch signal SL from the latch signal generation circuit 533. Each time the latch signal SL is input from the latch signal generation circuit 533, the random value storage circuit 531 reads the count value C updated by the counter 521 and stores the random R value.

  FIG. 17 is a circuit diagram showing a configuration example of the random value storage circuit 531. As shown in FIG. 17, the random value storage circuit 531 includes two AND circuits 201 and 203, two NOT circuits 202 and 204, 16 flip-flop circuits 2101 to 2116, and 16 OR circuits. 2201-2216.

  As shown in FIG. 17, the input terminal of the AND circuit 201 is connected to the output terminal of the latch signal generation circuit 533 and the output terminal of the NOT circuit 204, and the output terminal is connected to the input terminal of the NOT circuit 202 and the flip-flop circuit 2101. Are connected to clock terminals Clk1 to Clk16. The input terminal of the NOT circuit 202 is connected to the output terminal of the AND circuit 201, and the output terminal is connected to one input terminal of the AND circuit 203.

  The input terminal of the AND circuit 203 is connected to the output terminal of the NOT circuit 202 and the CPU 56 mounted on the game control microcomputer 560, and the output terminal is connected to the input terminal of the NOT circuit 204. The input terminal of the NOT circuit 204 is connected to the output terminal of the AND circuit 203, and the output terminal is connected to one input terminal of the AND circuit 201 and one input terminal of the OR circuits 2201 to 2216.

  The input terminals D1 to D16 of the flip-flop circuits 2101 to 2116 are connected to the output terminal of the comparator 522. The clock terminals Clk1 to Clk16 of the flip-flop circuits 2101 to 2116 are connected to the output terminal of the AND circuit 201, and the output terminals Q1 to Q16 are connected to the other input terminals of the OR circuits 2201 to 2216.

  The input terminals of the OR circuits 2201 to 2216 are connected to the output terminal of the NOT circuit 204 and the output terminals of the flip-flop circuits 2101 to 2116, and the output terminals are connected to the CPU 56 mounted on the game control microcomputer 560. .

  The operation of the random value storage circuit 531 will be described. FIG. 18 is a timing chart showing the timing at which each signal is input to the random value storage circuit 531 and the timing at which the random value storage circuit 531 outputs each signal. As shown in FIG. 18, when the output control signal SC (high level signal in this example) is not input from the CPU 56 mounted on the game control microcomputer 560 (that is, to one input terminal of the AND circuit 203). When the latch signal SL is input from the latch signal generation circuit 533 (when the input is at a low level) (at the timings T1, T2, and T7 in the example illustrated in FIG. 18), the input to the two input terminals of the AND circuit 201 is performed. Both inputs are high. Therefore, the signal SR output from the output terminal of the AND circuit 201 is at a high level. The signal SR output from the AND circuit 201 is input to the clock terminals Clk1 to Clk16 of the flip-flop circuits 2101 to 2116.

  The flip-flop circuits 2101 to 2116 are responsive to the rising edges of the signal SR input from the clock terminals Clk1 to Clk16, and the bit data C1 to C1 of the count value C input from the comparator 522 via the input terminals D1 to D16. C16 is latched and stored as bit data R1 to R16 of a random value. The flip-flop circuits 2101 to 2116 output random R bit data R1 to R16 to be stored from the output terminals Q1 to Q16.

  When the output control signal SC is not input (in the example shown in FIG. 18, the period up to the timing T3 and the period after the timing T6), the input to one input terminal of the AND circuit 203 is at the low level. The signal SG output from the output terminal of the circuit 203 is at a low level. The signal SG output from the AND circuit 203 is inverted in the NOT circuit 204 to be a high level signal. A high level signal is input from the NOT circuit 204 to one input terminal of the OR circuits 2201 to 2216.

  As described above, since the input to one of the input terminals of the OR circuits 2201 to 2216 is at a high level, the OR is input regardless of whether the signal input to the other input terminal is at a high level or a low level. The circuits 2201 to 2216 output high level signals. That is, the signals SO1 to SO16 output from the OR circuits 2201 to 2216 are all at a high level regardless of whether the values of the input random R bit data R1 to R16 are “0” or “1”. (“1”). By doing so, the value output from the random value storage circuit 531 is always “65535 (= 1111111111111111 (B))”, and the random R cannot be read from the random value storage circuit 531. That is, even if an attempt is made to read a random number from the random value storage circuit 531, only the same value “65535” can always be read from the random value storage circuit 531, and when the output control signal SC is not input, the random value storage circuit 531 is in an unreadable (disabled) state. When the 16-bit random number circuit 503b is used, the value “65535” as a random number value may be used. In this case, even if the game control microcomputer 560 reads the value “65535”, it cannot determine whether the value is a random number or an unreadable state. Therefore, in the determination table for each jackpot determination shown in FIG. 27, when the random R is “65535”, it may be set to be determined as “out of”.

  When the output control signal SC is input from the CPU 56 when the latch signal SL is not input from the latch signal generation circuit 533 (in the example shown in FIG. 18, the period from the timing T4 to the timing T6), Since the inputs to the two input terminals are both at the high level, the signal SG output from the output terminal of the AND circuit 203 is at the high level. The signal SG output from the AND circuit 203 is inverted in the NOT circuit 204 to be a low level signal. A low level signal is input from the NOT circuit 204 to one input terminal of the OR circuits 2201 to 2216.

  As described above, since the input to one input terminal of the OR circuits 2201 to 2216 is at a low level, when the signal input to the other input terminal is at a high level, the output from the output terminals of the OR circuits 2201 to 2216 is high. A level signal is output. In addition, when a signal input to the other input terminal of the OR circuits 2201 to 2216 is at a low level, a low level signal is output from the OR circuits 2201 to 2216. That is, the values of the random R bit data R1 to R16 input to the other input terminals of the OR circuits 2201 to 2216 are unchanged from the output terminals of the OR circuits 2201 to 2216 (that is, the values of the bit data R1 to R16 are “ “1” is output when it is “1” and “0” when it is “0”). By doing so, random R can be read from the random value storage circuit 531. That is, when the output control signal SC is input, the random value storage circuit 531 is in a readable (enable) state.

  However, if the latch signal SL is input from the latch signal generation circuit 533 before the output control signal SC is input from the CPU 56, the input to one input terminal of the AND circuit 203 is at a low level. Even if the output control signal SC is input while the signal SL is being input (in the example shown in FIG. 18, the period from the timing T3 to the timing T4), the signal SG output from the output terminal of the AND circuit 203. Remains low. The signal SG output from the AND circuit 203 is inverted in the NOT circuit 204 to be a high level signal. A high level signal is input from the NOT circuit 204 to one input terminal of the OR circuits 2201 to 2216.

  As described above, since the input to one of the input terminals of the OR circuits 2201 to 2216 is at a high level, the OR is input regardless of whether the signal input to the other input terminal is at a high level or a low level. The signals SO1 to SO16 output from the circuits 2201 to 2216 are all at a high level. Even though the output control signal SC is input, the random R cannot be read from the random value storage circuit 531. That is, when the latch signal SL is input, the random value storage circuit 531 cannot receive the output control signal SC. When the 16-bit random number circuit 503b is used, the value “65535” as a random number value may be used. In this case, even if the game control microcomputer 560 reads the value “65535”, it cannot determine whether the value is a random number or an unreadable state. Therefore, in the determination table for each jackpot determination shown in FIG. 27, when the random R is “65535”, it may be set to be determined as “out of”.

  In addition, when the output control signal SC is input from the CPU 56 before the latch signal SL is input from the latch signal generation circuit 533, the input to one input terminal of the AND circuit 201 is at a low level. Even if the latch signal SL is input while the control signal SC is being input (timing T5 in the example shown in FIG. 18), the signal SR output from the output terminal of the AND circuit 201 remains at the low level. It becomes. Therefore, the signal SR input to the clock terminals Clk1 to Clk16 of the flip-flop circuits 2101 to 2116 does not rise from the low level to the high level, and the random R bit data R1 to R16 stored in the flip-flop circuits 2101 to 2116. Although the latch signal SL is input, the stored random number is not updated. That is, when the output control signal SC is input, the random value storage circuit 531 cannot receive the latch signal SL.

  The inverting circuit 532 generates the inverted clock signal SI2 in which the polarity of the clock signal is inverted by inverting the signal level in the random number generating clock signal SI1 input from the clock signal output circuit 524. Further, the inverting circuit 532 outputs the generated inverted clock signal SI2 to the latch signal generating circuit 533.

  The latch signal generation circuit 533 is configured using a selector, a flip-flop circuit, and the like. The latch signal generation circuit 533 receives the random number read signal from the random number read signal output circuit 526 and the inverted clock signal SI2 from the inversion circuit 532, and stores the random value in the random value storage circuit 531. SL is output. The latch signal generation circuit 533 outputs the latch signal SL in accordance with the random value update method designated by the random number update method selection signal from the random number update method selection signal output circuit 527. In this case, when the first random number update method selection signal output circuit 527 receives the first random number update method selection signal output circuit 527, the latch signal generation circuit 533 selects the inverted clock signal SI2 output from the inversion circuit 532, and the latch signal It outputs to the random value storage circuit 531 as SL. On the other hand, the latch signal generation circuit 533 inverts the random value read signal output from the random number read signal output circuit 526 when the second random number update method selection signal is input from the random number update method selection signal output circuit 527. In synchronization with the rising edge of the inverted clock signal SI2 output from the circuit 532, it is output to the random value storage circuit 531 as the latch signal SL.

  The timer circuit 534 inputs a winning detection signal SS indicating that a winning of a game ball to the starting port 14 has been detected from the starting port switch 14a. The timer circuit 534 measures the time during which the winning detection signal SS is continuously input from the start port switch 14a. Then, when the measurement time reaches a predetermined period (for example, 3 ms), the timer circuit 534 writes the random number value capture data “01 (H)” into the random value capture register 539 of the random value read signal output circuit 526. For example, the timer circuit 534 is configured by an up counter or a down counter that is activated in response to the input of a high level signal. The timer circuit 534 receives the reference clock signal CLK sequentially input from the clock circuit 501 while the input from the start port switch 14a is at a high level (that is, while the winning detection signal SS is continuously input). Count up or down. Then, when the count value to be counted up or down reaches a value corresponding to 3 ms, the timer circuit 534 determines that the winning detection signal SS is input from the start port switch 14a, and the random number value capture data “01 (H ) ”Is written to the random number value acquisition register 539.

  FIG. 19 is an explanatory diagram showing an example of an address map of a storage area in the game control microcomputer 560. As shown in FIG. 19, the area from address 0000 (H) to address 1FFF (H) in the storage area of the game control microcomputer 560 is allocated to the ROM 54. An area from addresses 7E00 (H) to 7FFF (H) is allocated to the RAM 55. Further, the area from address FD00 (H) to address FE00 (H) is allocated to a built-in register such as the random number maximum value setting register 535.

  As shown in FIG. 19, the area from address 0000 (H) to address 1FFF (H) allocated to the ROM 54 includes a user program area and a user program management area. A program (user program) 550 created in advance by a user (for example, a game machine designer) is stored in the user program area in the area from address 0000 (H) to address 1F7F (H). Further, data (user program execution data) necessary for the CPU 56 to execute the user program 550 is stored in the user program management area in the area of addresses 1F80 (H) to 1FFF (H). Of the areas 7E00 (H) to 7FFF (H) allocated to the RAM 55, the areas 7E00 (H) to 7EFF (H) are unused areas, and the addresses 7F00 (H) to The area of address 7FFF (H) is used as a work area.

  FIG. 20 is an explanatory diagram showing an example of an address map in the user program management area. As shown in FIG. 20, in the area of address 1F97 (H), the initial value selected by the user among the initial value changing methods that are methods for changing the initial value input to the counter 521 of the random number circuit 503 is displayed. Initial value change method setting data for designating a value change method is stored. Further, in the areas 1F98 (H) and 1F99 (H), the addresses in the RAM 55 (designated RAM addresses) designated in advance by the user among the addresses 7F00 (H) to 7FFF (H) allocated to the RAM 55 are included. RAM address data for specifying) is stored. In this case, of the values indicating the designated RAM address, the lower value of the designated RAM address is stored in the 1F98 (H) address, and the higher value of the designated RAM address is stored in the 1F99 (H) address.

  FIG. 21 is an explanatory diagram of an example of initial value change method setting data. As shown in FIG. 21, the initial value change data is composed of 8-bit data. The initial value change data “00 (H)” is data specifying that the initial value is not changed as the initial value change method. In this embodiment, when the initial value change data “00 (H)” is set, the counter 521 of the random number circuit 503 updates the count value from a predetermined initial value “0” to a predetermined final value. Will do. Further, the initial value change data “01 (H)” indicates that the initial value input to the counter 521 is changed to a value based on an ID number for identifying the game control microcomputer 560 as an initial value change method. The data to be specified. In this embodiment, when the initial value change data “01 (H)” is set, the initial value of the counter value updated by the counter 521 is changed from “0” to a value based on the ID number, and the counter 521 The count value is updated from the changed initial value to a predetermined final value.

  The user program 550 stored in the user program area will be described. FIG. 22 is an explanatory diagram showing a configuration example of the user program 550. As shown in FIG. 22, in this embodiment, the user program 550 includes a random number circuit setting program 551 composed of a plurality of types of program modules, a display result determination program 552, a count value permutation change program 554, and a random program. And a numerical value update program 555.

  The random number circuit setting program 551 is a program for executing a random number circuit setting process for performing initial setting for causing the random number circuit 503 to update the value of the random R. That is, the CPU 56 functions as random number circuit setting means by executing processing according to the random number circuit setting program 551.

  FIG. 23 is an explanatory diagram showing a configuration example of the random number circuit setting program 551. As shown in FIG. 23, the random number circuit setting program 551 includes a random number maximum value setting module 551a, a random number update method selection module 551b, a cycle setting module 551c, a random number circuit activation module 551d, as a plurality of types of program modules. An initial value changing module 551e and a random number circuit selecting module 551f are included.

  The random number maximum value setting module 551a is a program module for causing the random number circuit 503 to set the maximum value of random R preset by a user (for example, a game machine designer). The CPU 56 executes processing according to the random number maximum value setting module 551a, thereby writing random number maximum value setting data for specifying the maximum value of the random R preset by the user in the random number maximum value setting register 535. By doing so, the CPU 56 sets the maximum value of the random R preset by the user in the random number circuit 503. For example, when “255” is set in advance as the maximum value of the random R by the user, the CPU 56 writes the random number maximum value setting data “00FF (H)” in the random number maximum value setting register 535, and the maximum value of the random R “255” is set in the random number circuit 503.

  The random number update method selection module 551b is a program module for causing the random number circuit 503 to set the random number update method (first random number update method or second random number update method) selected by the user. The CPU 56 executes the processing according to the random number update method selection module 551b, thereby assigning the random number update method selection data “01 (B)” or “10 (B)” specifying the random number update method selected by the user to the random number update method. Write to the selection register 540. By doing so, the CPU 56 sets the random number update method selected by the user in the random number circuit 503. Therefore, the game control microcomputer 560 has a function of selecting either the first random number update method or the second random number update method as the random number update method used by the random number circuit 503 for the random number update.

  The cycle setting module 551c is a program for causing the random number circuit 503 to set the cycle of the internal clock signal preset by the user (that is, the cycle in which the clock signal output circuit 524 outputs the clock signal to the selector 528 and the inverting circuit 532). It is a module. The CPU 56 writes processing in the cycle setting register 537 for designating the cycle of the internal clock signal preset by the user by executing processing in accordance with the cycle setting module 551c. By doing so, the CPU 56 sets the cycle of the internal clock signal preset by the user in the random number circuit 503. For example, when the cycle of the internal clock signal is previously set as “system clock signal cycle × 128 × 16” by the user, the CPU 56 writes the cycle setting data “0F (H)” in the cycle setting register 537 to The cycle of the clock signal “system clock signal cycle × 128 × 16” is set in the random number circuit 503.

  The random number circuit activation module 551d is a program module for activating the random number circuit 503. The CPU 56 activates the random number circuit 503 by writing the random number circuit activation data “80 (H)” into the random number circuit activation register 541 by executing processing according to the random number circuit activation module 551d.

  The initial value change module 551e is a program module for changing the initial value of the count value updated by the counter 521. The CPU 56 functions as an initial value changing unit by executing processing according to the initial value changing module 551e. The CPU 56 executes the initial value changing module 551e to change the initial value of the count value updated by the counter 521 by the initial value changing method selected by the user. By doing so, the game control microcomputer 560 has a function of selecting an initial value changing method.

  In this embodiment, when initial value change method setting data “01 (H)” is stored in the area of address 1F97 (H) in the user program management area, the CPU 56 sets the initial value of the count value as game control. The value is calculated based on the unique ID number assigned to each microcomputer 560.

  For example, the game control microcomputer 560 associates in advance a predetermined storage area of the RAM 55 with the ID number of the game control microcomputer 560 and a calculated value obtained by performing a predetermined calculation based on the ID number. I remember it. In this case, for example, if the ID number of the game control microcomputer 560 is “100”, the calculated value “150” obtained by adding the predetermined value “50” to the ID number “100” is set in advance as the ID number. Are stored in association with each other. Further, for example, the calculated value “50” obtained by subtracting the predetermined value “50” from the ID number “100” is stored in advance in association with the ID number. Further, for example, only a predetermined value may be stored in advance in association with the ID number. Then, the game control microcomputer 560 uses a value “150” obtained by adding an ID number (eg, “100”) to a predetermined value (eg, “50”) stored in advance as an initial value of the count value. In addition, the game control microcomputer 560 uses a value “50” obtained by subtracting a predetermined value (for example, “50”) stored in advance from the ID number (for example, “100”) as an initial count value. It may be a value.

  When the initial value change method setting data “01 (H)” is stored, the CPU 56 changes the initial value of the count value to the calculated value based on the ID number stored in advance. By doing so, the randomness of the random number generated by the random number circuit 503 can be further improved, and the initial value of the random number can be made difficult to recognize only by looking at the ID number of the game control microcomputer 560. . Therefore, it is possible to more reliably prevent the transition condition to the big hit state from being illegally established by an action such as generating a captured signal using a radio signal to the gaming machine, and improving security. Can be improved.

  For example, when the initial value change method setting data “01 (H)” is stored, the CPU 56 calculates the ID number of the game control microcomputer 560 and a predetermined value (for example, the ID number has a predetermined value). The initial value of the count value is changed to the calculated value obtained by adding the values. In this case, for example, the CPU 56 may calculate a value that is randomly changed using a random number as an ID number, thereby randomly updating a value used for the calculation and obtaining an initial value. By doing so, the randomness of the random numbers generated by the random number circuit 503 can be further improved.

  The random number circuit selection module 551f is a program module for setting a random number circuit to be used when executing a timer interrupt process including a game control process from among the random number circuits 503 built in the game control microcomputer 560. The CPU 56 executes processing in accordance with the random number circuit selection module 551f, so that any of the two random number circuits (12-bit random number circuit 503a and 16-bit random number circuit 503b) built in the game control microcomputer 560 is selected. Set whether to use when executing timer interrupt processing. For example, the CPU 56 uses a 12-bit random number circuit 503a or 16-bit as a random number circuit used when executing the timer interrupt process according to a predetermined set value (a value set in advance by the user) stored in a predetermined storage area of the RAM 55. The random number circuit 503b is set.

  Note that both the 12-bit random number circuit 503a and the 16-bit random number circuit 503b may be set as random number circuits used when the timer interrupt process is executed. In this case, for example, the game control microcomputer may perform a jackpot determination based on a random number generated by the 12-bit random number circuit 503a and may perform a probability change determination based on the random number generated by the 16-bit random number circuit 503b. . In this embodiment, the random value storage circuit 531 is present in each of the 12-bit random number circuit 503a and the 16-bit random number circuit 503b (that is, a random number storage circuit that stores a random number for 12 bits and a random number for 16 bits). And a random number storage circuit for storing the same). When both the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are set, the game control microcomputer 560 outputs the random number read from the 12-bit random number circuit 503a and the random number read from the 16-bit random number circuit 503b. , And stored in separate buffer areas provided in the RAM 55. Therefore, even when the timing for reading a random number from the 12-bit random number circuit 503a and the timing for reading a random number from the 16-bit random number circuit 503b are the same, two different random numbers can be extracted and stored in different buffer areas.

  The random value update program 555 is a program for updating the value of the random R stored in the random value storage circuit 531 when the first random number update method is selected as the random number update method. The CPU 56 functions as a random value updating unit by executing processing according to the random value updating program 555. When the first random number update method is selected, the CPU 56 executes the random number value update program 555 and writes the count value update data “01 (H)” to the count value update register 538, thereby causing the counter 521. The count value is updated, and the value of the random R stored in the random value storage circuit 531 is updated. When the second random number update method is selected as the random number update method, the counter 521 is updated with the random number generation clock signal output from the clock signal output circuit 537, and the random value storage circuit 531 is updated. The value of random R stored in is updated.

  The display result determination program 552 is a program for determining whether or not the display result in the special symbol display device 8 is a jackpot symbol. The CPU 56 functions as a display result determination unit by executing processing according to the display result determination program 552.

  In this embodiment, the CPU 56 follows the display result determination program 552 in response to a condition (execution condition) for the game ball winning the variable winning ball apparatus 15 and executing variable symbol special display. Execute the process. Then, the CPU 56 reads the updated random R value from the random value storage circuit 531, and determines whether or not the display result in the special symbol display device 8 is a jackpot symbol.

  FIG. 24 is an explanatory diagram illustrating an operation in which the CPU 56 updates the random R value or reads the random R value when the first random number update method is selected. As shown in FIG. 24, when the first random number update method is selected, the CPU 56 writes the count value update data “01 (H)” into the count value update register 538 so that the random value storage circuit 531 The stored random R value (for example, “2”) is updated. Then, the CPU 56 receives a random R value from the random value storage circuit 531 in response to the fact that the game ball has won the variable winning ball device 15 and the condition (execution condition) for executing the variable symbol special display is established. (For example, “2”) is read.

  When the random R value stored in the random value storage circuit 531 is further updated, an interval equal to or longer than the cycle of the system clock signal output from the clock circuit 501 has elapsed since the random R value was updated during the previous update. Sometimes, the count value update data “01 (H)” must be written to the count value update register 538. This is because it is necessary to secure time for reading the updated random R value from the random value storage circuit 531.

  FIG. 25 is an explanatory diagram illustrating an operation in which the CPU 56 reads the value of the random R when the second random number update method is selected. As shown in FIG. 25, when the second random number update method is selected, the timer circuit 534 writes the random value fetch data “01 (H)” into the random value fetch register 539, thereby counter 521. The random value storage circuit 531 takes in the count value (for example, “2”) output by Random and updates the random R value stored in the random value storage circuit 531. Then, the CPU 56 reads the updated random R value (for example, “2”) from the random value storage circuit 531.

  Specifically, when the second random number update method is selected, the counter 521 updates the count value C using the input of the random number generation clock signal SI1 as a trigger. Thereafter, when the random value fetch data “01 (H)” is written in the random value fetch register 539, the latch signal generation circuit 533 outputs the latch signal SL to the random value storage circuit 531. Then, the random value storage circuit 531 reads and stores the count value output from the counter 521 with the input of the latch signal SL as a trigger. Then, the CPU 56 reads the value of random R stored in the random value storage circuit 531.

  Note that if the timer circuit 534 does not write the random number value capture data “01 (H)” to the random value capture register 539, even if the counter 521 updates the count value, the random value storage circuit 531 Don't remember random numbers to update. For example, the timer circuit 534 writes the random value fetch data “01 (H)” into the random value fetch register 539, and the count value “3” output from the counter 521 is fetched into the random value storage circuit 531 so that the random value Assume that the random R value “3” stored in the storage circuit 531 is updated. In this case, if the timer circuit 534 does not write the random value fetch data “01 (H)” again in the random value fetch register 539, the count value output from the counter 521 is “3” to “4” or “5”. Is updated, the random value stored in the random value storage circuit 531 is not updated, and the random value read from the random value storage circuit 531 remains “3”.

  The count value permutation change program 554 writes the count value permutation change data “01 (H)” in the count value permutation change register 536, and changes the count value permutation stored in the random value storage circuit 531. It is a program for executing. The CPU 56 functions as numerical data permutation changing means by executing processing according to the count value permutation changing program 554. The CPU 56 executes the count value permutation change program 554 and writes the count value permutation change data “01 (H)” in the count value permutation change register 536, so that the count value permutation change circuit 523 outputs the random number value storage circuit. The permutation of the count values input to 531 is changed.

  Further, as shown in FIG. 26, the game control microcomputer 560 includes a special figure holding memory 570, a big hit determination table memory 571, a flag memory 572, and a start winning port switch timer memory 573.

  In the special figure holding memory 570, the game ball wins the variable winning ball device 15 and the execution condition of the variable symbol variable display is satisfied, but the variable display start condition is not yet satisfied (for example, the special symbol display device). 8 is a memory (storage area) for storing pending data including the number of times the execution condition for variable display is satisfied (8 is still executing variable display). The special figure holding memory 570 includes four entries. Each entry includes a holding number and a random R read from the random number storage circuit 531 according to the winning order in the order in which the game balls win the variable winning ball device 15. A value is stored in association with each other. In addition, each time the special symbol variable display in the special symbol display device 8 is finished once or the big hit gaming state is finished, the variable display start condition based on the top information of the special symbol holding memory 570 is set. It is established, and variable display based on the top information of the special figure holding memory 570 is executed. In this case, when the condition for starting the variable display of special symbols is satisfied, the information registered in the second or lower place in the special figure holding memory 570 is moved up by one place. In addition, when a game ball newly wins the variable winning ball apparatus 15 during the variable display of the special symbol, the value of the random R read from the random value storage circuit 531 based on the new winning is the special R value. It is registered in the empty entry in the figure holding memory 570.

  The jackpot determination table memory 571 stores a plurality of jackpot determination tables used by the CPU 56 to determine whether or not the display result of the special symbol display device 8 is a jackpot symbol. Specifically, as shown in FIG. 27A, the big hit determination table memory 571 stores a normal time big hit determination table 571a used in a gaming state (referred to as a normal state) other than the probability variation state. Further, as shown in FIG. 27B, the jackpot determination table memory 571 stores a probability change big hit determination table 571b used in the probability change state. When the big hit determination is performed using the determination table shown in FIG. 27, the probability of determining a big hit depends on the random number maximum value set in the random number maximum value setting register 535. In this case, for example, when the maximum value is set too small when the maximum value is set due to a malfunction, for example, when the normal big hit determination table 571a is used and when the probability change big hit determination table 571b is used. The difference in the probability of determining a big hit will be small, and the player's interest in the game will be reduced. Therefore, a plurality of determination tables (a plurality of normal time big hit determination tables 571a and a plurality of probability variation big hit determination tables 571b) are stored in the big hit determination table memory 571 in association with the random number circuit 503 and the maximum random number. Also good. The CPU 56 of the game control microcomputer 560 determines the display result by using the random number circuit 503 to be used and the determination tables 571a and 571b corresponding to the maximum random number among the determination tables stored in the jackpot determination table memory 571. In accordance with the program 552, it may be determined whether or not the display result of the special symbol display device 8 is a jackpot symbol. By doing so, even if the type of random number circuit 503 to be used and the maximum random number value are different, it is possible to control so that the probability of determining a jackpot is the same to some extent.

  In the flag memory 572, various flags used in the game control process for controlling the progress of the game are set. For example, in the flag memory 572, a probability change flag indicating that the gaming state is a probability change state and a big hit flag indicating that the game state is a big hit state are set.

  The start port switch timer memory 573 stores a timer value that is added or cleared in accordance with the winning detection signal SS input from the start port switch 14a.

  Here, the “spoofed substrate” will be described. The “spoofing board” means an illegal circuit board that executes illegal control such as “spoofing” to generate a big hit on the main board of a pachinko machine.

  Conventionally, an illegal act of illegally generating a big hit by exchanging a ROM storing a control program for causing a microcomputer to execute various processes. For this reason, in order to prevent the ROM from being replaced, the ROM is built into the microcomputer to be a one-chip microcomputer, and a predetermined calculation is performed based on the data stored in the ROM. A security check was performed.

  However, the one-chip microcomputer itself has been counterfeited and replaced with a regular microcomputer, and fraudulent acts that illegally generate big hits have been performed. Correspondingly, a board box that stores the main board is sealed so that a trace is left when the microcomputer is replaced, and a gaming machine that can be seen that the board box has been opened is used. It came to be able to.

  However, a fraudulent act in which an unauthorized circuit board is attached to the wiring between the start port switch and the main board and the start prize is illegally generated at the timing of the big hit judgment value of the big hit judgment random number has been performed. Correspondingly, the initial value of the jackpot determination random number is changed to shift the timing coincident with the jackpot determination value, or the hardware random number updated at high speed is used.

  Thereafter, an act of illegally generating a big hit by replacing the board box storing the main board with a board on which an illegal circuit is mounted has been performed. Correspondingly, a verification machine installed outside the main board is connected to the microcomputer so that it has a function of checking whether it is a legitimate microcomputer, so that it is easy to find an illegal circuit board. Came to be.

  However, while the regular main board is left in the gaming machine, only the power is supplied and the verification function of the regular microcomputer is utilized, while other main board functions such as winning and jackpot are executed instead of the main board. The “board” was installed on the back side of the main board, and fraudulent acts that illegally generated big hits occurred.

  FIG. 28 is a block diagram illustrating an example of a state in which an impersonation board is installed in a gaming machine. As shown in FIG. 28, the spoofing board 31X includes a main board 31 and other electric component control boards that exchange signals with the main board 31 (in this embodiment, the effect control board 80 and the payout control board 37). It is installed between. Then, the other electrical component control board that exchanges signals with the main board 31 exchanges signals with the spoofing board 31X instead of the main board 31. As an example, power supply power is supplied to the main board 31 from the spoofing board 31X.

  The spoofing board 31X is generally installed by removing all the connectors of the regular main board 31 and hiding them behind the board box. Since it is discovered as soon as the connector on the main board 31 side is removed, the connector on the mating board connected to the main board 31 is removed. As a result, an abnormality of the main board 31 is hardly detected visually. Then, all the electrical components connected to the main board 31 are connected to the spoofing board 31X. Further, wiring for supplying power from the spoofing board 31X to the regular main board 31 is connected. Therefore, since the verification function (function to output an authentication signal) of the game control microcomputer 560 operates, when verification is performed using the verification machine 365, the authentication target becomes the main board 31 instead of the spoofing board 31X. Therefore, the collation result is OK.

  Then, the impersonation substrate 31X is hidden behind the main substrate 31. The main board 31 mounted on the pachinko gaming machine is a single-sided mounting for the purpose of easily discovering whether an illegal circuit is mounted on the board itself, and the surface mounting parts cannot be used. It is relatively large. Therefore, if the control board having the same performance as the main board 31 is mounted on both sides and is made of the surface mounting components, the control board can be made smaller than the regular main board 31. In other words, an “spoofed substrate” having performance equivalent to that of the main substrate 31 can be made smaller than the main substrate 31. For this reason, the “spoofed substrate” can be easily installed hidden behind the main substrate 31.

  FIG. 29 is a front view schematically showing a game control board box that accommodates the main board 31. The main board 31 is accommodated in the game control board box on the back of the gaming machine. That is, the main board 31 is housed in a game control board box as a housing means, and is attached to the gaming machine in the form of a game control unit in which they are combined. The game control board box has a structure in which a box body 31A in which the main board 31 is accommodated is covered with a lid portion 31B. The lid 31B is fixed to the box body 31A with a one-way screw and other screws (not shown) screwed into one mounting hole in each of the mounting portions 31D and 31E. The one-way screw is a screw that turns only in the screw tightening direction, and is an example of a fixing unit that makes the game control board box unopenable. Therefore, once tightened, the screw cannot be removed. The game control board box has a “caulking structure” in which a joint portion between the box main body 31A and the lid portion 31B is firmly fastened by, for example, a metal fitting such as a screw.

  When the main board 31 is to be exposed by removing the lid 31B from the box body 31A, it is necessary to cut off the one-way screw attachment portions (attachment portions with the lid portion 31B) in the attachment portions 31D and 31E. Therefore, the number of times the main board 31 is exposed can be found from the cutting history of the mounting portion. When the actual number of times of cutting is larger than the cutting history (number of times) of the attachment portion known by the administrator or the like, the lid 31B is illegally removed and the main board 13 is exposed, and the game control micro It can be seen that the computer may have been replaced with an unauthorized microcomputer. Since the attachment portions 31D and 31E are each provided with three attachment holes, the lid portion 31B can be removed up to three times.

  Further, in order to prevent unauthorized removal of the lid portion 31B, sealing seals 31F and 31G on which holograms are printed are attached between the lid portion 31B and the box body 31A. When the seal seals 31F and 31G are peeled off, the hologram remains partially on the lid portion 31B and the box body 31A, so that it can be seen at a glance. This also shows that the lid 31B was illegally removed from the box body 31A to expose the main board 31.

  Further, the surface of the lid portion 31B has a region 366 printed with special fluorescent ink that emits fluorescence when irradiated with ultraviolet rays. The printing in the region 366 is not visible in a normal state, but when the ultraviolet ray is irradiated, the printed content in the region 366 is fluorescent and the printed content is visually recognized. The presence of the area 366 and the print contents of the area 366 are not disclosed.

  When the game control board box is replaced with a fake (fake game control board box equipped with a fraudulent game control microcomputer), the area 366 does not exist in the fake game control board box. The authenticity of the game control board box can be determined. This is because even if the false game control board box is irradiated with ultraviolet rays, the printed content in the region 366 does not emit light.

  In this embodiment, the area 366 printed with the special fluorescent ink is provided on the surface of the game control board box, but on the surface of the game control microcomputer 560 accommodated in the game control board box, Printing may be performed with special fluorescent ink.

  Further, instead of printing with the special fluorescent ink, a change may be made to a predetermined portion of the game control board box. For example, the shapes of the three attachment holes in the attachment portions 31D and 31E may be different from each other. In that case, the shape looks the same at first glance, but changes so that the difference can be seen when measured with a measuring instrument. Further, the positions of the three mounting holes are not provided at regular intervals, but may be at irregular intervals. In that case, it appears to be equally spaced at first glance, but changes to such an extent that it can be seen that it is unequal when measured with a measuring instrument. Furthermore, when the game control board box is provided with a plurality of heat radiation holes, the shapes of the holes may be different from each other. In that case, the shape looks the same at first glance, but changes so that the difference can be seen when measured with a measuring instrument. In addition, it is not announced that there is a difference in the interval of holes or the shape of holes. In addition, the game control board box or the main board or the game control microcomputer 560 performs special processing that cannot be seen at first glance (for example, a mark or the like is placed at a position that is difficult to see). You may do it.

  If the game control board box is configured in this way, when the game control board box is replaced with a fake game control board box, the fake game will be used unless it is known that there is a difference in the original hole interval or hole shape. It is hard to think of making a difference in hole spacing, hole shape, etc. in the control board box. Also, it's hard to think of doing the same special processing that is done on the original game control board box. That is, when it is replaced with a fake game control board box, there will be no difference in the hole interval, hole shape, etc., or there will be no special processing, so the hole interval or hole The true / false of the game control board box can be determined by measuring the shape of the game or the presence or absence of special processing.

  In this embodiment, a model name sticker 31a and an inspection history sticker 31b are attached to the lid 31B. The inspection history seal 31b is provided with an “inspector” field and an “inspection date” field that are filled in when the main board 31 is inspected, repaired, or exchanged. In this example, the gaming machine A management number is also listed. The gaming machine management number is, for example, a unit number of a gaming control board box (a number uniquely assigned to each gaming control unit).

  Further, in this embodiment, as shown in FIG. 29, a hole (opening) for projecting the interruption button 361 is provided in the lid part 31B, and the pressing operation part of the interruption button 361 is exposed from the hole. ing.

  The connector portion of the main board 31 is exposed outside the lid portion 31B. In the example shown in FIG. 29, a connector 31C for inputting / outputting identification information is illustrated. However, the main board 31 is also mounted with other connectors for connection with other boards.

  As described above, the main board 31 is accommodated in the board box sealed by the unsealing fixing means, and the pressing operation part of the interruption button 361 is installed in the opening provided in the board box. Since it is configured, a game control process interruption signal from the interruption button 361 can be surely input to the main board 31 when an impersonation board is installed. Therefore, when an impersonation board is installed, a game control processing interruption signal from the interruption button 361 is input to the impersonation board, and the game is prevented from being interrupted even though the impersonation board is installed. be able to.

  FIG. 30 is an explanatory diagram showing an example of a mounting state of the interruption button 361 mounted on the main board 31 and an installation state of the state notification LED 61. FIG. 30 shows a cross section of the main board 31 and the lid 31B of the game control board box when the interrupt button 361 and the state notification LED 61 are mounted on the main board 31 housed in the game control board box. . As shown in FIG. 30, the interrupt button 361 is mounted on the board of the main board 31 in a state where the button pressing operation part is exposed from a hole (see FIG. 29) provided in the lid part 31B of the game control board box. Is done. Therefore, even if the main board 31 is sealed in the game control board box, the interrupt button 361 can be pressed. The interrupt button 361 only needs to be provided on the main board 31, and is positioned so as to protrude from the hole provided in the lid portion 31B of the game control board box or in the game control board box facing the hole. It may be.

  Further, it is desirable that the gap between the hole provided in the lid portion 31B of the game control board box and the pressing operation portion of the interruption button 361 be as narrow as possible. In other words, the hole provided in the lid portion 31B of the game control board box is formed so as to be largely blocked by the interrupt button 361 in order to ensure the sealed state of the game control board box. For example, the outer wall of the pressing operation portion of the interruption button 361 may come into contact with the inner wall of the hole provided in the lid portion 31B of the game control board box so that the pressing operation can be performed. Further, a cover made of a flexible material that covers the interruption button 361 does not come off unless it is broken in a state where the hole provided in the lid portion 31B of the game control board box is closed and the interruption button 361 can be pressed. You may make it install so. In this way, if the gap between the hole provided in the lid portion 31B of the game control board box and the pressing operation part of the interruption button 361 is made as narrow as possible, or if it is completely closed by the cover, the game control board box Since it is impossible to change the wiring of the main board 31 unless it is destroyed, it is possible to prevent the signal from the main board 31 from being taken out and output to the outside of the spoofed board or the like.

  In general, the lid 31B of the game control board box is transparent (in some cases, it may be colored, but even in that case, the inside of the game control board box can be visually recognized from the outside). The lighting state of the state notification LED 61 installed on the board 31 can be viewed from the outside of the game control board box. Further, in this embodiment, the state notification LED 61 is installed on the main board 31, but may be installed in a place other than the main board 31 in the game control board box.

  Next, the operation of the gaming machine will be described. FIG. 31 and FIG. 32 show the game control microcomputer 560 (specifically, the CPU 56 in response to the fact that power supply to the game machine is started and the reset signal to the game control microcomputer 560 becomes high level. This is a flowchart showing the main process executed by. When the input level of the reset terminal to which the reset signal is input becomes a high level, the CPU 56 executes a security check process that is a process for confirming whether the contents of the program are valid, and then performs a main process after step S1. To start. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, an interrupt mode for maskable interrupts is set (step S2), and a stack pointer designation address is set for the stack pointer (step S3). In step S2, the address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device indicates the interrupt address. Set to mode. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Next, the built-in device register is set (initialized) (step S4). By the processing in step S4, CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits) are set (initialized). The game control microcomputer 560 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC) 504.

  Next, the CPU 56 outputs an authentication signal (board ID uniquely given to the main board 31) to the verification terminal 364 (step S81), and sets the RAM 55 in an accessible state (step S5).

  Next, the CPU 56 checks the state of the output signal of the clear switch (for example, mounted on the power supply board) input via the input port (step S6). When the on-state is detected in the confirmation, the CPU 56 executes normal initialization processing (steps S10 to S15).

  If the clear switch is not on, check whether data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) was performed when power supply to the gaming machine was stopped (Step S7). When it is confirmed that such protection processing is not performed, the CPU 56 executes initialization processing. Whether there is backup data in the backup RAM area is confirmed, for example, by the state of the backup flag set in the backup RAM area in the power supply stop process.

  When it is confirmed that the power supply stop process has been performed, the CPU 56 performs data check of the backup RAM area (step S8). In this embodiment, a parity check is performed as a data check. Therefore, in step S8, the calculated checksum is compared with the checksum calculated and stored by the same process in the power supply stop process. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, an initialization process that is executed when the power is turned on is not performed when the power supply is stopped.

  If the check result is normal, the CPU 56 recovers the game state restoration process (steps S41 to S43) for returning the internal state of the game control means and the control state of the electrical component control means such as the effect control means to the state when the power supply is stopped. Process). Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (step S41), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (step S42). ). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result of the processing in step S41 and step S42, the saved contents remain as they are in the portion of the work area that should not be initialized. The parts that should not be initialized include, for example, data indicating the gaming state before the power supply is stopped (special symbol process flag, probability change flag, etc.), the area where the output state of the output port is saved (output port buffer), This is a portion where data indicating the number of payout prize balls is set.

  Further, the CPU 56 transmits a power failure recovery designation command as an initialization command at the time of power supply recovery (step S43). Then, the process proceeds to step S14.

  In this embodiment, it is confirmed whether the data in the backup RAM area is stored using both the backup flag and the check data. However, only one of them may be used. That is, either the backup flag or the check data may be used as an opportunity for executing the game state restoration process.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S10). The RAM clear process initializes predetermined data (for example, count value data of a counter for generating a big hit determination random number) to 0, but is initialized to an arbitrary value or a predetermined value. You may make it do. Alternatively, the entire area of the RAM 55 may not be initialized, and predetermined data (for example, count value data of a counter for generating a big hit determination random number) may be left as it is. Further, the start address of the initialization setting table stored in the ROM 54 is set as a pointer (step S11), and the contents of the initialization setting table are sequentially set in the work area (step S12).

  By the processing in steps S11 and S12, for example, an initial value is set to a flag (a flag indicating a gaming state) for selectively performing processing according to a control state such as a special symbol process flag or a normal symbol process flag.

  Further, the CPU 56 initializes a sub board (a board on which a microcomputer other than the main board 31 is mounted) (a command indicating that the game control microcomputer 560 has executed an initialization process). Is also transmitted to the sub-board (step S13). For example, when receiving the initialization designation command, the production control microcomputer performs a screen display for notifying that the control of the gaming machine has been initialized, that is, initialization notification on the variable display device 9.

  Further, the CPU 56 executes a random number circuit setting process for initial setting of the random number circuit 503 (step S14). For example, the CPU 56 performs setting according to the random number circuit setting program to cause the random number circuit 503 to update the value of the random R. The random number circuit 503 generates a random number using a predetermined clock signal. In this embodiment, the random number circuit 503 outputs any numerical value from 0 to 65535 to the CPU 56 when the numerical value is read from the CPU 56.

  In step S15, the CPU 56 sets a register of the CTC built in the game control microcomputer 560 so that a timer interrupt is periodically taken every predetermined time (for example, 2 ms). That is, a value corresponding to, for example, 2 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 2 ms.

  When the execution of the initialization process (steps S10 to S15) is completed, the CPU 56 repeatedly executes the display random number update process (step S17) and the initial value random number update process (step S18) in the main process. When executing the display random number update process and the initial value random number update process, the interrupt disabled state is set (step S16). When the display random number update process and the initial value random number update process are finished, the interrupt enabled state is set. Set (step S19). In this embodiment, the display random number is a random number for determining the variation pattern, and the display random number update process is a process for updating the count value of the counter for generating the display random number. The initial value random number update process is a process for updating the count value of the counter for generating the initial value random number. In this embodiment, the initial value random number is an initial value of a count value such as a counter for generating a random number for determining whether or not to win a normal symbol (ordinary random number generation counter for normal symbol determination). It is a random number for determining. A game control process for controlling the progress of the game, which will be described later (the game control microcomputer 560 controls game devices such as a variable display device, a variable winning ball device, a ball payout device, etc. provided in the game machine itself. In the process of transmitting a command signal to be controlled by another microcomputer, or a game machine control process), the count value of the random number for determination per normal symbol is one round (the random number for determination per normal symbol is taken). When the value is incremented by the number of values between the minimum value and the maximum value of the possible values), an initial value is set in the counter.

  Next, the random number circuit setting process (step S15) in the main process will be described. FIG. 33 is a flowchart showing random number circuit setting processing. In the random number circuit setting process, the CPU 56 first executes the process according to the random number circuit selection module 551f included in the random number circuit setting program 551, and from among the random number circuits 503a and 503b built in the game control microcomputer 560, the game A random number circuit to be used when executing the timer interrupt process including the control process is set (step S151). For example, the CPU 56 stores specification information for specifying the random number circuit 503 used when executing the timer interrupt process set by the user (for example, the manufacturer of the gaming machine) in a predetermined storage area of the RAM 55 in advance. Then, the CPU 56 selects either the 12-bit random number circuit 503a or the 16-bit random number circuit 503b in accordance with the designation information stored in the predetermined storage area of the RAM 55, and uses the selected random number circuit when executing the timer interrupt process. Set as a random number circuit. Note that both the 12-bit random number circuit 503a and the 16-bit random number circuit 503b may be set as random number circuits used when the timer interrupt process is executed. In this case, for example, the game control microcomputer may perform a jackpot determination based on a random number generated by the 12-bit random number circuit 503a and may perform a probability change determination based on the random number generated by the 16-bit random number circuit 503b. .

  When the CPU 56 sets the random number circuit 503 to be used in step S151, the counter 521 of the random number circuit that is set not to be used is stopped by stopping the operation of the counter 521 or the clock signal output circuit 524, for example. Do not update. Further, for example, the CPU 56 updates the count value C of the counter 521 of the random number circuit that is set not to use, but the CPU 56 does not output the output control signal SC and reads the random number from the random value storage circuit 531. You may control so that it may not come out. Further, for example, the CPU 56 prevents the random value fetch data “01 (H)” from being written into the random value fetch register 539 of the random number circuit that is set not to be used, and the latch signal generation circuit 533 causes the latch signal to be Control may be performed so that SL is not output to the random value storage circuit 531.

  As described above, by setting the random number circuit 503 to be used, by setting only the random number circuit 503 to be used, the range of the random number value to be generated can be appropriately set. Further, it is possible to prevent unnecessary random numbers from being processed during the execution of the timer interrupt process, and the control burden on the game control microcomputer 560 can be reduced. For example, when the big hit determination is performed using a determination table including a distant value (for example, “1” and “100”) as the big hit determination value, the big hit is determined with a predetermined big hit probability (for example, 1/100). In this case, the number of types of determination values to be processed is smaller when the random number by the 12-bit random number circuit 503a is used than when the random number by the 16-bit random number circuit 503b is used, and the game control microcomputer 560 is used. The control burden is reduced.

  Further, the CPU 56 executes processing in accordance with the random number maximum value setting module 551a included in the random number circuit setting program 551, and generates random number maximum value setting data for designating a random number maximum value preset by the user as a random number maximum value setting register 535. (Step S152). By doing so, the random number maximum value of random R preset by the user is set in the random number circuit 503. When the 12-bit random number circuit 503a is set as the random number circuit used when the timer interrupt is executed, the CPU 56 sets the random number maximum value that specifies the random number maximum value (any value from “0” to “4095”). Data is written into the random number maximum value setting register 535 of the 12-bit random number circuit 503a. When the 16-bit random number circuit 503b is set as the random number circuit used when the timer interrupt is executed, the CPU 56 sets the random number maximum value that specifies the maximum random number value (any value from “0” to “65535”). Data is written into the random number maximum value setting register 535 of the 16-bit random number circuit 503b.

  In this embodiment, when “0” to “255” are set as the random number maximum value, the random number maximum value is reset to a predetermined value in the random number maximum value resetting process described later. Even when control is performed to write a value greater than “256” as the random number maximum value, values “0” to “255” are set in the random number maximum value setting register 535 due to data corruption or the like. In the case where it is lost, the random number maximum value is reset to a predetermined value in the random number maximum value resetting process described later.

  As described above, since the maximum value of the random number to be generated is set in advance in the random number maximum value setting register 535 in step S152, a random number having a value larger than the range of random numbers used during execution of the timer interrupt process is generated. Can be prevented, and the processing load of the random number circuit 503 and the game control microcomputer 560 can be reduced.

  The CPU 56 checks whether the random number maximum value set in the random number maximum value setting register 535 in step S152 is not less than a predetermined lower limit value. If the random number maximum value is not more than the lower limit value, the random number maximum value setting register A random number maximum value resetting process for resetting the random number maximum value set in 535 is executed (step S153).

  Further, the CPU 56 executes a process according to the initial value change module 551e included in the random number circuit setting program 551, and executes an initial value change process for changing the initial value of the count value updated by the counter 521 of the random number circuit 503 (step). S154).

  Further, the CPU 56 executes processing in accordance with the random number update method selection module 551b included in the random number circuit setting program 551, and writes the random number update method selection data in the random number update method selection register 540 (step S155). By doing so, the random number update method of the random number circuit 503 is set. In this embodiment, it is assumed that the CPU 56 writes the random number update method selection data “10 (H)” in the random number update method selection register 540. That is, in this embodiment, the second random number update method is set as the random number update method of the random number circuit 503.

  Further, the CPU 56 executes processing according to the cycle setting module 551c included in the random number circuit setting program 551, and sets the cycle setting data (the reference clock signal by how many minutes) that specifies the cycle of the random number generation clock signal SI1 preset by the user. The data for setting whether to circulate) is written in the period setting register 537 (step S156). By doing so, the cycle of the random number generating clock signal SI1 preset by the user is set in the random number circuit 503.

  Further, the CPU 56 sets whether or not to update the initial value input to the counter 521 when the count value is updated to a predetermined final value by the counter 521 of the random number circuit 503 (step S157). For example, when the count value is updated to a predetermined final value by the counter 521, the CPU 56 sets a setting value indicating whether or not to update the initial value input to the counter 521 in advance in a predetermined area of the RAM 55. I remember it. Whether or not the CPU 56 updates the initial value input to the counter 521 when the counter 521 updates the count value to a predetermined final value according to a predetermined set value stored in a predetermined storage area of the RAM 55. Set In this embodiment, when the CPU 56 determines in step S157 that the initial value input to the counter 521 is to be updated, the count value is updated to a predetermined final value (when a notification signal is input from the counter 521). An initial value update flag indicating that the initial value is updated is set.

  Further, the CPU 56 sets whether or not to change the permutation of the count values updated by the counter 521 when the count value is updated to a predetermined final value by the counter 521 of the random number circuit 503 (step S158). For example, the CPU 56 sets a setting value indicating whether or not to change the permutation of the count value output from the counter 521 when the count value is updated to a predetermined final value by the counter 521, and is set in advance in the RAM 55. It is stored in a predetermined area. Then, the CPU 56 changes the permutation of the count values output by the counter 521 when the count value is updated by the counter 521 to a predetermined final value according to a predetermined set value stored in a predetermined storage area of the RAM 55. Set whether or not. In this embodiment, if the CPU 56 determines in step S158 that the permutation of the count values output from the counter 521 is to be changed, the CPU 56 changes the permutation of the count values when the count values are updated to a predetermined final value. The indicated count value permutation change flag is set. In this embodiment, the case where the count value permutation change flag is set in step S158 according to a predetermined set value will be described. Then, the CPU 56 changes the permutation of the count values output by the counter 521 based on the fact that the count value permutation change flag is set in the count value permutation changing process described later.

  Then, the CPU 56 executes processing according to the random number circuit activation module 551d included in the random number circuit setting program 551, and writes the random number circuit activation data “80 (H)” in the random number circuit activation register 541 (step S159). By doing so, the CPU 56 activates the random number circuit 503.

  Next, the random number maximum value resetting process (step S153) in the random number circuit setting process will be described. FIG. 34 is a flowchart showing the random number maximum value resetting process. In the random number maximum value resetting process, the CPU 56 reads the random number maximum value set in the random number maximum value setting register 535 (step S153a). When the 12-bit random number circuit 503a is set as the random number circuit used when the timer interrupt process is executed, the CPU 56 reads the random number maximum value set in the random number maximum value setting register 535 of the 12-bit random number circuit 503a. When the 16-bit random number circuit 503b is set as the random number circuit used when the timer interrupt process is executed, the CPU 56 reads the random number maximum value set in the random number maximum value setting register 535 of the 16-bit random number circuit 503b.

  The CPU 56 determines whether or not the read random number maximum value is equal to or less than a predetermined lower limit value (step S153b). When the 12-bit random number circuit 503a is set, the maximum random number that can be set in the 12-bit random number circuit 503a is from “256” to “4095”, so the CPU 56 sets the random number maximum value setting register 535 of the 12-bit random number circuit 503a. It is determined whether or not the maximum random number read from is lower limit value “256” or less. When the 16-bit random number circuit 503b is set, the maximum random number that can be set in the 16-bit random number circuit 503b is from “256” to “65535”. Therefore, the CPU 56 sets the random number maximum value of the 16-bit random number circuit 503b. It is determined whether the maximum random number value read from the register 535 is equal to or lower than the lower limit value “256”.

  When the read random number maximum value is less than or equal to the lower limit value, the CPU 56 resets the random number maximum value set in the random number maximum value setting register 535 to a predetermined value (step S153c). When the 12-bit random number circuit 503a is set, if the random number maximum value read from the random number maximum value setting register 535 of the 12-bit random number circuit 503a is determined to be less than or equal to the lower limit “256”, the CPU 56 determines the random number maximum value setting register 535. The random number maximum value set in is reset to a predetermined value “4095”. Further, when the 16-bit random number circuit 503b is set, if the random number maximum value read from the random number maximum value setting register 535 of the 16-bit random number circuit 503b is determined to be less than or equal to the lower limit value “256”, the CPU 56 sets the random number maximum value setting. The random number maximum value set in the register 535 is reset to a predetermined value “65535”.

  As described above, when the random number maximum value set in the random number maximum value setting register 535 is equal to or smaller than the predetermined lower limit value, the random number maximum value is reset to a predetermined value. Therefore, it is possible to prevent an excessively small value from being set as the maximum value of the random number due to a malfunction of the game control microcomputer 560 or an action such as generating a capture signal using a radio signal for the game machine. be able to. Therefore, it is possible to prevent a situation in which a random number having an excessively small value range from the minimum value to the maximum value is generated.

  Next, the initial value changing process (step S154) in the random number circuit setting process will be described. FIG. 35 is a flowchart showing the initial value changing process. In the initial value changing process, the CPU 56 first reads the initial value changing method setting data stored in the area of address 1F97 (H) in the user program execution data area, and specifies the initial value changing method selected by the user. . In this case, the CPU 56 determines whether or not the value of the read initial value change method setting data is “01 (H)” (step S154a), thereby specifying the initial value change method selected by the user. .

  When the value of the initial value change method setting data is “01 (H)”, the CPU 56 sets the initial value input to the counter 521 of the random number circuit 503 based on the ID number unique to the game control microcomputer 560. (Step S154b). For example, the CPU 56 stores, in a predetermined storage area of the RAM 55, the ID number of the game control microcomputer 560 and the calculated value obtained by performing a predetermined calculation based on the ID number in association with each other. In step S154b, the CPU 56 changes the initial value of the count value to the calculated value based on the ID number stored in advance. Further, for example, in step S154b, the CPU 56 calculates the ID number of the game control microcomputer 560 and a predetermined value (for example, the ID number (for example, “100”) to a predetermined value (for example, “100”). The initial value of the count value is set to the calculated value (for example, “200”). When the initial value input to the counter 521 is changed, the CPU 56 sets an initial value change flag indicating that the initial value of the count value has been changed (step S154c).

  When the CPU 56 changes the initial value input to the counter 521 in step S154b, the CPU 56 checks the value of the random number maximum value setting register 535 of the comparator 522 of the random number circuit 503, and the value set based on the ID number is determined. It is determined whether or not it is greater than the maximum random number. If it is determined that the value set based on the ID number is equal to or greater than the maximum random number, the CPU 56 does not change the initial value input to the counter 521 (for example, the initial value remains “0” and does not change). By doing so, it is possible to prevent a situation where the initial value of the count value is set to a value equal to or greater than the random number maximum value.

  In step S154a, when the value of the initial value change method setting data is not “01 (H)” (that is, the value of the initial value change method setting data stored in the area of address 1F97 (H) in the user program execution data area) CPU is not “00 (H)”), the CPU 56 does not change the initial value of the count value, ends the initial value changing process as it is, and proceeds to step S155.

  By executing the random number circuit setting process, various signals are input to the random number circuit 503 when the timer interrupt process including the game control process is performed, and various signals are generated in the random number circuit 503. FIG. 36 is a timing chart showing the timing at which each signal is input to the random number circuit 503 and the timing at which each signal is generated in the random number circuit 503.

  As shown in FIG. 36, the clock circuit 501 increases the signal level of the output terminal from a low level to a high level at predetermined intervals (timing T11, T21,... Shown in FIG. 36). A reference clock signal CLK (see FIG. 36A) is input to 503.

  The clock signal output circuit 524 divides the reference clock signal CLK supplied from the clock circuit 501 to generate a random number generation clock signal SI1 (see FIG. 36B). For example, the clock signal output circuit 524 raises the signal level of the output terminal from the low level to the high level at timings T11, T12,..., And changes the signal level from the high level to the low level at timings T21, T22,. To output a random number generating clock signal SI1.

  In the example shown in FIG. 36, for ease of explanation, the clock signal output circuit 524 divides the reference clock signal CLK by two to generate the random number generating clock signal SI1. However, in an actual random number circuit, the period that can be set in the period setting register 537 is from “system clock signal period × 128 × 7” to “system clock signal period × 128 × 256”. Therefore, in an actual random number circuit, the clock signal output circuit 524 is set in the cycle setting register 537 in a range from “system clock signal cycle × 128 × 7” to “system clock signal cycle × 128 × 256”. The reference clock signal CLK is divided by a frequency division ratio corresponding to the cycle setting data “07 (H)” to “FF (H)” to generate a random number generating clock signal SI1. The random number generating clock signal SI 1 generated by the clock signal output circuit 524 is output to the selector 528 and the inverting circuit 532.

  In this embodiment, since the second random number update method is set in the random number circuit setting process, the second random number update method selection signal is input from the random number update method selection signal output circuit 527 to the selector 528. When the second random number update method selection signal output circuit 527 receives the second random number update method selection signal output circuit 527, the selector 528 selects the random number generation clock signal SI1 input from the clock signal output circuit 524 and outputs it to the counter 521. . The counter 521 updates the count value C and outputs it to the count value permutation change circuit 523 every time the rising edge of the random number generation clock signal SI1 supplied from the selector 528 is input.

  The inversion circuit 532 generates the inverted clock signal SI2 (see FIG. 36C) by inverting the signal level of the random number generation clock signal SI1 input from the clock signal output circuit 524. For example, the inverting circuit 532 lowers the signal level of the output terminal from the high level to the low level at timings T11, T12,..., And the signal level from the low level to the high level at timings T21, T22,. As a result, the inverted clock signal SI2 is output. Further, the inverted clock signal SI <b> 2 generated by the inverting circuit 532 is output to the latch signal generating circuit 533.

  When a predetermined time (for example, 3 milliseconds) elapses after the winning detection signal SS (see FIG. 36D) is input to the timer circuit 534, the latch signal generation circuit 533 receives a disturbance from the random value read signal output circuit 526. A numerical reading signal is input. For example, when the signal level of the output terminal of the random number read signal output circuit 526 rises from a low level to a high level, the random value read signal is input to the latch signal generation circuit 533. The latch signal generation circuit 533 inverts the random value read signal input from the random value read signal output circuit 526 in response to the input of the second random number update method selection signal from the random number update method selection signal output circuit 527. In synchronization with the rising edge of the inverted clock signal SI2 supplied from 532, the latch signal SL (see FIG. 36E) is output.

  As described above, the random number circuit 503 updates the count value C at the timings T11, T12, T13..., And outputs the latch signal SL at the timing T22 different from the timings T11, T12, T13. The random number value is stored in 531.

  Next, the game control process will be described. FIG. 37 is a flowchart showing the timer interrupt process. When a timer interrupt occurs during execution of the main process, specifically, during a period when the interrupt is permitted during execution of the loop process of steps S16 to S19, the CPU 56 performs steps S20 to S20 shown in FIG. The timer interrupt process of S35 is executed. In the timer interrupt process, the CPU 56 determines whether or not a game control process interruption signal from the interruption button 361 is input (step S85). If no game control process interruption signal is input (N in step S85). Then, the processing after step S20 is executed. If the game control process interruption signal is inputted, the state of the game control process interruption signal is monitored until the game control process interruption signal is not inputted, and the execution of the processes after step S20 is interrupted.

  In step S20, the CPU 56 executes a power-off process (power-off detection process) for detecting whether or not a power-off signal is output (whether the power-off signal is turned on). The power-off signal is output when, for example, a voltage drop monitoring circuit mounted on the power supply board 910 detects a drop in the voltage of the power supplied to the gaming machine. In the power-off detection process, when detecting that the power-off signal has been output, the CPU 56 executes a power supply stop process for saving necessary data in the backup RAM area. Next, detection signals of the gate switch 32a, the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a are input via the input driver circuit 58, and the state determination is performed (switch processing). : Step S21).

  Next, the CPU 56 executes display control processing for performing display control of the special symbol display 8, the normal symbol display 10, the special symbol hold storage display 18, and the normal symbol hold storage display 41 (step S22). For the special symbol display 8 and the normal symbol display 10, control for outputting a drive signal to each display is executed according to the contents of the output buffer set in steps S32 and S33.

  Next, the CPU 56 checks whether the initial value is set to be updated when the count value is updated to a predetermined final value in the random number circuit setting process (see step S157), and the counter of the random number circuit 503 is checked. A process of updating the initial value input to 521 is performed (initial value update process: step S22A).

  Further, the CPU 56 performs a process of updating the count value of each counter for generating a random number for determination such as a random number for determining a symbol per normal symbol (determination random number update process: step S23). The CPU 56 further performs a process of updating the count value of the counter for generating the initial value random number and the display random number (initial value random number update process, display random number update process: steps S24 and S25).

  Further, the CPU 56 performs a count value permutation changing process for causing the count value permutation changing circuit 523 to change the permutation of the count values output from the counter 521 of the random number circuit 503 (step S25A). In this embodiment, whether or not to execute the count value permutation change process is determined depending on whether or not the count value permutation change flag is set in step S158 of the random number circuit setting process. Then, the CPU 56 executes the count value permutation change process based on the fact that the count value permutation change flag is set.

  Further, the CPU 56 performs special symbol process processing (step S26). In the special symbol process, the corresponding symbol is executed in accordance with a special symbol process flag for controlling the special symbol display 8 and the special winning award in a predetermined order. The CPU 56 updates the value of the special symbol process flag according to the gaming state.

  Next, normal symbol process processing is performed (step S27). In the normal symbol process, the CPU 56 executes a corresponding process according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The CPU 56 updates the value of the normal symbol process flag according to the gaming state.

  Further, the CPU 56 performs a process of sending an effect control command to the effect control microcomputer (effect control command control process: step S28).

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer, for example (step S29).

  Further, the CPU 56 executes prize ball processing for setting the number of prize balls based on the detection signals of the start port switch 14a, the count switch 23, and the prize opening switches 29a, 30a, 33a, 39a (step S30). Specifically, the payout control mounted on the payout control board 37 in response to winning detection based on any of the start opening switch 14a, the count switch 23 and the winning opening switches 29a, 30a, 33a, 39a being turned on. The payout control command (prize ball number signal) indicating the number of prize balls is output to the microcomputer. The payout control microcomputer drives the ball payout device 97 in response to a payout control command indicating the number of winning balls.

  In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided. However, the CPU 56 relates to on / off of the solenoid in the RAM area corresponding to the output state of the output port. The contents are output to the output port (step S31: output process).

  Further, the CPU 56 performs special symbol display control processing for setting special symbol display control data for effect display of the special symbol in the output buffer for setting the special symbol display control data according to the value of the special symbol process flag ( Step S32). For example, if the variation speed is 1 frame / 0.2 seconds until the end flag is set when the start flag set in the special symbol process is set, the CPU 56, for example, every 0.2 seconds passes. Then, the value of the display control data set in the output buffer is incremented by one. Further, the CPU 56 performs variable display of the special symbol on the special symbol display 8 by outputting a drive signal in step S22 according to the display control data set in the output buffer.

  Further, the CPU 56 performs a normal symbol display control process for setting normal symbol display control data for effect display of the normal symbol in an output buffer for setting the normal symbol display control data according to the value of the normal symbol process flag ( Step S33). For example, when the start flag related to the variation of the normal symbol is set, the CPU 56 switches the display state (“◯” and “×”) for the variation rate of the normal symbol every 0.2 seconds until the end flag is set. With such a speed, the value of the display control data set in the output buffer (for example, 1 indicating “◯” and 0 indicating “x”) is switched every 0.2 seconds. Further, the CPU 56 outputs a normal signal on the normal symbol display 10 by outputting a drive signal in step S22 according to the display control data set in the output buffer.

  Further, the CPU 56 performs a state notification LED control process for controlling the lighting state of the state notification LED 61 in accordance with the gaming state (step S34).

  Thereafter, the interrupt permission state is set (step S35), and the process is terminated.

  With the above control, in this embodiment, the game control process is started every 2 ms. The game control process corresponds to the processes in steps S21 to S33 (excluding step S29) in the timer interrupt process. In this embodiment, the game control process is executed by the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process is performed by the main process. May be executed.

  Further, the CPU 56 executes a process for counting the number of times the timer interrupt process has been executed. In this embodiment, each time the timer interrupt process is executed, the CPU 56 counts up an interrupt counter that indicates the number of times the timer interrupt process has been executed. For example, when the output process of step S31 is completed, the CPU 56 adds 1 to the value of the interrupt number counter indicating the number of times the timer interrupt process has been executed.

  Next, the initial value update process (step S22A) in the timer interrupt process will be described. FIG. 38 is a flowchart showing the initial value update process. In the initial value update process, the CPU 56 checks the state of the notification signal indicating that the count value C output from the counter 521 of the random number circuit 503 has been updated to the final value (step S220). When it is detected that the notification signal is in the on state, the CPU 56 checks whether or not the initial value update flag is set (step S221). That is, in the random number circuit setting process, the CPU 56 checks whether or not the setting for updating the initial value is made when the count value is updated to a predetermined final value (see step S157).

  When the initial value update flag is set, the CPU 56 determines to update the initial value input to the counter 521 when the counter 521 of the random number circuit 503 updates the count value to a predetermined final value. When the initial value update flag is set, the CPU 56 checks whether or not the initial value change flag is set (step S222). That is, the CPU 56 determines whether or not the initial value of the count value is currently changed (that is, whether or not it is changed to a value based on the ID number of the CPU 56).

  When the initial value change flag is set (that is, when the initial value is currently changed based on the ID number of the game control microcomputer 560), the CPU 56 uses the initial value input to the counter 521 as the game control. The value based on the ID number of the microcomputer 560 is returned to the original value (for example, “1”) (step S223). Then, the CPU 56 resets the initial value change flag (step S224) and ends the initial value update process.

  If the initial value change flag is not set (that is, the initial value is not currently changed), the CPU 56 changes the initial value input to the counter 521 to a value based on the ID number of the game control microcomputer 560. (Step S225). In this case, for example, if the ID number of the game control microcomputer 560 is “100”, the initial value input to the counter 521 is calculated by adding a predetermined value “100” to the ID number “100”. Change to the value “200”. Further, for example, the initial value input to the counter 521 is changed to the calculated value “50” obtained by subtracting the predetermined value “50” from the ID number “100”. Then, the CPU 56 sets an initial value change flag (step S226) and ends the initial value update process.

  When both the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are set, in step S225, the CPU 56 uses the random number read from one random number circuit (for example, the 12-bit random number circuit 503a) as a predetermined value as an ID number. The initial value input to the counter 521 may be obtained. Then, the CPU 56 may use a random number read from the other one (for example, a 16-bit random number circuit 503b) as a random number for determining the big hit.

  When the CPU 56 updates the initial value input to the counter 521 in step S225, the CPU 56 checks the value of the random number maximum value setting register 535 of the comparator 522 of the random number circuit 503, and the value set based on the ID number is obtained. It is determined whether or not it is greater than the maximum random number. If the CPU 56 determines that the value set based on the ID number is equal to or greater than the maximum random number, the CPU 56 does not update the initial value input to the counter 521 with a predetermined value (for example, updates with the predetermined value “0”). do not do). By doing so, it is possible to prevent a situation where the initial value of the count value is set to a value equal to or greater than the random number maximum value.

  If it is determined in step S220 that the notification signal is in the OFF state, or if it is determined in step S221 that the initial value update flag is not set, the CPU 56 does not update the initial value input to the counter 521. Then, the initial value update process is finished as it is, and the routine goes to Step S23.

  Next, the count value permutation change process (step S25A) in the timer interrupt process will be described. FIG. 39 is a flowchart showing the count value permutation changing process. The CPU 56 performs a count value permutation change process by executing a process according to the count value permutation change program 554. In the count value permutation change process, the CPU 56 checks the state of the notification signal indicating that the count value C output from the counter 521 of the random number circuit 503 has been updated to the final value (step S241). When it is detected that the notification signal is in the on state, the CPU 56 checks whether or not the count value permutation change flag is set (step S242). That is, the CPU 56 determines whether or not the setting for changing the permutation of the count values updated by the counter 521 when the count values are updated to a predetermined final value has been made in the random number circuit setting process (see step S158). Check.

  When the count value permutation change flag is set, the CPU 56 determines that the permutation of the count values updated by the counter 521 is changed when the counter 521 of the random number circuit 503 updates the count value to a predetermined final value. Then, the CPU 56 writes the count value permutation change data “01 (H)” in the count value permutation change register 536 (step S243). That is, the CPU 56 causes the count value permutation change circuit 523 to change the permutation of the count values C input to the random value storage circuit 531 by writing the count value permutation change data “01 (H)”.

  As described above, in the count value permutation changing process, when the random number is updated to a predetermined final value, the permutation of the count value updated by the counter 521 is changed, so that the randomness generated by the random number circuit 503 is more random. Can be improved.

  FIG. 40 is a flowchart showing an example of the special symbol process (step S26) executed by the game control microcomputer 560 (specifically, the CPU 56). In the special symbol process, a process for controlling the special symbol display 8 and the special prize opening is executed. In the special symbol process, the CPU 56 performs the start opening switch passing process if the start opening switch 14a for detecting that the game ball has won the start winning opening 14 is turned on, that is, if a start winning is generated. Execute (Steps S311 and S312). Then, any one of steps S300 to S307 is performed.

  The processes in steps S300 to S307 are as follows.

  Special symbol normal processing (step S300): Executed when the value of the special symbol process flag is zero. When the game control microcomputer 560 is ready to start the variable display of the special symbol, it checks the number of reserved memories (the number of start winning memories). If the number of reserved memories is not 0, it is determined whether or not to win. If it is determined to be a big hit, a big hit flag is set. Then, the internal state (special symbol process flag) is updated to a value (1 in this example) corresponding to step S301. It should be noted that determining whether or not to win is also determining whether or not the display results of the special symbol and the decorative symbol are to be the jackpot symbol.

  Fluctuation pattern setting process (step S301): This process is executed when the value of the special symbol process flag is 1. The stop symbol after the variable display of the special symbol is determined. Also, the variation pattern is determined, and the variation time in the variation pattern (variable display time: the time from the start of variable display until the display result is derived and displayed (stop display)) Decide to do. Also, a command that can specify the variation time is transmitted to the effect control microcomputer, the variation of the special symbol is started, and a variation time timer that measures the variation time of the special symbol is started. Then, the internal state (special symbol process flag) is updated to a value (2 in this example) corresponding to step S302. The effect control microcomputer controls the variable display device 9 so that the variation of the decorative pattern is started when the command that can specify the variation time transmitted by the game control microcomputer 560 is received.

  Display result specifying command transmission process (step S302): executed when the value of the special symbol process flag is 2. Control is performed to transmit a display result specifying command, which is a command that can specify the display result of the decorative design, to the effect control microcomputer. Then, the internal state (special symbol process flag) is updated to a value (3 in this example) corresponding to step S303.

  Special symbol changing process (step S303): This process is executed when the value of the special symbol process flag is 3. When the variation time of the variation pattern selected in the variation pattern setting process elapses (the variation time timer set in step S301 times out, that is, the variation time timer value becomes 0), the internal state (special symbol process flag) is stepped. Update to a value corresponding to S304 (4 in this example).

  Special symbol stop process (step S304): executed when the value of the special symbol process flag is 4. The variable display on the special symbol display 8 is stopped and the stop symbol is derived and displayed. Further, control is performed to transmit a symbol confirmation designation command for instructing stop of the variation of the decorative symbol to the effect control microcomputer. If the big hit flag is set, the internal state (special symbol process flag) is updated to a value (5 in this example) corresponding to step S305. When the big hit flag is not set, the internal state (special symbol process flag) is updated to a value (0 in this example) corresponding to step S300. The effect control microcomputer controls the variable display device 9 so that the decorative symbols are stopped when the symbol confirmation designation command transmitted by the game control microcomputer 560 is received.

  Preliminary winning opening opening process (step S305): This is executed when the value of the special symbol process flag is 5. In the pre-opening process for the big prize opening, control for opening the big prize opening is performed. Specifically, a counter (for example, a counter that counts the number of game balls that have entered the big prize opening) is initialized, and the solenoid 21 is driven to open the big prize opening. Also, the execution time of the special prize opening opening process is set by the timer, and the internal state (special symbol process flag) is updated to a value corresponding to step S306 (6 in this example). The pre-opening process for the big winning opening is executed for each round, but when the first round is started, the pre-opening process for the big winning opening is also a process for starting the big hit game.

  Large winning opening opening process (step S306): This process is executed when the value of the special symbol process flag is 6. A control for transmitting an effect control command for round display during the big hit gaming state to the microcomputer for effect control, a process for confirming the establishment of the closing condition of the big prize opening, and the like are performed. If the closing condition for the special prize opening is satisfied and there are still remaining rounds, the internal state (special symbol process flag) is updated to a value (5 in this example) corresponding to step S305. When all the rounds are completed, the internal state (special symbol process flag) is updated to a value corresponding to step S307 (7 in this example).

  Big hit end process (step S307): executed when the value of the special symbol process flag is 7. Control is performed to cause the microcomputer for effect control to perform display control for notifying the player that the big hit gaming state has ended. Further, a process for setting a flag (for example, a probability variation flag) indicating a gaming state is performed. Then, the internal state (special symbol process flag) is updated to a value (0 in this example) corresponding to step S300.

  FIG. 41 is a flowchart showing the start port switch passage process (step S312). In the start port switch passing process, the CPU 56 outputs an authentication signal (a board ID uniquely given to the main board 31) to the verification terminal 364 (step S320). Next, it is confirmed whether or not the start winning memory number (or the starting winning memory number stored in the special figure holding memory 570) indicated by the start winning counter has reached the maximum value of 4 (step S321). If the start winning memory number has not reached 4, the CPU 56 checks whether or not the number of executions of the timer interruption process indicated by the interruption execution number counter has reached a predetermined number (for example, 3 times) (step). S322). When detecting that the game ball has won the start winning opening 14, the CPU 56 resets the interrupt execution counter. Then, after the game ball has won the start winning opening 14, the CPU 56 checks whether or not the interrupt execution counter has reached a predetermined number.

  The value set in advance as the predetermined number of times in step S322 is determined as follows. As described above, the timer circuit 534 of the random number circuit 503 measures the time that the winning detection signal SS is continuously input from the start port switch 14a, and detects that the measurement time has reached a predetermined period, Write numerical value capture data “01 (H)”. In this embodiment, a predetermined period (for example, 3 ms) measured by the timer circuit 534 is a period in which a predetermined number of timer interrupt processes are executed (for example, when the timer interrupt process for every 2 ms is executed three times). The predetermined number of times (for example, 3 times) used in step S322 is set so as to be shorter than 6 ms). By setting in this way, it is possible to prevent the random number from being read again after the random number is read and before the random number value stored in the random value storage circuit 531 is updated. It is possible to prevent a random number having the same value as the random number read from the circuit 531 from being read again.

  When the number of executions of the timer interrupt processing has reached a predetermined number, the CPU 56 can output the output control signal SC to the random number value storage circuit 531 of the specified random number circuit 503 and read the random number value storage circuit 531 (enable). The state is controlled (step S323).

  The CPU 56 reads the random R value stored as the random number value from the random value storage circuit 531 of the random number circuit 503 (step S324). Further, the CPU 56 stores the read random R value in, for example, a predetermined buffer area provided in the RAM 55 (step S325). When the CPU 56 stores the value of the random R in the buffer area, the CPU 56 stops outputting the output control signal SC to the random value storage circuit 531 and controls the random value storage circuit 531 to be unreadable (disabled) ( Step S326). In addition, the CPU 56 resets the interrupt execution number counter (step S327). Then, the CPU 56 sets the value of the random R stored in the predetermined buffer area to the head of the empty entry in the special figure reservation memory 570 (step S328), and adds 1 to the count number of the start winning counter, thereby storing the start winning memory. The number is incremented by 1 (step S329).

  If the start prize is stored in step S321 but the maximum value of 4 has been reached, and if the number of executions of the timer interrupt process has not reached the predetermined number in step S322, the start port switch passing process is terminated.

  As described above, the timer interrupt process has been executed a predetermined number of times in reading the random R from the random value storage circuit 531 in the starting port switch passing process (that is, continued while the timer interrupt process is executed a predetermined number of times). The random number is read from the random value storage circuit 531 on the condition that the winning detection signal SS is input). Therefore, it is possible to prevent the random number from being read again after the random number is read and before the value of the random number stored in the random value storage circuit 531 is updated. Further, it is possible to prevent a random number having the same value as the random number read from the previous random number value storage circuit 531 from being read again.

  FIG. 42 is an explanatory diagram showing the relationship between the lighting state of the state notification LED 61 mounted on the main board 31 and the gaming state. When the special symbol and the decorative symbol do not change and when the big hit game is not being played, as shown in FIG. That is, it is a lighting continuation state. 42A, 42B, and 42C, the upper row shows the lighting state of the state notification LED 61 (lit, extinguished, or blinking), and the lower row is The timing for switching on and off is shown. In addition, the upper part of FIGS. 42A, 42B, and 42C shows the state of the state notification LED 61 that is displayed in black.

  When the special symbol and the decorative symbol are fluctuating, lighting for 2 seconds and turning off for 2 seconds are repeated as shown in FIG. That is, it blinks at intervals of 2 seconds. Hereinafter, blinking at intervals of 2 seconds is referred to as slow blinking. During the big hit game, as shown in FIG. 42C, lighting for 0.5 seconds and turning off for 0.5 seconds are repeated. That is, it blinks at 0.5 second intervals. Hereinafter, flashing at intervals of 0.5 seconds is referred to as high-speed flashing.

  The relationship between the lighting state of the state notification LED 61 and the gaming state shown in FIG. 42 is an example, and is at least during a symbol variation, a big hit game, during a symbol variation and a big hit game (hereinafter referred to as a normal state). If the flashing mode (notification mode) is different, a notification mode different from the notification mode shown in FIG. 42 may be used. The notification mode includes a lighting continuation mode and a flashing mode, but in a normal state, the condition that the light is turned off is a predetermined time (for example, 5 seconds) or less. That is, it is a condition that the period during which no notification is made does not become long. In other words, it is a condition that control is performed so as to avoid a state in which notification is not made over a predetermined time when power is supplied to the main board 31. Since power is supplied to the game control microcomputer 560 and the status notification LED 61 in a state where power is supplied to the main board 31, the status notification LED 61 can perform notification, but the period during which it is turned off is long. This is because it cannot be distinguished from a state in which power is not supplied to the main board 31 (a state in which an impersonation board may be mounted). In this embodiment, when power is supplied to the main board 31, the state notification LED 61 is informed by being continuously lit or in a blinking state. Further, in order to make it difficult for an unauthorized person to recognize the notification mode of the state notification LED 61, the notification mode may be made more complicated.

  Further, in this embodiment, the game state that changes the state of notification of the state notification means (in this example, the state notification LED 61) is divided into “during symbol variation”, “during big hit game”, and “normal state”. The gaming state in which the notification mode is different is not limited to these, and various states are conceivable. For example, “Status of number of reserved memory”, “Opening / closing state of variable winning device”, “High probability state (probability changing state)”, “Variation shortening state of special symbol or normal symbol”, “Open extension of variable winning device The notification mode may be varied depending on the “state”.

  FIG. 43 is a flowchart showing the state notification LED control process in step S34 (see FIG. 37). In the state notification LED control process, the CPU 56 checks whether or not a big hit game is being played (step S901). Whether or not the jackpot game is in progress is confirmed by, for example, whether or not the value of the special symbol process flag is a value indicating that the jackpot game is being played (in this embodiment, 5, 6 or 7: see FIG. 40). it can.

  If it is during the big hit game, the CPU 56 checks whether or not the value of the blinking timer for determining the turn-on time and turn-off time for blinking is 0 (step S902). If it is 0, the lighting state of the state notification LED 61 is switched (step S903). That is, when the state notification LED 61 is turned on, the state notification LED 61 is turned off, and when the state notification LED 61 is turned off, the state notification LED 61 is turned on. In order to turn on or turn off the status notification LED 61, a value (for example, 1) corresponding to lighting is output to an output port that outputs a signal reaching the status notification LED 61 via the LED circuit 60, or is turned off. A corresponding value (for example, 0) is output. When a value corresponding to lighting is output to the output port, the lighting state flag in the RAM 55 is set to 1, for example, and when a value corresponding to lighting is output to the output port, The lighting state flag is set to 0, for example. With such control, the CPU 56 can determine whether or not the state notification LED 61 is lit based on the lighting state flag. Then, the CPU 56 sets a value corresponding to 0.5 seconds in the blinking timer (step S904).

  If the value of the blinking timer is not 0, the CPU 56 decrements the value of the blinking timer by 1 (step S905).

  If it is not during the big hit game, the CPU 56 checks whether or not the special symbol and the decorative symbol are changing (step S906). Whether or not it is changing can be confirmed, for example, by checking whether or not the value of the special symbol process flag is a value indicating that it is changing (in this embodiment, refer to 3: FIG. 40). If it is changing, the CPU 56 checks whether or not the value of the blinking timer is 0 (step S907). If it is 0, the lighting state of the state notification LED 61 is switched (step S908). That is, when the state notification LED 61 is turned on, the state notification LED 61 is turned off, and when the state notification LED 61 is turned off, the state notification LED 61 is turned on. Then, the CPU 56 sets a value corresponding to 2 seconds in the blinking timer (step S909).

  When the value of the blinking timer is not 0, the CPU 56 decrements the value of the blinking timer by −1 (step S910).

  If the special symbol and the decorative symbol are not changing, the state notification LED 61 is turned on (step S911).

  As described above, in this embodiment, the random number circuit 503 is initially set (random number circuit setting process) from the start of power-on to the gaming machine until the timer interrupt is set, and the random number circuit In the setting process, a value based on the ID number unique to the game control microcomputer 560 is set as the initial value of the random number. Therefore, the randomness of the random number generated by the random number circuit 503 can be improved. In addition, since randomness of random numbers can be improved, the timing of random number generation can be made difficult to be recognized by a player or a game store, and a capture signal using a radio signal can be generated for a gaming machine. It is possible to prevent the condition for shifting to a specific gaming state such as a big hit state from being illegally established.

  In this embodiment, the same ID is used for the ID used for collation and the ID for setting the initial value of the random number. However, separate IDs may be used.

  In this embodiment, the inverting circuit 532 of the random number circuit 503 generates the inverted clock signal SI2 whose polarity is inverted, and outputs a latch signal for instructing storage of the random number in synchronization with the inverted clock signal SI2. . Therefore, the timing for updating the random number and the timing for storing the random number in the random value storage circuit 531 can be shifted, and the generated random number can be stored stably and reliably.

  In this embodiment, the CPU 56 is configured to interrupt the game control process in response to the input of the game control process interrupt signal (interrupt operation signal) from the interrupt button 361. The game control process can be intentionally interrupted. Then, when the intentional interruption is impossible, it can be determined that an illegal circuit board (impersonation board) is installed, and the illegal circuit board can be easily found.

  In this embodiment, as an example of interrupting the game control process, the case where the loop process is performed according to the control program while the game control process interrupt signal is input has been described. However, the interrupt operation signal is input. It is only necessary to stop the game, and various methods for stopping the game can be taken. For example, the game control process may be interrupted by a known or publicly known method such as stopping the power supply to the gaming machine (that is, turning off the power). Further, for example, the processing of the CPU 56 may be stopped (system reset) so as to “interrupt the game control processing”, or the output of all control signals output from the game control microcomputer 560 may be stopped. The “game control process may be substantially interrupted”.

  Furthermore, in this embodiment, in the game control board box that accommodates the main board 31, a state notification LED 61 that changes the notification mode according to the gaming state is provided. As shown in FIG. 28, when the impersonation board 31X is installed and the power is supplied from the impersonation board 31X to the main board 31, the CPU 56 of the main board 31 is operating, so the collator 365 is used. When verification is performed, the verification target is OK because the authentication target is not the spoofing board 31X but the main board 31. However, the variation of the special design and the decorative design is controlled by the microcomputer mounted on the spoofing substrate 31X. Therefore, the CPU 56 of the main board 31 that is not controlling the fluctuation does not recognize that the special symbol and the decorative symbol are fluctuating, and therefore does not cause the state notification LED 61 to blink. Therefore, when mounted on the spoofing substrate 31X, the state notification LED 61 continues to be lit during the symbol variation (it remains in the normal state notification mode), so that the state notification LED 61 blinks. It is inspected that an illegal board is installed depending on whether or not. For example, it is possible to easily inspect whether or not an illegal board is installed by starting a change in the design by inserting a game ball into the start winning opening 14. The big hit game is controlled by a microcomputer mounted on the spoofing board 31X. Therefore, during the big hit game, the CPU 56 of the main board 31 does not recognize the big hit game state, and therefore does not blink the state notification LED 61. Therefore, when mounted on the spoofing substrate 31X, the state notification LED 61 continues to be lit during the symbol variation (it remains in the normal state notification mode), so that the state notification LED 61 blinks. It is inspected that an illegal board is installed depending on whether or not.

  Further, when the spoofing board 31X is installed and no power is supplied to the main board 31, the state notification LED 61 is not lit. As described above, in this embodiment, when power is supplied to the main board 31, the state notification LED 61 is lit in the normal state. Therefore, in the state where the power of the gaming machine is turned on, whether or not the unauthorized board is installed can be easily confirmed by whether or not the state notification LED 61 is lit.

Embodiment 2. FIG.
In the first embodiment, the game control process is interrupted using the interrupt button 361 to discover whether the impersonation board is installed. However, without using the interrupt button 361, It may be made to discover whether the impersonation board | substrate is installed as shown in.

  In the present embodiment, detailed description of the same configuration and processing as those in the first embodiment is omitted, and the portions different from those in the first embodiment and the first embodiment are mainly described. Then, the part which abbreviate | omitted description is demonstrated.

  FIG. 44 is a block diagram showing an example of the circuit configuration of the main board 31 in this embodiment. 44 also shows a payout control board 37, a lamp driver board 35, an audio output board 70, an interface board 66, a relay board 77, and an effect control board 80 mounted on the gaming machine. Unlike the example shown in FIG. 4, the interrupt button 361 is not mounted on the main board 31. Further, unlike the example shown in FIG. 4, the main board 31 has an unpaid excess LED 362 that is turned on when the number of unpaid game balls exceeds a predetermined number, and a winning that is turned on when a winning occurs. A notification lamp 363 is mounted.

  Next, payout control signals transmitted and received between the main board 31 and the payout control board 37 will be described. FIG. 45 shows the contents of the payout control signal output from the game control microcomputer 560 to the payout control microcomputer 370 and the payout control signal input from the payout control microcomputer 370 to the game control microcomputer 560. It is explanatory drawing which shows an example. In this embodiment, a plurality of types of control signals are transmitted and received (two-way communication) between the main board 31 and the payout control board 37 in order to perform various controls relating to payout control and the like.

  As shown in FIG. 45, the power supply confirmation signal rises (turns on when the main board 31 rises (when the game control microcomputer 560 enters a state in which the progress of the game can be controlled after the start of power supply). This is a signal for notifying the payout control board 37 that the main board 31 has risen (connection confirmation signal for the main board 31). The power supply confirmation signal indicates that the prize ball payout is permitted. That is, the game control microcomputer 560 can prevent the payout control microcomputer 370 from paying out a prize ball by turning off the power confirmation signal. If the payout control microcomputer 370 detects that the power supply confirmation signal is turned off during the payout of the prize ball, the payout control microcomputer 370 completes the number of prize balls to be paid out at that time. At this point, the system shifts to a state in which the prize ball payout process is not executed.

  The payout REQ signal is a signal (that is, a trigger signal for a prize ball payout request) that becomes an output state (= ON state) when a prize ball payout request is made. The payout REQ signal is stopped (off state) when a reception confirmation signal from the payout control microcomputer 370 is turned on.

  The payout number signal is a signal (prize ball number command) that is output to designate the number of game balls (for example, 1 to 15) that make a payout request. The payout number signal is received when the game control microcomputer 560 (specifically, the CPU 56) detects that the reception confirmation signal is turned on in the prize ball standby state or after the payout REQ signal is transmitted. It is also used as an error signal indicating a reception confirmation signal error that is output when it is detected that the confirmation signal has not been turned on, or when it has been detected that the confirmation signal has not been turned off after transmission of the payout REQ signal is stopped. . Specifically, if the payout number signal is 1E (H), it indicates a reception confirmation signal error. Further, the payout number signal is turned on when the CPU 56 detects that the payout operation in-progress signal is turned on in the prize ball standby state or after the reception confirmation signal is turned off. It is also used as an error signal indicating a signal error during payout operation that is output when it is detected that the state has not been reached. Specifically, if the payout number signal is 1F (H), it indicates a signal error during payout operation.

  The connection confirmation signal is a signal for the payout control microcomputer 370 to turn on when the payout control board 37 rises and to notify the game control microcomputer 560 that the payout control board 37 has risen. In other words, this is a signal for notifying that the payout control microcomputer 370 can execute the winning ball payout process. Therefore, the payout control microcomputer 370 turns off the connection confirmation signal when an error relating to payout of the game ball occurs. The reception confirmation signal is a signal that is turned on when the payout control microcomputer 370 receives a payout number signal in response to the payout REQ signal being turned on. The payout operation in-progress signal is a signal that is turned on when the payout control microcomputer 370 starts the prize ball payout process and is turned off when the number of prize balls paid out by the payout number signal is completed.

  FIG. 46 is a block diagram showing signal lines and the like used for transmission / reception of the payout control signal shown in FIG. As shown in FIG. 46, among the payout control signals, the power supply confirmation signal, the payout REQ signal, and the payout quantity signal are output by the CPU 56 via the output circuit 67, and the payout control microcomputer 370 via the input circuit 373A. Is input. Of the payout control signals, the connection confirmation signal, the reception confirmation signal, and the payout operation in-progress signal are output by the payout control microcomputer 370 via the output circuit 373B, and the game control microcomputer 560 via the input circuit 68. Is input. Each of the power supply confirmation signal, the payout REQ signal, the connection confirmation signal, the reception confirmation signal, and the payout operation in-progress signal is 1-bit data, and is transmitted through one signal line (signal path). The payout number signal is composed of 5-bit data and is transmitted through five signal lines (signal paths).

  FIG. 47 is a timing chart showing an example of how to output the payout control signal. As shown in FIG. 47, based on the winning detection switch detecting the winning of the game ball, the CPU 56 turns on the payout REQ signal and pays out the output state of the payout number signal according to the win. A state corresponding to the number of prize balls is set. In this embodiment, when a game ball is detected by the start port switch 14a, four prize balls are paid out, and when a game ball is detected by any of the prize port switches 33a, 39a, 29a, 30a. Seven prize balls are paid out. When a game ball is detected by the V count switch 22 or the count switch 23, 15 prize balls are paid out. As described above, since the payout number signal is composed of 5 bits, the lower 5 bits of the award ball number commands of 00 (H) to 0F (H) expressed in 8 bits are paid out. The number signal is transmitted from the main board 31 to the payout control board 37. Therefore, it is possible to designate 0 to 31 prize balls by the number-of-payout signal, but in this embodiment, 1F (H) and 1E (H) are used for error notification. Therefore, in practice, it is possible to specify the number of prize balls from 0 to 29. However, in this embodiment, up to 15 (0F (H)) is used for specifying the number, and therefore, it may be expressed as “payout number signal from 00 (H) to 0F (H)” hereinafter. .

  When the payout control microcomputer 370 confirms the receipt of the payout REQ signal, the payout control microcomputer 370 inputs the payout number signal and transmits (turns on) the reception confirmation signal. When the CPU 56 confirms reception of the reception confirmation signal, the CPU 56 stops transmission of the payout REQ signal (sets to an off state). When confirming that the payout REQ signal is turned off, the payout control microcomputer 370 drives the payout motor 289 so that the number of award balls specified by the payout number signal is paid. When driving is started, a payout operation in-progress signal is transmitted (ON state). When the payout control microcomputer 370 confirms that the number of award balls specified by the payout number signal has been paid based on the detection signal of the payout number count switch 301, the payout control microcomputer 370 stops transmitting the payout operation in-progress signal. (Turn off). When the CPU 56 confirms that the payout operation in-progress signal has been turned off, the CPU 56 sets the payout number signal to an off state (all 0).

  The CPU 56 may set the state of the payout number signal to the off state when the payout REQ signal is turned off.

  As shown in FIG. 47, when a new winning is detected when the payout REQ signal and the payout number signal are in the on state, the payout REQ signal is turned on and the payout number signal is output based on the win. Specifically, when the CPU 56 detects a new winning when the payout REQ signal is in the ON state, the number of winning balls to be paid out based on the winning is stored in the total winning ball number storage buffer formed in the RAM 55. Add to content. Then, when the content of the total winning ball number storage buffer is not 0 when the payout REQ signal is turned off, the CPU 56 receives an award of the number of winning balls indicated by the content of the total winning ball number storage buffer up to 15. In order to instruct ball payout, the payout REQ signal is turned on and a payout quantity signal is output.

  FIG. 48 is a flowchart showing an example of the prize ball processing in step S29. In the prize ball process, the CPU 56 executes a prize ball number addition process (step S201) and a prize ball control process (step S202). Then, the contents of the output port 0 buffer among the output port buffers formed in the RAM 55 are output to port 0 (step S203). The contents of the output port 0 buffer are updated in the prize ball control process.

  In the prize ball number adding process, a prize ball number table shown in FIG. 49 is used. The prize ball number table is set in the ROM 54. The number of processes (in this example, “7”) is set in the top address of the winning ball number table, and then the lower address of the switch-on buffer, and each switch of the winning opening that will pay out the winning ball by winning. The switch input bit determination value and the number of winning balls are sequentially set corresponding to each switch of the winning opening. The switch input bit determination value is a value corresponding to a bit to which the detection signal of each switch at the input port 0 is input. The upper address of the switch-on buffer is a fixed value (for example, 7F (H)). In the prize ball number table, the same data is set in each of the lower addresses of the seven switch-on buffers.

  FIG. 50 is a flowchart showing the prize ball number adding process. In the winning ball number adding process, the CPU 56 sets the head address of the winning ball number table in the pointer (step S161). Then, the data at the address pointed to by the pointer (in this case, the number of processes) is loaded (step S162). Next, the upper address (8 bits) of the switch-on buffer is set in the upper 1 byte of the 2-byte check pointer (step S163).

  Then, the value of the pointer is incremented by 1 (step S164), the prize ball number table data pointed to by the pointer (in this case, the lower address of the switch-on buffer) is set in the lower 1 byte of the check pointer (step S165), The pointer value is incremented by 1 (step S166). Next, the address data pointed to by the check pointer, that is, the contents of the switch-on buffer is loaded into the register (step S167), and the loaded contents and the data of the prize ball number table pointed to by the pointer (in this case, the switch input bit judgment value) ) And the logical product (step S168). As a result, 7 bits other than the bit corresponding to the detection signal of the switch to be inspected become 0 in the register loaded with the contents of the switch-on buffer. Then, the pointer value is incremented by 1 (step S169).

  If the calculation result in step S168 is zero, that is, if the detection signal of the switch to be inspected is on (step S170), the winning notification lamp 363 is turned on for a predetermined period of time (step S171), assuming that a winning has occurred. The data of the prize ball number table pointed to by the pointer (in this case, the number of prize balls) is set as the prize ball addition value (step S172), and the prize ball addition value is set as the total number of 16-bit prize balls formed in the RAM 55. It adds to the contents of the storage buffer (step S173). The total winning ball number storage buffer is formed in the backup RAM. Then, as a result of the addition in step S173, the CPU 56 determines an abnormality determination number (for example, 200, 500) in which the number of winning balls (total number of unpaid winning balls) stored in the total winning ball number storage buffer is predetermined. , 1000, etc.), the unpaid excess LED is turned on (steps S174, 175).

  In step S176, the number of processes is reduced by 1. If the number of processes is 0, the process ends. If the number of processes is not 0, the process returns to step S164 (step S177). In step S170, if it is confirmed that the calculation result in step S168 is 0, that is, if the detection signal of the switch to be inspected is in the OFF state, the process proceeds to step S176.

  FIG. 51 is a flowchart showing the prize ball control process in step S201. In the prize ball control process, the CPU 56 executes any one of steps S231 to S236 according to the value of the prize ball process code.

  FIG. 52 is a flowchart showing the standby process (step S231) executed when the value of the prize ball process code is 0. In the standby process, the CPU 56 checks the value of the prize ball timer (step S241A). When the value of the prize ball timer is not 0, the value of the prize ball timer is decremented by 1, and the process is terminated (step S242A). When the value of the prize ball timer is not 0, for example, when the award ball number signal is turned off after confirming that the payout operation in progress signal is turned off at the time of communication of the previous payout control signal, This is the case where a predetermined value is set in the prize ball timer in order to insert a waiting time until the payout REQ signal is turned on.

  If the value of the prize ball timer is 0, the CPU 56 checks whether or not the power confirmation signal is turned off (step S243A). When the power confirmation signal is turned off, the process is terminated. . Therefore, when the power confirmation signal is turned off, the payout REQ signal is not output. The CPU 56 can grasp the output state of the power confirmation signal from the state of bit 6 of the output port 0 buffer. Further, the CPU 56 confirms the state of the connection confirmation signal via the input port (step S243B). If the connection confirmation signal is off, the process is terminated. Therefore, when the connection confirmation signal is in the OFF state, the process is not shifted to the payout number signal transmission process (see FIG. 53) (specifically, the output value during payout REQ in step S254 described later is output to the output port 0 buffer). In this case, the payout REQ signal is not output.

  If the connection confirmation signal is on, the state of the reception confirmation signal is confirmed via the input port (step S244). Since the reception confirmation signal should not be turned on in the standby state, when the reception confirmation signal is on, the CPU 56 determines that a communication error has occurred. Then, the prize ball abnormal state output value (00 (H) or 1E (H)) is set in the output port 0 buffer, and the process is terminated (step S247). When the prize ball abnormal state output value is set in the output port 0 buffer, the contents of the output port 0 buffer are output to port 0 in step S203 (see FIG. 48), whereby a power supply confirmation signal and a payout REQ signal are output. Turns off. By such control, when the reception confirmation signal is turned on during the award ball waiting, the power confirmation signal is turned off. Even if a value other than 0 is stored in the total winning ball number storage buffer, the state does not shift to a state in which a payout command signal is output. That is, it is prohibited to turn on the payout command signal.

  Further, the case where 1E (H) is set as the prize ball abnormal state output value corresponds to the case shown in FIG. 22, and the case where 00 (H) is set as the prize ball abnormal state output value is shown in FIG. Corresponds to the indicated case. When 1E (H) as a prize ball abnormal state output value is set, 1E (H) is output as a payout number signal, and when 00 (H) as a prize ball abnormal state output value is set, the number of payouts 00 (H) is output as a signal. However, at this stage, normally, the payout quantity signal is 00 (H) before the prize ball abnormal state output value is set.

  If the reception confirmation signal is not on, the CPU 56 checks the state of the payout operation in-progress signal via the input port (step S245). Since the payout operation in-progress signal should not be turned on in the standby state, when the payout operation in-progress signal is on, the CPU 56 determines that a communication error has occurred. Then, the prize ball abnormal state output value (00 (H) or 1F (H)) is set in the output port 0 buffer, and the process is terminated (step S246). By such control, when the payout operation in-progress signal is turned on during the award ball payout standby, the power supply confirmation signal is turned off. Even if a value other than 0 is stored in the total winning ball number storage buffer, the state does not shift to a state in which a payout command signal is output. That is, it is prohibited to turn on the payout command signal.

  If no communication error has occurred, the prize ball standby output value (40 (H)) is set in the output port 0 buffer (step S248). When the prize ball waiting output value is set in the output port 0 buffer, the payout REQ signal is turned off by outputting the contents of the output port 0 buffer to port 0 in step S203, and the power supply confirmation signal Turns on. However, if the control related to communication has been normally continued, at this stage, the payout REQ signal is already in the off state and the power supply confirmation signal is in the on state. The processing in step S248 is valid when the communication error state is recovered (specifically, when the connection confirmation signal from the payout control board 37 returns to the on state).

  Next, the CPU 56 confirms the contents of the total winning ball number storage buffer (step S249). If the value is 0, the process ends. If not, the value of the prize ball process code is set to 1 (step S250), and the process ends.

  FIG. 53 is a flowchart showing the payout quantity signal transmission process (step S232) executed when the value of the prize ball process code is 1. In the payout number signal transmission process, the CPU 56 checks whether or not the content of the total prize ball number storage buffer is smaller than the prize ball command maximum value (“15” in this example) (step S251). If the content of the total prize ball number storage buffer is equal to or greater than the prize ball command maximum value, the prize ball command maximum value is set in the prize ball number buffer (step S252). If the content of the total prize ball number storage buffer is smaller than the maximum value of the prize ball command, the content of the total prize ball number storage buffer is set in the prize ball number buffer (step S253).

  Thereafter, the output value during payout REQ (60 (H)) is set in the output port 0 buffer (step S254). When the output value during the payout REQ is set in the output port 0 buffer, the content of the output port 0 buffer is output to the port 0 in step S203, whereby the payout REQ signal is turned on, and the power supply confirmation signal The on state is maintained. Further, the contents of the winning ball number buffer are set in the lower 5 bits of the output port 0 buffer (step S255). Further, a value (2500 in this example) corresponding to a predetermined time (for example, 5 seconds) for monitoring that the reception confirmation signal is turned on is set in the prize ball timer (step S256). Thereafter, the value of the prize ball process code is set to 2 (step S257), and the process is terminated. Note that 5 seconds is a sufficient time to complete one payout process (for example, payout of up to 25 game balls), and the payout control means is performing the ball lending process. This is a time considering a period during which the payout REQ signal is not confirmed. When it is allowed to continuously execute a plurality of ball lending processes (for example, paying out 25 game balls at a time), a predetermined time for monitoring that the reception confirmation signal is turned on Is determined in consideration of the maximum number of ball lending processes executed continuously.

  In this embodiment, the maximum prize ball command value is “15”. Accordingly, a payout number signal designating a payout number of “15” at the maximum is transmitted to the payout control board 37.

  FIG. 54 is a flowchart showing the reception confirmation signal ON waiting process (step S233) executed when the value of the prize ball process code is 2. In response to the reception confirmation signal being turned on in the reception confirmation signal ON waiting process (step S261), the CPU 56 determines the contents of the prize ball number buffer (the payout control micro) from the contents of the total prize ball number storage buffer. The number of prize balls paid out commanded to the computer 370 is subtracted (step S262). Then, the payout REQ signal output bit of the output port 0 buffer is reset (step S263). If the payout REQ signal output bit of the output port 0 buffer is reset, the payout REQ signal is turned off by outputting the contents of the output port 0 buffer to port 0 in step S203. Since the payout REQ signal, which is a signal, is turned off, the payout command signal is turned off.

  Further, a value corresponding to a predetermined time (100 ms as an example) for monitoring that the reception confirmation signal is turned off is set in the prize ball timer (step S264). Also, the value of the prize ball process code is set to 3 (step S265), and the process is terminated.

  If the reception confirmation signal is not on, the value of the prize ball timer is decremented by 1 (step S266). If the value of the prize ball timer is not 0, the process is terminated. When the value of the prize ball timer becomes 0 (step S267), the CPU 56 determines that a communication error has occurred. The prize ball abnormal state output value (00 (H) or 1E (H)) is set in the output port 0 buffer (step S268). When the prize ball abnormal state output value is set in the output port 0 buffer, the contents of the output port 0 buffer are output to port 0 in step S203 (see FIG. 48), thereby turning off the power confirmation signal and the payout REQ signal. It becomes a state. Then, the value of the prize ball process code is set to 0 corresponding to the standby process (step S269), and the process ends.

  FIG. 55 is a flowchart showing the reception confirmation signal OFF waiting process (step S234) executed when the value of the prize ball process code is 3. In the reception confirmation signal off waiting process, the CPU 56 determines whether the payout operation in-progress signal is turned on in response to the reception confirmation signal being turned off (step S271). ) Is set in the prize ball timer (step S272). Also, the value of the prize ball process code is set to 4 (step S273), and the process is terminated.

  If the reception confirmation signal is not OFF, the value of the prize ball timer is decremented by 1 (step S275). If the value of the prize ball timer is not 0, the process is terminated. When the value of the prize ball timer becomes 0 (step S276), the CPU 56 determines that a communication error has occurred. The prize ball abnormal state output value (00 (H) or 1E (H)) is set in the output port 0 buffer (step S277). Then, the value of the prize ball process code is set to 0 corresponding to the standby process (step S278), and the process ends.

  FIG. 56 is a flowchart showing the payout operation signal on waiting process (step S235) executed when the value of the prize ball process code is 4. In the payout operation signal on waiting process, the CPU 56 determines whether or not the payout operation in-progress signal is turned off in response to the payout operation in-progress signal being turned on (step S281). Is set to the prize ball timer (step S282). Also, the value of the prize ball process code is set to 5 (step S283), and the process is terminated.

  When the payout operation in-progress signal is not on, the value of the prize ball timer is decremented by 1 (step S285). If the value of the prize ball timer is not 0, the process is terminated. When the value of the prize ball timer becomes 0 (step S286), the CPU 56 determines that a communication error has occurred. Then, the prize ball abnormal state output value (00 (H) or 1F (H)) is set in the output port 0 buffer (step S287). When the prize ball abnormal state output value is set in the output port 0 buffer, the contents of the output port 0 buffer are output to port 0 in step S203 (see FIG. 48), thereby turning off the power confirmation signal and the payout REQ signal. It becomes a state. Then, the value of the prize ball process code is set to 0 corresponding to the standby process (step S288), and the process ends.

  FIG. 57 is a flowchart showing a payout operation signal off waiting process (step S236) executed when the value of the prize ball process code is 5. In the payout operation signal off waiting process, the CPU 56 sets a delay time value (10 corresponding to 20 ms as an example) in the prize ball timer in response to the payout operation signal being turned off (step S291). (Step S294), the payout number signal output bit (lower 5 bits) of the output port 0 buffer is set to 0 (Step S297), the value of the prize ball process code is set to 0 (Step S298), and the process is terminated. . In this case, the communication between the game control microcomputer 560 and the payout control microcomputer 370 is normally completed. The delay time value is set to provide a waiting time until the payout REQ signal is turned on next time.

  If the payout operation in-progress signal is not in the OFF state, the value of the prize ball timer is decremented by 1 (step S292). If the value of the prize ball timer is not 0, the process is terminated. When the value of the prize ball timer becomes 0 (step S293), the CPU 56 determines that a payout error has occurred. Then, the CPU 56 sets an abnormality notification command transmission request (step S295), and resets the power check signal output bit of the output port 0 buffer (step S296). Further, the payout number signal output bit (lower 5 bits) of the output port 0 buffer is set to 0 (step S297), the value of the winning ball process code is set to 0 (step S298), and the process is terminated. When an abnormality notification command transmission request is set, an abnormality notification command is transmitted to the effect control microcomputer.

  As described above, the gaming control microcomputer 560 controls to stop paying out the game ball (for example, power supply confirmation) when an abnormality (communication error) in communication with the payout control microcomputer 370 occurs. Signal off). The game control microcomputer 560 stops paying out the game balls until the abnormality in communication with the payout control microcomputer 370 is resolved. That is, even if a new event (game ball winning or the like) occurs, processing corresponding to the new event is not performed, for example, a newly generated event is stored. When the communication abnormality is resolved (for example, when the connection confirmation signal is turned on), the game control microcomputer 560 resumes communication.

  In this embodiment, the CPU 56 subtracts a value corresponding to the payout number specified by the payout command signal from the prize game medium number data stored in the prize game medium number storage means (in this example, the total prize ball number storage buffer). The predetermined condition for executing the subtraction processing is when the reception confirmation signal is received from the payout control microcomputer 370, specifically, when the reception confirmation signal is turned on. When the reception confirmation signal is turned on, the payout control microcomputer 370 has not yet paid out the number of prize balls instructed by the payout command signal. The total number of winning balls after the reception confirmation signal is turned on (for example, when the paying-in operation signal is turned off, that is, when the number of paying balls designated by the payout number signal is completed). If the storage buffer is subtracted, a large number of prize balls will be paid out illegally by fraudulent actions such as restoring the power supply after illegally stopping the power supply of the gaming machine during the prize ball payout. End up. For example, when 15 prize ball payouts are instructed by a payout command signal, when 10 prize ball payouts are made, if the power supply is restored after illegally stopping the power supply of the gaming machine, Since the contents of the total prize ball number storage buffer are not subtracted at all, it is assumed that the 10 prize balls are not paid out even though 10 prize balls are actually paid out. Control will continue.

  However, in this embodiment, when the reception confirmation signal is turned on, that is, when the payout control microcomputer 370 receives the payout command signal and transmits the reception confirmation signal, Since the subtraction process is executed, the above fraud can be prevented.

  The game control means and the payout control means perform two-way communication with respect to the prize ball payout control, and the game control means stores the prize game medium number storage means in response to receiving a signal corresponding to the reception confirmation signal. A gaming machine that performs a subtraction process for subtracting a value corresponding to the number of payouts specified by a payout command signal from the prize game medium number data that has been made is known (for example, see Japanese Patent Application Laid-Open No. 2004-65676).

  FIG. 58 is a timing chart showing how to output a payout control signal described in Japanese Patent Application Laid-Open No. 2004-65676. As shown in FIG. 58, in the gaming machine described in Japanese Patent Application Laid-Open No. 2004-65676, the game control means is turned off after the BUSY signal corresponding to the reception confirmation signal is turned on. Accordingly, a subtraction process is performed to subtract a value corresponding to the payout number specified by the payout command signal from the prize game medium number data stored in the prize game medium number storage means.

  However, in the gaming machine described in Japanese Patent Application Laid-Open No. 2004-65676, the game control means performs a payout command signal until the payout control means completes the designated number of prize balls even after performing the subtraction process. (In particular, the payout REQ signal) is kept on. Then, when the power is restored after the power is cut off in the state where the on-state of the payout command signal is maintained (for example, time T shown in FIG. 58), the game control means The payout command signal is turned on again by the recovery process. In that case, the payout control means restarts the prize ball payout process from the beginning (for example, the first one when receiving 15 prize ball payout instructions). If it is paid out as a prize ball, double payout will be made. On the other hand, in this embodiment, when the subtraction process is performed, the payout command signal is turned off, that is, since the payout command signal is turned off earlier, duplicate payout is performed and excessive payout balls are paid out. The possibility of being done is reduced.

  Next, the operation of the payout control means (the payout control microcomputer 370 and the I / O port) will be described. FIG. 59 is a flowchart showing main processing executed by the payout control microcomputer 370 in response to the start of power supply to the gaming machine and the reset signal to the payout control microcomputer 370 becoming high level. . In the main process, the payout control microcomputer 370 first performs necessary initial settings. That is, the payout control microcomputer 370 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to interrupt mode 2 (step S702), and a stack pointer designation address is set to the stack pointer (step S703). The payout control microcomputer 370 sets (initializes) the built-in device register (step S704), and after setting (initializing) the CTC and PIO (step S705), the RAM can be accessed. The state is set (step S706).

  In this embodiment, one channel of the built-in CTC is used in the timer mode. Accordingly, in the built-in device register setting process in step S704 and the process in step S705, register setting for setting the channel to be used to timer mode, register setting for permitting interrupt generation, and setting an interrupt vector. The register is set. The interrupt by the channel is used as a timer interrupt. For example, when it is desired to generate a timer interrupt every 2 ms, a value corresponding to 2 ms is set as an initial value in a predetermined register (time constant register).

  The interrupt vector set for the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. In the timer interruption process, a payout control process for controlling the payout means (including at least a process of driving the ball payout device 97 in response to a command signal related to award ball payout from the main board, and a ball payout device 97 in response to a ball lending request. A process for driving the program may be included.

  In this embodiment, the interruption mode 2 is also set in the payout control microcomputer 370. Therefore, an interrupt process based on counting up the built-in CTC can be used. Also, an interrupt processing start address can be set according to the interrupt vector sent by the CTC.

  The interrupt based on CTC channel 3 (CH3) count-up is an interrupt that occurs when the CPU internal clock (system clock) counts down and the register value becomes “0”, and is used as a timer interrupt. . Specifically, a clock obtained by dividing the operation clock of the payout control CPU 371 is supplied to the CTC, the register value is subtracted by the input of the clock, and when the register value becomes 0, a timer interrupt occurs. For example, the register value of CH3 is subtracted at 1/256 period of the system clock. Since the subtraction is performed based on the divided clock, the initial value of the register does not increase.

  Next, the payout control microcomputer 370 performs a RAM clear process (step S707). Also, initial values are set in the flags and counters of the RAM area (step S708). The processing in step S708 includes processing for setting a prize ball unpaid number counter initial value (for example, 0) in the prize ball unpaid number counter, and processing for turning on a connection confirmation signal (specifically, RAM The process of setting bit 4 of the output port 1 buffer formed in the The contents of the output port buffer are reflected in the output of the output port when the output process in step S760 described later is first executed. The main process is started in response to the start of power supply to the gaming machine, and when the output process in the payout control process is executed for the first time, a connection confirmation signal is output to the output port (turns on) Therefore, the connection confirmation signal is turned on when power supply to the gaming machine is started and the payout process can be executed.

  Then, a CTC register provided in the payout control microcomputer 370 is set so that a timer interrupt is periodically generated (step S709). That is, a value corresponding to the timer interrupt generation interval is set as an initial value in a predetermined register (time constant register). Since interruption is prohibited in step S701 of the initial setting process, interruption is permitted before the initialization process is completed (step S710). Thereafter, a loop process for monitoring the occurrence of a timer interrupt is entered.

  As described above, in this embodiment, the built-in CTC of the payout control microcomputer 3701 is set to repeatedly generate a timer interrupt. When a timer interrupt occurs, the payout control microcomputer 370 sets a timer interrupt flag in the timer interrupt process. In the loop process in the main process, when it is detected that the timer interrupt flag is set, the payout control process in step S750 and subsequent steps is executed.

  In step S750 of FIG. 60, the payout control microcomputer 370 performs excitation pattern output processing for the firing motor 94 (output of the patterns of the firing motors φ1 to φ4 to the output port 0). In the firing motor control process in step S752, the excitation pattern is stored in the excitation pattern buffer that is the RAM area. In step S750, the payout control microcomputer 370 stores the contents of the excitation pattern buffer in the lower 4 bits of the output port 0. Process to output to.

  Next, the payout control microcomputer 370 performs an input determination process (step S751). The input determination process includes a process of checking the status of the detection signals of the payout number count switch 301 and the error release switch 375. Specifically, switch timers (payout number count switch timer, error release switch timer) corresponding to each of them are formed in the RAM, and when it is detected in the switch check process that they are on, the corresponding switch timer The value of the switch timer is incremented by one, and when it is detected that the switch is off, the corresponding switch timer value is cleared.

  Next, the payout control microcomputer 370 executes a firing motor control process (step S752). In the firing motor control process, the patterns of the firing motors φ1 to φ4 are stored in the excitation pattern buffer. When the firing motor 94 should be disabled, the patterns of the firing motors φ1 to φ4 that do not rotate the firing motor 94 are stored in the excitation pattern buffer. Also, the payout control microcomputer 370 executes a payout motor control process (step S753). In the payout motor control process, when the payout motor 289 is to be driven, a process for outputting the patterns of the payout motors φ1 to φ4 to the output port 0 is performed.

  Also, the payout control microcomputer 370 executes a prepaid card unit control process for communicating with the card unit 50 (step S754). Next, main control communication processing for communicating with the CPU 56 is executed (step S755). Furthermore, a control for paying out a ball in accordance with a ball rental request from the card unit 50 and a control for paying out a ball for controlling the payout of the number of prize balls indicated by the number-of-payout signal from the main board are performed. It executes (step S756).

  Then, the payout control microcomputer 370 executes error processing for detecting various errors (step S757). Further, an information output process for outputting prize ball information and ball lending information output to the outside of the gaming machine is executed (step S758). Further, a predetermined display is performed on the error display LED 374 according to the result of the error processing, and a display control process for lighting the prize ball LED 51 and the ball out LED 52 is executed (step S759). In the display control process, the payout control microcomputer 370 performs control for lighting the prize ball LED 51 when the payout operation in-progress signal is on. Further, when the payout operation in-progress signal is turned off, control for turning off the prize ball LED 51 is performed.

  In this embodiment, a RAM area (output port 0 buffer, output port 1 buffer, output port 2 buffer) corresponding to the output state of the output port is provided. The contents of the output port 0 buffer, output port 1 buffer, and output port 2 buffer are output to the output port (step S760: output processing). However, since the lower 4 bits (fire motors φ1 to φ4) of output port 0 are executed in step S750, the output of the lower 4 bits of output port 0 is not performed in the output process. The output port 0 buffer, the output port 1 buffer, and the output port 2 buffer are a payout motor control process (step S753), a prepaid card control process (step S754), a main control communication process (step S755), and an information output process (step S758). And updated in the display control process (step S759).

  FIG. 61 is a flowchart showing the payout motor control process in step S753. In the payout motor control process, the payout control microcomputer 370 executes any one of steps S521 to S526 according to the value of the payout motor control code.

  In the payout motor normal process (step S521) executed when the value of the payout motor control code is 0, the payout control microcomputer 370 sets the pointer at the head address of the table stored in the ROM. The payout motor normal process setting table stores a payout motor excitation pattern table in which data of excitation patterns (payout motors φ1 to φ4) of each step for rotating the payout motor 289 at the time of ball payout is sequentially set. Yes.

  In the payout motor start preparation process (step S522) executed when the value of the payout motor control code is 1, the payout control microcomputer 370 outputs bits 4 to 4 of the output port 0 buffer corresponding to the output state of the output port 0. Processing such as setting the initial value of the excitation pattern to 7 is performed.

  In the payout motor slow-up process (step S523) executed when the value of the payout motor control code is 2, the payout control microcomputer 370 performs the constant speed process in order to smoothly start the payout motor 289. The output port 0 buffer corresponding to the output state of the output port 0 by reading the contents of the payout motor excitation pattern table at a time interval longer than the time interval and gradually approaching the time interval in the case of constant speed processing. Set to bits 4-7. At the time of reading, the contents of the payout motor excitation pattern table at the address pointed to by the pointer are read and the value of the pointer is incremented by one.

  In the payout motor constant speed process (step S524) executed when the value of the payout motor control code is 3, the payout control microcomputer 370 periodically reads the contents of the payout motor excitation pattern table and outputs the output port 0. Set to bits 4-7 of the output port 0 buffer corresponding to the output state.

  In the payout motor brake process (step S525) executed when the value of the payout motor control code is 4, the payout control microcomputer 370 stops the payout motor 289 more smoothly than in the case of the constant speed process. Bit 4 of the output port 0 buffer corresponding to the output state of the output port 0 by reading out the contents of the payout motor excitation pattern table at a long interval and gradually away from the time interval in the case of constant speed processing. Set to ~ 7.

  In the ball biting payout motor brake process (step S526) executed when the value of the payout motor control code is 5, the payout control microcomputer 370 performs the payout motor 289 in the case of rotation for releasing the ball biting. In order to smoothly stop the discharge, the payout motor at a longer interval than the rotation of the payout motor 289 for releasing the ball bite and at a time interval gradually moving away from the time interval in the case of constant speed processing. The contents of the excitation pattern table are read and set to bits 4 to 7 of the output port 0 buffer corresponding to the output state of output port 0.

  FIG. 62 is a flowchart showing the main control communication process of step S755. In the main control communication process, the payout control microcomputer 370 executes any one of steps S531 to S535 according to the value of the main control communication control code if the power confirmation signal is in the ON state (step S51). To do.

  If the power supply confirmation signal is off, if the payout number signal indicates 1F (H), the payout operation in-progress signal error bit is set in the error flag (steps S52 and S53), and the connection confirmation signal is turned off. Put it in a state. If the payout number signal indicates 1E (H), the reception confirmation signal error bit in the error flag is set (steps S54 and S55), and the connection confirmation signal is turned off (step S58). If the payout quantity signal does not indicate 1F (H) or 1E (H), and if the winning ball payout operation is in progress (step S56), the payout operation in progress signal error bit in the error flag is set (step S57). Then, the connection confirmation signal is turned off (step S58). Whether or not a prize ball payout operation is in progress is determined by whether or not a prize ball in-motion flag formed in the RAM is set. When the connection confirmation signal is turned off in step S58, the connection confirmation signal output bit (bit 4: refer to FIG. 37) of the output port 1 buffer formed in the RAM is reset, and in the output process of step S760, By outputting the contents of the output port 1 buffer to port 1, the connection confirmation signal is actually turned off.

  Further, the processing of steps S52 and S53 corresponds to the processing of step S287 executed by the CPU 56 (when 1F (H) is used as the prize ball abnormal output value). The processing of steps S54 and S55 corresponds to the processing of steps S268 and S277 executed by the CPU 56 (when 1E (H) is used as the prize ball abnormal output value). The processing in steps S56 and S57 corresponds to the processing in step S296 executed by the CPU 56. In this embodiment, the payout operation signal error bit is set in both steps S53 and S57. However, in the payout control microcomputer 370, the CPU 56 indicates that the payout operation signal is not turned on. Whether it is determined as a communication error when it is detected (in the case of step S287) or whether it is determined as a communication error when it is detected that the payout operation in-progress signal has not been turned off (in the case of step S296) can be distinguished. The error bit to be set may be changed between S53 and S57.

  FIG. 63 is a flowchart showing the standby process (step S531) executed when the value of the main control communication control code is 0. In the standby process, when the error bit is on, the payout control microcomputer 370 ends the process without executing the subsequent processes (step S541). In step S541, if any one of the bits in the error flag is set, it is determined that the error bit is set.

  The payout control microcomputer 370 executes the subsequent processing if the BRDY signal (unit operation signal), which is a signal output by the card unit 50 in response to the operation of the ball lending switch, is on. The process is ended (step S542). That the BRDY signal is in an ON state means that a ball lending request is generated from the card unit 50 or that a ball lending process is in progress. That is, when a ball lending request is generated or a ball lending process is in progress, communication with the game control microcomputer 560 of the main board 31 does not proceed.

  If the conditions of steps S541 to S542 are not satisfied and the power supply confirmation signal is on, the payout control microcomputer 370 checks whether the payout REQ signal is on (steps S543 and S544). ). If it is in the on state, the number of prize balls indicated by the number-of-payout signal is set in a prize ball unpaid-out number buffer that is a RAM area for temporary storage (step S545), and the reception confirmation signal is turned on. To perform the process (step S546). Specifically, the bit corresponding to the reception confirmation signal in the output port 1 buffer corresponding to the output state of the output port 1 is set to the on state. Further, a value corresponding to a predetermined time (100 ms as an example) for monitoring that the payout REQ signal is turned off is set in the main control communication control timer (step S547). Then, the value of the main control communication control code is set to 1 (step S548), and the process ends.

  The payout control microcomputer 370 does not execute the process of step S546 if the payout quantity signal indicates 0 as the number of prize balls in step S545. When the payout REQ signal is turned on, the CPU 56 does not transmit a payout number signal indicating 0 as the number of prize balls, and is in a state where the payout number signal indicates 0 during standby for paying out the prize balls (invalid Command output state), the payout REQ signal is in an on state and the payout number signal is in a state indicating 0. This means that the payout REQ signal is turned on between substrates due to noise or the like. It is thought that it has become. Therefore, in such a situation, it is preferable that the payout control microcomputer 370 does not turn on the reception confirmation signal by not executing the process of step S546.

  FIG. 64 is a flowchart showing a payout REQ signal OFF waiting process (step S532) executed when the value of the main control communication control code is 1. In the payout REQ signal OFF waiting process, if the payout REQ signal is in the OFF state (step S551), the payout control microcomputer 370 is a RAM ball for temporarily storing the number of award balls indicated by the payout number signal. The contents of the unpaid-out number buffer are set in the winning ball unpaid-out number counter (step S552). Further, a process for turning off the reception confirmation signal is performed (step S553). Specifically, the bit corresponding to the reception confirmation signal in the output port 1 buffer corresponding to the output state of the output port 1 is set to the off state. Then, the value of the main control communication control code is set to 2 (step S554), and the process ends. Note that in response to the execution of the process of step S553, a prize ball payout process is started in a payout operation start waiting process (see FIG. 69) described later.

  If the payout REQ signal is not in the OFF state, the payout control microcomputer 370 subtracts 1 from the value of the main control communication control timer (step S555). If the value of the main control communication control timer is not 0, the process is terminated (step S556). When the value of the main control communication control timer becomes 0, a payout REQ signal does not turn off even if a predetermined time elapses after the reception confirmation signal is transmitted (turned on), and a communication error occurs. Judge. Then, a process for turning off the reception confirmation signal and the connection confirmation signal is performed (step S557). Specifically, the bit corresponding to the reception confirmation signal and the connection confirmation signal in the output port 1 buffer corresponding to the output state of the output port 1 is set to the OFF state. Also, bit 4 (payout REQ signal error bit) of the error flag is set (step S558). Then, the value of the main control communication control code is set to 0 (step S559), and the process ends.

  FIG. 65 is a flowchart showing the payout operation start waiting process (step S533) executed when the value of the main control communication control code is 2. In the payout operation start waiting process, the payout control microcomputer 370, when the prize ball operating flag indicating that the prize ball payout process is being performed is turned on (1: set state) (step S561). Then, a process for turning on the payout operation in-progress signal is performed (step S562). Specifically, the bit corresponding to the payout operation in-progress signal in the output port 1 buffer corresponding to the output state of the output port 1 is set to the on state. Then, the value of the main control communication control code is set to 3 (step S563), and the process ends.

  FIG. 66 is a flowchart showing a payout operation process (step S534) executed when the value of the main control communication control code is 3. In the payout operation process, the payout control microcomputer 370, when the award ball operating flag is turned off (0: reset state) (step S571), the number of award balls specified by the payout number signal. Assuming that the payout process is completed, a process for turning off the payout operation in-progress signal is performed (step S572). Specifically, the bit corresponding to the payout operation in-progress signal in the output port 1 buffer corresponding to the output state of the output port 1 is set to the OFF state. Further, a value corresponding to a predetermined time (100 ms as an example) for monitoring that the payout number signal is turned off (all 5 bits are 0) is set in the main control communication control timer (step S573). Then, the value of the main control communication control code is set to 4 (step S574), and the process ends.

  FIG. 67 is a flowchart showing the payout number signal OFF waiting process (step S535) executed when the value of the main control communication control code is 4. In the payout number signal off waiting process, the payout control microcomputer 370 sets the value of the main control communication control code to 0 corresponding to the wait state (step S582) when the payout number signal is in the off state (step S581). ), The process is terminated. At this time, the communication between the game control microcomputer 560 and the payout control microcomputer 370 related to one prize ball payout is normally completed.

  If the payout number signal is not in the OFF state, the payout control microcomputer 370 subtracts 1 from the value of the main control communication control timer (step S583). If the value of the main control communication control timer is not 0, the process is terminated (step S584). When the value of the main control communication control timer becomes 0, the payout number signal does not turn off even after a predetermined time has elapsed since the transmission of the payout operation signal is stopped (turned off). It is determined that a communication error has occurred. Then, a process for turning off the connection confirmation signal is performed (step S585). Specifically, the bit corresponding to the connection confirmation signal in the output port 1 buffer corresponding to the output state of the output port 1 is set to the off state. Also, bit 5 (payout number signal error bit) of the error flag is set (step S586). Then, the value of the main control communication control code is set to 0 (step S582), and the process ends.

  FIG. 68 is a flowchart showing the prize ball lending control processing in step S756. In the winning ball lending control process, the payout control microcomputer 370 confirms that the detection signal of the payout number count switch 301 is turned on (step S601). The counter value is decremented by 1 (steps S602 and S604), and if the ball is not being lent, the value of the award ball unpaid out counter is decremented by 1 (steps S602 and S603). Thereafter, any one of steps S610 to S612 is executed according to the value of the payout control code.

  FIG. 69 is a flowchart showing a payout start waiting process (step S610) executed when the payout control code is 0. In the payout start waiting process, if the error bit is set, the payout control microcomputer 370 does not execute the subsequent processes (step S621). The error bit in the error flag includes a main control unconnected error bit. The main control unconnected error is set when the power supply confirmation signal from the main board 31 is turned off when the winning ball is not paid out. Accordingly, the payout control microcomputer 370 starts substantial control on condition that the power supply confirmation signal is turned on after power supply to the gaming machine is started.

  On the other hand, if the BRDY signal is not in the on state, processing for paying out a prize ball after step S631 is executed. If the BRDY signal is on and the BRQ signal (ball lending request signal) that is a ball lending request signal is on, the ball lending operation flag is set (steps S623 and S624). Then, “25” is set in the unpaid ball lending number counter (step S625), and “25” is set in the payout motor rotation number buffer (step S626). The BRQ signal is a signal output from the card unit 50 when a predetermined delay time has elapsed from the time when the BRDY signal is output.

  The payout motor rotation frequency buffer is referred to in the payout motor control process (step S768). That is, in the payout motor control process, control is performed to rotate the payout motor 289 by the number of rotations corresponding to the value set in the payout motor rotation frequency buffer.

  Thereafter, the payout control microcomputer 370 sets a value corresponding to the payout motor start preparation process (step S522) (specifically, “1”) to the payout motor control code for selecting the process executed in the payout motor control process. ) Is set (step S627), the value of the payout control code is set to 1 (step S628), and the process is terminated.

  In step S631, the payout control microcomputer 370 checks whether or not the value of the award ball unpaid-out counter is zero. If the value of the prize ball unpaid number counter is 0, the process is terminated. In the award ball unpaid number counter, in step S552 in the payout REQ signal OFF waiting process of the main control communication process, that is, when the payout REQ signal from the game control microcomputer 560 of the main board 31 is turned off. , A value other than 0 (the number indicated by the payout number signal) is set. If the value of the award ball unpaid number counter is not 0, the value of the award ball unpaid number counter is set in the payout motor rotation frequency buffer (step S633). Then, a winning ball operating flag is set (step S635), and the process proceeds to step S627.

  FIG. 70 is a flowchart showing a payout motor stop waiting process (step S611) executed when the payout control code is 1. In the payout motor stop waiting process, the payout control microcomputer 370 checks whether or not the payout operation is completed (step S641). For example, the payout control microcomputer 370 sets a flag to that effect when the payout motor brake process (step S525) in the payout motor control process ends, and the payout operation ends by checking the flag in step S641. It can be confirmed whether or not.

  When the payout operation is completed, the payout control microcomputer 370 sets the payout passing monitoring time in the payout control monitoring timer (step S642). The payout passing monitoring time is a time that has a margin in the time from when the last payout ball is paid out by the payout motor 289 until it passes through the payout number count switch 301. Then, the value of the payout control code is set to 2 (step S643), and the process ends.

  FIGS. 71 to 73 are flowcharts showing a payout passing waiting process (step S612) executed when the value of the payout control code is 2. FIG. In the payout passing waiting process, when a prize ball is being paid out, it is determined that the payout has been completed normally if the value of the prize ball unpaid number counter is zero. If the value of the award ball unpaid number counter is not 0, and if there is no error state, re-payout operation of game balls corresponding to insufficient payout (the number of game balls indicated by the value of the award ball unpaid number counter) To the upper limit of 2 times. In the re-payout operation, when it is detected by the payout number count switch 301 that the game ball is actually paid out, it is determined that the payout has been completed normally. In this embodiment, when the payout REQ signal is received, the payout motor 289 is rotated so that the number of game balls set in the award ball non-payout number counter is paid out. If the value of the number counter is not 0, the payout has not been completed normally.

  Further, when the ball lending is being paid out, it is determined that the payout has been completed normally if the value of the ball lending unpaid-out counter is 0. If the value of the unsold ball counter is not 0, if the error is not in an error state, an attempt is made to re-pay the remaining ball lending (corresponding to the unsold ball counter). In this embodiment, the number of game balls to be paid out in one ball lending and payout operation is 25 (fixed value), and the payout motor 289 is rotated so that 25 game balls are paid out. Therefore, when the value of the unpaid ball lending counter is not 0, the payout has not been completed normally.

  In the payout passing waiting process, the payout control microcomputer 370 first checks the value of the payout control timer. If the value is 0, the process proceeds to step S653 (step S650). If the value of the payout control timer is not 0, the value of the payout control timer is decremented by 1 (step S651). If the value of the payout control timer is not 0 (step S652), that is, if the payout control timer has not timed out, the process is terminated. Note that the process of step S650 is a process that takes into account when a game ball payout retry operation to be described later is started. When the process of step S807 described later is executed, a retry operation is started through a route that moves from step S650 to S653.

  If the payout control timer has timed out (step S652), it is confirmed whether or not the ball lending payout process (ball lending operation) has been executed (step S653). Whether or not the ball lending operation has been executed is confirmed by whether or not the ball lending operation in progress flag in the payout control state flag formed in the RAM is set. When the ball lending operation is not executed, that is, when the prize ball payout process (prize ball operation) is executed, the payout control microcomputer 370 confirms the value of the award ball unpaid number counter ( Step S654). If the value of the award ball unpaid-out counter is 0, it is assumed that the award ball payout processing has been completed normally, and 1 bit during re-payout operation, 2 bits during re-payout operation, The operating flag and the ball lending operating bit are reset (step S655), the payout control code is set to 0 (step S656), and the process ends.

  The “payout control state flag” includes a re-payout operation 1 bit indicating whether or not the first re-payout operation is being executed, and a re-payout operation indicating whether or not the second re-payout operation is being executed. A multi-bit configuration including a middle 2 bits, a winning ball operating flag indicating whether or not a winning ball payout operation is being performed, and a ball lending operating bit indicating whether or not a ball lending operation is being performed Flag.

  If the value of the award ball unpaid number counter is not 0, the payout control microcomputer 370 has an error flag for an error not related to communication (here, 1 bit of a payout switch abnormality detection error, an abnormality of the payout switch) On the condition that any one of the detection error 2 bits and the payout case error bit or a plurality of bits) is not set (step S659), the payout operation is executed. If any one or more of the payout switch abnormality detection error 1 bit, the payout switch abnormality detection error 2 bits and the payout case error bit is set, the re-payout operation is not executed.

  In order to execute the re-payout process (control for performing the re-payout operation), the payout control microcomputer 370 first checks whether or not 2 bits are set during the re-payout operation (step S662). If not set, it is confirmed whether or not 1 bit is set during the re-payout operation (step S663). If 1 bit is not set during the re-payout operation, 1 bit during the re-payout operation is set in order to execute the first re-payout operation (step S665), and the award ball non-payout number counter is stored in the payout motor rotation number buffer. Alternatively, the value of the unpaid ball lending counter is set (step S666). The payout motor rotation frequency buffer is referred to in the payout motor control process (step S768). That is, in the payout motor control process, control is performed to rotate the payout motor 289 by the number of rotations corresponding to the value set in the payout motor rotation frequency buffer. In step S666, the value of the unpaid ball lending counter is also handled because step S666 is also used in the re-payout process in the lend-out process. In step S666, the payout control microcomputer 370 sets the value of the award ball unpaid number counter in the re-payout process in the prize ball payout process, and the value of the ball lend-out unpaid number counter in the re-payout process in the ball lending payout process. Set. Thereafter, the payout control code is set to 1 (step S667), and the process is terminated.

  In step S663, when it is confirmed that 1 bit is set during the re-payout operation, the payout control microcomputer 370 resets 1 bit during the re-payout operation in order to execute the second re-payout (step S663). S669), 2 bits are set during the re-payout operation (step S670). Then, control goes to a step S666.

  In step S662, when it is confirmed that 2 bits are set during the re-payout operation, the payout control microcomputer 370 does not pay out the game balls for the shortage of payout even if the re-payout process is executed twice. The payout case error bit in the error flag is set (step S672). At that time, 2 bits are reset during the re-payout operation (step S671). Then, the process ends.

  As described above, if the game ball payout shortage is not resolved even after performing the predetermined payout operation (two times in this example) in the repayout process (corrected payout process), the game ball payout operation is defective. The payout count switch non-passing error bit (payout case error bit) is set.

  Therefore, in this embodiment, the prize game medium payout control means in the payout control means confirms that the payout of the prize game medium has not been completed based on the detection signal from the payout number count switch 301 as the payout detection means. When it is detected, the control is performed so that the payout means pays out the insufficient amount of prize game media up to a predetermined number of times (in this example, twice). In this embodiment, if the prize game medium is not paid out even if the retry operation for paying out the prize game medium is performed twice, the payout case error bit is set and an error is being generated. (Step S672), the payout case error bit may be set when it is detected for the first time that the payout of the premium game medium is not completed. Note that “retry operation (or“ retry ”,“ retry operation processing ”) means that the actual number of payouts is equal to the number of game balls paid out in spite of execution of a normal payout process. This is an operation to be executed when the number is small, and means an operation for re-executing the payout process (that is, a re-payout operation) in order to pay out unpaid game balls separately from the normal payout process.

  In the winning ball lending control process, the error bit is checked to determine whether or not to perform a payout operation (one winning ball payout or one ball lending). The payout start shown in FIG. Only in the waiting process. In the payout motor stop waiting process shown in FIG. 70 and the payout passing wait process shown in FIG. 71 and the like, the error bit is not checked. Note that the error bit is also checked in step S658 and the like in the payout passing waiting process, but this check is for determining whether or not to perform a payout operation again, and is a payout operation (single prize ball payout or 1 This is not to determine whether or not to start ball lending. Therefore, after the process of step S626 or S633 is performed and the game ball payout process is started, the payout process is not interrupted even if an error occurs. In other words, when an error occurs, the game ball payout process is continued until a point at which the game ball can be cut well (at the time when one prize ball payout or one ball lending ends). The error bit in the error flag checked in step S621 includes an error bit indicating that the power supply confirmation signal from the main board 31 has been turned off. Therefore, even when the power supply confirmation signal is turned off, the game ball payout process is stopped at a time when the turn is good. In addition, one-time prize ball payout or one-time ball rental means that a non-zero value is set in the prize ball unpaid number counter or the ball lending unpaid number counter, and the number of unpaid prize balls or the ball lending unpaid It means a game ball payout process until the value of the number counter becomes zero.

  When the power confirmation signal is turned off, similarly to the gaming machine described in Patent Document 1, if the payout is interrupted and the payout is resumed when recovered from the error state, the data (unpaid game) However, according to the present invention, the payout process is stopped at a time when the payout of the predetermined number of premium game media is completed and the cut-off time is good. Therefore, it is not necessary to manage such data, and the control can be simplified.

  When it is confirmed in step S653 that the ball lending / dispensing process (ball lending operation) has been executed, the payout control microcomputer 370 confirms whether or not the value of the lending / unpaid number counter is 0 (step). S657). If it is 0, it is determined that the ball lending / dispensing process is normally completed, and the process proceeds to step S655.

  If the value of the ball lending unpaid number counter is not 0, an error flag (specifically, any one of a payout switch abnormality detection error 1 bit, a payout switch abnormality detection error 2 bit, and a payout case error bit) On the condition that no bit or a plurality of bits) is set (step S658), the re-payout process is executed. If the error flag is set, the re-payout process is not executed.

  In order to execute the re-payout process, the pay-out control microcomputer 370 first checks whether or not 2 bits during re-payout operation are set (step S676). If not set, it is confirmed whether or not 1 bit is set during the re-payout operation (step S677). If 1 bit during re-payout operation is not set, 1 bit during re-payout operation is set to execute the first re-payout operation (step S679), and the process proceeds to step S666.

  In step S677, when it is confirmed that 1 bit is set during the re-payout operation, the payout control microcomputer 370 performs a process for executing the re-payout operation again. Specifically, 1 bit is reset during the re-payout operation (step S681). Then, 2 bits are set during the re-payout operation (step S685), and the process proceeds to step S666.

  In step S676, when it is confirmed that 2 bits during re-payout operation are set, the payout control microcomputer 370 resets 2 bits during re-payout operation (step S686), and sets the payout case error bit in the error flag. Set (step S688). Then, the process ends.

  As described above, in the case where the shortage of game balls is not solved even if two re-payout operations are continuously performed in the re-payout processing (corrected payout processing) related to the ball lending processing, As a failure, a payout count switch non-passing error bit (payout case error bit) is set.

  As described above, when the gaming control microcomputer 560 determines that the total number of unpaid award balls stored in the total award ball number storage buffer exceeds a predetermined abnormality determination number, the unpaid excess LED 362 is set. Since it is configured to be lit to notify the occurrence of an abnormality, the communication with the payout control microcomputer 370 is communicated with the microcomputer mounted on the unauthorized board by the notification of the occurrence of the abnormality by the unpaid excess LED 362. In this case, it is possible to notify that the illegal board is being executed.

  In this embodiment, when a winning occurs, the winning notification lamp 363 mounted on the main board 31 is lit for a predetermined period. Therefore, when a spoofing board is installed, the winning is not received. Even if it occurs, the winning notification lamp 363 can be prevented from being turned on, and it is possible to easily find out that the impersonation board is installed. Furthermore, when the winning notification lamp 363 is wired so that the detection signal of the winning detection switch (for example, the start opening switch 14a) is input not only to the spoofing board but also to the regular main board 31 so that the winning notification lamp 363 does not light up. Even so, since communication between the main board 31 and the payout control board 37 is not performed, the total number of unpaid prize balls stored in the total prize ball number storage buffer managed by the main board 31 is subtracted. As a result, the total number of unpaid prize balls stored in the total prize ball number storage buffer is equal to or greater than a predetermined abnormality determination number, and it is possible to easily find out that a spoofed board is installed. In the present invention, since the signal based on the progress of the game is recognized on the main board 31, for example, not only the start switch 14a but other winning detection switches (gate switch 32a, count switch 23, a winning notification lamp 363 may be turned on for a predetermined period by a detection signal of the winning opening switch 29a, 30a, 33a, 39a, etc.

  The unpaid excess LED 362 mounted on the main board 31 is housed in a board box (see FIG. 29) sealed by a fixing means that cannot be opened. Therefore, it is possible to prevent the unpaid excess LED 362 from being driven by a signal from the unauthorized board.

  In the first embodiment and the second embodiment, the initial setting of the random number circuit 503 (random number circuit setting process) is performed before the timer interrupt setting is performed. The timer interrupt may be set after the initial setting (random circuit setting processing) 503 (for example, steps S14 and S15 shown in FIG. 32 are performed in the reverse order). In the random number circuit setting process, a value based on the ID number unique to the game control microcomputer 560 may be set as the initial value of the random number. If comprised in this way, it can prevent that the setting of a random number circuit is changed during execution of a game control process, and can prevent an illegal act.

Embodiment 3 FIG.
In the first embodiment, the clock signal input to the latch signal generation circuit 533 is inverted, and the timing for updating the random number and the timing for storing the random number in the random value storage circuit 531 are shifted. The clock signal input to the generation circuit 533 may be delayed. Hereinafter, a third embodiment in which a clock signal input to the latch signal generation circuit 533 is delayed will be described.

  In the present embodiment, detailed description of the parts having the same configuration and processing as those of the first embodiment will be omitted, and parts different from the first embodiment will be mainly described.

  FIG. 74 is a block diagram illustrating another configuration example of the random number circuit 503. In this embodiment, the basic configurations of the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are the same. As shown in FIG. 74, this embodiment differs from the first embodiment in that the random number circuit 503 includes a delay circuit 532A instead of the inverting circuit 532 shown in FIG.

  The delay circuit 532A delays the random number generation clock signal SI1 input from the clock signal output circuit 524, thereby generating a delayed clock signal SI4 obtained by delaying the clock signal. Further, the delay circuit 532A outputs the generated delayed clock signal SI4 to the latch signal generation circuit 533. Therefore, in this embodiment, the latch signal generation circuit 533 outputs a latch signal to the random value storage circuit 531 in synchronization with the delayed clock signal SI4 obtained by delaying the random number generation clock signal SI1.

  The basic functions of the constituent elements of the random number circuit 503 other than the delay circuit 532A are the same as those functions described in the first embodiment.

  As described above, in this embodiment, the delay circuit 532A of the random number circuit 503 generates the delayed clock signal SI4 and outputs a latch signal for instructing storage of the random number in synchronization with the delayed clock signal SI4. . Therefore, the timing for updating the random number and the timing for storing the random number in the random value storage circuit 531 can be shifted, and the generated random number can be stored stably and reliably.

Embodiment 4 FIG.
FIG. 75 is a block diagram showing the configuration of the main board in the fourth embodiment. The configuration of the main board in the fourth embodiment is the same as the configuration of the main board in the first embodiment shown in FIG. 4 except that the interruption button 361 is not provided.

  FIG. 76 is a flowchart showing a part of main processing executed by the game control microcomputer 560 (specifically, the CPU 56). When the input level of the reset terminal to which the reset signal is input becomes high level, the game control microcomputer 560 executes a security check process that is a process for confirming whether the contents of the program are valid, The main processing after S1 is started.

  In this embodiment, the CPU 56 outputs an authentication signal (board ID uniquely given to the main board 31) to the verification terminal 364 in the main process (step S81), and sends the authentication signal to the effect control board 80. It transmits to (step S82). Other processes are the same as those shown in FIGS. 31 and 32.

  FIG. 77 is a flowchart showing a main process executed by the effect control microcomputer (the microcomputer mounted on the effect control board 80). In the main process, an initialization process is first performed for clearing the RAM area, setting various initial values, and initializing a 2 ms timer for determining the start interval of effect control (step S701). Thereafter, the effect control microcomputer proceeds to a loop process for confirming the monitoring of the timer interrupt flag (step S702). When a timer interrupt occurs, the effect control microcomputer sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set in the main process, the effect control microcomputer clears the flag (step S703) and executes the following effect control process.

  In this embodiment, the timer interrupt takes every 2 ms. That is, the effect control process is activated every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the specific effect control process is executed in the main process, but the effect control process may be executed in the timer interrupt process.

  In the effect control process, the effect control microcomputer first analyzes the received effect control command (command analysis process: step S704). Next, the effect control microcomputer performs effect control process processing (step S705). In the effect control process, a process corresponding to the current control state (effect control process flag) is selected from the processes corresponding to the control state, and display control of the variable display device 9 is executed. And the process which updates a random number counter is performed (step S706). Thereafter, the process returns to the process of checking the timer interrupt flag in step S702.

  Next, an effect control command reception process from the main board 31 will be described. FIG. 78 is an explanatory diagram showing a configuration example of a command reception buffer for storing the effect control command received from the main board 31. In this example, a command reception buffer of a ring buffer type capable of storing six 2-byte configuration effect control commands is used. Therefore, the command reception buffer is configured by a 12-byte area of reception command buffers 1 to 12. A command reception number counter indicating in which area the received command is stored is used. The command reception number counter takes a value from 0 to 11. It is not always necessary to use the ring buffer format. For example, three symbol designating command storage areas (2 × 3 = 6 byte command receiving buffer) and other command storing areas for designating other variation patterns ( (2 × 1 = 2-byte command reception buffer). Similarly, the sound control means and the lamp control means may have a buffer format other than the ring buffer format.

  An INT signal for effect control from the main board 31 is input to an interrupt terminal of the effect control microcomputer. For example, when the INT signal from the main board 31 is turned on, the production control microcomputer is interrupted. Then, the effect control microcomputer executes an effect control command reception process in the interrupt process. In the effect control command reception process, the effect control microcomputer stores the received effect control command data in the reception command buffer indicated by the command reception number counter.

  FIG. 79 is a flowchart showing a specific example of command analysis processing (step S704). The effect control command received from the main board 31 is stored in the reception command buffer, but in the command analysis process, the effect control microcomputer confirms the contents of the command stored in the command reception buffer.

  In the command analysis process, the effect control microcomputer first checks whether or not a reception command is stored in the command reception buffer (step S921). Whether it is stored or not is determined by comparing the value of the command reception number counter with the read pointer. The case where both match is the case where the received command is not stored. When the reception command is stored in the command reception buffer, the effect control microcomputer reads the reception command from the command reception buffer (step S922). When read, the value of the read pointer is incremented by +2 (step S923).

  If the received effect control command is an effect control command for designating a variation pattern (step S924), the effect control microcomputer stores the EXT data of the command in the variation pattern data storage area (step S925).

  If the received effect control command is an effect control command for designating a display result (step S926), the effect control microcomputer stores the EXT data of that command as a special symbol display result in the special symbol storage area (step S927). ).

  If the received effect control command is an effect control command indicating an authentication signal (board ID) (step S928), the effect control microcomputer stores the board ID indicated by the command and the ROM or RAM included in the effect control board 80. A collation process is performed in which the board ID of the main board 31 stored is collated to determine whether or not they match each other as a collation result (step S929). And the collation result is alert | reported by performing a predetermined display on the variable display apparatus 9 (step S930).

  If it is determined that the board ID received by the matching process matches the stored board ID, the effect control microcomputer, for example, displays “verification OK” in the variable display device 9 in step S930. To display.

  If it is determined that the board ID received by the matching process and the stored board ID do not match, the effect control microcomputer variably displays, for example, “matching NG” in the process of step S930. Display on the device 9.

  If the collation result is not collation OK (N in step S931), the effect control microcomputer controls the operation to be stopped (step S932). Note that the operation stop state means a state in which substantial control for effect control is stopped, such as a system reset state or a state where the effect control process is not executed.

  When the received command read in step S922 is another effect control command, the effect control microcomputer sets a command reception flag corresponding to the received command, and stores the received command if necessary (step S933). ).

  As described above, in this embodiment, the game control microcomputer 560 transmits the board ID to the collator 365 via the collation terminal 364 and the board ID to the effect control microcomputer. When the microcomputer for effect control determines whether or not to authenticate the main board 31 based on the board ID, and determines not to authenticate, it notifies that the main board 31 is not authenticated and operates. Since it is configured to perform control for stopping, for example, a game store clerk is allowed to transmit a board ID to the production control microcomputer (for example, power-on again, game ball to start prize opening) Thus, it is possible to easily find out that the illegal circuit board is installed. That is, the gaming machine of this embodiment has a function of mutually monitoring the ID of the game control microcomputer 560 and the IDs of microcomputers on other boards. If the microcomputer on the other board cannot receive the regular ID of the game control microcomputer 560, the spoofing board may be performing the game control process in place of the main board 31. In this embodiment, a microcomputer on another substrate (in this example, a production control microcomputer) detects the presence of a spoofed substrate.

  In this embodiment, the production control microcomputer determines whether or not to authenticate the main board 31 in response to receiving the board ID, but when power supply to the gaming machine is started. When the board ID is not received from the game control microcomputer 560 within a predetermined period from the first, a judgment is made that the verification is NG, and a notification that the main board 31 is not authenticated or a control for stopping the operation is performed. Good. In this case, the production control microcomputer notifies the variable display device 9 that the main board 31 is not authenticated until the board ID is received after the power supply to the gaming machine is started (for example, “verification NG” May be displayed). Specifically, for example, the display of “collation NG” is started in the process of step S701, and when it is determined as “collation OK” in step S619, the authenticated flag is set and the display of “collation NG” is displayed. It is sufficient to display the “verification OK” for a predetermined period. The authenticated flag is reset when power supply to the gaming machine is started (step S701) or when power supply is stopped. Also, in this case, the production control microcomputer controls the operation stop state until the board ID is received after the power supply to the gaming machine is started (except for the process for receiving the board ID). For example, it may be configured such that reception confirmation of the board ID is performed before starting the effect control process, and the effect control process is controlled not to be started). That is, when power supply to the gaming machine is started, the gaming control microcomputer 560 transmits the board ID to the presentation control microcomputer, and the presentation control microcomputer receives the board ID. Until now, it may be configured to perform at least one of notification that the game control board is not authenticated and control of the operation stop state. With such a configuration, it is possible to determine whether or not an unauthorized circuit board is installed every time power supply to the gaming machine is started.

  Note that any method of communicating the board ID from the main board 31 to the effect control board 80 may be used. For example, the main board 31 and the effect control board 80 may be synchronized to transmit and receive the board ID. May be.

  Further, in this embodiment, when it is determined that the main board 31 is not authenticated based on the board ID, a notification that the main board 31 is not authenticated is given, and a control for stopping the operation is performed. However, either the notification that the main board 31 is not authenticated or the control for stopping the operation may be performed.

  In each of the above embodiments, the same ID is used for the ID used for collation and the ID for setting the initial value of the random number. However, the present invention is not limited to this, and a separate ID is used. May be.

  Further, in each of the above embodiments, the game control microcomputer 560 is connected to the verification machine 365 via the verification terminal 364 on the condition that a winning detection signal is input from the start port switch 14a. When the microcomputer for effect control determines whether or not to authenticate the main board 31 based on the board ID, and determines not to authenticate, it notifies that the main board 31 is not authenticated and operates. Since it is configured to perform the control to be stopped, it can be easily found that the unauthorized circuit board is installed. That is, when the game ball is won at the start winning opening 14, if the verification NG is displayed, the game store clerk or the like can recognize that there is a possibility that some illegal act has been performed. If neither the display nor the verification NG is displayed, the verification process based on the board ID by the effect control microcomputer is not executed (the winning detection signal from the start port switch 14a is input to the spoofed board and the main board 31 is not processed). Therefore, the game shop clerk can recognize that an illegal circuit board is installed. Therefore, it can be easily found that the illegal circuit board is installed. Here, in the case where an illegal circuit board is installed, the display is not performed when the verification OK is supposed to be displayed, so that the verification OK is not displayed. This corresponds to notification that 31 is not authenticated.

  As a countermeasure when a winning detection signal from the start port switch 14a is input to the spoofing board and the main board 31, for example, display processing by the effect control microcomputer may be stopped during the matching process. In this way, when the illegal circuit board is installed, the variable display on the variable display device 9 is started before the result of the verification process based on the occurrence of the start winning is displayed. For this reason, even if the winning detection signal from the start port switch 14a is inputted to the spoofing board and the main board 31, it can be easily found that the illegal circuit board is installed.

  In each of the above embodiments, the game control microcomputer 560 is connected to the verification machine 365 via the verification terminal 364 on the condition that a winning detection signal is input from the start port switch 14a. However, the board ID may be transmitted on condition that a winning detection signal from another winning detection switch is input.

  In each of the above embodiments, the random number circuit 503 is initially set (random number circuit setting process) from the start of power-on to the gaming machine until the timer interrupt is set, and in the random number circuit setting process, A value based on the ID number unique to the game control microcomputer 560 is set as an initial value of the random number. Therefore, the randomness of the random number generated by the random number circuit 503 can be improved. In addition, since randomness of random numbers can be improved, the timing of random number generation can be made difficult to be recognized by a player or a game store, and a capture signal using a radio signal can be generated for a gaming machine. It is possible to prevent the condition for shifting to a specific gaming state such as a big hit state from being illegally established.

  In each of the above embodiments, the inversion circuit 532 of the random number circuit 503 generates the inverted clock signal SI2 whose polarity is inverted, and the latch signal for instructing the storage of the random number in synchronization with the inverted clock signal SI2. Output. Therefore, the timing for updating the random number and the timing for storing the random number in the random value storage circuit 531 can be shifted, and the generated random number can be stored stably and reliably.

  Further, the board ID transmitted as a signal may be encrypted. The board ID is an ID uniquely determined for the main board 31, but may be any of a plurality of IDs allowed for authentication by the manufacturer of the microcomputer. If the ID is one of a plurality of IDs, the subject executing the verification process (the verification machine 365, the production control microcomputer) uses a plurality of IDs permitted by the microcomputer manufacturer for authentication. What is necessary is just to determine whether it authenticates by memorizing | storing beforehand and determining whether the received board | substrate ID is one of them.

  In each of the above embodiments, the game store clerk or the like can check the connection state between the main board 31 and the effect control board 80 by notifying the presence / absence of the board ID and the collation result.

  Further, in each of the above embodiments, the variable display means capable of variably displaying a plurality of types of identification information that can identify each of them is provided, and variable display starts after a predetermined variable display execution condition is satisfied. A game in which the variable display means starts variable display of the identification information based on the establishment of the condition, and when the display result of the variable display of the identification information becomes a specific display result, the game shifts to a specific game state advantageous to the player Although a machine (hereinafter referred to as model A) is illustrated, the gaming machine according to the present invention is not limited to such a gaming machine, and has no “variable display means capable of variably displaying identification information”. It can also be applied to. In other words, the variable winning device is released a predetermined number of times by winning in a predetermined start winning area, and when the game medium that has won the variable winning apparatus through the opening passes through the specific area (V area), it enters a specific gaming state (big hit state). The present invention can also be applied to a controlled gaming machine (hereinafter referred to as model B).

  Further, the present invention can be applied to a mixed type model of model A and model B. In other words, variable display means is provided that can variably display a plurality of types of identification information that can identify each of them. After a predetermined variable display execution condition is satisfied, variable display is performed based on the satisfaction of the variable display start condition. The variable display of the identification information is started by the means, and when the display result of the variable display of the identification information becomes the specific display result, the control to shift to the specific gaming state advantageous to the player, and the variable display of the identification information When the display result becomes a predetermined display result (small hit) different from the specific display result, the variable winning device is released a predetermined number of times, and the game media that has won the variable winning device by the release has a specific region (V region). It may be a gaming machine that executes a control that shifts to a specific gaming state (big hit state) by passing through.

  In each of the above-described embodiments, the control command from the main board 31 is input to the effect control board 80, and the control command is input to the lamp driver board 35 and the audio output board 70 via the effect control board 80. However, other substrate configurations may be used. For example, the effect control board 80, the lamp driver board 35, and the audio output board 70 may be configured by a single board. Further, for example, a control command from the main board 31 is input to the lamp driver board 35 and the audio output board 70, and a control command is input to the effect control board 80 via the lamp driver board 35 or the audio output board 70. It may be configured.

  Further, in each of the above-described embodiments, the description has been made assuming that the “spoofed” illegal circuit board is found in the main board 31, but the present invention is applicable to those in which the “spoofed” illegal circuit board is found in the payout control board 37. Is also possible.

  Next, the overall configuration of a slot machine (slot machine), which is another example of the gaming machine in each of the embodiments described above, will be described. FIG. 80 is a front view of the slot machine as seen from the front.

  As shown in FIG. 80, in the slot machine 600, a game panel 601 is detachably attached near the center. Further, a variable display device 602 for variably displaying a plurality of types of symbols is provided near the center of the front surface of the game panel 601. In this embodiment, the variable display device 602 has three symbol display areas of “left”, “middle”, and “right”, and the symbol display reels 602a, 602b, and 602c correspond to the symbol display areas, respectively. Is provided.

  Below the game panel 601, an operation table 620 is provided in which various input switches and the like for the player to perform various operations are arranged. On the back side of the operation table 620, a BET switch 621 for betting (putting) coins one by one, and a MAXBET switch 622 for betting coins by the maximum number (three in this example) that can be placed in one game. A settlement switch 623 and a coin insertion slot 624 are provided. Coins inserted into the coin insertion slot 624 are detected by an inserted coin sensor (not shown).

  On the front side of the operation table 620, a start switch 625, a left reel stop switch 626a, a middle reel stop switch 626b, a right reel stop switch 626c, and a coin jam elimination switch 627 are provided. Lamps 628a and 628b are provided on the right and left sides of the operation table 620, respectively. Below the operation table 620, a speaker 630 for outputting sound effects and the like is provided.

  On the upper part of the game panel 601, an image display device (LCD: liquid crystal display device) 640 for notifying a player of a game method, a game state, and the like is provided. For example, when a winning occurs, an image in which a character performs a predetermined action is displayed on the image display device 640 to notify the player that a winning flag described later is set. Two speakers 641L and 641R that emit sound effects are provided on the left and right of the image display device 640.

  The winning combinations generated in the slot machine 600 include a small winning combination, a replay winning, a big bonus winning, and a regular bonus winning. In the slot machine 600, random numbers are extracted at the timing when the start switch 625 is operated, and it is determined whether or not the winning of any winning combination is allowed. The fact that winnings are allowed is said to be “winning internally”. When an internal winning is made, a winning flag indicating that is set in the slot machine 600. In the game with the winning flag set, the reels 602a to 602c are controlled so that the winning combination corresponding to the winning flag can be drawn. On the other hand, in a game in which the winning flag is not set, the reels 602a to 602c are controlled so that no winning is generated.

  Note that the game control microcomputer that controls the progress of the game of the slot machine 600 incorporates a random number circuit (12-bit random number circuit and 16-bit random number circuit) that generates random numbers. Further, the game control microcomputer extracts the random number (random R) generated by the random number circuit at the timing when the start switch 625 is operated. For example, when the start switch 625 is pressed, the CPU 56 inputs the detection signal SS from the start switch 625. When the timer circuit 534 of the random number circuit detects that the detection signal SS has been input continuously for a predetermined time, the random number value fetch data “01 (H)” is written in the random value fetch register 539, and the latch signal The generation circuit 533 outputs the latch signal SL to the random value storage circuit 531. When the latch signal SL is input, the random value storage circuit 531 reads and stores the count value updated by the counter 521. Further, when the CPU 56 detects that the detection signal SS is continuously input a predetermined number of times (for example, three times), the CPU 56 outputs the output control signal SC to the random number value storage circuit of the random number circuit, and the random number value is output from the random number circuit. (Random R) is extracted. Then, the game control microcomputer determines whether or not the winning is allowed based on the extracted random R.

Next, an outline of the game provided by the slot machine will be described.
For example, when a multiplier is set by inserting a coin from the coin insertion slot 624 and pressing the BET switch 621 or the MAXBET switch 622, the operation of the start switch 625 becomes effective. When the player operates the start switch 625, the symbol display reels 602a to 602c provided in the variable display device 602 start rotating. In addition, when a regular bonus prize or a big bonus prize is internally won at the timing when the start switch 625 is operated, for example, a screen on which a predetermined character performs a predetermined action is displayed on the image display device 640. Thus, the player or the like is notified that the internal winning is made.

  When a predetermined time elapses after the symbol display reels 602a to 602c start rotating, the operations of the reel stop switches 626a to 626c become effective. In this state, if the player presses one of the reel stop switches 626a to 626c, the rotation of the reel corresponding to the operated stop switch is stopped. When the symbol display reels 602a to 602c are left for a predetermined period or longer without being stopped, the symbol display reels 602a to 602c are automatically stopped.

  When all the symbol display reels 602a to 602c are stopped, the symbol display reels 602a to 602c displayed on the variable display device 602 are determined according to the number of symbols in the upper, middle and lower three symbols. Whether or not a prize is won is determined by a combination of symbols positioned on a valid winning line. When the multiplying number is 1, only the middle one horizontal winning line in the variable display device 602 is valid. When the multiplying number is 2, the top three, the middle, and the bottom three pay lines in the variable display device 602 are valid. When the number of multiplications is 3, a total of five pay lines of three horizontal rows and two diagonal diagonal lines in the variable display device 602 are effective lines.

  When a combination of symbols on the active line becomes a specific display mode determined in advance and a winning occurs, a predetermined game effect is made by sound, light, display on the image display device 640, etc., and the winning is generated The game according to is started.

  In the slot machine 600, the effect control means mounted on the slot machine 600 performs display control of the image display device 640 provided in the slot machine 600. The image display device 640 displays various kinds of information such as a decorative pattern change display and a display for notifying a game state and a game method under the control of the effect control means. Various information such as decorative pattern variation display, display for notifying a game state and a game method, and the like are displayed by a movie image, and display control of the movie image is performed by the image processing device 640. do it.

  In each of the above embodiments, a gaming machine configured as follows is also disclosed.

  A variable display means (for example, special symbol display 8) capable of variably displaying a plurality of types of identification information (for example, special symbols) that can identify each of them is provided, and predetermined variable display execution conditions (for example, starting) After the winning of the game ball to the winning opening 14 is established, the variable information is started to be displayed based on the establishment of the variable display start condition (for example, the final stop of the special symbol and the end of the jackpot game). A random number circuit that generates a random number (for example, a random number circuit) that shifts to a specific gaming state advantageous to the player when the display result of the variable display becomes a specific display result (for example, a jackpot symbol) 503) and a game control microcomputer (for example, a game control microcomputer 560) for executing a game control process for controlling the progress of the game, and a game control process. A game control board (for example, the main board 31) equipped with a game interruption operation means (for example, an interruption button 361) for outputting an interruption operation signal for interrupting the game control process. Based on the input of a signal (for example, a clock signal), the numerical data is updated in a predetermined order from a predetermined initial value to a predetermined final value within a predetermined range in which the numerical data (for example, count value) can be updated. Including a numerical value updating means (for example, a counter 521) and a random number storage means (for example, a random value storage circuit 531) for storing numerical data updated by the numerical value updating means as a random number value. Random circuit initial setting means for initializing the random number circuit when power supply to the gaming machine is started (for example, a game control micro Part for executing step S14 in the computer 560) and an interrupt setting means (for example, setting for generating a timer interrupt every predetermined time after the random number circuit initial setting means performs initial setting of the random number circuit) , A part for executing step S15 in the game control microcomputer 560) and a game control process (for example, processes in steps S21 to S33 (excluding step S29) in the timer interrupt process) when a timer interrupt occurs. Variable in the interrupt process execution means (for example, the part that executes the processes of steps S20 to S35 in the game control microcomputer 560) and the timer interrupt process by the interrupt process execution means. Random number reading that reads the random value stored in the random number storage means when the display execution condition is satisfied By determining whether or not the random number value read by the random number reading means matches the predetermined determination value by the output means (for example, the part of the game control microcomputer 560 that executes the process of step S324) Display result determining means for determining whether or not the display result of the variable display of the identification information is a specific display result (for example, a part for executing the process of step S300 in the game control microcomputer 560), and a game control process; A random number circuit initial setting means for initializing the numerical data to be updated by the numerical value updating means in the initial setting, including a game control process interrupting means for interrupting (for example, the portion of the game control microcomputer 560 that executes the process of step S85). A predetermined initial value is assigned to the game control microcomputer assigned to each game control microcomputer. Set based on microcomputer identification information for identifying the microcomputer (for example, the ID number unique to the game control microcomputer 560) (for example, the process of step S154b), the game control process interrupting means is selected from the game interrupt operating means. The game machine is characterized in that the game control process is interrupted in response to the input of the interrupt operation signal (for example, Y in step S85). According to such a configuration, the game control process can be intentionally interrupted, and when the intentional interruption cannot be performed, it is possible to easily find the illegal board as having the illegal board installed. Can do.

  The game control board is housed in a board box (for example, the game control board box shown in FIG. 29) sealed by a fixing means that cannot be opened, and an operation portion of the game interruption operation means (for example, a pressing operation portion of the interruption button 361). Is a game machine installed facing the opening formed in the board box (for example, the opening provided in the lid 31B). According to such a configuration, it is possible to prevent the game from being interrupted by inputting the interruption operation signal from the game interruption operation means to the unauthorized board.

  It is possible for a player to play a predetermined game using a game medium, and a prize game medium is paid out as a prize based on the fact that a payout condition is established by the game (for example, a prize is generated), and each can be identified. Variable display means (for example, special symbol display 8) capable of variably displaying the type of identification information (for example, special symbol) is provided, and a predetermined variable display execution condition (for example, a game to the start winning opening 14) After the winning of the ball) is established, the variable information display starts based on the establishment of the variable display start conditions (for example, the final stop of the special symbol and the end of the jackpot game), and the display result of the variable display of the identification information Is a gaming machine that shifts to a specific gaming state that is advantageous to the player when a specific display result (for example, a jackpot symbol) is obtained, and a random number circuit (for example, random number generation) that generates random numbers. A game control board (for example, the main board 31) on which a game control microcomputer (for example, the game control microcomputer 560) that executes a game control process for controlling the progress of the game is incorporated, and a prize game A random number circuit comprising: a payout means (for example, a ball payout device 97) for paying out a medium; and a payout control microcomputer (for example, a payout control microcomputer 370) for executing a payout control process for controlling the payout means. Numerical data according to a predetermined order from a predetermined initial value to a predetermined final value within a predetermined range in which numerical data (for example, a count value) can be updated based on an input of a predetermined signal (for example, a clock signal) Numerical value updating means (for example, counter 521) for updating the numerical value, and numerical values updated by the numerical value updating means Random number storage means (for example, a random value storage circuit 531) for storing the data as a random value, and the gaming control microcomputer performs initial setting of the random number circuit when power supply to the gaming machine is started. After the random number circuit initial setting means (for example, the portion of the game control microcomputer 560 that executes the process of step S14) and the random number circuit initial setting means perform the initial setting of the random number circuit, the timer allocation is performed every predetermined time. Interrupt setting means (for example, a part for executing the processing of step S15 in the game control microcomputer 560) for making a setting for generating an interrupt, and a game control process (for example, a timer when a timer interrupt occurs) Interrupt processing for executing timer interrupt processing including steps S21 to S33 (except for step S29) in the interrupt processing When the execution condition for variable display is satisfied in the physical execution means (for example, the part that executes the processing of steps S20 to S35 in the game control microcomputer 560) and the timer interruption process by the interruption process execution means, Random number reading means for reading the random number value stored in the storage means (for example, the part for executing the processing of step S324 in the game control microcomputer 560) and the random number value read by the random number reading means match the predetermined determination value. Display result determining means for determining whether or not the display result of the variable display of the identification information is to be a specific display result by determining whether or not to perform (for example, the process of step S300 in the game control microcomputer 560). And the number of premium game media to be paid out based on the establishment of the payout conditions. The prize game medium number data is stored in the prize game medium number storage means (for example, the RAM 55 in the game control microcomputer 560) for storing definite prize game medium number data, and the prize game medium number storage means. A payout command signal output means (for example, game control) for turning on a payout command signal for designating the number of prize game medium payouts to a payout control microcomputer based on a predetermined command condition. Portion of the microcomputer 560 for executing steps S254 and S255), and when the predetermined subtraction condition is satisfied after the payout command signal output means turns on the payout command signal, it is stored in the prize game medium number storage means. Subtraction to subtract the value corresponding to the number of payouts specified by the payout command signal from the number of prize game media data A prize game medium number data subtracting means (for example, a part for executing the processing of steps S261 and S262 in the game control microcomputer 560), and the payout control microcomputer receives the payout command signal. A reception confirmation signal output means for turning on a reception confirmation signal indicating that the payout command signal has been received (for example, a part for executing steps S544 and S546 in the payout control microcomputer 370), and a payout means. And a payout game medium payout control means (for example, steps S631, S633, S637 and the like in the payout control microcomputer 370) for executing payout processing for paying out the premium game media of the payout number specified by the payout command signal. Processing portion), and a prize game medium The number data subtracting means performs a subtraction process when the reception confirmation signal is turned on as a predetermined subtraction condition is satisfied (for example, the processes of steps S261 and S262 are executed), and the random number circuit initial setting means performs initial setting. The predetermined initial value of the numerical data updated by the numerical value updating means is microcomputer identification information for identifying the game control microcomputer assigned to each game control microcomputer (for example, unique to the game control microcomputer 560). The ID game number is set based on the ID number (for example, the process of step S154b is executed), and the game control microcomputer uses the prize game medium number data stored in the prize game medium number storage means to be paid out. A predetermined abnormality notification means (for example, unpaid excess) Controls ED362) reports the occurrence of abnormality (e.g., step S174, the process execution of S175) game machine, characterized in that. According to such a configuration, it is possible to notify that the communication with the payout control microcomputer is being executed with the microcomputer mounted on the unauthorized substrate by notifying the occurrence of the abnormality by the abnormality notifying means. This makes it possible to easily find illegal boards.

  The game control board is accommodated in a board box (for example, the game control board box shown in FIG. 29) sealed by an unopenable fixing means, and the abnormality notification means (eg, unpaid excess LED 362) is accommodated in the board box. Gaming machines. According to such a configuration, it is possible to prevent the abnormality notifying unit from being driven by a signal from the unauthorized substrate.

  In order for the interrupt setting means to generate a timer interrupt every predetermined time after the random number circuit initial setting means performs the initial setting of the random number circuit (for example, step S14) after the power supply to the gaming machine is started. (For example, the process of step S15 is performed after the process of step S14 is performed), and the random number circuit initial setting unit is set to generate a timer interrupt by the interrupt setting unit. A gaming machine configured to perform initial setting of a circuit. According to such a configuration, it is possible to prevent the setting of the random number circuit from being changed during the execution of the game control process, and to prevent fraud.

  The game control microcomputer includes a plurality of random number circuits (for example, a 12-bit random number circuit 503a and a 16-bit random number circuit 503b) having different predetermined ranges of numerical data that can be updated by the numerical value updating means, and the random number circuit initial setting means has In the initial setting, a random number circuit that can be used is set from among a plurality of random number circuits built in the game control microcomputer (for example, the game control microcomputer 560 executes the process of step S151). Random number stopping means for stopping the function of a random number circuit other than the random number circuit set to be usable by the setting means (for example, when the game control microcomputer 560 sets the random number circuit 503 used in the processing of step S151, it is not used. The counter 521 of the random number circuit that is set as The gaming machine having a part) be controlled so as not new. According to such a configuration, by setting only the random number circuit to be used, the range of the random number value to be generated can be appropriately set.

  In the initial setting, the random number circuit initial setting means sets a numerical value maximum value register (for example, the random number maximum value setting register 535) in which a value as a maximum value in a predetermined range in which numerical data is updated is set by the numerical value updating means. A predetermined maximum value (for example, a random number maximum value) is set within the range of the numerical data that can be updated (for example, the part in which the game control microcomputer 560 executes the process of step S152), and the numerical value updating means includes a random number circuit Setting value determination means for determining whether or not the predetermined maximum value set by the initial setting means is equal to or less than a predetermined lower limit value (for example, “256” when the 12-bit random number circuit 503a is set) The portion of the game control microcomputer 560 that executes the process of step S153b) and the set value determination means When it is determined that the predetermined maximum value set in the value register is equal to or smaller than the predetermined lower limit value, a predetermined value (for example, 12) within the range of numerical data that can be updated by the numerical value updating means is stored in the numerical maximum value register. A gaming machine including maximum value resetting means (for example, a part for executing step S153c in the gaming control microcomputer 560) for resetting “4095” when the bit random number circuit 503a is set. According to such a configuration, an excessively small value is set as the maximum value of the random number due to an action such as malfunction of the game control microcomputer or generation of a capture signal using a radio signal for the gaming machine. Can be prevented.

  Clock signal generation means (for example, clock circuit 501) that generates a clock signal with a predetermined period and outputs it to a random number circuit is provided, and the numerical value update means updates the numerical data on condition that the clock signal has been input a predetermined number of times. (For example, when the clock signal output circuit 524 inputs the random number generating clock signal SI obtained by dividing the reference clock signal CLK by 16, the counter 521 updates the count value C). A gaming machine configured to set the number of clock signal inputs, which is a condition for the numerical value updating means to update the numerical data (for example, the game control microcomputer 560 executes the process of step S156). According to such a configuration, the randomness of the random number generated by the random number circuit can be further improved.

  The game control microcomputer uses the microcomputer identification information to calculate a predetermined initial value of the numerical data set by the random number circuit initial setting means (for example, the processing of step S154b in the game microcomputer is executed) The game control microcomputer 560 calculates an ID number and a predetermined value (for example, a part for obtaining a calculated value by adding a predetermined value to the ID number), and the random number circuit initial setting means includes: An initial value is set based on the value calculated by the calculation by the numerical calculation means (for example, when the gaming microcomputer executes the process of step S154b, the calculated calculated value is set as the initial value of the count value). A gaming machine configured as follows. According to such a configuration, the randomness of the random number generated by the random number circuit can be further improved.

  The random number circuit initial setting means sets whether or not to change the predetermined initial value set by the random number circuit initial setting means when the numerical data is updated to a predetermined final value by the numerical value updating means in the initial setting. (For example, the game control microcomputer 560 executes the process of step S157). When the random number circuit is updated to the predetermined final value by the numerical value updating means, the numerical data is updated to the predetermined final value. Based on the notification signal output means (for example, the output terminal of the counter 521) that outputs a notification signal indicating the fact that the notification has been output, the initial value is set to be changed by the random number circuit initial setting means. The initial value changing means for changing the value of the predetermined initial value (eg, step S2 in the game control microcomputer 560) It constructed gaming machine so as to include a portion) and executing the processing in 0～S226. According to such a configuration, the randomness of the random number generated by the random number circuit can be further improved.

  A winning detection means for detecting that a game medium has won a winning area (for example, start winning opening 14) in the gaming area, and that a variable display execution condition is satisfied, and outputs a winning detection signal (for example, a winning detection signal SS). (For example, the start port switch 14a), and the random number circuit instructs the random number storage means to store numerical data to be updated by the numerical value updating means based on the input of the winning detection signal from the winning detection means. Including a latch signal output means (for example, a latch signal generation circuit 533) for outputting a latch signal for the condition, for example, on condition that the winning detection signal is continuously input from the winning detection means for a predetermined period (for example, When the timer circuit 534 measures a predetermined period (for example, 3 ms), the random value read signal output from the random value read signal output circuit 526 is input. (For example, the latch signal generation circuit 533 uses the random number read signal output from the random value read signal output circuit 526 as the rising edge of the inverted clock signal SI2 output from the inversion circuit 532). (The portion that is output to the random value storage circuit 531 as a latch signal SL). According to such a configuration, it is possible to prevent the occurrence of noise from being erroneously recognized as the input of the input detection signal, outputting the latch signal, and storing the generated random number. In addition, it is possible to reduce the possibility that a random number generated by an illegal latch signal is stored due to an output of a latch signal by an action such as generating a capture signal using a radio signal to the gaming machine. .

  A winning detection means (for example, a start port switch 14a) for detecting that a game medium has won a winning area in the gaming area, and that a variable display execution condition is satisfied, and outputs a winning detection signal, is provided. Latch signal output means (for example, latch signal) for outputting a latch signal for instructing the random number storage means to store numerical data updated by the numerical value update means based on the winning detection signal input from the detection means Generation circuit 533), and the latch signal output means outputs a latch signal (for example, the latch signal generation circuit 533 generates a random signal) on condition that the winning detection signal is continuously input from the winning detection means for a predetermined period. The random number read signal output from the numerical read signal output circuit 526 is used as the rising edge of the inverted clock signal SI2 output from the inverter circuit 532. The portion that is output to the random value storage circuit 531 as the latch signal SL), the random number reading means continues while the timer interruption processing is executed a predetermined number of times by the interruption processing execution means, If the detection signal is input (for example, when the game control microcomputer 560 executes the process of step S322, the number of executions of the timer interrupt process indicated by the interrupt counter is a predetermined number (for example, 3 The random number stored in the random number storage means is read (for example, the CPU 56 reads the random R value stored as the random number value from the random number storage circuit 531 of the random number circuit 503). ), A predetermined period (for example, 3 ms) is configured to be shorter than a period (for example, 6 ms) in which a predetermined number of timer interruption processes are executed. Tricks machine. According to such a configuration, it is possible to prevent the random number from being read again after the random number is read and before the value of the random number stored in the random number storage unit is updated. Therefore, it is possible to prevent a random number having the same value as the random number read from the previous random number storage unit from being read again. The randomness of the random number generated by the random number circuit can be further improved.

  In the initial setting, the random number circuit initial setting means sets the order of the values from the predetermined initial value to the predetermined final value of the numerical data updated by the numerical value updating means (for example, the permutation of the count value C updated by the counter 521). Including a numerical order setting means for setting whether or not to change (for example, a part for executing the processing of step S158 in the game control microcomputer 560), and the random number circuit receives numerical data up to a predetermined final value by the numerical value updating means. Based on the notification signal output means (for example, the output terminal of the counter 521) that outputs a notification signal indicating that the numerical data has been updated to a predetermined final value and the notification signal is output. The random number circuit initial setting means is configured to change the order of arrangement of numerical data from a predetermined initial value to a predetermined final value. Numerical value order changing means for changing the order of numerical data updated by the value updating means from a predetermined initial value to a predetermined final value (for example, a part for executing step S24 in the game control microcomputer 560). A gaming machine configured to. According to such a configuration, the randomness of the random number generated by the random number circuit can be further improved.

  A game machine in which a player can play a predetermined game, and executes a game control process for controlling the progress of the game (for example, the processes of steps S21 to S33 (excluding step S29) in the timer interrupt process) A game control board (for example, main board 31) on which a game control microcomputer (for example, game control microcomputer 560) is mounted, and directing means (for example, a variable display device) based on commands from the game control microcomputer 9, an effect control board (for example, effect control board 80) equipped with an effect control microcomputer (for example, a microcomputer mounted on the effect control board 80) for controlling the speaker 27, the lamp 25, etc., and a game control board Includes a game control microcomputer authentication information (for example, a game control microphone). A matching terminal (for example, a matching terminal 364) is provided for outputting the authentication information to a matching machine (for example, the matching machine 365) that checks the correctness by checking the ID number unique to the computer 560. The computer transmits first authentication information transmitting means (for example, a part for executing the processing of step S81 in the game control microcomputer 560) to the verification machine via the verification terminal, and the effect control micro Second authentication information transmitting means for transmitting authentication information to the computer (for example, the part of step S82 in the game control microcomputer 560). The effect control microcomputer includes the authentication information in the authentication information. Authentication determination means for determining whether or not to authenticate the game control board based on (for example, production system) When the authentication information is not received, or the authentication determining means determines that the authentication is not performed (for example, the part that executes the process of step S929 in the microcomputer for use) (for example, When the result of the collation by the process of step S929 is inconsistent), a notification that the game control board is not authenticated (for example, “verification NG” is displayed in the process of step S930) or a control to stop the operation (for example, step S932) A gaming machine that performs at least one of the following. According to such a configuration, it is possible to easily discover that the unauthorized circuit board is installed by causing the second authentication information transmitting means to transmit the authentication information.

  The second authentication information transmitting means transmits the authentication information to the effect control microcomputer when the power supply to the gaming machine is started (for example, the processing of step S82 is executed), and the effect control microcomputer is performed. However, for example, until the authentication information is received by the authentication information receiving means that receives the authentication information, a notification that the game control board is not authenticated is displayed (for example, display of “verification NG” in the process of step S701 is started, When it is determined that “verification is OK” in the process of S929, the display of “verification NG” is ended and “verification OK” is displayed.) Or at least one of the control to make the operation stop state (for example, step S932) is performed. A gaming machine configured as follows. According to such a configuration, it is possible to determine whether or not an unauthorized circuit board is installed every time power supply to the gaming machine is started.

  A gaming machine in which a player can perform a predetermined game using a game ball, and a winning detection signal is output when it is detected that the game ball has won a predetermined winning area (for example, a start winning port 14). The game winning control means (for example, the processing of steps S21 to S33 (excluding step S29) in the timer interrupt processing) for controlling the progress of the game and the winning detection means (for example, the start switch 14a) to be output. A game control board (for example, main board 31) on which a microcomputer (for example, a game control microcomputer 560) and an input circuit (for example, input driver circuit 58) for inputting a winning detection signal from the winning detection means are mounted. The game control board includes authentication information for the game control microcomputer (for example, I-specific information for the game control microcomputer 560). A verification terminal (for example, a verification terminal 364) for outputting the authentication information to a verification machine (for example, the verification machine 365) that verifies whether the game is correct or not. Authentication information transmitting means (for example, a part for executing the processing of step S320 in the game control microcomputer 560) for transmitting authentication information to the input circuit via the verification terminal. A gaming machine, wherein authentication information is transmitted (for example, step S320) on condition that a winning detection signal from the detection means is input (for example, Y in step S311). According to such a configuration, it is possible to easily discover that an unauthorized circuit board is installed by causing the winning detection means to detect the game medium and causing the authentication information transmitting means to transmit authentication information. Can do.

  Further, as described above, the main board 31 is housed in the board box, but the impersonation board (illegal board) has the same function as the original main board 31 and is smaller than the main board 31. Is formed. Therefore, it is difficult to find. In addition, it may have a function that causes a big hit illegally. Then, electrical components and other boards that should originally be connected to the main board 31 are connected to the spoofing board, and the game control process is executed in place of the main board 31. That is, the connector of the cable connecting the main board 31 and the electrical component or another board is removed and connected to the spoofed board side. Therefore, in addition to the above measures, it is desirable to take the following measures in order to facilitate the discovery of the spoofed substrate.

(1) A speaker is mounted in the board box, and the speaker is used for production. If the sound output from the speaker deviates from the effect, it can be estimated that an impersonation board exists.
(2) A test switch is mounted on the main board 31, and when the test switch is pressed, a test command is transmitted to another electric component control board. If the test command is not transmitted even when the test switch is pressed, there is a possibility that the spoofing board is performing the game control process instead of the main board 31.
(3) The main board 31 is equipped with a function for detecting and notifying the connector disconnection. When the notification is made, there is a possibility that the spoofing board is performing the game control process in place of the main board 31.
(4) An informing device for informing in accordance with a prize is mounted in the board box. If the notification is not made despite the winning, the spoofing board may be performing the game control process in place of the main board 31.

(5) In the verification test of the game control microcomputer 560, if there is no input signal to the game control microcomputer 560, a verification NG signal is output. If a verification NG signal is output when a verification test is performed while generating a prize, there is a possibility that the spoofing board is performing the game control process in place of the main board 31.

(6) The length of the cable connecting the main board 31 and the electrical components or other boards is made as short as possible. If there is a margin in the cable length, the spoofing board may be performing the game control process instead of the main board 31.
(7) A cable that connects the main board 31 to the electrical component or another board is installed so as not to pass through the back surface of the main board 31. If the cable is hidden behind the main board 31, the spoofing board may be performing the game control process instead of the main board 31.
(8) Provide a structure in which the connector of the cable connecting the main board 31 and the electrical components or other boards cannot be easily removed. If traces left on the connector remain, if the cable is hidden behind the main board 31, the spoofing board may be performing the game control process instead of the main board 31.
(9) Eliminate the gap between the board box and the mounting surface. If the board box is on the back side, the spoofed board may be performing game control processing instead of the main board 31.
(10) Provide a cover that covers each board on the back of the gaming machine so that the cover cannot be easily removed. If there is a trace of the cover being removed, there is a possibility that the spoofing board is performing the game control process instead of the main board 31.

  The present invention is applicable to gaming machines such as pachinko gaming machines and slot machines, and is particularly useful for easily discovering that an unauthorized circuit board is installed.

1 Pachinko machine 31 Game control board (main board)
56 CPU
61 Status indicator LED
503a 12-bit random number circuit 503b 16-bit random number circuit 521 Counter 522 Comparator 523 Counter value permutation change circuit 528 Selector 531 Random value storage circuit 532 Inversion circuit 532A Delay circuit 533 Latch signal generation circuit 560 Game control microcomputer 910 Power supply board

Claims (1)

It performed Yu technique using a game medium, a game machine to shift to an advantageous specific game state for the player when a specific condition is satisfied,
A payout control board equipped with a payout control microcomputer for executing payout control processing for paying out game media;
Wherein it is controlled by the payout controlling microcomputer, and a state informing means for performing recognizable notifying the status,
The payout control microcomputer includes state notification control means for controlling a notification mode of the state notification means,
Said state notification control means, in response to the state with different notification manner of the state informing unit,
The payout control board is housed in a board box that is sealed so that it cannot be opened.
The state notification means is housed in the board box.

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