JP5582064B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device that operates in synchronization with a clock.

  Current semiconductor devices equipped with integrated circuits, particularly semiconductors equipped with large-scale integrated circuits, are designed based on synchronous circuits. In synchronous circuit design, a storage element such as a flip-flop (FF) is provided between combinational circuits including a gate circuit that performs arithmetic processing, and the storage element is operated in synchronization with a clock signal supplied to the entire integrated circuit. Controls the data transfer between combinational circuits. Hereinafter, a case where an FF is used as a storage element will be described as an example. Memory elements such as FF have performance indexes called setup time and hold time.

  FIG. 1 is a diagram for explaining the setup time and hold time of the FF. The setup time is a predetermined time before the changing edge (the rising edge in this case) of the clock CLK, and the data must be determined in advance by the setup time. The hold time is a predetermined time after the change edge (the rising edge in this case) of the clock CLK, and the data must hold the same value during the hold time even after the change of CLK. As shown in the center of FIG. 1, if the input data changes during the setup time, or if the input data changes within the hold time as shown on the right side of FIG. Not held or guaranteed. In other words, the operation of the FF is not guaranteed. A malfunction of the FF due to failure to satisfy the setup time and hold time is called a timing error.

  In the synchronous circuit design, it is important to improve the processing capability by operating the circuit without interruption by designing the processing between the FFs to have the same time. However, the processing time of each circuit cannot be made exactly the same due to design errors and manufacturing variations. Therefore, these time differences are designed in consideration of the timing margin at the time of design.

  2A and 2B are diagrams for explaining timing margins to be considered in circuit design. FIG. 2A illustrates setup time and FIG. 2B illustrates hold time.

  As shown in FIG. 2A, the first condition is that the sum of the delay time of the combinational circuit, the setup time of the FF, and the setup margin is within one clock cycle. The second condition is that, as shown in FIG. 2B, the sum of the FF hole, time and hold margin is within the delay time of the combinational circuit. Both conditions must be satisfied in all paths of the circuit, and the delay time of the combinational circuit is adjusted so as to satisfy these conditions at the time of design.

  In recent years, due to miniaturization, the influence of transistor variation has become larger. Further, when the circuit operation is performed at a low voltage, the influence of the variation is further increased. Transistor variation affects the delay time of the circuit. If the variation is large, a large margin is required for timing design. When the necessary margin increases, the time allowed for the circuit operation decreases. Therefore, when the necessary margin becomes too large, the time necessary for the circuit operation cannot be secured and the desired design cannot be performed.

  For example, in a deep submicron semiconductor process, even if a chip can be designed under standard conditions such as standard voltage and room temperature, delay variation may vary by about 50% despite the same circuit within the same chip due to transistor variations. . This variation becomes more conspicuous when the voltage is low. With a power supply voltage of 0.5 V, the delay time may be several times different between a fast circuit and a slow circuit. In order to solve this problem with the design margin, a large margin over half the circuit operation cycle is required, and the device can operate only at a low operation speed (long one clock cycle). Cannot be realized.

  Using two sets of FFs with different operation timings and an exclusive OR (XOR) circuit, an operation timing error of the synchronous integrated circuit is acquired, and further, the power supply voltage or the substrate potential is controlled using the acquired error. Thus, techniques for compensating for timing errors have been proposed.

  However, although it is possible to solve the timing error problem by controlling the power supply voltage, a new power supply circuit that can control the voltage, or a power switch that switches the power supply voltage, and an effective power distribution mechanism It is necessary to consider the separation of the power supply area. This leads to a significant increase in design man-hours compared to the conventional design methods. In addition, since it is difficult to change the power supply with fine granularity, it is not possible to compensate only for the path where the timing error has occurred.

Special table 2009-512200 gazette

  According to the embodiment, a semiconductor device in which operation failures due to timing errors are reduced is provided.

  According to one aspect of the present invention, a combination circuit, at least one storage element that captures and holds data output from the combination circuit according to a clock, and a clock signal line that supplies the clock are provided. Each storage element includes at least one variable delay element that delays the clock supplied to the storage element and has a variable delay time, and the storage element is normal according to the delay clock output by the variable delay element There is provided a semiconductor device that is a memory element with a timing error detection function that detects whether or not to operate normally and changes the delay time of the variable delay element according to the detection result of whether or not to operate normally.

  According to the above aspect, it is possible to reduce malfunction due to timing errors in the semiconductor device, improve the yield of the semiconductor device, and improve the operation speed of the semiconductor device.

FIG. 1 is a diagram for explaining the setup time and hold time of the FF. 2A and 2B are diagrams for explaining timing margins to be considered in circuit design. FIG. 2A illustrates setup time and FIG. 2B illustrates hold time. FIG. 3 is a diagram illustrating the internal configuration of the semiconductor device according to the first embodiment. FIG. 4 is a diagram illustrating a circuit configuration of the memory element with a timing error detection function and the delay element. FIG. 5 is a circuit diagram of an example of the first delay element. FIG. 6 is a circuit diagram of another example of the first delay element. FIG. 7 is a diagram illustrating a circuit example of a 2-bit saturation counter. FIG. 8 is a diagram showing a circuit diagram of the second variable delay element. FIG. 9 is a diagram showing the relationship between the power supply voltage, delay time, and delay time variation (σ) to delay time (μ) ratio (σ / μ) in the semiconductor element. FIG. 10 is a time chart showing the operation of the memory element portion with the timing error detection function shown in FIG. 4 of the semiconductor device of the first embodiment. FIG. 11 is a flowchart showing a calibration operation for setting the delay times of the first variable delay element and the second variable delay element after the power is turned on or the operating voltage is changed in the semiconductor device of the first embodiment. FIG. 12 is a diagram illustrating an overall configuration of a semiconductor device according to the second embodiment. FIG. 13 is a flowchart showing the calibration operation in the semiconductor device of the second embodiment. FIG. 14 is a diagram illustrating the internal configuration of the semiconductor device of the third embodiment. FIG. 15 is a circuit diagram of a memory element with a timing error detection function. FIG. 16 shows the third embodiment in which the first variable delay elements of the storage elements with timing error detection function are connected in series, and the delay clock delayed by each first variable delay element is stored with each timing error detection function. It is a figure which shows a mode that it supplies to an element. FIG. 17 is a diagram illustrating a circuit configuration of a 16-bit data path portion of the semiconductor device according to the fourth embodiment.

  Embodiments of the present invention will be specifically described below with reference to the drawings.

  FIG. 3 is a diagram illustrating the internal configuration of the semiconductor device according to the first embodiment.

  The semiconductor device of the first embodiment is equipped with a synchronous integrated circuit that operates in synchronization with the clock CLK. The synchronous integrated circuit includes combinational circuits 1A, 1B, and 1C including gate circuits that perform arithmetic processing, and flip-flops (FF) 2A, 2B, and 2C provided between the combinational circuits 1A, 1B, and 1C. Storage elements such as 2D. The FFs 2 </ b> A, 2 </ b> B, 2 </ b> C, and 2 </ b> D operate in synchronization with the clock CLK supplied via the clock signal line 3 and control data transfer between combinational circuits supplied via the data line 6.

  In order to test the operation of the semiconductor device, a scan chain is formed. The scan chain is formed by using flip-flops (FF) capable of scan input and scan output as FFs provided in the semiconductor device, and connecting these FFs by a scan line. During the scan input operation, the scan input data SCI is sequentially shifted by each FF in synchronization with the clock, and each FF is set to a state holding a predetermined value. After completing the setting, perform normal operation for a predetermined number of clocks, then switch to scan output operation, sequentially read the values held in each FF, and determine whether they match a predetermined value column Check whether the semiconductor device operates normally. Since the scan chain is widely known, further explanation is omitted.

  Also in the semiconductor device of the first embodiment, a scan chain is formed by FFs 2A, 2B, 2C, and 2D so that the FFs 2A, 2B, 2C, and 2D can be set to a state in which a predetermined value is held. Specifically, the scan lines 4 are connected in the order of FF2A, 2B, 2C, and 2D, the scan mode is set, and the scan input data SCI is shifted in the order of FF2A, 2B, 2C, and 2D in synchronization with the clock CLK. , FF2A, 2B, 2C, and 2D are set to predetermined values.

  In the semiconductor device of the first embodiment, any FF (FF2C and 2D in this case) of the FFs 2A, 2B, 2C, and 2D is a memory element with a timing error detection function having a timing error detection circuit described later. Which FF is a memory element with a timing error detection function is determined at the time of design in consideration of the delay time of the output from the preceding combinational circuit. Specifically, an FF provided in the subsequent stage of the combinational circuit having a large delay time is a storage element with a timing error detection function. In the example of FIG. 3, since the delay time of the outputs from the combinational circuits 1A and 1C is small and the delay time of the output from the combinational circuit 1B is large, the FF2C at the subsequent stage of the combinational circuit 1B is used as a memory element with a timing error detection function. . Furthermore, as will be described later, since the delay time of the output from the combinational circuit 1C is also expected to increase, the subsequent stage FF2D of the combinational circuit 1C is used as a memory element with a timing error detection function. Data DS for setting a delay time of a second delay element to be described later is supplied to the memory elements 2C and 2D with a timing error detection function via the DS signal line 5.

  In the semiconductor device of the first embodiment, the delay elements 11A and 11B are further provided on the clock signal line 3 that supplies the clock CLK to the memory elements 2C and 2D with timing error detection function. As shown in the figure, the delay elements 11A and 11B are provided on the clock signal line that supplies the clock CLK only to the memory elements 2C and 2D with timing error detection function branched from the main clock signal line 3. Although not shown, it is desirable to provide a buffer that generates a delay time equal to the minimum delay time of the delay elements 11A and 11B on the clock signal line that supplies the clock CLK to the normal FFs 2A and 2B. A combination of the memory element 2C or 2D with timing error detection function and the delay element 11A or 11B may be described as a memory element with timing error detection function.

  FIG. 4 is a diagram showing a circuit configuration of the memory element with the timing error detection function, and the first delay element 12 and the second delay element 13 correspond to the delay element 11A or 11B.

  As described above, the delay element 11 </ b> A or 11 </ b> B is realized by a set of the first delay element 12 and the second delay element 13. The first delay element 12 delays the clock CLK supplied via the clock signal line 3 and outputs a first delay clock. The delay time of the first delay element 12 is variable, increases when the error signal ERROR supplied from the AND gate 25 is “high (H)”, and returns to the initial value by the reset signal RESET. The clock CLK supplied via the clock signal line 3 is supplied as the clock CLK-NEXT to the next stage FF or the memory element with timing error detection function. The second delay element 13 further delays the first delay clock output from the first delay element 12 and outputs the second delay clock. The delay time of the second delay element 13 is variable and is set by the data DS supplied via the DS signal line 5.

  The memory with timing error detection function further includes a first memory element (FF) 22, a second memory element (FF) 23, an EXOR gate 24, and an AND gate 25. The first FF 22 takes in (latches) and holds the data DATA output from the preceding combination circuit supplied via the data signal line 6 in accordance with the first delay clock. The second FF 23 latches and holds the data DATA output from the preceding combination circuit supplied via the data signal line 6 according to the second delay clock. The output of the second FF 23 becomes the input of the subsequent combinational circuit. Therefore, the first FF 22 and the second FF 23 perform a latch operation at a timing that differs by the delay time of the second delay element 13. The EXOR gate 24 determines whether the outputs of the first FF 22 and the second FF 23 match, and outputs “low (L)” if they match, and “high (H)” if they do not match. The AND gate 25 calculates the logical sum of the output of the EXOR gate 24 and the signal obtained by inverting the clock CLK, and generates an error signal ERROR. Therefore, the error signal ERROR is generated according to CLK when the output of the EXOR gate 24 is H, that is, when the outputs of the first FF 22 and the second FF 23 do not coincide with each other, and remains L at other times.

  FIG. 5 is a circuit diagram of an example of the first delay element 12.

  As shown in FIG. 5, the first delay element 12 includes a 2-bit saturation counter 30, a buffer 31, a selector 32, a buffer 33 and a buffer 34 connected in series, and a selector 35. The count value of the 2-bit saturation counter 30 is cleared when the reset signal RESET is inactive, and while the RESET is inactive, the count value increases by counting the change in the error signal ERROR. Since the 2-bit saturation counter 30 is used here, 2-bit values BIT0 and BIT1 are output, and the count value is 0, 1, 2, or 3. The selector 32 selects the directly input CLK when BIT0 is “0”, and the output of the buffer 31 when “1”. The selector 35 selects the output of the selector 32 when BIT1 is “0”, and selects the output of the buffer 34 when “1”. The count value is 3 and is saturated.

  Therefore, when the count value of the 2-bit saturation counter 30 is “0”, the clock CLK is supplied to the FF 22 via the selectors 32 and 35. The delay time at this time is the sum of the delay times of the selector 32 and the selector 35 and is the minimum delay time of the first delay element 12. When the count value is “1”, the clock CLK is supplied to the FF 22 via the buffer 31 and the selectors 32 and 35, and the delay time is the sum of the minimum delay time and the delay time of the buffer 31. When the count value is “2”, the clock CLK is supplied to the FF 22 via the selector 32, the buffers 33 and 34, and the selector 35, and the delay time is the sum of the minimum delay time and the delay times of the buffer 33 and the buffer 34. It is. When the count value is “3”, the clock CLK is supplied to the FF 22 via the buffer 31, the selector 32, the buffers 33 and 34, and the selector 35, and the delay time is the minimum delay time, the buffer 31, the buffer 33, and the buffer. This is the sum of 34 delay times. As described above, the delay time of the clock supplied to the FF 22 can be changed.

  FIG. 6 is a circuit diagram of another example of the first delay element 12. The first delay element 12 is a variable delay element in which a 2-bit saturation counter 30, inverters 41 and 42, three gated inverters 44, and a buffer 43 are combined. The 2-bit saturation counter 30 performs the same operation as the circuit of FIG. The total output current of the three gated inverters 44 is designed to be smaller than the output current of the inverter 41. Depending on the count value of the 2-bit saturation counter 30, the number of operations of the gated inverter 44 that outputs a current that cancels the output of the inverter 41 is switched between 0 and 3. The output of the gated inverter 44 and the value of the inverter 41 cancel each other out at the node A. Since the output current of the inverter 41 is larger than the total output current of the gated inverter 44, the value of the node A finally becomes a value determined by the inverter 41, but the slope of the signal waveform of the node A becomes gentle. As the number of gated inverters 44 that operate increases, the slope of the signal waveform becomes gentle. Since the logical threshold value of the inverter 42 is constant, the delay time from the input of the inverter 41 to the output of the inverter 42 becomes longer as the slope of the signal waveform at the node A becomes gentler. By switching the number of operations of the gated inverter 44 by the count value of the 2-bit saturation counter 30, the delay time can be controlled in four stages.

  FIG. 7 is a diagram illustrating a circuit example of the 2-bit saturation counter 30 illustrated in FIGS. 5 and 6. Since such a circuit configuration is widely known, the description is omitted, but the count value is reset to 0 in response to the reset signal RESET, and the count value increases in response to CLK when the error signal ERROR is H. .

  FIG. 8 is a diagram showing a circuit diagram of the second variable delay element 13. This circuit has a circuit configuration similar to that of the first variable delay element 12 shown in FIG. 5, except that a 2-bit saturation counter is not provided and a buffer 36 is provided in the preceding stage. The buffer 36 is provided to set the minimum value of the delay time of the second variable delay element 13 to a predetermined value or more. The selection in the selectors 32 and 35 is determined according to the values of VDDCODE0 and VDDCODE1 which are bits of the data DS.

  The delay time of the second variable delay element 13 is set to a time that allows for the stability margin of the integrated circuit of the semiconductor device. If the delay time is long, the safety margin becomes large and it becomes difficult to generate an error. However, since the operating frequency is lowered accordingly, the value is set according to the purpose of the circuit. By changing the power supply voltage for operating the semiconductor element, the delay time of the second variable delay element 13 can be changed, and the trade-off between the safety margin and the operating frequency can be avoided. For example, when it is necessary to increase the operating frequency, the power margin is increased to reduce the allowable safety margin. This will be described in more detail.

  FIG. 9 is a diagram showing the relationship between the power supply voltage, delay time, and delay time variation (σ) to delay time (μ) ratio (σ / μ) in the semiconductor element. In a semiconductor device, the delay time increases exponentially when the operating power supply voltage is lowered. At the same time, random variation in delay time increases more rapidly than the delay time, and σ / μ (delay variation / delay time) increases as the power supply voltage decreases. That is, the lower the power supply voltage, the longer the circuit stability margin, that is, the delay time of the second variable delay element 13 needs to be increased.

  In the circuit of the second variable delay element 13 shown in FIG. 8, the delay amount is set according to the values of VDDCODE0 and VDDCODE1 which are bits of the data DS. Therefore, the values of VDDCODE0 and VDDCODE1 are set as shown in Table 1 corresponding to the operating power supply voltage of the semiconductor device of the first embodiment. Specifically, when the power supply voltage is in a relatively high range of 0.80 to 1.20 V, VDDCODE0 = 0 and VDDCODE1 = 0. As a result, the delay time of the second variable delay element 13 is minimized. Similarly, when the power supply voltage is in the range of 0.65 to 0.80 V, the delay time is slightly increased by setting VDDCODE0 = 1 and VDDCODE1 = 0. When the power supply voltage is in the range of 0.50-0.65V, VDDCODE0 = 1 and VDDCODE1 = 0 are set to further increase the delay time. When the power supply voltage is in the range of 0.35-0.50V, VDDCODE0 = 1 And VDDCODE1 = 1 to maximize the delay time.

  If the circuit operating conditions are determined in advance, the delay time of the second variable delay element 13 may be fixed at the time of circuit design, and a simple delay element may be used.

  Note that any variable delay element can be used as long as the delay time can be set as described above, and it is not necessary to use the illustrated circuit, but a small circuit scale is desirable.

  FIG. 10 is a time chart illustrating the operation of the memory element with timing error detection function shown in FIG. 4 of the semiconductor device of the first embodiment. CLK is a clock supplied from the clock signal line 3, DATA is data supplied from the preceding combinational circuit, CLKA is the first delay clock, QA is the output of the first FF 22, CLKB and the second delay clock, QB indicates the output of the second FF 23, respectively.

  If DATA output from the preceding combinational circuit arrives at the first FF 22 and the second FF 23 sufficiently earlier than CLK, data can be retained without any problem. However, the delay time of the output of the preceding combination circuit may become longer due to the influence of circuit variations and the like. In this case, since the data fetch timing is delayed by the delay time of the second variable delay element 13 in the second FF 23, the expected value is held in the first FF 22 and the expected value is held in the second FF 23. Become. The comparator 24 detects the difference between the values held in the first FF 22 and the second FF 23 storage element, and the AND gate 25 generates an ERROR signal. When this ERROR signal is generated, the delay time of the first variable delay element 12 is immediately increased, and the first delay clock is delayed. As a result, the data fetch timing of both the first FF 22 and the second FF 23 is delayed, and both are not affected by the increase in the delay time of the logic circuit in the previous stage, and can hold a correct value.

  FIG. 11 is a flowchart showing a calibration operation for setting the delay times of the first variable delay element 12 and the second variable delay element 13 after the power is turned on or the operating voltage is changed in the semiconductor device of the first embodiment. The calibration operation is simultaneously performed for all the memory elements with a timing error detection function and the delay elements included in the semiconductor device of the first embodiment.

  In step S1, the power is turned on and the operating voltage is changed.

  In step S2, the delay time of the second variable delay element 13 is set as shown in Table 1 according to the power supply voltage.

  In step S3, a scan mode is set, a data pattern that increases the activation rate of a path that can be a critical path in the combinational logic circuit is input using a scan chain, and each stage of FFs and storage elements with timing error detection function Is set to the state corresponding to the data.

  In step S4, after changing to the normal operation mode, the clock CLK is supplied to all circuit portions, and at least the number of clocks obtained by multiplying the number of stages of the storage elements with FF and timing error detection function by the number of adjustment stages of the first variable delay element. Operate more than a few. In response to this, each storage element with a timing error detection function performs a timing error check and correction. Even when the number of clocks is operated more than the above-mentioned number, if the delay time of the first variable delay element falls within the normal operating range, the ERROR signal is not generated thereafter, so that no particular problem occurs.

  As shown in FIG. 3, for example, the value error time of the variable delay element 11 </ b> A (the combination of the first variable delay element 12 and the second variable delay element 13) is changed by the memory element 2 </ b> C with the timing error detection function to thereby generate a timing error. Consider the case of correction. In this case, since the operation timing of the second FF 23 in the memory element 2C with the timing error detection function is delayed, a delay is also generated in the signal input to the next combinational circuit 1C. As a result, a timing error may occur in the next-stage combinational circuit 1C where the timing error did not occur before correction.

  Therefore, in the semiconductor device according to the first embodiment, as shown in FIG. 3, the FF in the subsequent stage of the combinational circuit 1C with a small output delay time is also a memory element with a timing error detection function including the variable delay element 11B. 2D so that the latch timing can be adjusted. If the number of clocks for correcting the above latch timing is operated, the timing errors of the storage elements with the timing error detection function arranged in series are corrected over the circuits of all stages.

  Of course, if the delay of the output of the combinational circuit 1C is sufficiently small, and even if the latch timing of the memory element 2D with the timing error detection function is corrected, the latch in the FF in the subsequent stage of the combinational circuit 1C can be normally performed. There is no need to provide the memory element 2D with the timing error detection function.

  FIG. 12 is a diagram illustrating an overall configuration of the semiconductor device 50 according to the second embodiment.

  The semiconductor device 50 according to the second embodiment includes a data input terminal 51, a data output terminal 52, and an error signal output terminal 53. In addition, although there are a clock input terminal, a power supply terminal, etc., illustration is omitted. Further, the semiconductor device 50 according to the second embodiment includes a synchronous integrated circuit as in the first embodiment, and includes combinational circuits 62X, 62Y, 62Z, and storage elements 63P-63W such as FFs. Output memory elements 64L-64N, output buffers 65L-65N, and a three-input OR gate 66 are provided. A range 61 including the combinational circuits 62X, 62Y, 62Z and the like and the storage elements 63P-63W is a timing error correction range. The storage elements 63P-63T are the storage elements with timing error detection function shown in FIG. 4 as necessary. The memory elements 63U to 63W are all memory elements with a timing error detection function, and can generate the error signal ERROR generated by each, and the output error signal ERROR is input to the three-input OR gate 66. The memory elements 63U-63W are realized by providing an output terminal for the error signal ERROR in the circuit shown in FIG.

  The storage elements 63P-63R are supplied with data from the data input terminal 51, and the output is supplied to the combinational circuits 62X and 62Y. The storage elements 63S and 63T are supplied with data from the combinational circuits 62X and 62Y, and the output is supplied to the combinational circuit 62Z. The storage elements 63U-63W are supplied with data from the combinational circuit 62Z, and the output is supplied to the output storage elements 64L-64N.

  In the second embodiment, the timing error is adjusted for the memory element with a timing error detection function within the timing error correction range, as in the first embodiment. Then, the 3-input OR gate 66 outputs a signal indicating that the error signal ERROR is generated in any of the storage elements 63U to 63W for each clock CLK from the error signal output terminal 53 during the timing error adjustment.

  When the timing error adjustment is performed, depending on the internal timing error situation, the correction result may be accumulated in the final stage, and the final stage timing may not be corrected. Further, when the operation timing of the output storage elements 64L-64N changes greatly, it becomes difficult to connect the semiconductor device of the second embodiment and the peripheral circuit. In order to avoid these problems, in the semiconductor device of the second embodiment, the error signal ERROR output from the error signal output terminal 53 is monitored to determine whether all of the memory elements 63U-63W are in a state where no error signal is generated. Check. If all of the memory elements 63U-63W are not in a state that does not generate an error signal, the voltage of a power supply circuit (not shown) that supplies power to the semiconductor device 50 is controlled. As described above, if the voltage of the power supply circuit is increased, variations in the operation speed of the transistor are reduced, and therefore correction can be performed by the memory element with a timing error detection function and the variable delay element.

  FIG. 13 is a flowchart showing the calibration operation in the semiconductor device of the second embodiment. S11 to S13 are the same operations as the calibration operation of the first embodiment shown in FIG. In the calibration operation of the second embodiment, in step S15 after S14, it is confirmed whether all the storage elements 63U-63W in the final stage are in a state where no error signal is generated. If the error signal is not generated, the calibration is terminated. If the error signal is generated, the process proceeds to step S16. In S16, the operating power supply voltage is changed, that is, the operating power supply voltage is increased by one step, and the process proceeds to Step S12, and S12 to S16 are repeated until all of the storage elements 63U-63W do not generate an error signal.

  In the semiconductor devices of the first and second embodiments, the part that detects the timing error and the part that eliminates the error can be configured as one circuit, and this circuit can be replaced with an existing storage element such as an FF. It is.

  When taking measures against random variations of the semiconductor devices of the first and second embodiments, a signal that easily causes a setup error to occur by stopping the operation of the semiconductor device when the semiconductor device is powered on or at a certain operation time. A pattern is set using a scan chain and the obtained error information is used. As a result, it can be used not only for random variations during manufacturing but also for compensation for variations due to aging.

  Furthermore, if you do not consider aging deterioration, set a pattern that easily induces setup errors in the inspection at the time of shipment to each FF or memory element with timing error detection function using a scan chain, and according to the obtained error information It is also possible to write inside so as to set the delay time of the first variable delay element 12.

  Also, the configuration of the first and second embodiments can be applied even when it is determined that a hold error is likely to occur in a certain path based on the result of operation analysis or the like at the time of design. In this case, the first variable delay element 12 is designed with a long delay time set in advance, and the ERROR signal is used as the delay time reduction signal. When a hold error occurs, the operation timing of the first memory element 12 and the second memory element 13 is advanced, and the hold error is eliminated.

  As described above, in the semiconductor devices of the first and second embodiments, the setup error that causes the data to be stored later than the required timing or the hold error that causes the data to be rewritten earlier than the required timing. In the case where a timing error occurs at a place where the error can occur, the delay time of the clock supplied to the memory element is lengthened or shortened. Thereby, the operation timing of the storage element is delayed or advanced, and it becomes possible to eliminate the setup error or the hold error.

  FIG. 14 is a diagram illustrating the internal configuration of the semiconductor device of the third embodiment.

  Similar to the first embodiment, the semiconductor device according to the third embodiment includes a synchronous integrated circuit, and includes combinational circuits 71A and 71B and storage elements 72A to 72C with timing error detection function.

  FIG. 15 is a circuit diagram of a memory element with a timing error detection function, and each of the memory elements 72A to 72C with a timing error detection function has the circuit configuration of FIG. As shown in FIG. 15, the memory element with timing error detection function has a configuration similar to the circuit shown in FIG. 4, and the first variable delay element 70 is connected to the memory element with timing error detection function in the next stage. Unlike the circuit shown in FIG. 4, the rest is the same as the clock signal line provided. Data DATA is input to the memory element 72A with the timing error detection function from the previous stage or the input terminal, and the output of the second FF 23 of the memory element 72A with the timing error detection function is output to the combinational circuit 71A. Data output from the combinational circuit 71A is input to the memory element 72B with timing error detection function, and the output of the second FF 23 of the storage element 72B with timing error detection function is output to the combinational circuit 71B. Data output from the combinational circuit 71B is input to the memory element 72C with the timing error detection function, and the output of the second FF 23 of the storage element 72C with the timing error detection function is output to the combinational circuit at the next stage.

  Further, the first variable delay element 70 of the memory element 72A with timing error detection function delays the clock CLK input from the clock signal line or the memory element with timing error detection function in the previous stage and generates a first delay clock. The first delay clock is supplied to the first FF 22 of the memory element 72A with a timing error detection function and also supplied to the memory element 72B with a timing error detection function in the next stage. Hereinafter, similarly, the first variable delay elements of the memory elements with timing error detection function are connected in series, and the respective outputs are supplied to the corresponding first FFs 22.

  FIG. 16 shows the third embodiment in which the first variable delay elements of the storage elements with timing error detection function are connected in series, and the delay clock delayed by each first variable delay element is stored with each timing error detection function. The state of supplying to the element is shown.

  As shown in FIG. 16A, since the first variable delay elements of the memory elements with timing error detection function are connected in series, the delay of the first variable delay element of the memory element with timing error detection function Consider a case where the time (here, the first variable delay element of the memory element with the second stage timing error detection function) is adjusted. In such a case, in the first and second embodiments, when the delay time of the first variable delay element of the second-stage storage element with timing error detection function is corrected, the data output from the second FF 23 is also delayed accordingly. Therefore, a timing error may occur in the next stage where no timing error occurred before correction. In contrast, in the third embodiment, as shown in FIG. 16B, the adjusted delay time is propagated to the first variable delay element at the subsequent stage. Therefore, since the latch timing by the first and second FFs in the subsequent stage is also delayed, a timing error does not occur in the memory element with a timing error detection function in the subsequent stage where no timing error has occurred.

  The third embodiment has an advantage that the timing error correction converges faster than the first and second embodiments, but the delay time of the first variable delay elements connected in series is accumulated. There is a disadvantage that connection is limited. When the circuit operation order is determined in advance at the time of design, it is desirable to use the configuration of the third embodiment, and otherwise use the configuration of the first embodiment. Note that the configuration of the first embodiment and the configuration of the third embodiment can be mixed on the same semiconductor device.

  FIG. 17 is a diagram illustrating a circuit configuration of a 16-bit data path portion of the semiconductor device according to the fourth embodiment. This circuit portion has a first variable delay element 12, a second variable delay element 13, 16 sets of first FF 23, second FF 23 and EXOR gate 24, 16-input OR gate 26, and AND gate 25. . In this circuit portion, it can be said that the circuit of FIG. 4 is provided for every 16 data, the first variable delay element 12, the second variable delay element 13, and the AND gate 25 are integrated, and further, an OR gate 26 of 16 inputs is provided.

  This circuit portion of the fourth embodiment is provided at the exit of a data path such as an adder circuit, and the latch timing of a plurality of bits is commonly changed by one variable delay clock. The first FF 23, the second FF 23, and the EXOR gate 24 of each set detect the timing error of each bit, and the OR gate 26 calculates a logical sum of 16 inputs, so that an error occurs at any bit in the data path. Detect what happened. When there is an error, the delay time of the first variable delay element 12 is increased to compensate for the timing error by shifting all the operation timings of the FFs at the data path exit. By integrating the first variable delay element 12, the second variable delay element 13, and the AND gate 25 as in the fourth embodiment, it is possible to reduce the number of these elements and improve the circuit area efficiency. .

  As described above, according to the first to fourth embodiments, it is possible to reduce malfunctions due to timing errors in semiconductor circuit design, thereby improving yield and operating speed.

  Since the transistor characteristic variation is expected to increase in the future due to miniaturization of the semiconductor circuit, the configurations of the first to fourth embodiments are effective for relaxing the design criteria at that time. Even when aiming at low voltage operation, the delay variation of the circuit tends to increase, so the configurations of the first to fourth embodiments are effective.

According to the configuration of the first to fourth embodiments, a timing error due to variations in transistor characteristics can be corrected based on actual performance after manufacture, not on a margin at the time of design. This eliminates the need for extra design margins and eliminates the need for margin estimation.
Compared to the technologies proposed so far, it is possible to mount memory elements such as FFs simply by replacing them with the memory elements described in FIG. Design is possible.

  Although the embodiment has been described above, all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and the technology. It is not intended to limit the scope of the invention, and the construction of such examples in the specification does not indicate the advantages and disadvantages of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

Hereinafter, the following additional notes will be disclosed with respect to the embodiment.
(Appendix 1)
A combinational circuit;
One or more storage elements that capture and hold data output from the combinational circuit in response to a clock;
A clock signal line for supplying the clock,
At least one of the storage elements is
Delaying the clock supplied to the memory element, comprising at least one variable delay element having a variable delay time;
According to the delay clock output from the variable delay element, it is detected whether the storage element operates normally, and the delay time of the variable delay element is changed according to the detection result of whether the storage element operates normally. A semiconductor device characterized by being a memory element with a timing error detection function.
(Appendix 2)
The variable delay element is
A first variable delay element that delays the clock and outputs a first delay clock, the delay time of which is variable;
A second delay element that further delays the first delay clock and outputs a second delay clock; and a variable delay time;
A counter that changes a set value of the delay time of the first variable delay element,
The memory element with the timing error detection function is:
A first storage element that captures and holds the data supplied to the storage element in response to the first delay clock;
A second memory element that captures and holds the data supplied to the memory element in response to the second delay clock;
A comparator that compares the data held in the first memory element with the data held in the second memory element;
The semiconductor device according to appendix 1, wherein the counter of the variable delay element changes a count value based on a comparison result of the comparator.
(Appendix 3)
The semiconductor device according to appendix 2, wherein the delay time of the second delay element can be set from the outside.
(Appendix 4)
The semiconductor device according to appendix 3, wherein a delay time of the second delay element is set according to an operating voltage of the semiconductor device.
(Appendix 5)
The first delay element is provided on the clock signal line that branches from the clock signal line that supplies the clock to the first memory element in the subsequent stage and that supplies the clock only to the corresponding first memory element. 5. The semiconductor device according to any one of 2 to 4.
(Appendix 6)
The semiconductor device according to any one of appendices 2 to 4, wherein the first delay element is provided in the clock signal line that supplies the clock to the first memory element in a subsequent stage.
(Appendix 7)
The second memory elements form a scan chain, and a value held by each second memory element is set by the scan chain,
The memory element with a timing error detection function is configured such that the first memory element and the second memory element are in a state where the semiconductor device is operated after the second memory element is set to a predetermined state by the scan chain. 7. The semiconductor device according to any one of appendices 2 to 6, which detects whether or not the same data is captured.

1A-1C combinational circuit 2A, 2B storage element 2C, 2D storage element with timing error detection function 11A, 11B variable delay element 12 first variable delay element 13 second variable delay element 22 first storage element (FF)
23 Second memory element (FF)
24 EXOR gate 25 AND gate

Claims (4)

A combinational circuit;
One or more storage elements that capture and hold data output from the combinational circuit in response to a clock;
A clock signal line for supplying the clock,
At least one of the storage elements is
Delaying the clock supplied to the memory element, and comprising at least one variable delay element having a variable delay time,
According to the delay clock output from the variable delay element, it is detected whether the storage element operates normally, and the delay time of the variable delay element is changed according to the detection result of whether the storage element operates normally. Ri Oh timing error detection function storage element which,
The variable delay element is
A first delay element that delays the clock and outputs a first delay clock, the delay time being variable;
A second delay element that further delays the first delay clock and outputs a second delay clock; and a variable delay time;
A counter that changes a set value of the delay time of the first variable delay element,
The memory element with the timing error detection function is:
A first storage element that captures and holds the data supplied to the storage element in response to the first delay clock;
A second memory element that captures and holds the data supplied to the memory element in response to the second delay clock;
A comparator that compares the data held in the first memory element with the data held in the second memory element;
The semiconductor device according to claim 1, wherein the counter of the variable delay element changes a count value based on a comparison result of the comparator . The first delay element is provided in the clock signal line that branches from the clock signal line that supplies the clock to the first memory element in the subsequent stage and that supplies the clock only to the corresponding first memory element. Item 14. A semiconductor device according to Item 1 . 3. The semiconductor device according to claim 1, wherein the first delay element is provided in the clock signal line that supplies the clock to the first memory element in a subsequent stage. The second memory elements form a scan chain, and a value held by each second memory element is set by the scan chain,
The memory element with a timing error detection function is configured such that the first memory element and the second memory element are in a state where the semiconductor device is operated after the second memory element is set to a predetermined state by the scan chain. the semiconductor device of any one of claims 1 to detect whether capture the same data 3.

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