JP5659514B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having a trench gate structure. In particular, the present invention relates to a semiconductor device having a trench capacitance for increasing the gate-emitter capacitance.

  In order to effectively use power energy, power converters such as inverters are widely used. As power semiconductor devices used in these power conversion devices, voltage-driven insulated gate semiconductor devices having excellent controllability have become mainstream. In particular, due to the progress of low loss and high breakdown tolerance technology of IGBT (insulated gate bipolar transistor), its application has been extended to the field of high withstand voltage and large current.

  An insulated gate semiconductor device using an IGBT or the like has a wide safe operation region and thus does not require a protection circuit such as a snubber circuit. In recent years, the switching loss has been further reduced by reducing the impedance (gate resistance) of the gate drive circuit and switching at higher speed.

  However, these measures are accompanied by a large voltage change rate (dV / dt) and a current change rate (dI / dt). Furthermore, the large dI / dt is caused by a synergistic effect with the floating inductance of the circuit, thereby increasing the surge voltage and the larger dV. / Dt is generated.

  As a result, the gate voltage of the semiconductor device may fluctuate and cause malfunction. The fluctuation of the gate voltage depends on the gate-collector capacitance and the gate-emitter capacitance. That is, the larger the gate-collector capacitance or the smaller the gate-emitter capacitance, the greater the variation in gate voltage. Patent Documents 1 and 2 disclose measures for suppressing the fluctuation of the gate voltage.

FIG. 9 is a cross-sectional view of a main part of the conventional semiconductor device disclosed in Patent Document 1. In FIG. Capacitance portion 64 is formed between trench gate portions 63, and this capacitance portion 64 is added to trench gate portion 63 to increase gate capacitance _CG0 , whereby voltage change rate (dV / dt), current change rate (dI / dt) is reduced to suppress the gate voltage fluctuation.

  In the drawing, 51 is an n-type drift layer, 52 is a p-type collector layer, 53 is a collector electrode, 54 is a p-type base layer, 55 is an n-type emitter layer, 56 is a gate insulating film, and 57 is a gate. An electrode, 58 is an emitter electrode, and 59 is an interlayer insulating film.

FIG. 10 is a cross-sectional view of a main part of the conventional semiconductor device shown in Patent Document 2. A floating region 96 is formed between the trench gate portions 95, and an electrode 93 connected to the emitter electrode 81 via the insulating film 91 is provided thereon, thereby reducing the gate-collector capacitance _CGCO and reducing the gate voltage. Fluctuation is suppressed.

  In the figure, reference numeral 71 denotes a collector electrode, 72 denotes a p-type collector layer, 73 denotes an n-type buffer layer, 74 denotes an n-type drift layer, 75 denotes a p-type base layer, 76 denotes an emitter potential region, and 77 denotes a floating state. p region, 78 is a trench, 81 is an emitter electrode, 82 is a gate electrode, 83 is a gate insulating film, 84 is a gate metal electrode, and 92 is an emitter potential region.

JP 2004-14547 A JP 2005-32941 A

However, in the semiconductor device shown in Patent Document 1 (FIG. 9), the trench 65 of the capacitor portion 64 is formed in the same manner as the trench 66 of the trench gate portion 63, and therefore the capacitance without affecting the trench gate portion 63. The trench capacitance C _T0 of the portion 64 cannot be changed as necessary.

In addition, in the semiconductor device shown in Patent Document 2 (FIG. 10), although it is described that the gate-collector capacitance _CGCO is reduced, the gate-emitter capacitance _CGEO is increased to suppress the fluctuation of the gate voltage. There is no mention of what to do.

  An object of the present invention is to solve the above-mentioned problems and increase the gate-emitter capacitance without affecting the trench gate structure (gate capacitance portion) formed in the active region, thereby generating a gate generated during switching. An object of the present invention is to provide a semiconductor device capable of suppressing voltage fluctuation (high frequency noise or the like).

In order to achieve the above object, according to the invention described in the claims,
A first conductivity type semiconductor substrate;
A first semiconductor layer of a second conductivity type disposed on a surface layer of the semiconductor substrate;
A first trench disposed from the surface of the first semiconductor layer through the first semiconductor layer and reaching the semiconductor substrate;
A gate insulating film disposed on the inner wall of the first trench;
A second semiconductor layer of a first conductivity type disposed on a surface layer of the first semiconductor layer in contact with a side wall of the first trench;
A gate electrode filled in the first trench through the gate insulating film;
An interlayer insulating film covering the gate electrode;
A main electrode in contact with the second semiconductor layer and the first semiconductor layer through an opening disposed in the interlayer insulating film;
A third semiconductor layer of a second conductivity type disposed on the surface layer of the semiconductor substrate apart from the first semiconductor layer;
A second trench disposed in the third semiconductor layer;
An insulating film disposed on the inner wall of the second trench;
A conductor filled in the second trench through the insulating film,
A semiconductor device in which the conductor is connected to the gate electrode and the third semiconductor layer is connected to the main electrode;
The second trench is disposed at least under a gate electrode pad connected to the gate electrode and disposed on the semiconductor substrate,
The semiconductor device has a surface density of the second trench larger than that of the first trench.

According to the invention described in the claims,
A first conductivity type semiconductor substrate;
A first semiconductor layer of a second conductivity type disposed on a surface layer of the semiconductor substrate;
A first trench disposed from the surface of the first semiconductor layer through the first semiconductor layer and reaching the semiconductor substrate;
A gate insulating film disposed on the inner wall of the first trench;
A second semiconductor layer of a first conductivity type disposed on a surface layer of the first semiconductor layer in contact with a side wall of the first trench;
A gate electrode filled in the first trench through the gate insulating film;
An interlayer insulating film covering the gate electrode;
A main electrode in contact with the second semiconductor layer and the first semiconductor layer through an opening disposed in the interlayer insulating film;
A third semiconductor layer of the second conductivity type which is disposed in contact with said first semiconductor layer on the surface layer of the semiconductor substrate,
A second trench disposed in the third semiconductor layer;
An insulating film disposed on the inner wall of the second trench;
A conductor filled in the second trench through the insulating film,
A semiconductor device in which the conductor is connected to the gate electrode,
The second trench is disposed at least under a gate electrode pad connected to the gate electrode and disposed on the semiconductor substrate,
The surface density of the second trench is greater than the surface density of the first trench;
A semiconductor device in which the depth of the third semiconductor layer is deeper than the depth of the first semiconductor layer.

The front SL may third semiconductor layer connected to said main electrode.
Further, when the surface density of the previous SL trench is the sum of S1 of the surface area of the opening upper part of the trench, and the sum of the surface area of said semiconductor layer sandwiched between the trenches and S2, S1 / (S1 + S2 ) × 100 It may be expressed in (%). Further, it is pre-SL and the first semiconductor layer, a gate capacitance section composed of the gate insulating film and the gate electrode, and said third semiconductor layer, when having a trench capacitor unit consisting of the insulating film and the conductor.

Further, it is preferable prior Symbol gate electrode and the conductor is a polysilicon.
The front SL may planar shape of the second trench is in a stripe-like or lattice-like.

In the present invention, by adding the trench capacitance to the gate-emitter capacitance, fluctuations in gate voltage (high frequency noise, etc.) during switching can be suppressed.
By forming the trench capacitance under the gate electrode pad or the current detection electrode pad including the gate electrode pad, the trench capacitance can be formed without reducing the active region.

  Further, by making the surface density of the trench serving as the trench capacity larger than the surface density of the trench serving as the gate capacity of the active region, the gate-emitter capacity can be made large enough to suppress the variation of the gate voltage.

1 is a schematic plan view of a chip of a semiconductor device according to a first embodiment of the present invention. It is the A section enlarged view of FIG. It is the detailed sectional view cut | disconnected by the XX line of FIG. It is a figure explaining areal density. It is a figure explaining the length of the depth direction which acts as a gate capacity | capacitance and a trench capacity | capacitance, (a) is a figure in the case of gate capacity, (b) is a figure in the case of trench capacity. It is a schematic plan view of the chip | tip of the semiconductor device of 2nd Example of this invention. It is the detailed sectional view cut | disconnected by the X1-X1 line | wire of FIG. It is a principal part top view of the semiconductor device of 3rd Example of this invention. It is principal part sectional drawing of the conventional semiconductor device shown in patent document 1. 10 is a cross-sectional view of a main part of a conventional semiconductor device shown in Patent Document 2. FIG.

  Embodiments will be described in the following examples.

  1 to 3 are block diagrams of a semiconductor device according to a first embodiment of the present invention. FIG. 1 is a schematic plan view of a chip, FIG. 2 is an enlarged view of a portion A in FIG. 1, and FIG. It is detail sectional drawing cut | disconnected by -X-ray. An IGBT is given as an example of the semiconductor device 100.

  The semiconductor device 100 includes an n semiconductor substrate 1, a first p well region 2 disposed in a surface layer of the n semiconductor substrate 1, and a diffusion depth deeper than the first p well region 2 and in contact with the first p well region 2. The second p well region 7 is formed.

  A plurality of striped first trenches 3 penetrating from the surface of the first p well region 2 through the first p well region 2, a gate insulating film 4 disposed on the inner wall of the first trench 3, and the first An n emitter region 5 disposed on the surface layer of the first p well region 2 in contact with the sidewall of one trench 3 is connected to the gate electrode 6 via a gate runner 16 and disposed on the n semiconductor substrate 1. Gate electrode pad 15, interlayer insulating film 12 disposed on gate electrode 6, n emitter region 5 and first p well are disposed on interlayer insulating film 12 through contact hole 13 of interlayer insulating film 12. The emitter electrode 14 is connected to the region 2. The first p well region 2 in which the first trench 3 is disposed becomes an active region SA. The first p-well region 2 includes a region 2a that becomes an emitter potential and a region 2b that becomes a floating potential.

  In addition, a plurality of stripe-shaped second trenches 8 disposed in the second p well region 7 below the gate electrode pad 15 via an interlayer insulating film 12 and insulation disposed on the inner wall of the second trench 8. A film 9, a conductor 10 filled in the second trench 8 via the insulating film 9, and a wiring connected to the conductor 10 and connected to the gate electrode pad 15 and disposed under the interlayer insulating film 12 It consists of a conductor 11. The second p well region 7 is connected to the emitter electrode 14 through a contact hole 13 formed in the interlayer insulating film 12. The wiring conductor 11 and the upper gate electrode pad 15 are connected by a connection conductor 17 through a contact hole (not shown) of the interlayer insulating film 12.

The n-type semiconductor substrate 1 includes an n-buffer region 18 and a p-collector layer 19 disposed on the surface layer on the back side, and a collector electrode 20 disposed on the p-collector layer 19.
When the first p well region 2 near the boundary where the first p well region 2 and the second p well region 7 are connected is connected to the emitter electrode 14 via the contact hole 13 formed in the interlayer insulating film 12 ( In the case of an IGBT having no floating region), it is not always necessary to connect the second p well region 7 to the emitter electrode 14 through the contact hole 13 formed in the interlayer insulating film 12.

The gate capacitance C _G in the active region SA in the 1p well region 2 and the gate insulating film 4 and the gate electrode 6 is formed, the trench capacitor below the gate electrode pad 15 with the insulating film 9 and the conductor 10 and the 2p well region 7 C _T is formed. The gate capacitor _CG is formed in the gate capacitor 31.

By forming the trench capacitor portion 32 formed trench capacitor C _T is below the electrode pad for detecting the current which is not shown or a gate electrode pad 15, without reducing the active area SA, can form a trench capacitor portion 32.

The length of the second trench 8 can be any of a trench capacitor C _T by changing the width, depth and spacing. However, because the size of the gate electrode pad 15 is smaller than the active region SA, in order to obtain a large trench capacitance C _T is or increasing the number and or narrow width or reduce the width of each second trench 8 Since the depth of the second trench 8 needs to be increased, the surface density of the second trench 8 formed under the gate electrode pad 15 is preferably made larger than the surface density of the first trench 3.

By volume using a chip 1a entire area by adding a trench capacitor C _T, which is formed in the second trench 8 to the gate capacitance C _G formed in the first trench 3 _(that volume using the active region SA) A certain gate-emitter capacitance G _GE becomes a large value, and the fluctuation of the gate voltage generated at the time of switching can be suppressed.

  Next, the surface density will be described. The surface area of the region where the trench is formed is S0, the total surface area of the upper end of the opening of the trench is S1, and the total surface area of the semiconductor layers (p-well region and n-emitter region) sandwiched between the trenches is When S2, S0 = S1 + S2. The area density of the trench is expressed as S1 / S0 × 100% = S1 / (S1 + S2) × 100 (%) (see FIG. 4 for the reference).

FIG. 4 is a diagram for explaining the surface density. Here, a general description will be given of the surface density when the length and interval of the trench are different.
The width of the opening of the trench is W (constant), the length is L1, L2 (L1> L2), the trench spacing of L1 is D1, D2 (D1 <D2), and the spacing of the L2 trench is D3, D4 (D3 < D4), the distance between the D1 group trench and the D2 group trench is D5, the distance between the D3 group trench and the D4 group trench is D6, and the distance between the trenches having different trench lengths (here, the D2 group trench). The distance between the trench and the trench of the D3 group) is D7, the number of L1 trenches is nL1, the number of L2 trenches is nL2, the number of D1 intervals is nD1, the number of D2 intervals is nD2, and the interval of D3 If the number is nD3, the number of intervals of D4 is nD4, the number of intervals of D5 is nD5, the number of intervals of D6 is nD6, and the number of intervals of D7 is nD7.
S1 is W × L1 × nL1 + W × L2 × nL2 = W × (L1 × nL1 + L2 × nL2).

  S2 is (D1 × L1 × nD1) + (D2 × L1 × nD2) + (D3 × L2 × nD3) + (D4 × L2 × nD4) + (D5 × L1 × nD5) + (D6 × L2 × nD6) ) + (D7 * L2 * nD7) = L1 * (D1 * nD1 + D2 * nD2 + D5 * nD5) + L2 * (D3 * nD3 + D4 * nD4 + D6 * nD6 + D7 * nD7).

  Therefore, the surface density of the trench is S1 / (S1 + S2) × 100% = W × (L1 × nL1 + L2 × nL2) / (W × (L1 × nL1 + L2 × nL2) + (L1 × (D1 × nD1 + D2 × nD2 + D5 × nD5)) + L2 × (D3 × nD3 + D4 × nD4 + D6 × nD6 + D7 × nD7)) × 100%.

  Next, although not shown in the figure, the surface density when the length and the interval of the trench are equal will be described. When the width of the opening of the trench is W, the length is L, the interval is D, and the number is n, S1 is W × L × n, and S2 is L × D × (n−1). Accordingly, the surface density of the trench is (W × L × n) / ((W × L × n) + (L1 × D × (n−1)) × 100 (%).

  5A and 5B are diagrams for explaining the length in the depth direction acting as a gate capacitor and a trench capacitor. FIG. 5A is a diagram in the case of a gate capacitor, and FIG. 5B is a diagram in the case of a trench capacitor. . Since the trench is deeper than the first p-well region 2, the length T acting as the gate capacitance shown in FIG. 5A is the length T1 in the depth direction of the trench in the p-well region where the n-emitter region is formed. The length T acting as the trench capacitance shown in FIG. 4B is a length T2 in which the trenches are shallower than the second p-well region 7 and the both walls and bottom of the trench are combined.

Hereinafter, the surface density of the first trench, the surface density of the second trench, the gate capacitance, and the trench capacitance of the semiconductor device 100 illustrated in FIG. 1 will be specifically described.
The width of the first trench 3 is 1 μm, the interval is 4 μm, the width of the floating region is 20 μm (the width of the wide trench interval only in the first trench 3), and the number of trenches falling within the width of 4 μm + 20 μm = 24 μm is two. width 1μm of second trenches 8, the length T2 in the depth direction serve as trenches capacitance _{C T} is 9 .mu.m, spacing and 17 present the number of trenches into the width of 24μm in 0.4 .mu.m, the surface density of the first trench 3 Is 1 μm × 2 pieces / 24 μm × 100 = 8.3%. On the other hand, the surface density of the second trench 8 is 1 μm × 17/24 μm = 71%. Therefore, the surface density of the second trench 8 is 8.6 times the surface density of the first trench 3.

Assuming a surface area of 1 mm × 1 mm, the area of the gate capacitance portion 31 (where the gate capacitance _CG is formed) of the first trench 3 (active region SA) formed on this surface area is (3 μm (T1) × 1 mm). ) × (1 mm ÷ 24 μm) × 2 = 2.5 × 10 ⁵ μm ² , and the trench capacitance portion 32 (trench capacitance _CT is formed in the second trench 8 (formed under the gate electrode pad 15). Area is (9 μm (T2) × 1 mm) × (1 mm ÷ 24 μm) × 17 = 6.4 × 10 ⁶ μm ² .

Therefore, when the surface area of the portion where the first trench 3 is formed to 96 mm ^2, the total area of the gate capacitance _{C G} of the gate capacitance section 31 formed in the active region SA is 96mm ² ÷ 1mm ² × 2.5 × 10 ⁵ μm ² = 2.4 × 10 ⁷ μm ²

Further, when the area of the gate electrode pad 15 and 4 mm ^2, the total area of the trench capacitor _{C T} of the trench capacitor 32 which is formed below the gate electrode pad 15 is ^{4mm 2 ÷ 1mm 2 × 6.4 ×} 10 6 μm ² = 2.6 × 10 ⁷ μm ²

Since capacity = dielectric constant × area ÷ insulating film thickness, when the dielectric constant and the insulating film thickness are the same, it is proportional to the area (total area). In other words, the total area of the trench capacitor C _T of the trench capacitor 32 because approximately equal to the total area to be the gate capacitance C _G of the gate capacitance section 31, the trench capacitor C _T and the gate capacitance C _G are approximately equal. Therefore, the gate-emitter capacitance _{C GE} of IGBT plus trench capacitor _{C T} is two times the gate capacitance _{C G} formed in the active region SA. The size of the gate capacitance _{C G} of about 100 mm ² chip is on the order of approximately 10 nF.

Experiments since it is known that can suppress the fluctuation of the gate voltage using an external capacitor is substantially equal capacitance to the gate capacitance C _G of the magnitude of the IGBT of about 100 mm 2 ⁽¹⁰ mm square) between the gate and emitter , by adding a trench capacitor C _T of the present invention to the gate capacitance C _G, it is effective for suppressing the fluctuation of the gate voltage. The noise level by adding a trench capacitor C _T was measured variation of the gate voltage is reduced about 25% in order to confirm this effect.

In this embodiment, the second trench 8 is formed under the gate electrode pad 15. However, as described above, other than the current detection electrode pad and the active region (not shown) other than the gate electrode pad 15 are not shown. If there is region by forming a second trench 8 in that position, it is possible to increase the trench capacitor C _T.

Further, it is possible or the depth of the second trench 8, by increasing the increasing surface density the number by narrowing the width and spacing increasing trench capacitor C _T.
Alternatively, the second p well region 7 may be formed simultaneously with the same depth as the first p well region 2. However, if the depth of the second trench 8 is made shallower than the depth of the first trench 3, the trench capacitor C _T than the same depth decreases.

  In this embodiment, the IGBT having the floating region (region 2b) has been described as an example. However, the present invention can also be applied to an IGBT or MOSFET having no floating region.

  6 and 7 are configuration diagrams of a semiconductor device according to a second embodiment of the present invention. FIG. 6 is a schematic plan view of the chip. FIG. 7 is a detailed sectional view taken along line X1-X1 in FIG. . An IGBT is given as an example of the semiconductor device 200.

  The difference from the first embodiment is that the first p well region 2 and the second p well region 7 formed in the chip 201 are separated from each other. The second p well region 7 is connected to the emitter electrode 14, and the conductor 10 is connected to the gate electrode 6. In this case, the same effect as in the first embodiment can be obtained.

  FIG. 8 is a plan view of an essential part of a semiconductor device according to the third embodiment of the present invention. This is a planar pattern at the location of the second trench 8. An example of the semiconductor device 300 is an IGBT.

The difference from the first embodiment is that the planar pattern of the second trench is not a stripe pattern but a lattice pattern.
In this case, the surface density of the second trench 8 is as follows: the surface area S1 of the opening of the second trench 8 / (the surface area S1 of the opening of the second trench 8 + the semiconductor layer sandwiched between the second trenches 8 (the second p well region 7). ) Surface area sum S2) × 100 (%).

With this structure, the surface density of the second trench 8 can be raised from the above embodiment, it is possible to further increase than the trench capacitor C _T of the embodiment. As a result, the fluctuation of the gate voltage can be further suppressed.

DESCRIPTION OF SYMBOLS 1 n Semiconductor substrate 1a n drift area | region 2 1st p well area | region 2a area | region used as emitter potential 2b area | region used as floating potential 3 1st trench 4 gate insulating film 5 n emitter area | region 6 gate electrode 7 2nd p well area | region 8 2nd trench 9 Insulating film 10 Conductor 11 Wiring conductor 12 Interlayer insulating film 13 Contact hole 14 Emitter electrode 15 Gate electrode pad 16 Gate runner 17 Connection conductor (formed in contact hole)
18 n buffer layer 19 p collector layer 20 collector electrode 31 gate capacitance part 32 trench capacitance part 100, 200, 300 semiconductor device 101, 201 chip S0 S1 + S2
S1 Total surface area of the upper end of the opening of the trench S2 Total surface area of the semiconductor layer sandwiched between the trenches SA Active region _CG Gate capacitance (capacitance formed in the first trench 3)
_CT trench capacitance (capacitance formed in the second trench 8)
C _GE gate-emitter capacitance (C _G + C _T )

Claims (7)

A first conductivity type semiconductor substrate;
A first semiconductor layer of a second conductivity type disposed on a surface layer of the semiconductor substrate;
A first trench disposed from the surface of the first semiconductor layer through the first semiconductor layer and reaching the semiconductor substrate;
A gate insulating film disposed on the inner wall of the first trench;
A second semiconductor layer of a first conductivity type disposed on a surface layer of the first semiconductor layer in contact with a side wall of the first trench;
A gate electrode filled in the first trench through the gate insulating film;
An interlayer insulating film covering the gate electrode;
A main electrode in contact with the second semiconductor layer and the first semiconductor layer through an opening disposed in the interlayer insulating film;
A third semiconductor layer of a second conductivity type disposed on the surface layer of the semiconductor substrate apart from the first semiconductor layer;
A second trench disposed in the third semiconductor layer;
An insulating film disposed on the inner wall of the second trench;
A conductor filled in the second trench through the insulating film,
A semiconductor device in which the conductor is connected to the gate electrode and the third semiconductor layer is connected to the main electrode;
The second trench is disposed at least under a gate electrode pad connected to the gate electrode and disposed on the semiconductor substrate,
A semiconductor device, wherein a surface density of the second trench is larger than a surface density of the first trench. A first conductivity type semiconductor substrate;
A first semiconductor layer of a second conductivity type disposed on a surface layer of the semiconductor substrate;
A first trench disposed from the surface of the first semiconductor layer through the first semiconductor layer and reaching the semiconductor substrate;
A gate insulating film disposed on the inner wall of the first trench;
A second semiconductor layer of a first conductivity type disposed on a surface layer of the first semiconductor layer in contact with a side wall of the first trench;
A gate electrode filled in the first trench through the gate insulating film;
An interlayer insulating film covering the gate electrode;
A main electrode in contact with the second semiconductor layer and the first semiconductor layer through an opening disposed in the interlayer insulating film;
A third semiconductor layer of the second conductivity type which is disposed in contact with said first semiconductor layer on the surface layer of the semiconductor substrate,
A second trench disposed in the third semiconductor layer;
An insulating film disposed on the inner wall of the second trench;
A conductor filled in the second trench through the insulating film,
A semiconductor device in which the conductor is connected to the gate electrode,
The second trench is disposed at least under a gate electrode pad connected to the gate electrode and disposed on the semiconductor substrate,
The surface density of the second trench is greater than the surface density of the first trench;
A semiconductor device, wherein the depth of the third semiconductor layer is deeper than the depth of the first semiconductor layer.   The semiconductor device according to claim 2, wherein the third semiconductor layer is connected to the main electrode.   S1 / (S1 + S2) × 100 (%) where the surface density of the trench is S1 when the total surface area of the upper end of the opening of the trench is S1 and the total surface area of the semiconductor layer sandwiched between the trenches is S2. It is represented by these. The semiconductor device as described in any one of Claims 1-3 characterized by the above-mentioned.   2. The semiconductor device according to claim 1, further comprising: a gate capacitor portion including the first semiconductor layer, the gate insulating film and the gate electrode, a third semiconductor layer, and a trench capacitor portion including the insulating film and the conductor. Item 5. The semiconductor device according to any one of Items 1 to 4.   The semiconductor device according to claim 1, wherein the gate electrode and the conductor are polysilicon.   The semiconductor device according to claim 1, wherein the planar shape of the second trench is a stripe shape or a lattice shape.

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