JP5677679B2 - Receiver circuit for radio clock - Google Patents

Description

  The present invention relates to a radio timepiece receiver circuit that receives a standard radio wave and corrects the time.

  Conventionally, various configurations are known as a radio timepiece that automatically corrects and displays an internal time based on time information included in a standard radio wave. These radio timepieces are provided with a receiving circuit that receives standard radio waves, performs analog processing, and outputs time information. This receiving circuit amplifies and demodulates a received signal received by an antenna, binarizes it with a predetermined determination threshold value, and outputs it as time information. As shown, a receiving antenna 101, a tuning unit 102, an amplifier circuit 103, a filter circuit 104 including a BPF (Band Pass Filter), a detection circuit 105, an LPF (Low Pass Filter) 106, and binarization. A circuit 107 and an AGC (Auto Gain Control) 108 are provided. Further, based on a configuration that employs a differential amplifier circuit as an amplifier circuit (see, for example, Patent Document 1), a comparator that generates and outputs a binarized signal from a filtered received signal and a reference voltage, and the control signal A reference voltage switching unit that switches a reference voltage to be output to the comparison unit; and a storage unit that stores a switching state of the reference voltage. The reference voltage switching unit receives a standard radio wave received by a control signal based on the switching state information. A configuration is also known in which a reference voltage suitable for the above is output to the comparison unit (see Patent Document 2).

JP 2004-64262 A JP 2008-20291 A

However, these conventional radio timepiece receiving circuits have the following problems because demodulation and binarization are processed by analog circuits.
First, since the detection circuit performs full-wave rectification using a diode, a large ripple occurs in the detection waveform, and an LPF with a large time constant using external components is indispensable to eliminate this ripple. Since everything can not be made on-chip when it is made into an IC, an inexpensive receiving circuit cannot be provided.
Second, when the AGC process is performed on the detected waveform, since the AGC output value is held by the capacitor, a constant value cannot be held for a long time. Also, due to the function of the capacitor, an AGC output at an arbitrary level cannot be set by the receiving circuit IC alone, and the output level of the AGC cannot be held for a long time during standby. In addition, it is difficult to make the time constant of the AGC process variable because it leads to an increase in cost. For this reason, it is difficult to make the AGC follow-up time variable. Furthermore, in the AGC process, the detection waveform is delayed due to the high Q of BPF. Therefore, in order to satisfy AGC stability, the time constant for tracking the AGC output must always be increased. It is difficult to converge. Further, depending on the reception protocol, there is a situation where the convergence of the AGC output is not optimal. Such inconvenience is apparent from the AGC operation waveform diagram shown in FIG.
Third, the threshold value for binarization is made of an analog circuit and its accuracy is required, and it is made of an analog circuit, leading to an increase in cost. Further, when the amplitude of the detection waveform falls below the determination threshold value, a situation in which the binarized signal is not output occurs.
An object of the present invention is to provide a radio-controlled timepiece receiving circuit that solves many problems caused by analog processing by performing digital processing.

The inventors of the present invention initially studied by adopting a configuration using a square operation as a detection means for digital processing. In the case of performing a square operation with a digital circuit, it is necessary to perform a multiplication and a subsequent square operation, which led to the radio clock receiver circuit (first comparative example) shown in FIG. The radio clock receiver circuit according to the first comparative example includes a receiving antenna 51, a variable capacitance element 52 as a tuning unit, and a VGA (Variable) as an amplifier circuit.
Gain amplifier 53, a filter circuit 54 having a buffer before and after the band-pass filter, an A / D conversion circuit 55, a square calculation circuit 56 and a square calculation circuit 57 that constitute detection means, an LPF 58, and binarization A circuit 59, an AGC 60, and a D / A conversion circuit 61 are provided. Although not shown, the output of the D / A conversion circuit 61 is input to the VGA 53 through an LPF (low pass filter).

  However, according to the configuration of the first comparative example, the digital processing in the detection means composed of the square calculation circuit 56 and the square calculation circuit 57 is heavy, and as shown in FIG. Since the components remain, the LPF 58 for removing the components must be made heavy, and as a result, the detection waveform processed by the LPF 58 becomes dull as shown in FIG.

  In order to eliminate the inconvenience in the filter processing after the detection described above, the present inventors next examined the radio-controlled timepiece receiving circuit (second comparative example) shown in FIG. The radio clock receiver circuit according to the second comparative example is provided with a pair of square calculation circuits 76a and 76b in place of the square calculation circuit 56, and the digitized reception signal output from the A / D conversion circuit 75 is local to the received signal. The I component and Q component of the local signal frequency generated by the frequency generation circuit 82 are mixed, and the signals converted to different frequencies are input to the square calculation circuits 76a and 76b, squared, and added. , And is input to the square operation circuit 77. That is, in the second comparative example, the I and Q components are used to reduce the second harmonic component generated during detection. Other configurations are the same as those of the first comparative example shown in FIG.

  However, according to the configuration of FIG. 7, since further multiplication and addition processing is performed using the pair of square arithmetic circuits 76a and 76b, the filter processing is certainly light, but the circuit scale is increased and the current consumption is also large. This causes the inconvenience. FIG. 8 is a waveform diagram in digital processing of the radio clock receiver circuit shown in FIG.

  In order to solve the above inconvenience and achieve the above-mentioned object, the radio clock receiver circuit according to the present invention generates time information binarized from a long wave standard radio wave including time information received by an external antenna, A receiving circuit for a radio timepiece that outputs a tuning unit that sets a tuning capacity value of the antenna to a frequency of a received long wave standard radio wave, and an intermediate that includes the time information based on a signal received by the setting of the tuning unit A filter circuit for acquiring a received signal, an A / D converter circuit for converting the intermediate received signal into a digital signal, an absolute value detecting circuit for detecting an absolute value of the converted digital signal, and an absolute value detected digital signal A comb filter for removing spurious and an AG for controlling the gain of the received long wave standard radio wave based on the digital signal from which the spurious has been removed. And a D / A conversion circuit that converts the output of the AGC into an analog signal, and a binarization circuit that can change a slice level that is a determination threshold value that binarizes the digital signal from which spurious has been removed. Prepare.

  The binarization circuit is preferably configured so that both the peak level and the bottom level of the detection waveform for obtaining the slice level follow the detection waveform. Further, it is more preferable that the slice level of the binarization circuit is configured to have a hysteresis width. Further, it is more preferable that the binarization circuit has a duty adjustment mechanism constituted by a digital circuit. Furthermore, it is more preferable to have a variable gain amplifier that amplifies the received longwave standard radio wave signal and a gain adjustment mechanism that generates a signal for controlling the gain based on the digital signal from which the spurious has been removed by the comb filter. . Furthermore, the gain adjustment mechanism has a gain control signal holding unit that holds a set value of a specific gain control signal, and the set value of the gain control signal that is held when returning from the standby state or during control by an external signal Thus, it is more preferable to control the gain of the variable gain amplifier. Further, it is more preferable that the digital signal output from the comb filter is input to the binarization circuit through the LPF.

  According to the radio-controlled timepiece receiving circuit of the present invention, the digital processing is performed to eliminate the problems associated with the conventional analog processing, and in particular, absolute value detection is performed and the absolute value detection is generated. By removing the spurious noise with a comb filter that has a large attenuation at the spurious frequency, a clean detection waveform can be obtained and the subsequent filtering can be simplified, greatly reducing the circuit scale and current consumption. can do. In addition, since the time constant of the AGC output can be freely changed due to digital processing, the time constant can be shortened only at the time of start-up to achieve high-speed convergence of the AGC output, and the time constant can be changed according to the reception protocol. As a result, the optimal AGC output convergence operation can be realized in all protocols. Furthermore, since the binarized slice level can be changed according to the detection waveform for digital processing, the duty adjustment is easy, and the peak level for obtaining the slice level so as to follow the peak and bottom of the detection waveform By setting the bottom level, even if the amplitude of the detection waveform varies, binarization can always be performed at the optimum slice level, and the sensitivity of the radio-wave timepiece receiving circuit can be improved.

1 is a block diagram showing a preferred embodiment of the present invention. The wave form diagram which shows the operation | movement of an absolute value detection circuit and a comb filter. The wave form diagram which shows the operation | movement of AGC. The wave form diagram which shows the operation | movement of a binarization circuit. The block diagram which shows a 1st comparative example. The wave form diagram which shows the operation | movement of the detection means and filter of a 1st comparative example. The block diagram which shows the 2nd comparative example. The wave form diagram which shows the operation | movement of the detection means and filter of a 2nd comparative example. The block diagram which shows a general prior art example. The wave form diagram which shows the operation | movement of AGC in the prior art example.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, a preferred embodiment of the invention will be described with reference to FIGS.
As shown in FIG. 1, the radio clock receiving circuit includes an external antenna 1, a variable capacitance element 2 that is a tuning unit that tunes the tuning capacitance value of the antenna 1 to the frequency of a radio signal to be received, and the antenna 1. The VGA (variable gain amplifier) 3 for amplifying the radio signal received at 1, the filter circuit 4 for acquiring only the frequency of the long wave standard wave received from the amplified signal of the VGA 3, and the intermediate received signal that has passed through the filter circuit 4 An A / D conversion circuit 5 for digitization, an absolute value detection circuit 6 for absolute detection of the digitized intermediate received signal, a comb filter 7 for removing spurious generated by detection by the absolute value detection circuit 6, and An LPF 8 for smoothing the output signal of the comb filter 7 and a gain when the received signal is amplified by the VGA 3 based on the signal input from the LPF 8 An AGC 9 that outputs a signal to be controlled, a D / A conversion circuit 10 that converts the output of the AGC 9 into an analog signal and inputs the analog signal, and binarizes the output of the LPF 8 and outputs it as time information 2 And a valuation circuit 11. Although not shown, the output of the D / A conversion circuit 10 is input to the VGA 3 through an LPF (low pass filter).

  Next, the main configuration will be described in more detail. As shown in FIG. 1, the filter circuit 4 includes a first buffer 4a and a second buffer 4b, and the output of the first buffer 4a is input to the second buffer 4b via a BPF 4c. It is composed.

  The absolute value detection circuit 6 detects an absolute value of the intermediate reception signal that has been digitized and input by the A / D conversion circuit 5 (see FIGS. 2A and 2B). At the time of absolute value detection, as shown in the absolute value waveform spectrum of FIG. 2 (f), a DC component and a double wave component are generated by the absolute value calculation, and are generated based on the relationship between the sampling frequency and the carrier frequency before detection. Spurious components that are frequency components are generated (see the solid line in FIG. 2F). Here, since the frequency of the spurious component is obtained from each of the known frequencies that are the cause of the occurrence, the comb filter 7 whose frequency characteristic has a large attenuation at the frequency of the spurious component (see the broken line in FIG. 2 (f)). The detection output from which the spurious component is removed (see FIG. 2C) is obtained. 2 (e), (f), (g), and (h) are the spectra of the waveforms in FIGS. 2 (a), (b), (c), and (d), respectively.

  The LPF 8 to which the detection output from the comb filter 7 is input smoothes the detection output (see FIG. 2D). The AGC 9 to which the output of the LPF 8 is input digitally outputs a signal for controlling the gain when the received signal is amplified by the VGA 3, and constitutes a gain adjustment mechanism. The output digital signal can converge the output voltage of the AGC 9 in a short time by setting the time constant at startup short to speed up the rise and then setting it to a normal time constant (see FIG. 3). Further, during the intermittent operation, the output voltage of the AGC 9 after convergence is digitally held and stored, so that it is possible to shift to the convergence state almost immediately after returning from the standby state (see FIG. 3). . In order to digitally hold the output voltage of the AGC 9, the AGC 9 has a gain control signal holding unit (not shown) therein. In addition, the signal held in the gain control signal holding unit can be fixed to an arbitrary set value regardless of the level of the received signal by an external control signal. By using this fixing function, the signal to the entire receiving circuit can be fixed. Testability is improved.

  On the other hand, as shown in FIG. 4A, the binarization circuit 11 to which the output of the LPF 8 inputs obtains a slice level from a peak level and a bottom level that follow the detection waveform with a time constant arbitrarily set in advance. It is a valuation. That is, if the detected waveform value is larger than the current value, the peak level is corrected to the detected waveform value. Otherwise, the peak level is attenuated by the time constant set, and the bottom level is lower than the current value. When the detection waveform value is small, the detection waveform value is corrected. In other cases, the detection waveform value is increased by a time constant with a bottom level set. In binarization, slice level 1 and slice level 2 having a predetermined hysteresis width are set to reduce glitches. These slice levels 1 and 2 are obtained by multiplying the difference between the peak level and the bottom level by a predetermined coefficient. By reversing from “1” to “0” when slice level 1 intersects the rising region of the detection waveform, and by reversing from “0” to “1” when slice level 2 intersects the falling region of the detection waveform. The binarized waveform shown in FIG. 4B can be obtained.

  Subsequently, the operation of the above-described embodiment will be described. First, the variable capacitance element 2 tunes the tuning frequency of the antenna 1 to the frequency of a standard radio wave received in advance. The standard radio signal having a predetermined frequency received by the antenna 1 is amplified by the VGA 3 and only the frequency received by the filter circuit 4 is acquired. The selected intermediate received signal is digitally converted by the A / D conversion circuit 5. , Input to the absolute value detection circuit 6.

  The absolute value detection circuit 6 detects the absolute value of the digitized intermediate received signal, removes the spurious component of the detection signal with the comb filter 7 (see FIG. 2), and smoothes it with the LPF 8 to suppress the noise. Output as a digital demodulated signal containing information. This demodulated signal is digitized by the binarization circuit 12 (see FIG. 4B). However, since each slice level 1 and 2 follows the detection waveform, the amplitude of the detection waveform varies. However, binarization can always be performed at an optimal slice level. Further, by providing a duty adjustment mechanism including a digital circuit that changes the slice level, the duty adjustment can be easily performed. By this duty adjustment, an optimum demodulated signal can be obtained for various detection waveforms. The binarized demodulated signal is sent to a control unit (not shown) and converted into time information, and this time information is used to correct the time of the radio timepiece.

  On the other hand, the digital signal from the LPF 8 is also input to the AGC 9, and the AGC 9 outputs the output voltage as a digital signal that determines the gain when the received signal is amplified by the VGA 3. Since this digital signal can be set to an arbitrary time constant, it can be converged at high speed. The digital signal is converted to an analog signal by the D / A conversion circuit 10 and input to the VGA 3, and the signal received by the antenna 1 is amplified with a predetermined gain determined by the AGC 9. The received signal is input to the A / D conversion circuit 5 through the filter circuit 4, and the above-described operation is repeated, and is output from the binarization circuit 12 as binarized information including time information.

  The present invention is not limited to the above-described embodiment, and a heterodyne system may be adopted instead of the so-called straight detection system that does not perform frequency conversion. When this heterodyne method is employed, a local oscillation circuit is provided to generate a local signal having a predetermined frequency, and the local signal and the received standard radio wave signal are mixed to generate an intermediate frequency signal. Then, the intermediate frequency signal may be digitized by the A / D conversion circuit 5 through the BPF and input to the absolute value detection circuit 6.

1 Antenna 2 Variable Capacitor 3 VGA
4 Filter circuit 5 A / D conversion circuit 6 Absolute value detection circuit 7 Comb filter 8 LPF
9 AGC
10 D / A conversion circuit 11 Binary circuit

Claims (7)

A reception circuit for a radio clock that generates and outputs binary time information from a long wave standard radio wave including time information received by an external antenna, and sets a tuning capacity value of the antenna to the frequency of the received long wave standard radio wave A tuning unit for setting, a filter circuit for obtaining an intermediate reception signal including the time information based on a signal received by setting of the tuning unit, an A / D conversion circuit for converting the intermediate reception signal into a digital signal, An absolute value detection circuit for detecting the absolute value of the converted digital signal, a comb filter for removing the spurious signal of the digital signal subjected to the absolute value detection, and a slice level for binarizing the digital signal from which the spurious signal has been removed by the comb filter. And a binarization circuit that can be changed. 2. The radio clock receiver circuit according to claim 1, wherein the binarization circuit is configured to follow both the peak level and the bottom level of the detection waveform for obtaining the slice level. 3. The radio clock receiver circuit according to claim 2, wherein the binarization circuit is configured to set a slice level having hysteresis. 4. The radio-controlled timepiece receiving circuit according to claim 2, wherein the binarizing circuit has a duty adjustment mechanism constituted by a digital circuit. A variable gain amplifier that amplifies the received long wave standard wave signal based on the digital signal from which spurious is removed by the comb filter, and a gain adjustment mechanism that generates a signal for controlling the gain. The radio timepiece receiver circuit according to claim 1. The gain adjustment mechanism has a gain control signal holding unit that holds a set value of a specific gain control signal, and the gain control mechanism holds the set value of the gain control signal when returning from a standby state or during control by an external signal. 6. The radio clock receiver circuit according to claim 5, wherein the gain of the variable gain amplifier is controlled. The radio clock receiver circuit according to claim 1, wherein the digital signal output from the comb filter is input to a binarization circuit through an LPF.

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