JP5721934B2 - Semiconductor device design support method - Google Patents

Description

The present invention relates to a design support method for a semiconductor device in which timing verification is performed.

  2. Description of the Related Art In recent years, with the advancement of semiconductor technology, hierarchical design techniques have been frequently used in large-scale LSI (Large Scale Integrated circuit) designs or LSI designs incorporating a plurality of identical functions. That is, by designing the upper hierarchy (chip) and the lower hierarchy (circuit block) separately and arranging the circuit blocks on the chip to form one, a system LSI composed of a small-scale LSI is formed. . Note that the circuit block is configured by arranging a plurality of basic cells constituting a logic circuit. A basic cell is a minimum unit that is repeatedly arranged and has one or more transistors.

Such a system LSI is designed through each process of LSI function design, front-end design, and back-end design (see, for example, Patent Document 1).
In LSI function design, the system to be realized is defined as LSI, and the defined LSI functions are described in RTL (Register Transfer Level) using the Hardware Description Language (HDL) language. Verify whether the desired operation is performed.

  In the front-end design, the RTL described in the LSI functional design is converted into a net list composed of circuit blocks. Timing verification or the like is performed on the netlist to check whether the created circuit satisfies a timing condition such as operating at a desired frequency and a specified value.

  In back-end design, floor plans, power supply wiring, and circuit block placement are performed using a netlist that was not found abnormal in each verification of front-end design, and operation and quality assurance of the manufactured LSI is realized. Verification to do is done last.

  In particular, in order to reduce the size of system LSIs in recent years, there are cases where circuit blocks are arranged on a chip while being rotated.

JP 2005-251976 A

  However, when the circuit block is rotated and placed on the chip, the basic cells that make up the circuit block rotate with the rotation of the circuit block, the direction of the gate of the transistor changes, and the electrical characteristics of the transistor Will also change. In recent miniaturized semiconductor devices, there has been a problem in that the amount of change in electrical characteristics becomes large, causing a delay in the delay time, resulting in a problem in timing design.

In order to avoid timing design problems, it is necessary to redesign the circuit block, which increases the possibility of reworking the development, and the manufacturing of the semiconductor device becomes complicated.
In view of the above points, an object of the present invention is to provide a design support method for a semiconductor device with improved manufacturing efficiency.

In order to achieve the above object, a design support method for a semiconductor device in which timing verification is performed is provided.
Design support method of the semiconductor device, and more Engineering you get the electrical characteristics including an on-current of the transistor in each arrangement angle of the transistor, based on the electrical characteristics, the delay information of the basic cell having the transistor , and as engineering you extracted for each placement angle of the basic cell, based on said delay information, having a higher Engineering you verify timing circuit block including the basic cell.

In such a semiconductor device design support method, electrical characteristics are acquired for each arrangement angle of a transistor, and delay information of a basic cell having a transistor is extracted for each arrangement angle of the basic cell based on the electrical characteristics. Thus, the timing of the circuit block composed of the basic cells is verified based on the delay information.

The semiconductor device design support method improves the manufacturing efficiency.

3 is a flowchart showing a method for manufacturing the semiconductor device of the first embodiment. It is a figure which shows the hardware constitutions of the design support apparatus of a semiconductor device. It is a figure for demonstrating an example of a test chip. It is a table | surface which shows the delay time and consumption current for every arrangement angle of a basic cell. It is a graph which shows the on current with respect to the threshold voltage of a transistor. 6 is a flowchart illustrating a method for manufacturing a semiconductor device according to a second embodiment.

Hereinafter, embodiments will be described with reference to the drawings.
First, the first embodiment will be described.
FIG. 1 is a flowchart showing a semiconductor device manufacturing method according to the first embodiment, and FIG. 2 is a diagram showing a hardware configuration of a semiconductor device design support apparatus.

First, FIG. 2 will be described.
The design support apparatus 100 for supporting the design of the semiconductor device shown in FIG. 2 is controlled by a CPU (Central Processing Unit) 101 as a whole. A random access memory (RAM) 102, a hard disk drive (HDD) 103, a graphic processing device 104, an input interface 105, and a communication interface 106 are connected to the CPU 101 via a bus 107.

  The RAM 102 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the CPU 101. The RAM 102 temporarily stores at least a part of various data necessary for processing by the CPU 101. In addition, at least a part of the data generated by the processing of the CPU 101 is temporarily stored.

  The HDD 103 stores an OS program and application programs. The HDD 103 stores various data such as basic cell, circuit block, and chip layout data D1, D2, and D3. In addition, data acquired by the tester 114 and data generated by the process of the CPU 101 are also stored.

  A monitor 111 is connected to the graphic processing device 104. The graphic processing device 104 displays an image on the screen of the monitor 111 in accordance with a command from the CPU 101.

  A keyboard 112 and a mouse 113 are connected to the input interface 105. The input interface 105 transmits a signal sent from the keyboard 112 or the mouse 113 to the CPU 101 via the bus 107.

  A tester 114 that is a test apparatus is connected to the communication interface 106. The communication interface 106 transmits, to the CPU 101 via the bus 107, a signal of electrical characteristics of a transistor of a tester chip described later acquired by the tester 114.

By using the design support apparatus 100 having the above configuration, for example, a semiconductor device is manufactured according to the flowchart of FIG.
A method for manufacturing a semiconductor device will now be described along the flow of FIG.

First, data stored in advance in the HDD 103 will be described.
The layout data D1 holds data related to layout such as arrangement, wiring, floor plan, and the like of transistors constituting the basic cell of the semiconductor device to be manufactured.

  The layout data D2 and D3 hold data relating to layouts such as layout, wiring, and floor plan of the basic cells constituting the circuit block and the circuit blocks constituting the chip.

  The layout data D2 is generated from the net list and constraints (both not shown) of the semiconductor device to be manufactured and the layout data D1. Similarly, the layout data D3 is generated from the netlist and constraints and the layout data D2.

When the test chip measurement data D4 is measured by the tester 114 and acquired, it is stored in the HDD 103.
The transistor electrical characteristic data D5a and D5b and the library L1 are generated in the course of processing performed by the CPU 101 and stored in the HDD 103.

  [Step S11] The tester 114 measures the DC characteristics, which are electrical characteristics such as the voltage and current of the test chip prepared in advance, and the AC characteristics, which are electrical characteristics such as the operating frequency and the delay time of the input / output signals. Is done. The communication interface 106 stores the measurement result received from the tester 114 in the HDD 103, and forms test chip measurement data D4.

  FIG. 3 is a diagram for explaining an example of a test chip. 3A shows the test cell T in which the basic cell 10 is arranged, and FIG. 3B shows the test chip T in which the circuit blocks 20 composed of the transistors 10a and 10b and the basic cell 10 are arranged.

  As a specific example, the test chip T shown in FIG. 3 includes transistors 10 a and 10 b and a circuit block 20. The circuit block 20 is configured by arranging the basic cells 10 in two rows.

  A basic cell 10 shown in FIG. 3A is composed of transistors 10 a and 10 b having P-type and N-type diffusion regions 11 and 12 and gates 13 and 14. X is the origin position of the basic cell 10 and the state shown in FIG. 3A is the basic position (arrangement angle 0 degree). When the basic cell 10 is arranged so as to rotate around the origin position X, the transistors 10a and 10b also rotate and the direction of the gates 13 and 14 changes.

  In the test chip T shown in FIG. 3B, two circuit blocks 20 (c1) configured by arranging a plurality of transistors 10a, 10b (a1, b1) and basic cells 10 are arranged. Further, on the test chip T, transistors 10a and 10b (a2 and b2) and two circuit blocks 20 (c2) which are rotated 90 degrees clockwise in the drawing are arranged. As the circuit block 20 and the like arranged on the test chip T rotate by 90 degrees, the origin position X also rotates by 90 degrees. Further, the test chip T shown in FIG. 3B is one example of the arrangement of the circuit block 20 and the like, and other types of basic cells and circuit blocks may be used. Further, the circuit block 20 or the like may have a different arrangement angle.

  As described above, by using the test chip T, it is possible to efficiently measure and acquire the DC characteristics and AC characteristics of each arrangement angle. Test chip measurement data D4 holding the measurement result is formed.

  [Step S12] The CPU 101 represents a transistor model having an angle arranged on the test chip T using, for example, SPICE based on the test chip measurement data D4. Electrical characteristics such as on-current and threshold voltage are reproduced from the transistor model. From the reproduced electrical characteristics, the transistor electrical characteristic data D5a when there is no rotation and the transistor electrical characteristic data D5b when there is rotation are formed for each presence / absence of the transistor arrangement angle. The transistor electrical characteristic data D5a and D5b are stored in the HDD 103, respectively.

  [Step S13] The CPU 101 calculates the delay time due to the wiring of the basic cell configured by laying out the transistors according to the layout data D1 for each of the presence / absence of rotation of the transistor based on the transistor electrical characteristic data D5a and D5b. Note that the basic cell of the first embodiment is composed of transistors 10a and 10b as shown in FIG.

  The calculated delay time is extracted for each rotation of the basic cell composed of transistors, and the extracted delay time is formed as the delay information in the library L2a (without rotation) and the library L2b (with rotation), respectively. Is done. The libraries L2a and L2b are stored in the HDD 103, respectively. In step S13, the delay time and / or current consumption can also be extracted for each rotation, and the libraries L2a and L2b can be formed in the same manner.

FIG. 4 is a table showing the delay time and current consumption for each basic cell arrangement angle.
As a specific example, the minimum value and the maximum value of the delay time are extracted from the basic cell libraries L2a and L2b having the arrangement angles of 0 degrees and 90 degrees shown in FIGS. 4A and 4B, respectively. The same applies to current consumption.

  [Step S14] The CPU 101 integrates the libraries L2a and L2b, synthesizes the delay time depending on the presence / absence of the arrangement angle of the basic cell, and replaces (includes) the delay information with one delay information. Create

  As a specific example, the library L1 shown in FIG. 4C includes both the libraries L2a and L2b shown in FIGS. 4A and 4B. The minimum value and the maximum value of the delay time and current consumption are described from the libraries L2a and L2b, respectively.

  [Step S15] The CPU 101 verifies the timing of the circuit block in which the basic cell is laid out according to the layout data D2 based on the library L1. The timing verification verifies whether each circuit block operates at a desired frequency or satisfies a desired standard value.

  [Step S16] As in step S15, the CPU 101 verifies the timing of chips laid out in circuit blocks according to the layout data D3, between chip and circuit blocks, and between circuit blocks based on the library L1. The timing verification verifies whether the chip, the chip / circuit block, and the circuit blocks operate at a desired frequency or satisfy a desired standard value.

  In step S16, if the arrangement state (rotation) of the circuit block is confirmed, the same result is obtained even if the timing verification is performed using the libraries L2a and L2b according to the arrangement angle. can get.

  In step S15 and step S16, timing verification of circuit blocks, chips, and the like can be performed efficiently. As a result of the timing verification performed, if there is no problem in the operation state and the specified value is satisfied, the manufacture of the LSI designed according to the layout data D1, D2, D3, the net list, etc. is started.

The libraries L1, L2a, and L2b thus obtained will be described below with reference to graphs.
FIG. 5 is a graph showing the on-state current with respect to the threshold voltage of the transistor.

  The horizontal axis Vth represents the threshold voltage, and the vertical axis Ion represents the on-current. That is, as the threshold voltage decreases and the on-state current increases, the operation speed of the transistor increases. On the other hand, the operation speed of the transistor becomes slower as the threshold voltage increases and the on-current decreases.

  A solid line graph connecting the circles (white circles) represents the on-state current with respect to the threshold voltage when the transistors are arranged so that there is no arrangement angle (rotation). The delay time of the basic cell having the transistor having such characteristics is held in the library L2a.

  A solid line graph connecting (black circles) represents the on-state current with respect to the threshold voltage when the transistors are arranged so as to have an arrangement angle (rotation). The delay time of the basic cell having the transistor having such characteristics is held in the library L2b.

  According to the two types of graphs, it can be seen that an error occurs in the on-current with respect to the threshold voltage depending on the presence or absence of rotation. Therefore, when performing timing verification of circuit blocks having various arrangement angles, if any one of the libraries L2a and L2b that hold delay information related to the delay time is used for each rotation, there is an error in any verification result. Arise.

  On the other hand, a broken line graph connecting ○ (left side) and ● (right side) represents the on-state current with respect to the threshold voltage of the transistor including the case where there is no rotation and the case where there is no rotation. In this case, it almost matches the combined range of the above two types of graphs. The library L1 obtained by integrating the libraries L2a and L2b corresponds to a basic cell having a transistor having such characteristics.

  As described above, the library L1 holds delay information related to the delay time for each arrangement angle of the basic cells. In the timing verification using the library L1 in step S15 and step S16, it is possible to eliminate errors in the verification result even if there is a circuit block laid out by the layout data D2 and D3 or a chip that is rotated and arranged. It becomes.

  For this reason, it is not necessary to rearrange the circuit blocks according to the verification result and perform timing verification again, thereby reducing the complexity of the manufacturing process. In addition, timing verification can be properly performed for various arrangement states of the basic cell in consideration of the area efficiency of the LSI, and the manufacturing efficiency is improved.

Next, a second embodiment will be described.
Also in the second embodiment, the semiconductor device is manufactured by the design support apparatus 100 shown in FIG. 2, and the test chip T shown in FIG. 3 and the library L1 used in FIG. Each is used.

Hereinafter, processing performed by the CPU 101 will be described along the flow of FIG.
FIG. 6 is a flowchart showing a method for manufacturing the semiconductor device of the second embodiment. Note that detailed description of steps in which processing similar to that in the first embodiment is performed is omitted.

  Similar to the first embodiment, layout data D1, D2, and D3 are stored in the HDD 103 in advance. The test chip measurement data D4 measured by the tester 114 and the library L1 generated in the process of the CPU 101 are stored in the HDD 103, respectively.

Now, processing performed by the CPU 101 will be described along the flow of FIG.
[Step S11] The measurement results of the DC characteristics and AC characteristics of the test chip T measured by the tester 114 are stored in the HDD 103.

The details of the specific test chip T are the same as those in FIG. 3 referred to in the first embodiment.
[Step S22] Based on the test chip measurement data D4, the CPU 101 represents a transistor model having an angle arranged on the test chip T using, for example, SPICE. From the transistor model, electrical characteristics such as on-current and threshold voltage are reproduced. Transistor electrical characteristic data D5 including electrical characteristics for each reproduced arrangement angle is created. The created transistor electrical characteristic data D5 is stored in the HDD 103.

  [Step S23] The CPU 101 calculates the delay time of the signal due to the wiring of the basic cell in which the transistor is laid out according to the layout data D1, based on the transistor electrical characteristic data D5. The calculated delay time is extracted for each arrangement angle of the basic cell composed of transistors, and the delay time obtained by synthesizing the delay time depending on the arrangement angle and replacing it with one delay time is held as delay information. Library L1 is formed. The library L1 is stored in the HDD 103. In step S23, the delay time and / or current consumption can also be extracted, and the library L1 can be formed similarly.

  As a specific example, in the library L1 shown in FIG. 4C, the minimum value and the maximum value of the delay time obtained in the case of both arrangement angles are extracted for the basic cells having the arrangement angles of 0 degrees and 90 degrees. It has been described. Similarly, the minimum value and the maximum value are also extracted and described for the current consumption.

  [Step S15] The CPU 101 verifies the timing in the circuit block in which the basic cell is laid out according to the layout data D2 based on the library L1. The timing verification verifies whether each circuit block operates at a desired frequency or satisfies a desired standard value.

  [Step S16] As in step S15, the CPU 101 verifies the timing of the chip on which the circuit block is laid out according to the layout data D3 based on the library L1. Specifically, timing verification is performed between chips, chips and circuit blocks, and between circuit blocks. The timing verification verifies whether the chip or the like operates at a desired frequency or satisfies a desired standard value.

  As a result of the timing verification performed in step S15 and step S16, if there is no problem in the operation status and the specified value is satisfied, the LSI manufactured according to the layout data D1, D2, D3, the netlist, etc. Is started.

  As described above, the library L1 holds delay information related to the delay time for each arrangement angle of the basic cells. In the timing verification using the library L1 in step S15 and step S16, it is possible to eliminate errors in the verification result even if there is a circuit block laid out by the layout data D2 and D3 or a chip that is rotated and arranged. It becomes.

  For this reason, it is not necessary to rearrange the circuit blocks according to the verification result and perform timing verification again, thereby reducing the complexity of the manufacturing process. In addition, timing verification can be properly performed for various arrangement states of the basic cell in consideration of the area efficiency of the LSI, and the manufacturing efficiency is improved.

  The above processing functions can be realized by a computer. In that case, a program describing the processing contents of the functions that the design support apparatus 100 should have is provided. By executing the program on a computer, the above processing functions are realized on the computer. The program describing the processing contents can be recorded on a computer-readable recording medium. Examples of the computer-readable recording medium include a magnetic recording device, an optical disk, a magneto-optical recording medium, and a semiconductor memory. Examples of the magnetic recording device include a hard disk device (HDD), a flexible disk (FD), and a magnetic tape. Examples of the optical disc include a DVD (Digital Versatile Disc), a DVD-RAM, a CD-ROM (Compact Disc Read Only Memory), and a CD-R (Recordable) / RW (ReWritable). Examples of the magneto-optical recording medium include MO (Magneto-Optical disk).

  When distributing the program, for example, a portable recording medium such as a DVD or a CD-ROM in which the program is recorded is sold. It is also possible to store the program in a storage device of a server computer and transfer the program from the server computer to another computer via a network.

  A computer that executes a design support program stores, for example, a program recorded on a portable recording medium or a program transferred from a server computer in its own storage device. Then, the computer reads the program from its own storage device and executes processing according to the program. The computer can also read the program directly from the portable recording medium and execute processing according to the program. Further, each time the program is transferred from the server computer, the computer can sequentially execute processing according to the received program.

DESCRIPTION OF SYMBOLS 10 Basic cell 10a, 10b Transistor 11 P-type activation region 12 N-type activation region 13, 14 Gate 20 Circuit block 100 Design support apparatus 101 CPU
102 RAM
103 HDD
104 Graphic Processing Device 105 Input Interface 106 Communication Interface 107 Bus 111 Monitor 112 Keyboard 113 Mouse 114 Tester X Origin Position T Test Chip D1 Layout Data (Basic Cell)
D2 Layout data (circuit block)
D3 Layout data (chip)
D4 Test chip measurement data D5 Transistor electrical property data D5a Transistor electrical property data (no rotation)
D5b Transistor electrical characteristics data (with rotation)
L1 library (including both rotations)
L2a library (no rotation)
L2b library (with rotation)

Claims (2)

The design support apparatus obtains electrical characteristics including the on-current of the transistor for each transistor arrangement angle, measured by the test apparatus using a test chip in which transistors arranged at a plurality of different arrangement angles are arranged on the chip. Process,
The design support apparatus, based on the electrical characteristics, extracting delay information of the basic cell having the transistor for each arrangement angle of the basic cell;
The design support device has a step of verifying a timing of a circuit block including the basic cell based on the delay information ; and
In the step of acquiring the electrical characteristics, the design support device acquires, for the transistor, a first electrical characteristic and a second electrical characteristic in the case of a first arrangement angle and a second arrangement angle, respectively.
In the step of extracting the delay information, the design support apparatus uses the first arrangement angle and the second arrangement angle for the basic cell based on the first electric characteristic and the second electric characteristic. In the case of the first delay information and the second delay information including the maximum delay time and the minimum delay time, respectively,
In the step of verifying the timing of the circuit block, the design support apparatus selects a larger one of the maximum delay times included in the first delay information and the second delay information, and the first delay information and the The delay information is acquired by integrating the first delay information and the second delay information by selecting a smaller one of the minimum delay times included in the second delay information.
Design support method of a semiconductor device which is characterized a call. The design support method for a semiconductor device according to claim 1, further comprising a step of verifying a timing of a chip including the circuit block by the design support device based on the delay information.

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