JP5774804B2 - Time synchronization system, time synchronization apparatus, time synchronization method, and time synchronization program - Google Patents

Description

  The present invention relates to a time synchronization system that performs time management in a system including a plurality of devices.

Currently, the ETC system installed at tollgates on expressways has a discount service for tolls according to the time of day, and the time information when the vehicle passes the gate indicates whether the discount service is appropriate. It is important data for judgment.
In addition, when it is determined that a vehicle passing through the ETC lane is an abnormal ETC vehicle (a vehicle in which normal exchange is not performed between the ETC system and the ETC on-board device), or a non-ETC vehicle (no ETC on-board device is installed) When it is determined that the vehicle is a vehicle, time information recorded together with the log may be required to analyze the determination.
However, the time information in the conventional ETC system is often inaccurate, which has been a major obstacle in executing the charge service and log analysis.

In describing the reason why the time information of the ETC system is inaccurate, first, a mechanism of time management in the ETC system will be described.
FIG. 20 is an external view showing the entire conventional ETC system, and FIG. 21 is a block diagram for explaining a time management method in the conventional ETC system.
In general, the ETC system is a system configured by various devices including a roadside wireless device 1a as shown in FIG. 20, but particularly as a device related to time management, as shown in FIG. In addition, the system is configured by devices installed at a toll gate such as a toll server 3a, a lane monitoring server 4a, and a video 5a.

As shown in FIG. 21, in the conventional ETC system, first, the toll gate server 3a receives accurate reference time data from the upper system 2a once a day via the LAN interface. .
The toll booth server 3a receives the reference time data from the host system 2a and simultaneously outputs the same time data to the roadside apparatus 1a. Subsequently, the roadside apparatus 1a receives the same time data to the lane monitoring server 4a. Send.
Then, the lane monitoring server 4a transmits time data to the video 5a (video in which the vehicles passing through the ETC lane are photographed one by one) through the contact interface.
That is, the time synchronization between the devices constituting the ETC system is achieved by such a mechanism.

Therefore, in order to realize accurate time management as a whole system, it is indispensable that the roadside wireless device always manages accurate time data as well as the toll booth server.
That is, if the time data recognized by the roadside device is not accurate, the time data of other devices will be inaccurate, and the time data of the entire system cannot be kept accurate.

A conventional roadside wireless device will be described with reference to the drawings.
FIG. 22 is a block diagram showing a configuration of a roadside wireless device of a conventional ETC system.
As shown in FIG. 22, the conventional roadside apparatus 1a includes a plurality of panels such as a CPU board 10a, a radio interface board 20a, an apparatus monitoring board 21a, and an encryption / composite (SAM) board 22a.
In this roadside apparatus 1a, the CPU board 10a first receives time data in an IP packet received from the toll gate server 3a through the LAN interface.

In the CPU board 10a, according to the received time data, the timer of the OS built in the panel is periodically interrupted to increase the counter register in the memory, and by reading this register value, It was time.
Further, the CPU board 10a is configured to distribute the received time data in a telegram format (software processing) to other panels.
When each panel receives a message distributed from the CPU board 10a, each panel performs a timer interrupt of the OS built in each panel according to the time data included in the message and counts up each panel. It was time of.
Technologies related to such an ETC system are disclosed in, for example, Patent Documents 1 to 4.

JP 2002-216182 A JP 2004-038764 A JP 2004-171230 A JP 2005-258726 A

However, in the above-described time management method normally performed in the conventional ETC system as proposed in Patent Documents 1 to 4, each received panel performs synchronization by periodically performing timer interrupts on the OS. Therefore, if a higher priority interrupt task or a task for which interrupt processing is prohibited operates during the timer interrupt, an accurate count-up cannot be performed.
In this case, there is a situation in which the time is gradually shifted from the correct time until delivery of the next synchronization time, and the maximum time is shifted by 10 seconds or more.

In addition, since the time is counted by the timer on the OS in each panel, the time data varies from panel to panel.
For example, the time stamped in the log information on each panel when a certain event occurs is recorded with a large or small deviation.
As a result, an error also occurs with respect to the time recognized by other devices constituting the ETC system, such as an in-vehicle monitoring server and a video, and it is difficult to associate the passing vehicle with the log recording time.
In particular, in the ETC system, there are cases where a plurality of vehicles pass through in a short time, and although it is necessary to accurately manage time information in milliseconds, it has been extremely difficult to realize.

  As described above, in the ETC system, even if a mechanism for periodically acquiring accurate reference time data is provided, the time recognized by each device constituting the system is inconsistent and inaccurate. Management was not performed properly, and as a result, the reliability of the system was impaired.

  An object of the present invention is to provide a time synchronization system that eliminates the inaccuracy of time recognition in a system configured by combining a plurality of devices, which is a problem described above, and enables time management in a minimum time unit. There is.

  In order to achieve the above object, a time synchronization system of the present invention is a time synchronization system in a system including one device and one or more other devices, the one device corresponding to predetermined reference time data. The time data in the one device is corrected and the corrected time data is measured based on a predetermined oscillating means, and the other device in the other device according to the time data in the one device. Time data is measured.

  The time synchronization device of the present invention is a time synchronization device connected to one or more other devices, which corrects its own time data in accordance with predetermined reference time data and is based on predetermined oscillation means. The apparatus includes a means for measuring the corrected time data, and a means for measuring the time data in the other device according to its own time data.

The time synchronization method of the present invention is a time synchronization method in a system including one device and one or more other devices, and corrects the time data in the one device according to predetermined reference time data. And a step of measuring the corrected time data based on a predetermined oscillating means, and a step of measuring the time data in the other device according to the time data in the one device.

  The time synchronization program of the present invention is a time synchronization program in a system composed of one device and one or more other devices, and the computer constituting the one device is controlled according to predetermined reference time data. The time data in the one device is corrected, and the computer constituting the other device is used as the time data in the one device by functioning as a means for measuring the corrected time data based on predetermined oscillation means. Accordingly, it is a program for functioning as means for measuring time data in the other apparatus.

  According to the time synchronization system of the present invention, it is possible to eliminate the time error recognized by each device constituting the system and appropriately manage the time in the system.

A preferred embodiment of the present invention will be described below with reference to FIGS.
Here, the time synchronization system and the time synchronization apparatus according to the embodiments of the present invention described below are realized by processes, means, and functions executed by a computer in accordance with instructions of a program (software). The program sends a command to each component of the computer to perform predetermined processing and functions as shown below. That is, each processing / means in the roadside apparatus of the present embodiment is realized by specific means in which a program and a computer cooperate.
Note that all or part of the program is provided by, for example, a magnetic disk, optical disk, semiconductor memory, or any other computer-readable recording medium, and the program read from the recording medium is installed in the computer and executed. The The program can also be loaded and executed directly on a computer through a communication line without using a recording medium.

[First embodiment]
FIG. 1 is an external view showing the entire ETC system according to the first embodiment of the present invention.
As shown in FIG. 1, the ETC system according to the present embodiment is configured by various devices. Among them, the roadside wireless device 1 not only communicates with the vehicle-mounted device of the passing vehicle, but also manages the time. It has become an important device.
Here, a time management method in the ETC system will be described with reference to FIG.
FIG. 2 is a block diagram for explaining a time management method in the ETC system according to the present embodiment.
As shown in FIG. 2, in the ETC system according to this embodiment, in addition to the roadside wireless device 1, time management is performed by the cooperation of a plurality of devices including a charge server 3, a lane monitoring server 4, and a video 5. ing.

Specifically, first, the toll gate server 3 receives accurate reference time data from the host system 2 via the LAN interface once a day.
The toll gate server 3 receives the reference time data from the host system 2 and outputs the same time data to the roadside radio device 1 at the same time, and then the roadside radio device 1 sends the same time data to the lane monitoring server 4. Send.
Then, the lane monitoring server 4 transmits time data to the video 5 (video in which the vehicles passing through the ETC lane are photographed one by one) through the contact interface.

  The lane monitoring server 4 is a server that monitors the ETC lane, and records the passing time and the like as a log when it is determined that the vehicle passing through the ETC lane is an abnormal ETC vehicle or a non-ETC vehicle. At the same time, it has a mechanism to issue an alarm immediately.

Therefore, a detailed description will be given focusing on roadside radio apparatuses that play an important role in time management of the ETC system.
FIG. 3 is a block diagram showing the configuration of the roadside apparatus according to the present embodiment.
As shown in FIG. 3, the roadside apparatus 1 according to this embodiment includes a panel of a radio interface board 20, an apparatus monitoring board 21, and an encryption / decryption (SAM) board 22 in addition to a CPU board 10.
Among them, the central CPU board 10 is connected to an external device that provides accurate reference time data via a LAN interface, and each panel is connected to a predetermined bus (for example, a backboard wiring of a printer board). Signal line bus).
Then, the time data is measured by counting up the register value in the binary register 102 mounted on the CPU board 10.
At the same time, the CPU board 10 distributes this register value to each panel.
As a result, each panel reads the register value and measures time data.

Next, the CPU panel and each panel constituting the roadside apparatus will be described with reference to FIGS.
FIG. 4 is a block diagram showing the configuration of the CPU board of the roadside apparatus according to this embodiment, and FIG. 5 is a block diagram showing the configuration of each panel of the roadside apparatus according to this embodiment.
As shown in FIG. 4, the CPU board 10 according to the present embodiment includes a CPU 100, a clock 101, and a binary register 102.
In general, the CPU 100 is formed by a microprocessor or the like that performs various arithmetic processes and instruction processes. In particular, in this embodiment, the CPU 100 controls operations of the binary register 102, the clock 101, and the like.

For example, the CPU 100 receives predetermined reference time data from the outside via the LAN interface (reference time acquisition means of the present invention), and triggers reception of this reference time data to output a reset signal to the binary register 102, Time data reset control is performed (first correction means of the present invention).
Further, the CPU 100 performs an operation of reading the register value of the binary register 102 as a CPU data bus based on the clock 101 and counting time data (first time measuring means of the present invention).
Further, the CPU 100 also has a role of distributing the register value of the binary register 102 to each panel through the backboard (time adjustment data distribution means of the present invention).

The clock 101 is an oscillator provided with a predetermined oscillating means, which has a frequency of 1 kHz (1000 counts / second) as described above, and has an accuracy of an error of several ppm or less.
This is because, in the ETC system according to the present embodiment, synchronization (reset) based on accurate time is performed with the host system 2 once a day (for example, PM 11:30). This is because it is necessary to provide a function capable of self-running so that no error occurs in units of ms (milliseconds) for 24 hours.

For this reason, the binary register 102 employs a memory capable of counting at least 27 digits of binary numbers.
When the time of the day is converted into milliseconds, 24 hours × 3600 seconds × 1000 ms = 86,400,000 ms (decimal number), and when converted into binary numbers, 101,0010,0110, This is because it becomes 0101, 1100, 0000, 0000 and becomes binary data of 27 digits.

  That is, by combining the clock 101 and the binary register 102, the register value is counted up by one clock, and the time data can be measured in milliseconds.

On the other hand, as shown in FIG. 5, each panel has a CPU 200, and receives the register value (27 digits) distributed from the CPU board 10 via the backboard (time adjustment data receiving means of the present invention). The data is read as a CPU data bus.
The CPU 200 of each panel can measure its own time data based on the read register value (second time measuring means of the present invention), thereby realizing synchronization with the time of the CPU panel 10.
Each panel may be equipped with a binary register as in the case of the CPU panel 10 so that the distributed register value is always reflected in the binary register.
For example, in the ETC system, when recording a time zone discount software process or an event occurrence log, it is easy to obtain accurate time information by accessing this binary register.

Next, an operation procedure of the roadside apparatus according to the present embodiment configured as described above will be described with reference to FIG.
FIG. 6 is a flowchart showing an operation procedure in the roadside apparatus according to the present embodiment.
As shown in FIG. 6, the CPU board 10 of the roadside apparatus 1 determines whether or not predetermined reference time data has been acquired (S11).
In the present embodiment, accurate reference time data is input from the outside (the toll gate server 3 connected to the host system 2) every 24 hours (for example, PM 11:30). The CPU 100 of the CPU panel 10 is configured to detect.

As a result of step S11, when the CPU 100 of the CPU board 10 detects the reference time data (S11: YES), the CPU 100 resets the binary register 102 accordingly (S12).
Specifically, the CPU 100 of the CPU board 10 outputs a predetermined reset signal to the binary register 102 and corrects the register value to an appropriate value.
As a result, the time data of the CPU board 10 is corrected to accurate time data.
On the other hand, when the reference time data is not detected as a result of step S11 (S11: NO), the process proceeds to step S13 without going through step S12.

Next, in the CPU board 10, the binary register 102 counts up the register value based on the clock 101 (S13), and as a result, time data is measured.
Specifically, the CPU 100 reads (reads) the register value and recognizes it as the time on the CPU board 10.
That is, the CPU board 10 is required to self-run in other time zones while periodically correcting the time data once every 24 hours.
For this reason, a highly accurate oscillator (for example, an error number of ppm or less) is required for the clock 101.
The binary register 102 is mounted with a register that can count at least 27-digit bit data so that the CPU panel 10 can measure in milliseconds.
As a result, accurate time data can be measured in milliseconds for a considerable period (at least for 24 hours).

The CPU board 10 distributes the register value measured by the binary register 102 to other panels (wireless interface board 20, device monitoring board 21, encryption / decryption (SAM) board 22) through the backboard (S14).
Thereby, each panel can always share the time recognized by the CPU board 10.
Specifically, the CPU 200 mounted on each panel can recognize the time on each panel by reading the register value distributed from the CPU board 10.

As described above, according to the roadside apparatus 1 of the present embodiment, the CPU board 10 corrects its own time data according to the accurate reference time data input from the outside every 24 hours. Yes.
Then, after correcting the time data, the binary register 102 counts bit data corresponding to the 27-digit time based on the high-accuracy clock 101, so that the CPU 100 independently measures accurate time data. I can do it.
Also, by distributing the register value of the binary register 102 counted in the CPU board 10 to other panels, the CPU 200 of the other panel reads the register value and measures time data. .

  In particular, in the present embodiment, the clock 101 mounted on the CPU board 10 has a predetermined frequency, and the binary register 102 can also count a considerable number of digits correspondingly, so that it can be measured in milliseconds. Time measurement is possible.

  For this reason, conventional problems such as differences in time data between panels and devices and the inability to recognize accurate time are solved, and as a result, various processes related to time can be reliably performed in the ETC system. Become.

Specifically, event information of vehicles passing through the ETC lane can be recorded in milliseconds.
Thereby, for example, even when an abnormal ETC vehicle or a non-ETC vehicle is detected, or even when a plurality of target vehicles pass within an extremely short time, analysis of related events and identification of each vehicle are easily performed. be able to.

  In addition, when performing clearance for illegal traffic or detecting an abnormal ETC vehicle, the time data between the devices is recorded in a unified unit in milliseconds, so each panel in the roadside wireless device The time data recorded together with the log and the log of the lane monitoring server and the video data of the corresponding vehicle can be accurately verified, and the target vehicle can be easily discriminated.

  Furthermore, since the time data can be accurately recognized when executing a so-called time zone discount service that discounts the toll based on the time when the vehicle passes, an appropriate service can be provided.

  In this way, by providing the roadside apparatus according to the present embodiment, it is possible to make time management in the ETC system appropriate and fair, and to realize an ETC system with excellent reliability.

[Second Embodiment]
Next, a roadside apparatus according to a second embodiment of the present invention will be described with reference to FIGS.
FIG. 7 is a block diagram showing the configuration of the roadside apparatus according to the present embodiment.
As shown in FIG. 7, the roadside apparatus 1 according to this embodiment includes a CPU board 10, a radio interface board 20, an apparatus monitoring board 21, and an encryption / decryption (SAM) board 22, as in the first embodiment.
However, this embodiment is different from the first embodiment in that the clock 201 and the binary register 202 are mounted on each panel.
Also, the data distributed from the CPU board 10 to each panel is not a register value but a trigger signal for resetting the binary register 202 mounted on each panel.

Each panel has a LAN interface, and a LAN connection such as 100BASE-TX is established between the CPU board 10 and each panel.
In particular, this embodiment is also characterized in that invalid symbol data that is not normally used in so-called 4B / 5B code conversion executed in physical layer coding in 100BASE-TX is used as reset information.

Next, the CPU panel and each panel constituting the roadside apparatus of the present embodiment will be described with reference to FIGS.
FIG. 8 is a block diagram showing the configuration of the CPU board of the roadside apparatus according to this embodiment, and FIG. 9 is a block diagram showing the configuration of each panel of the roadside apparatus according to this embodiment.
As shown in FIG. 8, the CPU board 10 according to the present embodiment is equipped with a CPU 100, a clock 101, and a binary register 102 as in the first embodiment, but also has unique symbol data via the MAC unit 103. Is different to each panel.

On the other hand, each panel has a clock 201, a binary register 202, and a MAC unit 203 in addition to the CPU 200, as shown in FIG.
The reason why the clock 201 and the binary register 202 are mounted is to measure the time independently in each panel as in the case of the CPU board 10, and this point is also different from the first embodiment.

The MAC unit 203 has a role of detecting reset information from data received via the LAN interface and outputting a reset signal to the binary register 202.
In particular, in the present embodiment, the MAC unit 203 has a function of detecting symbol data periodically distributed from the CPU board 10 as reset information.
As this symbol data, invalid data which is not used in 4B / 5B code conversion in 100BASE-TX is used.
Specifically, the data “00110” “11001” “00000” “00001” “00010” “00011” “00101” “01000” “01100” “01” corresponding to the symbol “V” shown in the lower part of the table shown in FIG. “10000” is used.

Here, among the data shown above, for example, “00110” is used as the symbol data.
In this case, as shown in FIG. 11, the symbol data “00110” is inserted into the MAC unit 103 periodically (every 24 hours) and distributed to each panel via the LAN interface.
Therefore, in each panel, as shown in FIG. 12, the symbol data “00110” is detected periodically (every 24 hours) from the data received via the LAN interface. .
When the symbol data “00110” is detected by the MAC unit 203 of each panel, the MAC unit 203 outputs a predetermined reset signal to the binary register 202, thereby resetting the register value and correcting the time data as a result. (Second correction means of the present invention).

Next, an operation procedure of the roadside apparatus according to the second embodiment configured as described above will be described with reference to FIG.
FIG. 13 is a flowchart showing an operation procedure in the roadside apparatus according to the present embodiment.
As shown in FIG. 13, the CPU board 10 of the roadside apparatus 1 determines whether or not predetermined reference time data has been acquired (S21).
Also in the present embodiment, accurate reference time data is input from the outside every 24 hours (for example, PM 11:30), and this is a mechanism in which the CPU 100 of the CPU panel 10 detects this. .

As a result of step S21, when the CPU 100 of the CPU board 10 detects the reference time data (S21: YES), the CPU 100 resets the binary register 102 accordingly (S22).
Specifically, the CPU 100 of the CPU board 10 outputs a predetermined reset signal to the binary register 102 and corrects the register value to an appropriate value.
As a result, the time of the CPU board 10 is corrected to accurate time data.
On the other hand, when the reference time data is not detected as a result of step S21 (S21: NO), the process proceeds to step S23 without going through step S22.

Next, in the CPU board 10, the binary register 102 counts up the register value based on the clock 101 (S23), and as a result, time data is measured.
Specifically, the CPU 100 reads (reads) the register value and recognizes it as the time on the CPU board 10.
That is, the CPU board 10 is required to self-run in other time zones while periodically correcting the time data once every 24 hours.
For this reason, a highly accurate oscillator (for example, an error number of ppm or less) is required for the clock 101.
The binary register 102 is mounted with a register that can count at least 27-digit bit data so that the CPU panel 10 can measure in milliseconds.
As a result, accurate time data can be measured in milliseconds for a considerable period (at least for 24 hours).

Note that the CPU board 10 always monitors the timing of distributing symbol data as reset information to other panels (wireless interface board 20, device monitoring board 21, encryption / decryption (SAM) board 22).
In the present embodiment, the reset information is distributed to each panel every 24 hours. For this reason, the CPU panel 10 always determines whether or not it is the distribution time of the reset information (S24). .
Here, if it is a predetermined distribution time (S24: YES), symbol data is distributed to each panel (S25).

In each panel that has received the symbol data, the register value of the binary register 202 is reset (S26).
Specifically, when the MAC unit 203 of each panel detects symbol data, a reset signal is output to the binary register 202, and the register value is reset.
Thereby, the time data of each panel is synchronously corrected to accurate data.
As the symbol data, data invalidated in so-called 4B / 5B code conversion is used.

On the other hand, if it is other than the predetermined distribution time (S24: NO), the process proceeds to step S27 without performing the processes of steps S25 and S26.
In step S27, the register value of the binary register 202 of each panel is counted up based on its own clock 201, and as a result, time data in each panel is measured.
Specifically, the CPU 200 can recognize the time of each panel by reading the register value of the binary register 202 that is counted according to the clock 201.

As described above, according to the roadside apparatus 1 of the present embodiment, the basic configuration is the same as that of the first embodiment, but periodically, the CPU panel 10 displays symbol data as reset information, The data is distributed to each panel via the LAN interface.
In each panel, the time data is corrected in response to the reception of the symbol data, and thereafter the time data is measured independently.
For this reason, compared with 1st embodiment, the frequency of data transmission / reception between the CPU board 10 and each panel and the data amount handled can be reduced significantly.

As a result, it is possible to reduce the load on the network and reduce the burden on the CPU panel 10 and each panel required for time control.
Therefore, according to the present embodiment, it is possible to provide the roadside wireless device 1 with excellent response and provide an ETC system with high reliability while exhibiting the same effects as the first embodiment. .

[Third embodiment]
Next, a roadside apparatus according to a third embodiment of the present invention will be described with reference to FIGS.
FIG. 14 is a block diagram showing the configuration of the roadside apparatus according to the present embodiment.
As shown in FIG. 14, the roadside apparatus 1 of this embodiment is similar to the first embodiment and the second embodiment in that the CPU board 10, the radio interface board 20, the apparatus monitoring board 21, and the encryption / decryption (SAM) board 22 Consists of
Further, as in the second embodiment, reset information is periodically distributed from the CPU panel 10 to each panel, but a feature is that a multicast packet is used as the reset information.

Next, the CPU panel and each panel constituting the roadside apparatus of the present embodiment will be described with reference to FIGS. 15 and 16.
FIG. 15 is a block diagram showing the configuration of the CPU board of the roadside apparatus according to this embodiment, and FIG. 16 is a block diagram showing the configuration of each panel of the roadside apparatus according to this embodiment.
As shown in FIG. 15, the CPU board 10 according to this embodiment has the same basic configuration as that of the first embodiment or the second embodiment, but is different from the previous embodiment in that it has a multicast packet generation unit 104. Is different.

Specifically, as shown in FIG. 17, the multicast packet generated by the multicast packet generation unit 104 of the CPU panel 10 is periodically (every 24 hours) inserted into the MAC unit 103 and is connected to each panel via the LAN interface. To be delivered to.
An example of the frame structure of the multicast packet generated by the multicast packet generator 104 is shown in FIG.
As shown in FIG. 19, the multicast packet used in the present embodiment is “01.00.5E” (hexadecimal number) from the beginning of the destination MAC address part (DA) of the Ethernet® packet frame to the third byte. The identification becomes possible.
In addition, as a destination belonging to a group, a predetermined packet can be distributed to a desired panel by referring to the lower 3 bytes.
Accordingly, in the case of the example shown in FIG. 19, it is only necessary that the multicast IP address corresponding to the lower 3 bytes “0A.0A.0A” of the destination address portion (DA) is set in each panel.

On the other hand, each panel differs from the above-described embodiment in that it includes a multicast packet detection unit 204 as shown in FIG.
Specifically, as shown in FIG. 18, the multicast packet detection unit 204 is a multicast distributed periodically (every 24 hours) from the CPU board 10 from the data acquired via the LAN interface and the MAC unit 203. It detects packets.
In addition, the multicast packet detection unit 204 outputs a predetermined reset signal to the binary register 202 in response to the detection of the multicast packet, thereby resetting the register value and correcting the time data as a result.

As described above, according to the roadside apparatus 1 of this embodiment, the configuration is almost the same as that of the above-described embodiment, but the CPU panel 10 includes the multicast packet generator 104 and each panel includes A multicast packet detection unit 204 is provided, and a multicast packet is used as reset information that is periodically distributed from the CPU panel 10 to each panel.
For this reason, desired reset information can be simultaneously distributed to each panel only by setting an address.
Therefore, it is possible to realize a highly reliable ETC system and to provide an ETC system with various variations while further easily configuring the roadside apparatus 1 having the same effects as those of the above-described embodiment.

The time synchronization system of the present invention has been described with reference to the preferred embodiment. However, the time synchronization system according to the present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the present invention. It goes without saying that implementation is possible.
For example, the time synchronization system of the present invention is not limited to an ETC system, and may be applied to other systems including a plurality of devices.
As a result, it is possible to realize a time synchronization system that has excellent expandability and can be applied to various fields of use.

  The present invention can be suitably used for an ETC system or the like that requires accurate time management.

It is an external view showing the whole ETC system concerning a first embodiment of the present invention. It is a block diagram for demonstrating the time management method in the ETC system which concerns on 1st embodiment of this invention. It is a block diagram which shows the structure of the roadside radio | wireless apparatus which concerns on 1st embodiment of this invention. It is the block diagram which showed the structure of CPU board of the roadside apparatus which concerns on 1st embodiment of this invention. It is the block diagram which showed the structure of each panel of the roadside apparatus which concerns on 1st embodiment of this invention. It is the flowchart which showed the operation | movement procedure in the roadside radio | wireless apparatus which concerns on 1st embodiment of this invention. It is a block diagram which shows the structure of the roadside apparatus which concerns on 2nd embodiment of this invention. It is the block diagram which showed the structure of CPU board of the roadside radio | wireless apparatus which concerns on 2nd embodiment of this invention. It is the block diagram which showed the structure of each panel of the roadside apparatus which concerns on 2nd embodiment of this invention. 4 is a symbol table listing 4B / 5B coding rules. It is explanatory drawing which showed a mode that CPU board delivers symbol data periodically in the roadside radio | wireless apparatus which concerns on 2nd embodiment of this invention. It is explanatory drawing which showed a mode that each panel detected symbol data periodically in the roadside apparatus which concerns on 2nd embodiment of this invention. It is the flowchart which showed the operation | movement procedure in the roadside apparatus which concerns on 2nd embodiment of this invention. It is a block diagram which shows the structure of the roadside apparatus which concerns on 3rd embodiment of this invention. It is the block diagram which showed the structure of CPU board of the roadside radio | wireless apparatus which concerns on 3rd embodiment of this invention. It is the block diagram which showed the structure of each panel of the roadside apparatus which concerns on 3rd embodiment of this invention. It is explanatory drawing which showed a mode that CPU board delivers a multicast packet periodically in the roadside radio | wireless apparatus which concerns on 3rd embodiment of this invention. It is explanatory drawing which showed a mode that each panel detected a multicast packet periodically in the roadside apparatus which concerns on 3rd embodiment of this invention. It is a format figure for demonstrating the frame structure of the multicast packet used in the roadside apparatus which concerns on 3rd embodiment of this invention. It is the external view showing the whole conventional ETC system. It is a block diagram for demonstrating the time management method in the conventional ETC system. It is a block diagram which shows the structure of the roadside radio | wireless apparatus of the conventional ETC system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Roadside apparatus 10 CPU board 20 Wireless interface board 21 Apparatus monitoring board 22 Encryption / decryption (SAM) board 100 CPU
101 Clock 102 Binary Register 103 MAC Unit 104 Multicast Packet Generation Unit 200 CPU
201 Clock 202 Binary register 203 MAC unit 204 Multicast packet detection unit

Claims (5)

A time synchronization system that synchronizes time between one device and one or more other devices,
The one device is:
First time measuring means for measuring time data in the one device based on binary data of a predetermined number of digits counted based on independent self oscillation means;
A reference time acquisition means for acquiring predetermined reference time data every predetermined time;
First correction means for correcting the binary data according to the reference time information;
In the one device, for every predetermined time, the reset information having a predetermined Ethernet packet frame includes a time adjustment data distributing means for distributing to the other device as a multicast packet, a,
The other device is
Time adjustment data receiving means for receiving reset information comprising the Ethernet (registered trademark) packet frame as a multicast packet from the one device;
Second time measuring means for measuring time data in the other device based on binary data of a predetermined number of digits counted based on independent self oscillation means;
A time synchronization system comprising: a second correction unit that corrects binary data counted in the other device when the reset information is received from the one device. The one device is:
A register capable of counting 27-digit binary data and a clock with a frequency of 1 kHz,
The first time measuring means includes
The time synchronization system according to claim 1, wherein time data in the one device is measured based on 27-digit binary data counted based on the operation of the clock. The one device is:
The reference time acquisition means is
The time synchronization system according to claim 1 or 2, wherein the reference time data is acquired every 24 hours. The time synchronization system according to any one of claims 1 to 3, wherein the one device and the other device are devices constituting a predetermined ETC system. A time synchronization method for synchronizing time between one device and one or more other devices,
The one device is
Measuring time data in the one apparatus based on binary data of a predetermined number of digits counted based on independent self oscillation means;
Obtaining predetermined reference time data every predetermined time;
Correcting the binary data according to the reference time information;
In the one apparatus, at predetermined time intervals, the reset information consisting of a predetermined Ethernet (registered trademark) packet frame is delivered to the other apparatus as a multicast packet , and
The other device is
Receiving reset information consisting of the Ethernet (registered trademark) packet frame as a multicast packet from the one device;
Measuring time data in the other device based on binary data of a predetermined number of digits counted based on independent self oscillation means;
And a step of correcting binary data counted in the other device when the reset information is received from the one device.

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