JP5840067B2 - Current detection device for power conversion device and semiconductor module provided with this current detection device - Google Patents

Description

  The present invention relates to a current detection device for a power conversion device using a Rogowski coil that realizes high accuracy at low cost, and a semiconductor module equipped with the current detection device.

  Conventionally, a power converter is used to control the drive current of an electric device such as a motor, and a self-extinguishing semiconductor element such as an IGBT is used as a switching element of this type of power converter. . If an overcurrent flows through such a switching element, element destruction or the like may occur. Therefore, a current detection device may be provided to detect whether or not an overcurrent has occurred.

  Conventionally, current detection devices in this case include those using a switching element with a current detection sensor and those in which a CT (current transformer) is arranged outside the switching element. In the former switching element with a current detection sensor, a shunt resistor is connected to the sensor unit, and it is necessary to increase the resistance value of the shunt resistor in order to increase detection accuracy. There are drawbacks such as generation of heat, and the element itself is more expensive than those without current detection sense. In addition, the latter current detection device using CT requires a large core to prevent magnetic saturation of the core made of a magnetic material used in CT in order to detect a large current or a direct current with CT. Thus, there is a problem that the apparatus is increased in size and cost.

  Conventionally, there is a current detection device using a Rogowski coil that detects a change in magnetic field intensity proportional to the current flowing through the signal line. A current detection device using such a Rogowski coil is suitable for the measurement of a large current or a direct current because it does not have a core such as a CT and is compact and does not cause magnetic saturation. When such a Rogowski coil is used, an integrating circuit combining an operational amplifier and a capacitor is used to convert an electromotive force corresponding to the current value into a voltage value.

  Such an integration circuit can detect a relatively low frequency current with high accuracy. However, due to the characteristics of the operational amplifier, the gain characteristic in the low frequency region is poor, and the integration circuit is configured by a drift voltage. Charge accumulates in the capacitor. Therefore, when used continuously, there is a problem that the detection output of the integrating circuit deviates from the actual current value.

  As a countermeasure, conventionally, as described in Patent Document 1 below, a period in which a current flowing through a Rogowski coil arranged in each arm is zero (hereinafter simply referred to as a zero current period) is predicted. Provided is a current prediction circuit and a reset circuit that discharges a capacitor constituting the integration circuit during the zero current period predicted by the zero current prediction circuit, and resets the integration circuit during the zero current period predicted by the zero current prediction circuit There is a proposal that corrects the deviation of the output of the integration circuit by resetting at.

Japanese Patent No. 4286413

However, the prior art described in Patent Document 1 still has the following problems.
That is, the reset signal is output from the reset circuit because the reset signal is output within the turn-on delay time from immediately after the ON pulse of the gate control signal applied to the switching element of the power conversion device to when the current actually starts to flow through the switching element. Considering the delay time of the reset signal itself and the turn-on delay time of the switching element, the capacitor in the integration circuit cannot be fully discharged, or the delay time is generated in the reset signal itself and the zero current period has passed and the current has already passed. There is a problem that an accurate current value cannot be detected because a reset signal is output when the flow starts.

  In addition, the power conversion device includes a pair of upper and lower positive and negative arms connected in series for each phase, and each of these arms is composed of a switching element and a reflux diode connected in reverse parallel thereto. However, in this case, when resetting the current detection integration circuit of the switching element of one arm (for example, the negative arm), the gate control signal applied to the switching element of the other arm (for example, the positive arm) Since the reset signal is generated by using this method, it is necessary to make a circuit that can secure electrical insulation between the positive and negative arms using some method. There is a problem of inviting an increase in size.

  The present invention has been made to solve the above-described problems, and has an object to provide a small-sized, low-cost, high-accuracy power conversion device current detection device, and a semiconductor module including the current detection device. And

In the current detection device for a power converter according to the present invention, a pair of upper and lower positive and negative arms are connected in series, and each of the arms is composed of a switching element and a free-wheeling diode connected in antiparallel to the switching element. A Rogowski coil for detecting a current flowing through the arm of the power conversion device, and detecting a change in magnetic field strength proportional to the current flowing through the arm individually corresponding to each of the arms ; , An integration circuit for integrating the detection output of the Rogowski coil, and a zero current period in which the current flowing through the arm is zero. Based on the prediction result, a capacitor constituting the integration circuit in the zero current period is predicted. a reset circuit for outputting a reset signal for discharging the accumulated charges is provided, among the upper and lower pair of the arms, one of a to be current detected If the other arm is referred to as the reverse arm, the reset circuit performs the dead time, reverse arm after turning off the gate control signal for the switching element of the current arm to be detected. From the time when the turn-on delay time of the switching element and the recovery time of the diode of its own arm have elapsed when the gate control signal to the switching element of the current arm is turned on, and then from the time when the gate control signal to the switching element of its own arm is turned on A period up to the time point before the time is estimated to be the zero current period of the self arm, and the reset signal is output during the zero current period.

  According to the present invention, sufficient consideration is given to the output timing of the reset signal output from the reset circuit, and the reset circuit has a zero current period in which the current flowing through the Rogowski coil arranged in each arm is zero. Since the prediction is reliably performed and the reset signal is output during the zero current period, the integration circuit is more reliably reset than before, and the current value flowing through each arm can always be detected accurately.

  In addition, the integration circuit of the current detection device provided in the own arm is not reset using the gate control signal of the reverse arm as in the prior art, and the integration circuit is used only by using the gate control signal of the own arm. Since resetting is performed, it is not necessary to use a gate control signal of the reverse arm that requires electrical insulation, and the circuit can be simplified and miniaturized.

It is a block diagram which shows the power converter device which has an electric current detection apparatus which concerns on Embodiment 1 of this invention. It is a circuit diagram which shows the specific structure of the electric current detection apparatus shown in FIG. It is a timing chart with which it uses for operation | movement description of the same power converter device and a current detection apparatus. It is a timing chart with which it uses for operation | movement description of the power converter device and electric current detection apparatus which concern on Embodiment 2 of this invention. It is a block diagram of the electric current detection apparatus which concerns on Embodiment 3 of this invention. 6 is a timing chart illustrating an example of an overcurrent protection operation of the current detection device illustrated in FIG. 5. It is a block diagram which shows the modification of the same electric current detection apparatus. It is a timing chart which shows an example of the overcurrent protection operation | movement of the current detection apparatus shown in FIG. It is a perspective view which shows the external appearance of the semiconductor module which has a current detection apparatus with an overcurrent protection circuit which concerns on Embodiment 4 of this invention. It is sectional drawing which follows the AA line of FIG.

Embodiment 1 FIG.
1 is a configuration diagram showing a power conversion device having a current detection device according to Embodiment 1 of the present invention, and FIG. 2 is a circuit diagram showing a specific configuration of the current detection device shown in FIG.

  The power conversion device according to the first embodiment is a two-level inverter, which shows one phase here, and a pair of upper and lower arms Pa (positive side) and N side (negative side) 5a, 5b are connected in series. Both ends thereof are connected to a DC power source 9. Moreover, the connection point of both switching elements 10a and 10b is connected to AC terminal AC. The AC terminal AC is generally a terminal connected to a device including an inductance component such as a motor.

  Each of the arms 5a and 5b is composed of switching elements 10a and 10b made of self-extinguishing semiconductor elements such as IGBTs and power MOSFETs, and free-wheeling diodes 11a and 11b connected in reverse parallel thereto. . The gates of the switching elements 10a and 10b are provided with gate drivers 7a and 7b for driving the switching elements 10a and 10b on / off, and the gate drivers 7a and 7b include the switching elements 10a and 10b. A gate control signal generation circuit 8 that outputs a gate control signal for on / off control is connected.

  In addition, current detection devices 1a and 1b are provided for the respective arms 5a and 5b individually. Each of the current detection devices 1a and 1b has the same configuration, and includes a Rogowski coil 2, a switch 3, a reset circuit 4, and an integration circuit 6.

  The Rogowski coil 2 detects a change in magnetic field strength proportional to the current flowing through the arms 5a and 5b. Therefore, if the current flowing through the switching element 10a of the P-side arm 5a or the diode 11a connected in antiparallel is Ip, and the current flowing through the switching element 10b of the N-side arm 5b or the diode 11b connected in antiparallel is In, The Rogowski coil 2 is arranged so as to surround the arms 5a and 5b through which the currents Ip and In flow.

  The integration circuit 6 is configured by combining an operational amplifier Amp, capacitors Ca, Cb, and C2, and resistors R1 to R3, Ra, and Rb. Then, the electromotive force Vin corresponding to the current value applied from the Rogowski coil 2 to the input terminal in is integrated in the integration circuit 6 and output from the output terminal out as the detection voltage Vout.

  The reset circuit 4 predicts a zero current period in which the currents Ip and In flowing through the arms 5a and 5b are zero, and based on the prediction result, the capacitors Ca, Cb and C2 constituting the integration circuit 6 in the zero current period. A reset signal for discharging the accumulated charge is output. The reset circuit 4 includes a zero current prediction circuit 41 that predicts a zero current period in which the current flowing through the arms 5a and 5b is zero based on the gate control signal output from the gate control signal generation circuit 8, and the prediction result. And a reset signal generating circuit 42 for outputting the reset signal based on the above.

  In this case, the zero current prediction circuit 41 includes, for example, a trigger circuit that outputs a trigger signal according to the gate control signal output from the gate control signal generation circuit 8 and a current that flows the trigger signal from the trigger circuit to each arm. A delay circuit such as a filter (none of which is shown) that delays until a zero current period in which the current is zero can be combined. The reset signal generation circuit 42 outputs a reset signal in accordance with the delayed trigger signal. The operation of the reset circuit 4 will be described in detail later.

  The switch 3 is electrically connected to both ends of the capacitors Ca, Cb, C2 constituting the integrating circuit 6 in parallel. When the reset signal from the reset circuit 4 is input to the switch 3, the contacts connected to the capacitors Ca, Cb, and C 2 are closed, whereby both ends of the capacitors Ca, Cb, and C 2 pass through the switch 3. By short-circuiting, the accumulated charge is prevented from being discharged and the zero point of the integrated value is prevented from shifting.

  Here, in the two-level inverter having the configuration shown in FIG. 1, when the gate control signal is not output from the gate control signal generation circuit 8, the switching elements 10a and 10b of both the P-side and N-side arms 5a and 5b are both Although no current flows, if one of the arms, for example, the switching element 10a of the P-side arm 5a is turned on by a gate control signal, the device passes through the P-side arm 5a and includes an inductance component (L) from the AC terminal AC. Through the switching element of the N-side arm of the other phase through the current, and a current flows in a loop passing through the N side of the DC power supply 9. In this case, the value of the current flowing through the switching element 10a of the P-side arm 5a depends on the inductance component (L) of the device.

  Then, when the switching element 10a of the P-side arm 5a is turned off by the gate control signal, the switching element 10b of the N-side arm 5b is turned on with the dead time interposed therebetween. Not flowing. The reason is that when the switching element 10a of the P-side arm 5a is turned off, the current flowing in the device including the inductance component (L) flows back through the diode 11b of the N-side arm 5b.

  When the switching elements 10a and 10b of both arms 5a and 5b are repeatedly turned on / off as described above, the switching elements 10a of the P-side arm 5a and the N-side arm 5b, depending on the direction of the current Iac flowing through the AC terminal AC. Which of the currents 10b is determined is determined. That is, when the current Iac is in the same direction as the arrow shown in FIG. 1, the current flows to the switching element 10a of the P-side arm 5a, and when the current Iac is the opposite direction to the arrow shown in FIG. Flows.

  Next, a timing operation when the reset circuit 4 outputs a reset signal will be described with reference to FIG.

  FIG. 3 shows a state in which a positive-side voltage is generated when a sinusoidal phase voltage is output from the AC terminal AC by the two-level inverter (referred to herein as a positive-polarity mode). In the sex mode, the switching element 10a of the P-side arm 5a is turned on / off, and the current Iac flows in the arrow direction shown in FIG. Even in this positive polarity mode, the current flows back through the diode 11b of the N-side arm 5b while the switching element 10b of the N-side arm 5b is turned on / off and the switching element 10a of the P-side arm 5a is turned off. To do.

  In this positive polarity mode, in a state where the switching element 10a of the P-side arm 5a is turned off and current is flowing back through the diode 11b of the N-side arm 5b, the gate is next to the switching element 10a of the P-side arm 5a. When the control signal is input and the switching element 10a is turned on, after the turn-on delay time, the switching element 10a is turned on, and the diode 11b of the N-side arm 5b is recovered and turned off. Thereafter, when the gate control signal for the switching element 10a of the P-side arm 5a is turned off, the switching element 10a is turned off after the turn-off delay time, and a current starts to flow through the diode 11b of the N-side arm 5b.

  Therefore, now, when focusing on the N-side arm 5b, after the gate control signal for the switching element 10b is turned off, the switching associated with the dead time Td and the turning on of the gate control signal for the switching element 10a of the P-side arm 5a. During a period Tn from the time when the turn-on delay time To of the element 10a and the recovery period Tr of the diode 11b of the N-side arm 5b elapse until the time when the gate control signal for the switching element 10a of the P-side arm 5a is turned off. Since no current In flows through the N-side arm 5b, this period is defined as a zero current period Tn.

  Therefore, regarding the N-side arm 5b, if the reset signal generated by the reset circuit 4 is given to the switch 3 during the zero-current period Tn in which the current In flowing through the N-side arm 5b is zero (In = 0), each capacitor The accumulated charges of Ca, Cb, and C2 can be reliably discharged (reset).

  On the other hand, when attention is paid to the P-side arm 5a, after the gate control signal for the switching element 10a is turned off, the switching element 10b associated with the dead time Td and the turning on of the gate control signal for the switching element 10b of the N-side arm 5b. , And the recovery period of the diode 11a of the P-side arm 5a (here, the turn-on delay time of the switching element 10b and the recovery period of the diode 11a are collectively indicated by the symbol Tg), then N Since the current Ip does not flow through the P-side arm 5a during the period Tp until the gate control signal for the switching element 10b of the side arm 5b is turned off, this period is defined as a zero current period Tp.

  Therefore, regarding the P-side arm 5a, if the reset signal generated by the reset circuit 4 is given to the switch 3 during the zero current period Tp in which the current Ip flowing through the P-side arm 5a is zero (Ip = 0), each capacitor The accumulated charges of Ca, Cb, and C2 can be reliably discharged (reset).

  Thus, although the substantial zero current periods Tn and Tp are longer in the P-side arm 5a than in the N-side arm 5b, the switching element 10b of the N-side arm 5b is turned on / off even in the positive polarity mode. The timing of resetting each integration circuit 6 of the P-side arm 5a is the same as the timing of resetting each integration circuit 6 of the N-side arm 5b, and the current detection is performed in both arms 5a and 5b. If we focus on one of the target arms and call the other arm the opposite arm, the output timing of the reset signal will be summarized for both the P-side arm 5a and the N-side arm 5b. It can be expressed as follows.

  That is, the reset circuit 4 has a dead time after turning off the gate control signal for the switching element of its own arm as a current detection target, a turn-on delay time of the switching element when the gate control signal is turned on for the switching element of the reverse arm, and From the time when the recovery time of the diode of the self arm has elapsed, the time after which the gate control signal for the switching element of the reverse arm is turned off again, that is, the time before the dead time from the time when the gate control signal for the switching element of the self arm is turned on. The period up to this point is predicted to be the zero current period of its own arm, and a reset signal is output during the zero current period. As a result, the integration circuit 6 can be reset to reliably correct the detection signal deviation.

  In this case, the recovery time of the diode of its own arm varies depending on the current value flowing back to the diode, the voltage applied to the diode, and the like, so it is desirable to set the recovery time to the maximum.

  Further, FIG. 3 shows the case of the positive polarity mode in which the positive side voltage is generated when the sinusoidal phase voltage is output from the AC terminal AC. 1 is generated (here, referred to as negative polarity mode), the switching element 10b of the N-side arm 5b is turned on / off, and the current Iac flows through the AC terminal AC in the direction opposite to the arrow direction shown in FIG. . Even in this case, the operating principle is the same except that the operating states of the P-side arm 5a and the N-side arm 5b are switched. Accordingly, even in this negative polarity mode, the output timing of the reset signal output from the reset circuit 4 can be expressed generally as in the positive polarity mode.

  As described above, in the first embodiment, the output timing of the reset signal output from the reset circuit 4 is sufficiently considered, and the reset signal is output during the zero current periods Tn and Tp in which no current flows through the arms 5a and 5b. Therefore, even when the switching elements 10a and 10b of the arms 5a and 5b are continuously turned on / off, the integration circuit 6 can be reset more reliably than in the past, and always accurately. It is possible to detect the current value flowing through each arm 5a, 5b. In addition, since the reset circuit 4 uses only the gate control signal applied to the gate driver of its own arm, it is not necessary to electrically insulate from the gate driver of the reverse arm, and the circuit can be simplified and downsized.

Embodiment 2. FIG.
FIG. 4 is a timing chart for explaining operations of the power conversion device and the current detection device according to Embodiment 2 of the present invention. FIG. 4 shows a case where the power conversion device is a two-level inverter and is in the positive polarity mode, as in the case of the first embodiment shown in FIG.

  The ON time during switching of the switching elements 10a and 10b of the P-side and N-side arms 5a and 5b is characterized in that it is long and short when PWM control is performed. It has been converted to AC. Therefore, when the switching elements 10a and 10b are switched by the gate control signal, the minimum on-time (hereinafter simply referred to as the minimum on-time) Tmin is set within the on-time of the gate control signal in all operation modes. Therefore, in the second embodiment, the output timing of the reset signal from the reset circuit 4 is determined in consideration of the minimum on-time Tmin.

  For example, in FIG. 4, when focusing on the N-side arm 5b, if the minimum ON time Tmin of the gate control signal applied to the switching element 10a of the P-side arm 5a is known in advance, the gate of the N-side arm 5b with respect to the switching element 10b After the control signal is turned off, the dead time Td, the turn-on delay time To of the switching element 10a when the gate control signal is turned on for the switching element 10a of the P-side arm 5a, and the recovery period of the diode 11b of the N-side arm 5b During the period Tn from the time when Tr elapses until the time when the minimum on time Tmin of the gate control signal for the switching element 10a of the P-side arm 5a elapses, the on-time of the gate control signal is changed by PWM control. However, the current In always flows through the N-side arm 5b. It has zero current period Tn exists.

  Therefore, if the reset signal generated by the reset circuit 4 regarding the N-side arm 5b is given to the switch 3 during the zero-current period Tn in which the current In flowing through the N-side arm 5b is zero (In = 0), each capacitor Ca , Cb, C2 can be reliably discharged (reset).

  The above explanation is when focusing on the N-side arm 5b, but the operating principle is the same when focusing on the P-side arm 5a. Furthermore, although the case of the positive polarity mode has been described here, the operation principle is the same even in the case of the negative polarity mode. Therefore, in the case of the second embodiment, the output timing of the reset signal from the reset circuit 4 can be generally expressed as follows.

  That is, the reset circuit 4 has a dead time after turning off the gate control signal for the switching element of its own arm as a current detection target, a turn-on delay time of the switching element when the gate control signal is turned on for the switching element of the reverse arm, and From the time when the recovery time of the diode of the own arm has elapsed, the dead time from the time when the minimum on-time of the gate control signal for the switching element of the reverse arm elapses, that is, the time when the gate control signal for the switching element of the own arm is turned on A period up to a time point before the time is predicted to be a zero current period of the self arm, and a reset signal is output during the zero current period.

  As described above, if the minimum on-time Tmin in all the operation modes is known in advance, if the reset signal is output from the reset circuit 4 during the zero current period, the capacitor constituting the integration circuit 6 is always produced during the zero current period. Accumulated charges of Ca, Cb, and C2 can be discharged, and an accurate current value can be detected.

  Since the recovery time of the diode of its own arm varies depending on the current value flowing back to the diode, the voltage applied to the diode, etc., as in the first embodiment, it is desirable to set the recovery time to the maximum recovery time.

  As described above, in the second embodiment, since the reset signal is output in consideration of the minimum on-time Tmin of the gate control signal, the switching elements 10a and 10b of the arms 5a and 5b are continuously turned on / off. Even in this case, the integration circuit 6 can be reset more reliably than in the first embodiment. Other functions and effects are the same as those in the first embodiment.

Embodiment 3 FIG.
5 is a block diagram of a current detection device according to Embodiment 3 of the present invention. In FIG. 5, only one current detection device is extracted from the current detection devices provided corresponding to each arm individually.

  In the configuration of FIG. 1, for example, when the switching element 10a of one P-side arm 5a is turned on and the switching element 10b of the N-side arm 5b is short-circuited for some reason, the current flows to the switching elements 10a and 10b. Flows up to saturation current. When overcurrent protection or short circuit protection cannot be performed in a short time, the voltage applied to each switching element 10a, 10b rises to the power supply voltage, and eventually the switching elements 10a, 10b are destroyed by heat generation.

  Therefore, in order to prevent the occurrence of such a problem, in the third embodiment, as shown in FIG. 5, a current detection device 1 provided for an arm 5 (referred to as its own arm here) that is a current detection target. , An overcurrent protection circuit 13 is provided for detecting the occurrence of overcurrent based on the current detection value by the integration circuit 6 and preventing the overcurrent from continuously flowing through the own arm 5.

  That is, the overcurrent protection circuit 13 of the current detection device according to the third embodiment compares the output voltage Vout of the integration circuit 6 with the reference voltage Voc, and the output voltage Vout of the integration circuit 6 is larger than the reference voltage Voc. The comparator 14 outputs a high level error signal FO, the knot circuit 15 for inverting the level of the error signal FO, and the output of the knot circuit 15 and the gate control signal from the gate control signal generation circuit 8 are input together. And an output side of the AND gate 16 is connected to the gate driver 7.

  Here, the operation of the overcurrent protection circuit 13 will be described with reference to FIG. 6, taking as an example a case where overcurrent flows through the own arm 5.

  The overcurrent protection circuit 13 inputs the output voltage Vout of the integrating circuit 6 and the reference voltage Voc to the comparator 14 and compares the two voltages Vout and Voc. When an overcurrent flows through the own arm 5, the output voltage Vout of the integrating circuit 6 exceeds the reference voltage Voc, so that a high level error signal FO is output. This error signal FO is used as the gate control signal generation circuit 8. And the level is inverted by the knot circuit 15 and applied to the AND gate 16, so that the AND gate 16 is closed and the gate control signal from the gate control signal generating circuit 8 is prevented from being applied to the gate driver 7. Thereby, it is protected that the switching element 10 is turned off and an overcurrent flows.

  When the overcurrent protection circuit 13 detects an overcurrent and prevents the gate driver 7 from applying a gate control signal, if the switching element 10 is turned off while maintaining a normal gate resistance, the current flowing through the switching element 10 There is a possibility that the change becomes large, and a large surge voltage is applied to the switching element 10 at the time of shutoff, resulting in destruction of the element. Therefore, when switching element 10 is turned off when overcurrent is detected, it is desirable to attach a circuit for switching the gate resistance to a value larger than a normal value.

  Depending on the overcurrent protection level, a filter is provided on the output side of the integration circuit 6 so that the overcurrent protection circuit 13 does not perform a protective operation accidentally due to the peak current generated when the diode 11 recovers. While this filter prevents the output voltage Vout of the integration circuit 6 from abruptly changing, the malfunction is prevented. On the other hand, when short-circuit protection of overcurrent is performed, integration is performed without a filter in order to increase protection accuracy. It is desirable to take measures such that the output voltage Vout of the circuit 6 changes abruptly.

  Also in this third embodiment, as in the first and second embodiments, the reset circuit 4 uses only the gate control signal applied to the gate driver 7 of its own arm 5, and the gates of the other arms. Since it is independent of the driver, the circuit can be simplified. With respect to the overcurrent protection circuit, the reset circuit 4 after overcurrent protection is closed in its own arm 5 so that the overcurrent protection circuit can be reliably reset.

  That is, when the reset signal is generated using the gate control signal applied to the gate driver of the reverse arm, the reset signal is output from the reset circuit 4 after the gate control signal of the reverse arm is switched from OFF to ON. When both arms are turned on and an arm short circuit occurs, the detected current value is reset, and accurate current detection cannot be performed. Therefore, there is a possibility that overcurrent protection is delayed and the switching element 10 is destroyed. On the other hand, in the third embodiment, the overcurrent protection circuit 13 can reset the integration circuit 6 more reliably by using only the gate control signal for the own arm 5.

  Further, when the overcurrent protection circuit 13 is operated, if the switching element 10 is turned off by inserting a larger gate resistance than usual in order to prevent the switching element 10 from being destroyed as described above, the turn-off delay time of the switching element 10 Etc. become longer. Therefore, if a reset signal is output from the reset circuit 4 at normal timing, the reset signal may be input to the integration circuit 6 before the current flowing through the arm 5 becomes zero. Therefore, in order to avoid this problem, it is necessary to change the output timing of the reset signal when the overcurrent protection circuit 13 is operated.

  For example, as shown in FIG. 6, if the output timing of the reset signal in the normal case is at the position indicated by the broken line in the figure, the output timing of the reset signal is indicated by the solid line when the overcurrent protection circuit 13 is operated. Delay to the position indicated by. For this purpose, for example, in the zero current prediction circuit 41 in the reset circuit 4 shown in FIG. 2, the filter constant of the delay circuit constituting this is changed according to the operation of the overcurrent protection circuit 13. be able to.

  As shown in FIG. 7, when an overcurrent is detected by the overcurrent protection circuit 13, an error signal FO is input to the gate control signal generation circuit 8, and information on the overcurrent is fed back to the gate control. . The output of the error signal FO is continued for a certain period Ts until the system is restored even after the overcurrent is cut off, and the switching element 10 is set not to be turned on for a new gate control signal. Has been.

Therefore, in the state where the overcurrent is detected and the error signal FO is output, no current flows through the switching element 10 for a certain period Ts until the system is restored. Therefore, as shown in FIG. 8, the reset circuit 4 takes in the error signal FO from the comparator 14 and generates a reset signal for a period of several μsec immediately before completion of the period Ts so as to match the period Ts. If the capacitors Ca, Cb, and C2 of the circuit 6 are discharged (reset), the current can be detected with higher accuracy.

Embodiment 4 FIG.
9 is a perspective view showing an external appearance of a semiconductor module having a current detection device with an overcurrent protection circuit according to Embodiment 4 of the present invention, and FIG. 10 is a cross-sectional view taken along line AA of FIG. 5 and components corresponding to or corresponding to those of the third embodiment shown in FIG. In the fourth embodiment, a 1 in 1 high voltage semiconductor module that constitutes a single arm is shown as an example. However, even a 2 in 1 that constitutes a pair of arms or a 6 in 1 semiconductor module that constitutes six arms. The invention can be applied.

  The structure of the semiconductor module according to the fourth embodiment will be described with reference to FIGS.

  In the semiconductor module according to the fourth embodiment, a metal plate 25 that is a metal radiator that radiates heat is attached to the lower part of the module case 20 so that the inside is formed hollow. An insulating circuit board 28 is provided. A wiring pattern made of a metal foil is formed on the surface of the insulating circuit board 28 opposite to the surface bonded to the metal plate 25. On the wiring pattern, the switching element 10 and the diode 11 are made of solder or the like. Connected by a bonding material. On the wiring pattern, the emitter surface of the switching element 10 and the emitter surface of the wiring pattern, or the anode surface of the diode 11 and the emitter surface of the wiring pattern are electrically connected through a wire bond 24. .

  Further, one end of the collector electrode 22 and the emitter electrode 23 is connected on the wiring pattern of the insulating circuit board 28, and the other end of the electrodes 22 and 23 is exposed on the upper surface of the module case 20. The power converter is assembled by connecting external bus bars, capacitors, and the like on the exposed surfaces.

  In the switching element 10, the gate / emitter wiring is connected to the wiring pattern of the control drive substrate 30 using wire bonds 24, and the control drive substrate 30 is connected to each gate of the control substrate 29 via the control terminal 31. • Connected to the emitter pattern. In order to maintain insulation inside the module, an insulating gel 21 is filled below the control board 29 in the space surrounded by the module case 20 and the metal plate 25.

  In the module case 20, the Rogowski coil 2 is inserted into the emitter electrode 23 located above the control board 29. Further, the output of the Rogowski coil 2 is connected to the control board 29.

  Although not shown, the control circuit 29 has the integration circuit 6 and the overcurrent protection circuit 13 mounted and wired together with the gate driver 7. Further, a connector 32 is provided outside the module case 20 and is connected to the control board 29. A drive power supply to the gate driver 7 is connected via the connector 32. In addition, a gate control signal from an external gate control signal generation circuit 8 (not shown) is input to the control board 29 via the connector 32, or an error signal from the overcurrent protection circuit 13 is input to the gate control signal generation circuit 8. Or output.

  Conventionally, a semiconductor module with an overcurrent protection function has a sense resistor for current detection attached to a switching element, and many of the currents flowing through the switching element are detected using this sense resistor. However, such a semiconductor module has a drawback that the cost of the switching element is increased. On the other hand, since the semiconductor module of the fourth embodiment detects the current flowing through the switching element 10 using the Rogowski coil 2, it is possible to detect the current with high accuracy and overcurrent protection at a low cost.

  In particular, as shown in the third embodiment, if the reset circuit 4 and the overcurrent protection circuit 13 are configured to generate a reset signal and overcurrent protection from the gate control signal for the own arm 5, Since high-voltage insulation is not required, it is possible to further reduce the size of the semiconductor module and simplify the gate driver circuit.

  In each of the above first to fourth embodiments, the semiconductor material of the switching elements 10, 10a, and 10b is not particularly limited, but generally silicon can be used. However, if a wide band gap semiconductor material such as silicon carbide, a gallium nitride-based material, or diamond is used as the semiconductor material, the loss can be reduced while maintaining the effect of the present invention. Efficiency can be improved. In addition, since the withstand voltage is high and the allowable current density is also high, the power converter can be downsized. In addition, wide band gap semiconductor elements have high heat resistance, so they can operate at high temperatures, and the heat sink fins can be downsized and the water cooling section can be air cooled. It becomes possible.

  In addition, since the wide band gap semiconductor material can perform high-speed switching, the switching frequency can be increased. However, as the switching frequency is increased, the capacitors Ca, Cb, and C2 of the integration circuit 6 are discharged. It becomes more difficult. Even in such a case, if the present invention is applied, the output timing of the reset signal from the reset circuit 4 is set appropriately, so that the capacitors Ca, Cb, and C2 of the integrating circuit 6 can be reliably discharged.

  The present invention is not limited to the respective configurations shown in the first to fourth embodiments, and various modifications can be made without departing from the spirit of the present invention. It is also possible to adopt a configuration in which the first to fourth embodiments are appropriately combined.

1, 1a, 1b Current detector, 2 Rogowski coil, 3 switches,
4 reset circuit, 41 zero current prediction circuit, 42 reset signal generation circuit, 5 arm, 5a P side (positive side) arm, 5b N side (negative side) arm, 6 integration circuit,
7, 7a, 7b gate driver, 8 gate control signal generation circuit,
10, 10a, 10b switching element, 11, 11a, 11b diode,
13 Overcurrent protection circuit.

Claims (8)

A pair of upper and lower positive and negative arms are connected in series, and each of the arms has a current flowing through the arm of the power conversion device including a switching element and a return diode connected in reverse parallel to the switching element. Which detects
Corresponding to each of the arms individually, a Rogowski coil that detects a change in magnetic field strength proportional to the current flowing through the arm , an integration circuit that integrates the detection output of the Rogowski coil, and a current flowing through the arm And a reset circuit that outputs a reset signal for discharging the accumulated charge of the capacitor constituting the integration circuit during the zero current period based on the prediction result. ,
When one of the upper and lower arms is focused on one arm that is a current detection target, and the other arm is referred to as a reverse arm, the reset circuit is connected to the current detection target arm. After turning off the gate control signal for the switching element, from the time when the dead time, the turn-on delay time of the switching element accompanying the turning on of the gate control signal for the switching element of the reverse arm, and the recovery time of the diode of the own arm have passed, The period from the time when the gate control signal for the switching element of the own arm is turned on to the time before the dead time is predicted to be the zero current period of the own arm, and the reset signal is output during the zero current period. A current detection device for a power conversion device. The period for which the reset circuit predicts the zero current period of the self arm is replaced with the period of claim 1, the dead time after the gate control signal for the switching element of the self arm as a current detection target is turned off, The turn-on delay time of the switching element when the gate control signal is turned on for the switching element of the reverse arm and the recovery time of the diode of the self-arm, and then the minimum on time of the gate control signal for the switching element of the reverse arm The current detection device for a power conversion device according to claim 1, wherein the current detection device is a period up to a point in time when elapses. The reset circuit receives the gate control signal applied to the own arm, outputs a trigger signal in response to the gate control signal, and delays the trigger signal until the zero current period in the own arm. A current detection device for a power converter according to claim 1, further comprising a delay circuit that outputs the reset signal. The switching element, a current detection system for a power conversion device according to any one of claims 1 to 3, which is formed by a wide band gap semiconductor. The current detection device for a power converter according to claim 4, wherein the wide band gap semiconductor is silicon carbide, a gallium nitride-based material, or diamond. The output voltage of the integration circuit is compared with a reference voltage, and if the output voltage of the integration circuit is higher than the reference voltage, it is determined that an overcurrent has occurred and output of the gate control signal to the switching element is blocked. and a current detecting system for a power conversion device according to any one of claims 1 to 5 which comprises an overcurrent protection circuit that turns off the switching element. When the overcurrent protection circuit outputs an error signal that prevents the gate control signal from being output to the switching element, the reset circuit outputs a reset signal immediately before completion of the output of the error signal. The current detection device for a power converter according to claim 6 , wherein the output timing is switched. The switching element and the diode constituting the power conversion device according to claim 6 or 7, and the Rogowski coil and the overcurrent protection circuit constituting the current detection device are integrally assembled. Semiconductor module.

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