JP5867966B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

In a conventional semiconductor device, for example, as in Patent Document 1, a semiconductor chip is fixed to the main surface of an arrangement plate such as a heat sink or a substrate, and the semiconductor chip and connection terminals are electrically connected by wires, and then these arrangement plates are arranged. The main surface, the semiconductor chip and the wire are sealed with a sealing resin (hard resin). Furthermore, in the semiconductor device described in Patent Document 1, a soft resin such as silicone gel and a filling resin (hard resin) are sequentially laminated on the sealing resin. In this semiconductor device, when an excessive current flows through the wire due to a defect of the semiconductor chip or the like and the wire is to be disconnected, the resin is prevented from being ignited to ensure safety. In addition, the soft resin layer is prevented from being scattered outward due to an impact generated when the wire is disconnected.
Conventionally, the periphery (side part) of the semiconductor chip, connection terminals, and wires is enclosed in a frame and sealed in the frame so that the semiconductor device having the above-described resin laminated structure can be easily manufactured. It is also considered that a resin, a soft resin, and a filling resin are sequentially poured and molded.

JP 2012-9759 A

However, in the above-described conventional semiconductor device, the soft resin layer expands due to an impact generated when the wire is disconnected, and therefore the filling resin may float in the resin lamination direction with respect to the sealing resin or the soft resin, and may be peeled off. As a result, a gap may be generated between the filling resin and the soft resin or the frame. In this case, there is a possibility that air or moisture may enter the soft resin from the gap and cause a discharge at the broken portion of the wire. In other words, in this type of semiconductor device, further safety is desired.
In addition, although the structure which covers the circumference | surroundings (side part) of sealing resin and soft resin with filling resin is described in patent document 1, the interface of the side part of sealing resin and filling resin is the lamination direction of resin. It extends to. For this reason, shear stress is applied to the interface between the sealing resin and the filling resin due to the impact described above, and the filling resin is peeled off from the sealing resin, and there is still a gap between the filling resin and the soft resin or the frame. May occur.

  The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a semiconductor device capable of improving the safety by suppressing the peeling of the filling resin when the wire is disconnected.

  In order to solve this problem, the semiconductor device of the present invention is a semiconductor device having a configuration in which the semiconductor chip is fixed to the main surface of the arrangement plate and the semiconductor chip and the connection terminal are electrically connected by a wire, A frame body that protrudes from the main surface of the arrangement plate and surrounds the semiconductor chip and the wire, and a sealing resin layer and a soft resin layer that are sequentially stacked from the main surface of the arrangement plate in the frame body And a filling resin layer, wherein the sealing resin layer seals the main surface of the arrangement plate, the semiconductor chip, the connection terminal and the wire, and the soft resin layer has fluidity and the It is made of a soft resin material softer than the sealing resin layer and the filling resin layer, and is further formed in a partial region including at least the upper part of the wire in the upper surface of the sealing resin layer orthogonal to the stacking direction. Tree Layer, characterized in that is in close contact with the peripheral region surrounding said partial area of the upper surface of the sealing resin layer.

According to the semiconductor device of the present invention, the interface between the sealing resin layer and the filling resin layer that are in close contact with each other is orthogonal to the laminating direction of the resin layer. Even if the resin layer is about to expand, it is possible to prevent the filled resin layer from peeling off from the sealing resin layer. That is, it can suppress that a filling resin layer floats up, and can suppress that a clearance gap produces between a filling resin layer, a soft resin layer, and a frame.
In addition, when molding the sealing resin layer, the soft resin layer, and the filling resin layer, it is only necessary to pour each resin material that becomes the sealing resin layer, the soft resin layer, and the filling resin layer into the frame in order, A semiconductor device can be easily manufactured.

  And in the said semiconductor device, the cylindrical sub-frame which protrudes from the upper surface of the said sealing resin layer and surrounds the said wire at the position spaced apart inside the said frame is distribute | arranged, The said soft resin It is preferable that the layer is filled only inside the subframe.

  With this configuration, when the soft resin layer is molded, it is easy to overspread the upper surface of the sealing resin layer simply by pouring the resin material (soft resin material) that becomes the soft resin layer inside the subframe. Can be prevented. Therefore, a sufficient adhesion area of the filling resin layer with respect to the upper surface of the sealing resin layer can be ensured, and the semiconductor device can be manufactured more easily. This effect is particularly effective when the soft resin material has low viscosity and the soft resin material has low wettability with respect to the upper surface of the sealing resin layer.

  Furthermore, in the semiconductor device, a lower end portion of the sub-frame body along the stacking direction is embedded in the sealing resin layer, and an upper end portion of the sub-frame body is embedded in the filling resin layer. It is good to be.

  In this configuration, the both end portions of the sub-frame body are embedded in the sealing resin layer and the filling resin layer, respectively, so that the sealing resin layer and the filling resin layer can be firmly fixed. Therefore, even if the soft resin layer is about to expand due to an impact when the wire is broken, it is possible to more effectively suppress the filling resin layer from being peeled off from the sealing resin layer.

  Further, in the semiconductor device, a protruding portion is formed on the upper end portion of the sub-frame body so as to protrude radially outward of the sub-frame body and to be spaced from the upper surface of the sealing resin layer. It is good to be.

  In this configuration, since the filling resin layer enters between the upper surface of the sealing resin layer and the protrusion of the sub-frame, the filling resin layer engages with the protrusion. Can be fixed more firmly. Therefore, it can prevent reliably that a filling resin layer peels from a sealing resin layer.

  Furthermore, in the semiconductor device, it is preferable that a passage communicating the inner space and the outer space of the sub-frame body is formed between the main surface of the arrangement plate and the lower end portion of the sub-frame body.

  In this configuration, the sealing resin material flows into both the inner space and the outer space simply by pouring the resin material (sealing resin material) to be the sealing resin layer into only the inner space or the outer space of the sub-frame. It becomes possible to mold the sealing resin layer in a short time.

  In the semiconductor device, the soft resin material may be a gel-like resin material having viscosity or wettability that remains in the partial region when poured into the upper surface of the sealing resin layer.

  In this configuration, even if the soft resin material is poured into the upper surface of the sealing resin layer, the soft resin material does not excessively wet and spread on the upper surface of the sealing resin layer. For this reason, the soft resin layer formed by pouring the soft resin material into the upper surface of the sealing resin layer has a shape that is piled up in a part of the upper surface of the sealing resin layer. Accordingly, the peripheral region on the upper surface of the sealing resin layer to be in close contact with the filling resin layer can be easily ensured without providing a subframe.

  According to this invention, it can suppress that a filling resin layer peels from a sealing resin layer, and can suppress that a clearance gap produces between a filling resin layer, a soft resin layer, and a frame. That is, the safety of the semiconductor device can be improved.

1 is a schematic cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a top view showing a state before pouring resin into a frame in the semiconductor device of FIG. 1. (A) is AA arrow sectional drawing of FIG. 2, (b) is BB arrow sectional drawing of FIG. It is a schematic sectional drawing which shows the semiconductor device which concerns on 2nd embodiment of this invention. FIG. 5 is a top view showing a state before the resin is poured into the frame in the semiconductor device of FIG. 4.

[First embodiment]
The first embodiment of the present invention will be described below with reference to FIGS.
As shown in FIGS. 1 and 2, the semiconductor device 1 is configured by fixing the semiconductor chip 3 to the main surface of the arrangement plate 2 and then electrically connecting the semiconductor chip 3 and the connection terminals 4 with wires 5. . In the present embodiment, the arrangement plate 2 includes a substrate 11 and a plate-shaped heat sink 12 fixed to the upper surface 11 a of the substrate 11. Further, the upper surface 11 a of the substrate 11 and the upper surface 12 a of the heat sink constitute the main surface of the arrangement plate 2.

The substrate 11 is an aluminum substrate with high heat dissipation, for example, and an electrical wiring pattern (not shown) is formed on the upper surface 11a and the like. The connection terminal 4 is formed on the upper surface 11 a of the substrate 11 and is electrically connected to the wiring pattern of the substrate 11. Furthermore, pin-shaped external terminals 6 electrically connected to the wiring pattern are also formed on the upper surface 11a of the substrate 11 of the present embodiment.
The heat sink 12 is formed in a plate shape with a material having high heat dissipation such as copper (Cu), tungsten, molybdenum, or the like, or is formed by performing Ni plating in addition to this, for example. The heat sink 12 is fixed to the upper surface 11a of the substrate 11 via a bonding agent (not shown).

The semiconductor chip 3 is fixed to the upper surface 12a of the heat sink 12 with a bonding agent (not shown) such as solder having high thermal conductivity. Therefore, in the semiconductor device 1 of the present embodiment, the heat generated in the semiconductor chip 3 can be efficiently radiated from the heat sink 12 to the substrate 11, and the temperature rise of the semiconductor chip 3 can be suppressed.
Both ends of the wire 5 are joined to the semiconductor chip 3 and the connection terminal 4, and are formed in an arch shape that swells upward between the semiconductor chip 3 and the connection terminal 4.
In the illustrated example (FIG. 2), a plurality of units each including the heat sink 12, the semiconductor chip 3, the connection terminals 4, and the wires 5 are provided on the substrate 11, but only one set is provided, for example. Also good.

The semiconductor device 1 includes a frame 7 that is disposed so as to protrude from the upper surface 11 a of the substrate 11 and surrounds the semiconductor chip 3 and the wires 5. In the present embodiment, the frame body 7 is formed so as to extend upward from the periphery of the upper surface 11 a of the substrate 11, and also surrounds the connection terminals 4 and the external terminals 6 formed on the substrate 11. That is, in this embodiment, a case that opens upward is constituted by the substrate 11 and the frame body 7.
Further, the frame body 7 of the present embodiment partitions its internal space into a first space S1 in which the semiconductor chip 3, the connection terminals 4 and the wires 5 are arranged, and a second space S2 in which the external terminals 6 are arranged. It has the partition wall part 13 to do. However, there is a gap between the upper surface 11a of the substrate 11 and the lower end portion of the partition wall 13 facing the substrate 11, and this gap communicates with the communication port 13A for communicating the two spaces S1, S2 in the frame body 7. It has become.

Furthermore, the semiconductor device 1 includes a sealing resin layer 21, a soft resin layer 22, and a filling resin layer 23 that are sequentially stacked on the upper surface 11 a of the substrate 11 in the frame body 7.
The sealing resin layer 21 is made of, for example, a hard resin material such as an epoxy resin, and seals the upper surface of the substrate 11, the side and upper surfaces 12 a of the heat sink 12, the semiconductor chip 3, the connection terminals 4, and the wires 5. In the present embodiment, the sealing resin layer 21 also seals the base end portion of the external terminal 6 and the communication port 13A. The upper surface 21 a of the sealing resin layer 21 is orthogonal to the stacking direction of the sealing resin layer 21, the soft resin layer 22, and the filling resin layer 23.

The distance from the wire 5 embedded in the sealing resin layer 21 to the upper surface 21a of the sealing resin layer 21 is generated in the sealing resin layer 21 based on the energy (disconnection energy) generated when the wire 5 is disconnected. The crack is set so as to reach the upper surface 21 a of the sealing resin layer 21.
The disconnection energy generated when the wire 5 is disconnected is, for example, heat generated in a local portion of the wire 5 having an electrical resistance larger than that of other portions when an overcurrent flows through the wire 5. The portion becomes a disconnection portion of the wire 5. Moreover, as a local part of the wire 5 where electric resistance becomes large, the part where a diameter dimension is small compared with the other part of the wire 5, for example, and the part in which defects, such as a crack among the wires 5, have arisen are mentioned. In addition to the diameters and defects of the wires 5, for example, the composition of the wires 5 itself is not uniform, so that the electrical resistance of a local portion of the wire 5 may be larger than that of other portions.

The soft resin layer 22 is made of a soft resin material that has fluidity and is softer than the hard resin material that forms the sealing resin layer 21. The soft resin layer 22 of the present embodiment is made of a gel-like resin material such as silicone resin (for example, KE-1065 (trade name) manufactured by Shin-Etsu Chemical Co., Ltd.).
The fact that the soft resin layer 22 has fluidity does not always mean that it has fluidity, and it is sufficient that it has fluidity at least when the wire 5 is disconnected. For example, gel-like resin materials such as silicone resins themselves do not have fluidity unless they are subjected to an external force exceeding a predetermined value, but are subdivided into fine fragments based on the disconnection energy generated when the wire 5 is disconnected. For example, it has fluidity.
The soft resin layer 22 is formed in a partial region including the upper side of the wire 5 in the upper surface 21 a of the sealing resin layer 21. In the present embodiment, the semiconductor chip 3 and the connection terminal 4 are also included in the partial area.

  Like the sealing resin layer 21, the filling resin layer 23 is made of a hard resin material such as an epoxy resin that is harder than the soft resin material forming the soft resin layer 22. The filling resin layer 23 is also laminated on the soft resin layer 22, but also closely adheres to a peripheral region surrounding a partial region where the soft resin layer 22 is laminated on the upper surface 21 a of the sealing resin layer 21. ing.

In the present embodiment, the upper surface 21 a of the sealing resin layer 21 is partitioned into a partial region and a peripheral region by the cylindrical sub-frame 8. In other words, in this embodiment, the formation region of the soft resin layer 22 on the upper surface 21 a of the sealing resin layer 21 is limited by the sub-frame 8.
The sub-frame 8 protrudes from the upper surface 21a of the sealing resin layer 21 at a position spaced from the inner side of the frame 7, and the wire 5 and the semiconductor chip 3 are connected to the upper surface 21a of the sealing resin layer 21. It is arranged so as to surround a partial region located above the terminal 4. In the present embodiment, the sub-frame 8 collectively surrounds a plurality of sets of units including the heat sink 12, the semiconductor chip 3, the connection terminals 4, and the wires 5. . That is, a plurality of partial regions may be formed on the upper surface 21 a of the sealing resin layer 21.

Further, the lower end portion of the sub-frame 8 along the stacking direction of the sealing resin layer 21, the soft resin layer 22 and the filling resin layer 23 is embedded in the sealing resin layer 21. Further, the lower end portion of the sub-frame 8 is positioned with a space between the upper surface 11 a of the substrate 11. Thus, a passage 8 </ b> A that connects the inner space and the outer space of the sub-frame 8 is formed between the upper surface 11 a of the substrate 11 and the lower end portion of the sub-frame 8. The soft resin layer 22 described above is filled only inside the sub-frame 8 arranged in this way.
In the present embodiment, since the upper surface 22a of the soft resin layer 22 filled inside the sub-frame 8 is positioned lower than the upper end of the sub-frame 8, the filled resin layer 23 is also subframe. It is inside the body 8. Thereby, the upper end portion of the sub-frame 8 is embedded in the filling resin layer 23.

  In addition, a protrusion 14 that protrudes radially outward of the sub-frame 8 is formed at the upper end of the sub-frame 8. The protruding portion 14 is disposed with a space between the upper surface 21 a of the sealing resin layer 21. A filling resin layer 23 enters between the protrusion 14 and the upper surface 21 a of the sealing resin layer 21. Further, the protrusion 14 is embedded in the filling resin layer 23. Thereby, the filling resin layer 23 is engaged with the protrusion 14. In the illustrated example, the protrusions 14 are formed in the entire circumferential direction of the sub-frame 8, that is, formed in an annular shape. However, for example, a plurality of projections 14 may be arranged at intervals in the circumferential direction. For example, only one may be formed in a part in the circumferential direction.

  The sub-frame body 8 configured and arranged as described above may be formed integrally with the frame body 7, for example, but is formed separately from the frame body 7 in the present embodiment. For this reason, as shown in FIGS. 2 and 3, the sub-frame 8 is in a state before each resin material that becomes the sealing resin layer 21, the soft resin layer 22, and the filling resin layer 23 is poured into the frame body 7. It is necessary to be arranged at a position spaced from the upper surface 11a of the substrate 11 so that the inner space and the outer space of the sub-frame 8 are communicated by the passage 8A.

  In view of this, in the frame body 7 of the present embodiment, support protrusions 15 for supporting the sub-frame body 8 at a position spaced upward from the upper surface 11a of the substrate 11 are formed. The support protrusion 15 is formed so as to protrude from the inner peripheral surface of the frame body 7 including the partition wall portion 13 toward the first space S1. The supporting protrusions 15 are arranged on the upper surface 11 a of the substrate 11, and a plurality of supporting protrusions 15 are arranged at intervals in the circumferential direction of the frame body 7.

  In addition, the sub-frame 8 of the present embodiment is formed with a supported protrusion 16 that protrudes radially outward from the outer peripheral surface of the sub-frame 8 in a part of the circumferential direction. The supported protrusion 16 protrudes radially outward from the protrusion 14 described above. The supported protrusion 16 is disposed on an annular protrusion 17 formed on the frame body 7 in a state where the sub-frame body 8 is disposed on the supporting protrusion 15 described above. The annular protrusion 17 protrudes inside the frame body 7 and plays a role of positioning the frame body 7 with respect to the substrate 11 by contacting the upper surface 11 a of the substrate 11.

  The sub-frame 8 is arranged on the support protrusion 15 formed as described above, and the support-use protrusion 16 of the sub-frame 8 is arranged on the annular protrusion 17 of the frame 7 so that the sub-frame 8 The body 8 is supported from the lower end side at a plurality of locations in the circumferential direction. Accordingly, the sub-frame 8 can be disposed at a position spaced upward from the upper surface 11a of the substrate 11, and further, a passage 8A that connects the inner space and the outer space of the sub-frame 8 is formed. Can do.

In the semiconductor device 1 configured as described above, for example, when the wire 5 is disconnected, the sealing resin layer 21 generated based on the disconnection energy of the wire 5 is the same as in the conventional case (Patent Document 1). The gel-like resin material forming the soft resin layer 22 enters the crack with fluidity, and reaches the gap in the broken portion of the wire 5. Thereby, it can prevent that discharge arises in the disconnection part of the wire 5, and can prevent the ignition of the sealing resin layer 21 accompanying discharge etc. reliably. That is, the safety of the semiconductor device 1 can be ensured.
Furthermore, since the soft resin layer 22 is covered with the filling resin layer 23, it is possible to prevent the gel-like resin material from splashing outward when the wire 5 is disconnected.

According to the semiconductor device 1 of the present embodiment, the interface between the sealing resin layer 21 and the filling resin layer 23 that are in close contact with each other is orthogonal to the stacking direction of the resin layers 21 to 23, so Even if the soft resin layer 22 tries to expand due to an impact generated when the wire 5 is disconnected based on the above, it is possible to prevent the filling resin layer 23 from being peeled off from the sealing resin layer 21.
In particular, in the semiconductor device 1 of the present embodiment, the lower end portion and the upper end portion of the sub-frame 8 are embedded in the sealing resin layer 21 and the filling resin layer 23, respectively, so that the sealing resin layer 21 and the filling resin layer 23 can be firmly fixed. Therefore, even when the soft resin layer 22 is about to expand due to an impact when the wire 5 is disconnected, it is possible to more effectively suppress the filling resin layer 23 from peeling from the sealing resin layer 21.

Furthermore, in the semiconductor device 1 of the present embodiment, the filling resin layer 23 enters between the upper surface of the sealing resin layer 21 and the protrusion 14 of the sub-frame 8, so that the filling resin layer 23 is associated with the protrusion 14. Therefore, the sealing resin layer 21 and the filling resin layer 23 can be more firmly fixed. Therefore, it is possible to reliably prevent the filling resin layer 23 from being peeled off from the sealing resin layer 21.
From the above, according to the semiconductor device 1 of the present embodiment, the filling resin layer 23 is prevented from floating from the sealing resin layer 21 when the wire 5 is disconnected, and the filling resin layer 23 and the soft resin layer 22 are prevented. And a gap between the frame body 7 and the frame body 7 can be prevented. Therefore, the safety of the semiconductor device 1 can be improved.

  Further, according to the semiconductor device 1 of the present embodiment, when the sealing resin layer 21, the soft resin layer 22, and the filling resin layer 23 are molded, the sealing resin layer 21, the soft resin layer 22, and the filling resin layer 23 are formed. Therefore, the semiconductor device 1 can be easily manufactured.

Furthermore, according to the semiconductor device 1 of the present embodiment, when the sealing resin layer 21 is molded, the resin material (sealing resin material) to be the sealing resin layer 21 is used as the inner space and the outer side of the sub-frame 8. By flowing into only one of the spaces, it is possible to flow into the other space from the passage 8A formed between the substrate 11 and the sub-frame 8. That is, the sealing resin material can be caused to flow into both the inner space and the outer space only by flowing the sealing resin material once.
Furthermore, according to the semiconductor device 1 of the present embodiment, when the sealing resin layer 21 is formed, the sealing resin material is simply poured into one of the first space S1 and the second space S2, and the other is communicated from the communication port 13A. It can also flow into the space. That is, the base of the heat sink 12, the semiconductor chip 3, the connection terminal 4 and the wire 5 disposed in the first space S1, and the external terminal 6 disposed in the second space S2 can be obtained by flowing the sealing resin material once. The end portion can be sealed with the sealing resin layer 21.
From the above, it becomes possible to mold the sealing resin layer 21 in a short time.

  Further, according to the semiconductor device 1 of the present embodiment, the molding region of the soft resin layer 22 in the upper surface 21 a of the sealing resin layer 21 is restricted by the sub-frame 8. For this reason, when the soft resin layer 22 is molded, the soft resin material is simply poured into the inner side of the sub-frame 8 so that the soft resin material becomes the upper surface of the sealing resin layer 21. It is possible to easily prevent the liquid 21a from being excessively wet and spread. Therefore, the contact area of the filling resin layer 23 with respect to the upper surface 21a of the sealing resin layer 21 can be secured sufficiently and easily, and the semiconductor device 1 can be manufactured more easily. This effect is particularly effective when the soft resin material has low viscosity and the soft resin material has high wettability with respect to the upper surface 21a of the sealing resin layer 21.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIGS.
As shown in FIG. 4, the semiconductor device 31 according to this embodiment is the same as the configuration of the first embodiment, except that the sub-frame 8 is not provided, as compared with the semiconductor device 1 of the first embodiment. It is. In this embodiment, only differences from the first embodiment will be described, and the same components as those in the first embodiment will be denoted by the same reference numerals, and the description thereof will be omitted.

And the soft resin layer 32 of this embodiment consists of soft resin material softer than the hard resin material which has fluidity | liquidity and makes the sealing resin layer 21 similarly to 1st embodiment.
However, the soft resin material forming the soft resin layer 32 of the present embodiment is a partial region including the upper side of the wire 5 in the upper surface 21a of the sealing resin layer 21 when poured into the upper surface 21a of the sealing resin layer 21. It is comprised by the gel-like resin material which has the viscosity or wettability which stays. Examples of such a soft resin material include a thixotropic resin material (for example, KE-1151 (trade name) manufactured by Shin-Etsu Chemical Co., Ltd.).

Therefore, according to the semiconductor device 1 of this embodiment, in addition to the same effects as those of the first embodiment, the following effects are also obtained.
That is, even when the soft resin material is poured into the upper surface 21 a of the sealing resin layer 21 when the soft resin layer 22 is formed, the soft resin material is not excessively wetted and spread on the upper surface 21 a of the sealing resin layer 21. For this reason, the soft resin layer 22 formed on the upper surface 21a of the sealing resin layer 21 has a shape stacked in a mountain shape in a partial region of the upper surface of the sealing resin layer. Therefore, even if the sub-frame 8 is not provided as in the first embodiment, it is possible to easily secure a peripheral region where the filling resin layer 23 is in close contact with the upper surface 21a of the sealing resin layer 21.

Further, for example, as shown in FIG. 5, when a plurality of units each including the heat sink 12, the semiconductor chip 3, the connection terminals 4, and the wires 5 are provided on the substrate 11, It is possible to easily form separate soft resin layers 22 on the wires 5).
Furthermore, the amount of the soft resin material to be used can be reduced as compared with the case where the soft resin layers 22 are molded together on a plurality of sets of units. Moreover, since the contact area between the sealing resin layer 21 and the filling resin layer 23 is increased by reducing the formation region of the soft resin layer 22, the filling resin layer 23 is sealed by the impact when the wire 5 is disconnected. Peeling from the layer 21 can be effectively suppressed.
The soft resin material having the characteristics described in the second embodiment and the formation region of the soft resin layer 22 may be applied to the semiconductor device 1 of the first embodiment described above.

The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.
For example, in the semiconductor device 1 according to the first embodiment, the sub-frame body 8 is disposed on the support protrusion 15 or the annular protrusion 17 of the frame body 7, but may be disposed on the upper surface 11 a of the substrate 11, for example. . In this case, a passage 8A similar to the first embodiment is formed by forming a hole penetrating in the radial direction of the sub-frame 8 at the lower end of the sub-frame 8 embedded in the sealing resin layer 21. It is preferable to do.
Moreover, in 1st embodiment, although the lower end part of the subframe 8 is embed | buried under the sealing resin layer 21, it may be distribute | arranged to the upper surface 21a of the sealing resin layer 21, for example, without being embedded.

Furthermore, in the first embodiment, the upper surface of the soft resin layer 22 filled inside the sub-frame 8 is positioned lower than the upper end of the sub-frame 8, for example, the same as the upper end of the sub-frame 8. It may be located at a height.
In all the embodiments, the arrangement plate 2 includes the heat sink 12. However, the arrangement plate 2 may include only the substrate 11, for example. That is, the semiconductor chip 3 may be directly fixed to the upper surface 11 a of the substrate 11.

DESCRIPTION OF SYMBOLS 1,31 Semiconductor device 2 Arrangement board 3 Semiconductor chip 4 Connection terminal 5 Wire 7 Frame 8 Subframe 8A Passage 11 Substrate 11a Upper surface (main surface)
12 Heat sink 12a Upper surface (main surface)
14 Protrusion 21 Sealing resin layer 21a Upper surface 22, 32 Soft resin layer 23 Filling resin layer

Claims (6)

A semiconductor device having a configuration in which the semiconductor chip is fixed to the main surface of the arrangement plate and the semiconductor chip and the connection terminal are electrically connected by a wire,
A frame body that protrudes from the main surface of the arrangement plate and surrounds the semiconductor chip and the wire, and a sealing resin layer and a soft resin layer that are sequentially stacked from the main surface of the arrangement plate in the frame body And a filling resin layer,
The sealing resin layer seals the main surface of the arrangement plate, the semiconductor chip, the connection terminal and the wire;
The soft resin layer is made of a soft resin material having fluidity and softer than the sealing resin layer and the filling resin layer, and further, at least of the upper surface of the sealing resin layer orthogonal to the stacking direction. Formed in a partial region including the upper part,
The semiconductor device, wherein the filling resin layer is in close contact with a peripheral region surrounding the partial region of the upper surface of the sealing resin layer. A cylindrical sub-frame that protrudes from the upper surface of the sealing resin layer and surrounds at least the wire is disposed at a position spaced inside the frame,
The semiconductor device according to claim 1, wherein the soft resin layer is filled only inside the subframe.   The lower end portion of the sub-frame body along the stacking direction is embedded in the sealing resin layer, and the upper end portion of the sub-frame body is embedded in the filling resin layer. 2. The semiconductor device according to 2.   The upper end portion of the sub-frame body is formed with a protruding portion that protrudes outward in the radial direction of the sub-frame body and is spaced from the upper surface of the sealing resin layer. The semiconductor device according to claim 3.   5. A passage that communicates the inner space and the outer space of the sub-frame body is formed between a main surface of the arrangement plate and a lower end portion of the sub-frame body. The semiconductor device according to any one of the above.   6. The soft resin material is a gel-like resin material having viscosity or wettability that remains in the partial region when poured into the upper surface of the sealing resin layer. The semiconductor device according to any one of the above.

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