JP5898587B2 - パターン形成方法 - Google Patents
パターン形成方法 Download PDFInfo
- Publication number
- JP5898587B2 JP5898587B2 JP2012176841A JP2012176841A JP5898587B2 JP 5898587 B2 JP5898587 B2 JP 5898587B2 JP 2012176841 A JP2012176841 A JP 2012176841A JP 2012176841 A JP2012176841 A JP 2012176841A JP 5898587 B2 JP5898587 B2 JP 5898587B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- polymer
- processed
- pattern
- physical guide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
- H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
- H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
- H10P50/696—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
- H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
- H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
- H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
Landscapes
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Shaping Of Tube Ends By Bending Or Straightening (AREA)
- Drying Of Semiconductors (AREA)
Description
102 被加工膜
103 SOC膜
104 SOG膜
104a 傾斜面
107 ブロックコポリマー層
Claims (5)
- 被加工膜上に第1膜を形成し、
前記第1膜上に、前記第1膜より撥水性の高い第2膜を形成し、
前記第2膜に、ホール側壁部が傾斜面となるホールパターンを形成し、
前記ホールパターンが形成された前記第2膜をマスクに前記第1膜を加工して物理ガイドを形成し、
前記物理ガイドのホール部内に少なくとも2種以上のセグメントを含むポリマー層を形成し、
前記ポリマー層をミクロ相分離させ、第1ポリマー部及び第2ポリマー部を含む自己組織化相を形成し、
前記自己組織化相の前記第1ポリマー部を除去し、
前記第1ポリマー部の除去後、前記第2ポリマー部をマスクに前記被加工膜を加工する、
パターン形成方法。 - 被加工膜上に、凹部の側壁面の少なくとも上部が傾斜面となっている物理ガイドを形成し、
前記物理ガイドの前記凹部内に少なくとも2種以上のセグメントを含むポリマー層を形成し、
前記ポリマー層をミクロ相分離させ、第1ポリマー部及び第2ポリマー部を含む自己組織化相を形成し、
前記自己組織化相を用いて前記被加工膜を加工する、
パターン形成方法。 - 前記自己組織化相の前記第1ポリマー部を除去し、
前記第1ポリマー部の除去後、前記第2ポリマー部をマスクに前記被加工膜を加工する、
請求項2に記載のパターン形成方法。 - 前記被加工膜上に第1膜を形成し、
前記第1膜上に第2膜を形成し、
前記第2膜に、ホール側壁部が傾斜面となるホールパターンを形成し、
前記ホールパターンが形成された前記第2膜をマスクに前記第1膜を加工して前記物理ガイドを形成することを特徴とする請求項2に記載のパターン形成方法。 - 前記第2膜は前記第1膜より高い撥水性を有することを特徴とする請求項4に記載のパターン形成方法。
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012176841A JP5898587B2 (ja) | 2012-08-09 | 2012-08-09 | パターン形成方法 |
| US13/762,892 US20140045341A1 (en) | 2012-08-09 | 2013-02-08 | Pattern forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012176841A JP5898587B2 (ja) | 2012-08-09 | 2012-08-09 | パターン形成方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2014036126A JP2014036126A (ja) | 2014-02-24 |
| JP5898587B2 true JP5898587B2 (ja) | 2016-04-06 |
Family
ID=50066516
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012176841A Expired - Fee Related JP5898587B2 (ja) | 2012-08-09 | 2012-08-09 | パターン形成方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US20140045341A1 (ja) |
| JP (1) | JP5898587B2 (ja) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101624814B1 (ko) * | 2011-12-15 | 2016-05-26 | 인텔 코포레이션 | 단일 노광-자기 정렬된 이중, 삼중 및 사중 패터닝을 위한 방법 |
| WO2015127084A1 (en) * | 2014-02-23 | 2015-08-27 | Tokyo Electron Limited | Method for creating contacts in semiconductor substrates |
| US9229326B2 (en) * | 2014-03-14 | 2016-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for integrated circuit patterning |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6117793A (en) * | 1998-09-03 | 2000-09-12 | Micron Technology, Inc. | Using silicide cap as an etch stop for multilayer metal process and structures so formed |
| JP5414011B2 (ja) * | 2006-05-23 | 2014-02-12 | 国立大学法人京都大学 | 微細構造体、パターン媒体、及びそれらの製造方法 |
| TWI455203B (zh) * | 2007-05-03 | 2014-10-01 | 蘭姆研究公司 | 開孔之硬遮罩及藉由開孔之硬遮罩施行之蝕刻輪廓控制 |
| JP5118073B2 (ja) * | 2009-01-26 | 2013-01-16 | 信越化学工業株式会社 | レジスト下層膜形成方法及びこれを用いたパターン形成方法 |
| US9233840B2 (en) * | 2010-10-28 | 2016-01-12 | International Business Machines Corporation | Method for improving self-assembled polymer features |
| JP5537400B2 (ja) * | 2010-12-22 | 2014-07-02 | 株式会社東芝 | パターン形成方法及び装置 |
-
2012
- 2012-08-09 JP JP2012176841A patent/JP5898587B2/ja not_active Expired - Fee Related
-
2013
- 2013-02-08 US US13/762,892 patent/US20140045341A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| US20140045341A1 (en) | 2014-02-13 |
| JP2014036126A (ja) | 2014-02-24 |
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